| stats.txt (9289:a31a1243a3ed) | stats.txt (9312:e05e1b69ebf2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.023747 # Number of seconds simulated 4sim_ticks 23747395500 # Number of ticks simulated 5final_tick 23747395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.024118 # Number of seconds simulated 4sim_ticks 24118236000 # Number of ticks simulated 5final_tick 24118236000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 142184 # Simulator instruction rate (inst/s) 8host_op_rate 201762 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47606944 # Simulator tick rate (ticks/s) 10host_mem_usage 237384 # Number of bytes of host memory used 11host_seconds 498.82 # Real time elapsed on the host 12sim_insts 70924309 # Number of instructions simulated 13sim_ops 100643556 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 325888 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8028992 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8354880 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 325888 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 325888 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5417728 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5417728 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 5092 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125453 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 130545 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 84652 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 84652 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 13723105 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 338099898 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 351823003 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 13723105 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 13723105 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 228139882 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 228139882 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 228139882 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 13723105 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 338099898 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 579962885 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 96109 # Simulator instruction rate (inst/s) 8host_op_rate 136382 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32682486 # Simulator tick rate (ticks/s) 10host_mem_usage 260548 # Number of bytes of host memory used 11host_seconds 737.96 # Real time elapsed on the host 12sim_insts 70924474 # Number of instructions simulated 13sim_ops 100643721 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 326720 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8354752 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 326720 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 326720 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5417408 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5417408 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 5105 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 130543 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 84647 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 84647 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 13546596 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 332861491 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 346408087 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 13546596 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 13546596 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 224618749 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 224618749 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 224618749 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 13546596 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 332861491 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 571026836 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 130544 # Total number of read requests seen 38system.physmem.writeReqs 84647 # Total number of write requests seen 39system.physmem.cpureqs 215212 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 8354752 # Total number of bytes read from memory 41system.physmem.bytesWritten 5417408 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 8354752 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 5417408 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 21 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 8259 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 8120 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 8253 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 7969 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 7982 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 8186 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 8215 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 8129 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 8104 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 8304 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 8313 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 8256 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 8235 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 8061 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 8114 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 8038 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 5294 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 5079 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 5310 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 5269 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 5220 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 5401 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 5230 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 5186 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 5230 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 5326 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 5458 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 5400 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 5367 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 5357 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 5265 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 5255 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 24118216500 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 130544 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 84647 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 21 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 69205 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 57726 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 3491 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 3556 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 3679 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 3681 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 3681 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 3681 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 3681 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 3680 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 3680 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 3680 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 3680 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 3680 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 3680 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 3680 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 3680 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 3680 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 3680 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 3680 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 3680 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 3680 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 3680 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 3680 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 125 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 2308860118 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 4224446118 # Sum of mem lat for all requests 176system.physmem.totBusLat 522152000 # Total cycles spent in databus access 177system.physmem.totBankLat 1393434000 # Total cycles spent in bank access 178system.physmem.avgQLat 17687.26 # Average queueing delay per request 179system.physmem.avgBankLat 10674.55 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 32361.81 # Average memory access latency 182system.physmem.avgRdBW 346.41 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 224.62 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 346.41 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 224.62 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 3.57 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.18 # Average read queue length over time 189system.physmem.avgWrQLen 10.22 # Average write queue length over time 190system.physmem.readRowHits 119025 # Number of row buffer hits during reads 191system.physmem.writeRowHits 63519 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes 194system.physmem.avgGap 112078.18 # Average gap between requests |
| 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 1946 # Number of system calls | 195system.cpu.dtb.inst_hits 0 # ITB inst hits 196system.cpu.dtb.inst_misses 0 # ITB inst misses 197system.cpu.dtb.read_hits 0 # DTB read hits 198system.cpu.dtb.read_misses 0 # DTB read misses 199system.cpu.dtb.write_hits 0 # DTB write hits 200system.cpu.dtb.write_misses 0 # DTB write misses 201system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 202system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 230system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu.itb.read_accesses 0 # DTB read accesses 232system.cpu.itb.write_accesses 0 # DTB write accesses 233system.cpu.itb.inst_accesses 0 # ITB inst accesses 234system.cpu.itb.hits 0 # DTB hits 235system.cpu.itb.misses 0 # DTB misses 236system.cpu.itb.accesses 0 # DTB accesses 237system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 80system.cpu.numCycles 47494792 # number of cpu cycles simulated | 238system.cpu.numCycles 48236473 # number of cpu cycles simulated |
| 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 239system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 240system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 83system.cpu.BPredUnit.lookups 16945853 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 12976600 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 671047 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 11791616 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 7980415 # Number of BTB hits | 241system.cpu.BPredUnit.lookups 16941730 # Number of BP lookups 242system.cpu.BPredUnit.condPredicted 12971297 # Number of conditional branches predicted 243system.cpu.BPredUnit.condIncorrect 673506 # Number of conditional branches incorrect 244system.cpu.BPredUnit.BTBLookups 11955063 # Number of BTB lookups 245system.cpu.BPredUnit.BTBHits 7993850 # Number of BTB hits |
| 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 89system.cpu.BPredUnit.usedRAS 1850372 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 114214 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 12555295 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 86800259 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 16945853 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 9830787 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 21603869 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 2612787 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 10088905 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 11920379 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 192164 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 46165707 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.632126 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.343505 # Number of instructions fetched each cycle (Total) | 247system.cpu.BPredUnit.usedRAS 1846956 # Number of times the RAS was used to get a target. 248system.cpu.BPredUnit.RASInCorrect 114386 # Number of incorrect RAS predictions. 249system.cpu.fetch.icacheStallCycles 12578866 # Number of cycles fetch is stalled on an Icache miss 250system.cpu.fetch.Insts 86846522 # Number of instructions fetch has processed 251system.cpu.fetch.Branches 16941730 # Number of branches that fetch encountered 252system.cpu.fetch.predictedBranches 9840806 # Number of branches that fetch has predicted taken 253system.cpu.fetch.Cycles 21621241 # Number of cycles fetch has run and was not squashing or blocked 254system.cpu.fetch.SquashCycles 2621679 # Number of cycles fetch has spent squashing 255system.cpu.fetch.BlockedCycles 9822158 # Number of cycles fetch has spent blocked 256system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 257system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps 258system.cpu.fetch.CacheLines 11935876 # Number of cache lines fetched 259system.cpu.fetch.IcacheSquashes 192083 # Number of outstanding Icache misses that were squashed 260system.cpu.fetch.rateDist::samples 45946369 # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::mean 2.646136 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::stdev 3.346825 # Number of instructions fetched each cycle (Total) |
| 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 263system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 106system.cpu.fetch.rateDist::0 24583523 53.25% 53.25% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 2172032 4.70% 57.96% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 2013449 4.36% 62.32% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 2091121 4.53% 66.85% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 1494392 3.24% 70.08% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 1411801 3.06% 73.14% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 982905 2.13% 75.27% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 1224192 2.65% 77.92% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 10192292 22.08% 100.00% # Number of instructions fetched each cycle (Total) | 264system.cpu.fetch.rateDist::0 24346810 52.99% 52.99% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::1 2176798 4.74% 57.73% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::2 2018114 4.39% 62.12% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::3 2096656 4.56% 66.68% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::4 1493050 3.25% 69.93% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::5 1410144 3.07% 73.00% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::6 982338 2.14% 75.14% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::7 1219252 2.65% 77.79% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::8 10203207 22.21% 100.00% # Number of instructions fetched each cycle (Total) |
| 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 273system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 118system.cpu.fetch.rateDist::total 46165707 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.356794 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.827574 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 14647959 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 8470510 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 19858799 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 1377235 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 1811204 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 3409264 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 108749 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 118806925 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 370081 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 1811204 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 16375618 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 2381141 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 742521 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 19461585 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 5393638 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 116666793 # Number of instructions processed by rename 137system.cpu.rename.ROBFullEvents 61 # Number of times rename has blocked due to ROB full 138system.cpu.rename.IQFullEvents 9401 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 4563999 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 255 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 117035573 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 537232740 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 537225721 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 7019 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 99159360 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 17876213 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 25291 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 25289 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 12820996 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 29922759 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 22636012 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 3511140 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 4209388 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 112770529 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 41465 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 108119060 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 319934 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 12017924 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 28288746 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 4343 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 46165707 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 2.341978 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.993843 # Number of insts issued each cycle | 276system.cpu.fetch.rateDist::total 45946369 # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.branchRate 0.351222 # Number of branch fetches per cycle 278system.cpu.fetch.rate 1.800433 # Number of inst fetches per cycle 279system.cpu.decode.IdleCycles 14667970 # Number of cycles decode is idle 280system.cpu.decode.BlockedCycles 8208523 # Number of cycles decode is blocked 281system.cpu.decode.RunCycles 19889635 # Number of cycles decode is running 282system.cpu.decode.UnblockCycles 1362773 # Number of cycles decode is unblocking 283system.cpu.decode.SquashCycles 1817468 # Number of cycles decode is squashing 284system.cpu.decode.BranchResolved 3410064 # Number of times decode resolved a branch 285system.cpu.decode.BranchMispred 108805 # Number of times decode detected a branch misprediction 286system.cpu.decode.DecodedInsts 118869438 # Number of instructions handled by decode 287system.cpu.decode.SquashedInsts 371525 # Number of squashed instructions handled by decode 288system.cpu.rename.SquashCycles 1817468 # Number of cycles rename is squashing 289system.cpu.rename.IdleCycles 16391147 # Number of cycles rename is idle 290system.cpu.rename.BlockCycles 2180805 # Number of cycles rename is blocking 291system.cpu.rename.serializeStallCycles 744758 # count of cycles rename stalled for serializing inst 292system.cpu.rename.RunCycles 19482609 # Number of cycles rename is running 293system.cpu.rename.UnblockCycles 5329582 # Number of cycles rename is unblocking 294system.cpu.rename.RenamedInsts 116713190 # Number of instructions processed by rename 295system.cpu.rename.ROBFullEvents 108 # Number of times rename has blocked due to ROB full 296system.cpu.rename.IQFullEvents 9859 # Number of times rename has blocked due to IQ full 297system.cpu.rename.LSQFullEvents 4505903 # Number of times rename has blocked due to LSQ full 298system.cpu.rename.FullRegisterEvents 207 # Number of times there has been no free registers 299system.cpu.rename.RenamedOperands 117071318 # Number of destination operands rename has renamed 300system.cpu.rename.RenameLookups 537479367 # Number of register rename lookups that rename has made 301system.cpu.rename.int_rename_lookups 537472531 # Number of integer rename lookups 302system.cpu.rename.fp_rename_lookups 6836 # Number of floating rename lookups 303system.cpu.rename.CommittedMaps 99159624 # Number of HB maps that are committed 304system.cpu.rename.UndoneMaps 17911694 # Number of HB maps that are undone due to squashing 305system.cpu.rename.serializingInsts 25668 # count of serializing insts renamed 306system.cpu.rename.tempSerializingInsts 25645 # count of temporary serializing insts renamed 307system.cpu.rename.skidInsts 12679365 # count of insts added to the skid buffer 308system.cpu.memDep0.insertedLoads 29945230 # Number of loads inserted to the mem dependence unit. 309system.cpu.memDep0.insertedStores 22644975 # Number of stores inserted to the mem dependence unit. 310system.cpu.memDep0.conflictingLoads 3554453 # Number of conflicting loads. 311system.cpu.memDep0.conflictingStores 4308488 # Number of conflicting stores. 312system.cpu.iq.iqInstsAdded 112817859 # Number of instructions added to the IQ (excludes non-spec) 313system.cpu.iq.iqNonSpecInstsAdded 41708 # Number of non-speculative instructions added to the IQ 314system.cpu.iq.iqInstsIssued 108131794 # Number of instructions issued 315system.cpu.iq.iqSquashedInstsIssued 320520 # Number of squashed instructions issued 316system.cpu.iq.iqSquashedInstsExamined 12061302 # Number of squashed instructions iterated over during squash; mainly for profiling 317system.cpu.iq.iqSquashedOperandsExamined 28451439 # Number of squashed operands that are examined and possibly removed from graph 318system.cpu.iq.iqSquashedNonSpecRemoved 4553 # Number of squashed non-spec instructions that were removed 319system.cpu.iq.issued_per_cycle::samples 45946369 # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::mean 2.353435 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::stdev 1.992555 # Number of insts issued each cycle |
| 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 322system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 165system.cpu.iq.issued_per_cycle::0 10763393 23.31% 23.31% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 8065577 17.47% 40.79% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 7395154 16.02% 56.80% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 7189034 15.57% 72.38% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 5495666 11.90% 84.28% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 3896907 8.44% 92.72% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 1882413 4.08% 96.80% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 886108 1.92% 98.72% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 591455 1.28% 100.00% # Number of insts issued each cycle | 323system.cpu.iq.issued_per_cycle::0 10567306 23.00% 23.00% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::1 8020118 17.46% 40.45% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::2 7429171 16.17% 56.62% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::3 7172224 15.61% 72.23% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::4 5474021 11.91% 84.15% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::5 3920572 8.53% 92.68% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::6 1887629 4.11% 96.79% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::7 890680 1.94% 98.73% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::8 584648 1.27% 100.00% # Number of insts issued each cycle |
| 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 332system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 177system.cpu.iq.issued_per_cycle::total 46165707 # Number of insts issued each cycle | 335system.cpu.iq.issued_per_cycle::total 45946369 # Number of insts issued each cycle |
| 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 336system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 179system.cpu.iq.fu_full::IntAlu 111137 4.37% 4.37% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 1401194 55.04% 59.40% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 1033519 40.60% 100.00% # attempts to use FU when none available | 337system.cpu.iq.fu_full::IntAlu 112571 4.42% 4.42% # attempts to use FU when none available 338system.cpu.iq.fu_full::IntMult 0 0.00% 4.42% # attempts to use FU when none available 339system.cpu.iq.fu_full::IntDiv 0 0.00% 4.42% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.42% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.42% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.42% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatMult 0 0.00% 4.42% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.42% # attempts to use FU when none available 345system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.42% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.42% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.42% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.42% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.42% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.42% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.42% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdMult 0 0.00% 4.42% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.42% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdShift 0 0.00% 4.42% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.42% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.42% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.42% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.42% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.42% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.42% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.42% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.42% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.42% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.42% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.42% # attempts to use FU when none available 366system.cpu.iq.fu_full::MemRead 1415190 55.57% 59.99% # attempts to use FU when none available 367system.cpu.iq.fu_full::MemWrite 1018757 40.01% 100.00% # attempts to use FU when none available |
| 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 368system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 369system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 370system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 213system.cpu.iq.FU_type_0::IntAlu 57171551 52.88% 52.88% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 91476 0.08% 52.96% # Type of FU issued | 371system.cpu.iq.FU_type_0::IntAlu 57176824 52.88% 52.88% # Type of FU issued 372system.cpu.iq.FU_type_0::IntMult 91588 0.08% 52.96% # Type of FU issued |
| 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.96% # Type of FU issued | 373system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.96% # Type of FU issued |
| 216system.cpu.iq.FU_type_0::FloatAdd 254 0.00% 52.96% # Type of FU issued | 374system.cpu.iq.FU_type_0::FloatAdd 236 0.00% 52.96% # Type of FU issued |
| 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.96% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.96% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.96% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.96% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.96% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.96% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.96% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.96% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.96% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.96% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.96% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.96% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.96% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.96% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.96% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.96% # Type of FU issued | 375system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.96% # Type of FU issued 376system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.96% # Type of FU issued 377system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.96% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.96% # Type of FU issued 379system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.96% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.96% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.96% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.96% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 392system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.96% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.96% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.96% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.96% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.96% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.96% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.96% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.96% # Type of FU issued |
| 242system.cpu.iq.FU_type_0::MemRead 29115621 26.93% 79.89% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 21740151 20.11% 100.00% # Type of FU issued | 400system.cpu.iq.FU_type_0::MemRead 29115499 26.93% 79.89% # Type of FU issued 401system.cpu.iq.FU_type_0::MemWrite 21747640 20.11% 100.00% # Type of FU issued |
| 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 402system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 403system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 246system.cpu.iq.FU_type_0::total 108119060 # Type of FU issued 247system.cpu.iq.rate 2.276440 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 2545850 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.023547 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 265268953 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 124855497 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 106214423 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 658 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 1042 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 198 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 110664579 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 331 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 2183386 # Number of loads that had data forwarded from stores | 404system.cpu.iq.FU_type_0::total 108131794 # Type of FU issued 405system.cpu.iq.rate 2.241702 # Inst issue rate 406system.cpu.iq.fu_busy_cnt 2546520 # FU busy when requested 407system.cpu.iq.fu_busy_rate 0.023550 # FU busy rate (busy events/executed inst) 408system.cpu.iq.int_inst_queue_reads 265076321 # Number of integer instruction queue reads 409system.cpu.iq.int_inst_queue_writes 124946354 # Number of integer instruction queue writes 410system.cpu.iq.int_inst_queue_wakeup_accesses 106228285 # Number of integer instruction queue wakeup accesses 411system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads 412system.cpu.iq.fp_inst_queue_writes 1064 # Number of floating instruction queue writes 413system.cpu.iq.fp_inst_queue_wakeup_accesses 184 # Number of floating instruction queue wakeup accesses 414system.cpu.iq.int_alu_accesses 110677977 # Number of integer alu accesses 415system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses 416system.cpu.iew.lsq.thread0.forwLoads 2176777 # Number of loads that had data forwarded from stores |
| 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 417system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 260system.cpu.iew.lsq.thread0.squashedLoads 2612315 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 8134 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 27815 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 2076938 # Number of stores squashed | 418system.cpu.iew.lsq.thread0.squashedLoads 2634753 # Number of loads squashed 419system.cpu.iew.lsq.thread0.ignoredResponses 7333 # Number of memory responses ignored because the instruction is squashed 420system.cpu.iew.lsq.thread0.memOrderViolation 27466 # Number of memory ordering violations 421system.cpu.iew.lsq.thread0.squashedStores 2085868 # Number of stores squashed |
| 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 266system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled | 422system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 423system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 424system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled |
| 267system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked | 425system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked |
| 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 426system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 269system.cpu.iew.iewSquashCycles 1811204 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 969930 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 37593 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 112821828 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 344750 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 29922759 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 22636012 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 24938 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 1077 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 4742 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 27815 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 448633 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 200270 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 648903 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 106941825 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 28766464 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 1177235 # Number of squashed instructions skipped in execute | 427system.cpu.iew.iewSquashCycles 1817468 # Number of cycles IEW is squashing 428system.cpu.iew.iewBlockCycles 825568 # Number of cycles IEW is blocking 429system.cpu.iew.iewUnblockCycles 31883 # Number of cycles IEW is unblocking 430system.cpu.iew.iewDispatchedInsts 112869381 # Number of instructions dispatched to IQ 431system.cpu.iew.iewDispSquashedInsts 345659 # Number of squashed instructions skipped by dispatch 432system.cpu.iew.iewDispLoadInsts 29945230 # Number of dispatched load instructions 433system.cpu.iew.iewDispStoreInsts 22644975 # Number of dispatched store instructions 434system.cpu.iew.iewDispNonSpecInsts 25238 # Number of dispatched non-speculative instructions 435system.cpu.iew.iewIQFullEvents 1097 # Number of times the IQ has become full, causing a stall 436system.cpu.iew.iewLSQFullEvents 3023 # Number of times the LSQ has become full, causing a stall 437system.cpu.iew.memOrderViolationEvents 27466 # Number of memory order violations 438system.cpu.iew.predictedTakenIncorrect 452017 # Number of branches that were predicted taken incorrectly 439system.cpu.iew.predictedNotTakenIncorrect 199338 # Number of branches that were predicted not taken incorrectly 440system.cpu.iew.branchMispredicts 651355 # Number of branch mispredicts detected at execute 441system.cpu.iew.iewExecutedInsts 106955311 # Number of executed instructions 442system.cpu.iew.iewExecLoadInsts 28765738 # Number of load instructions executed 443system.cpu.iew.iewExecSquashedInsts 1176483 # Number of squashed instructions skipped in execute |
| 286system.cpu.iew.exec_swp 0 # number of swp insts executed | 444system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 287system.cpu.iew.exec_nop 9834 # number of nop insts executed 288system.cpu.iew.exec_refs 50197967 # number of memory reference insts executed 289system.cpu.iew.exec_branches 14707935 # Number of branches executed 290system.cpu.iew.exec_stores 21431503 # Number of stores executed 291system.cpu.iew.exec_rate 2.251654 # Inst execution rate 292system.cpu.iew.wb_sent 106459563 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 106214621 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 53551409 # num instructions producing a value 295system.cpu.iew.wb_consumers 103987749 # num instructions consuming a value | 445system.cpu.iew.exec_nop 9814 # number of nop insts executed 446system.cpu.iew.exec_refs 50205955 # number of memory reference insts executed 447system.cpu.iew.exec_branches 14704580 # Number of branches executed 448system.cpu.iew.exec_stores 21440217 # Number of stores executed 449system.cpu.iew.exec_rate 2.217312 # Inst execution rate 450system.cpu.iew.wb_sent 106472209 # cumulative count of insts sent to commit 451system.cpu.iew.wb_count 106228469 # cumulative count of insts written-back 452system.cpu.iew.wb_producers 53599142 # num instructions producing a value 453system.cpu.iew.wb_consumers 104275439 # num instructions consuming a value |
| 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 454system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 297system.cpu.iew.wb_rate 2.236342 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.514978 # average fanout of values written-back | 455system.cpu.iew.wb_rate 2.202244 # insts written-back per cycle 456system.cpu.iew.wb_fanout 0.514015 # average fanout of values written-back |
| 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 457system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 300system.cpu.commit.commitSquashedInsts 12173182 # The number of squashed insts skipped by commit 301system.cpu.commit.commitNonSpecStalls 37122 # The number of times commit has been forced to stall to communicate backwards 302system.cpu.commit.branchMispredicts 565028 # The number of times a branch was mispredicted 303system.cpu.commit.committed_per_cycle::samples 44354504 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::mean 2.269197 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::stdev 2.754788 # Number of insts commited each cycle | 458system.cpu.commit.commitSquashedInsts 12220612 # The number of squashed insts skipped by commit 459system.cpu.commit.commitNonSpecStalls 37155 # The number of times commit has been forced to stall to communicate backwards 460system.cpu.commit.branchMispredicts 567157 # The number of times a branch was mispredicted 461system.cpu.commit.committed_per_cycle::samples 44128902 # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::mean 2.280802 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::stdev 2.756042 # Number of insts commited each cycle |
| 306system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 464system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 307system.cpu.commit.committed_per_cycle::0 15099779 34.04% 34.04% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::1 11755524 26.50% 60.55% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::2 3528202 7.95% 68.50% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::3 2907503 6.56% 75.06% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::4 1884478 4.25% 79.31% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::5 1967896 4.44% 83.74% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::6 685684 1.55% 85.29% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::7 580329 1.31% 86.60% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::8 5945109 13.40% 100.00% # Number of insts commited each cycle | 465system.cpu.commit.committed_per_cycle::0 14889585 33.74% 33.74% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::1 11723135 26.57% 60.31% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::2 3525477 7.99% 68.30% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::3 2911105 6.60% 74.89% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::4 1898953 4.30% 79.20% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::5 1983472 4.49% 83.69% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::6 685141 1.55% 85.24% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::7 578421 1.31% 86.55% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::8 5933613 13.45% 100.00% # Number of insts commited each cycle |
| 316system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 474system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 319system.cpu.commit.committed_per_cycle::total 44354504 # Number of insts commited each cycle 320system.cpu.commit.committedInsts 70929861 # Number of instructions committed 321system.cpu.commit.committedOps 100649108 # Number of ops (including micro ops) committed | 477system.cpu.commit.committed_per_cycle::total 44128902 # Number of insts commited each cycle 478system.cpu.commit.committedInsts 70930026 # Number of instructions committed 479system.cpu.commit.committedOps 100649273 # Number of ops (including micro ops) committed |
| 322system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 480system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 323system.cpu.commit.refs 47869518 # Number of memory references committed 324system.cpu.commit.loads 27310444 # Number of loads committed | 481system.cpu.commit.refs 47869584 # Number of memory references committed 482system.cpu.commit.loads 27310477 # Number of loads committed |
| 325system.cpu.commit.membars 15920 # Number of memory barriers committed | 483system.cpu.commit.membars 15920 # Number of memory barriers committed |
| 326system.cpu.commit.branches 13744841 # Number of branches committed | 484system.cpu.commit.branches 13744874 # Number of branches committed |
| 327system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. | 485system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. |
| 328system.cpu.commit.int_insts 91486123 # Number of committed integer instructions. | 486system.cpu.commit.int_insts 91486255 # Number of committed integer instructions. |
| 329system.cpu.commit.function_calls 1679850 # Number of function calls committed. | 487system.cpu.commit.function_calls 1679850 # Number of function calls committed. |
| 330system.cpu.commit.bw_lim_events 5945109 # number cycles where commit BW limit reached | 488system.cpu.commit.bw_lim_events 5933613 # number cycles where commit BW limit reached |
| 331system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 489system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 332system.cpu.rob.rob_reads 151206386 # The number of ROB reads 333system.cpu.rob.rob_writes 227466743 # The number of ROB writes 334system.cpu.timesIdled 61795 # Number of times that the entire CPU went into an idle state and unscheduled itself 335system.cpu.idleCycles 1329085 # Total number of cycles that the CPU has spent unscheduled due to idling 336system.cpu.committedInsts 70924309 # Number of Instructions Simulated 337system.cpu.committedOps 100643556 # Number of Ops (including micro ops) Simulated 338system.cpu.committedInsts_total 70924309 # Number of Instructions Simulated 339system.cpu.cpi 0.669655 # CPI: Cycles Per Instruction 340system.cpu.cpi_total 0.669655 # CPI: Total CPI of All Threads 341system.cpu.ipc 1.493307 # IPC: Instructions Per Cycle 342system.cpu.ipc_total 1.493307 # IPC: Total IPC of All Threads 343system.cpu.int_regfile_reads 514746035 # number of integer regfile reads 344system.cpu.int_regfile_writes 104090442 # number of integer regfile writes 345system.cpu.fp_regfile_reads 1004 # number of floating regfile reads 346system.cpu.fp_regfile_writes 868 # number of floating regfile writes 347system.cpu.misc_regfile_reads 145207051 # number of misc regfile reads 348system.cpu.misc_regfile_writes 38512 # number of misc regfile writes 349system.cpu.icache.replacements 28686 # number of replacements 350system.cpu.icache.tagsinuse 1815.800680 # Cycle average of tags in use 351system.cpu.icache.total_refs 11888473 # Total number of references to valid blocks. 352system.cpu.icache.sampled_refs 30726 # Sample count of references to valid blocks. 353system.cpu.icache.avg_refs 386.918994 # Average number of references to valid blocks. | 490system.cpu.rob.rob_reads 151039875 # The number of ROB reads 491system.cpu.rob.rob_writes 227567987 # The number of ROB writes 492system.cpu.timesIdled 41986 # Number of times that the entire CPU went into an idle state and unscheduled itself 493system.cpu.idleCycles 2290104 # Total number of cycles that the CPU has spent unscheduled due to idling 494system.cpu.committedInsts 70924474 # Number of Instructions Simulated 495system.cpu.committedOps 100643721 # Number of Ops (including micro ops) Simulated 496system.cpu.committedInsts_total 70924474 # Number of Instructions Simulated 497system.cpu.cpi 0.680110 # CPI: Cycles Per Instruction 498system.cpu.cpi_total 0.680110 # CPI: Total CPI of All Threads 499system.cpu.ipc 1.470350 # IPC: Instructions Per Cycle 500system.cpu.ipc_total 1.470350 # IPC: Total IPC of All Threads 501system.cpu.int_regfile_reads 514798749 # number of integer regfile reads 502system.cpu.int_regfile_writes 104102920 # number of integer regfile writes 503system.cpu.fp_regfile_reads 856 # number of floating regfile reads 504system.cpu.fp_regfile_writes 720 # number of floating regfile writes 505system.cpu.misc_regfile_reads 145263086 # number of misc regfile reads 506system.cpu.misc_regfile_writes 38578 # number of misc regfile writes 507system.cpu.icache.replacements 29552 # number of replacements 508system.cpu.icache.tagsinuse 1826.273597 # Cycle average of tags in use 509system.cpu.icache.total_refs 11903209 # Total number of references to valid blocks. 510system.cpu.icache.sampled_refs 31595 # Sample count of references to valid blocks. 511system.cpu.icache.avg_refs 376.743440 # Average number of references to valid blocks. |
| 354system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 512system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 355system.cpu.icache.occ_blocks::cpu.inst 1815.800680 # Average occupied blocks per requestor 356system.cpu.icache.occ_percent::cpu.inst 0.886621 # Average percentage of cache occupancy 357system.cpu.icache.occ_percent::total 0.886621 # Average percentage of cache occupancy 358system.cpu.icache.ReadReq_hits::cpu.inst 11888474 # number of ReadReq hits 359system.cpu.icache.ReadReq_hits::total 11888474 # number of ReadReq hits 360system.cpu.icache.demand_hits::cpu.inst 11888474 # number of demand (read+write) hits 361system.cpu.icache.demand_hits::total 11888474 # number of demand (read+write) hits 362system.cpu.icache.overall_hits::cpu.inst 11888474 # number of overall hits 363system.cpu.icache.overall_hits::total 11888474 # number of overall hits 364system.cpu.icache.ReadReq_misses::cpu.inst 31905 # number of ReadReq misses 365system.cpu.icache.ReadReq_misses::total 31905 # number of ReadReq misses 366system.cpu.icache.demand_misses::cpu.inst 31905 # number of demand (read+write) misses 367system.cpu.icache.demand_misses::total 31905 # number of demand (read+write) misses 368system.cpu.icache.overall_misses::cpu.inst 31905 # number of overall misses 369system.cpu.icache.overall_misses::total 31905 # number of overall misses 370system.cpu.icache.ReadReq_miss_latency::cpu.inst 328897000 # number of ReadReq miss cycles 371system.cpu.icache.ReadReq_miss_latency::total 328897000 # number of ReadReq miss cycles 372system.cpu.icache.demand_miss_latency::cpu.inst 328897000 # number of demand (read+write) miss cycles 373system.cpu.icache.demand_miss_latency::total 328897000 # number of demand (read+write) miss cycles 374system.cpu.icache.overall_miss_latency::cpu.inst 328897000 # number of overall miss cycles 375system.cpu.icache.overall_miss_latency::total 328897000 # number of overall miss cycles 376system.cpu.icache.ReadReq_accesses::cpu.inst 11920379 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.ReadReq_accesses::total 11920379 # number of ReadReq accesses(hits+misses) 378system.cpu.icache.demand_accesses::cpu.inst 11920379 # number of demand (read+write) accesses 379system.cpu.icache.demand_accesses::total 11920379 # number of demand (read+write) accesses 380system.cpu.icache.overall_accesses::cpu.inst 11920379 # number of overall (read+write) accesses 381system.cpu.icache.overall_accesses::total 11920379 # number of overall (read+write) accesses 382system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002677 # miss rate for ReadReq accesses 383system.cpu.icache.ReadReq_miss_rate::total 0.002677 # miss rate for ReadReq accesses 384system.cpu.icache.demand_miss_rate::cpu.inst 0.002677 # miss rate for demand accesses 385system.cpu.icache.demand_miss_rate::total 0.002677 # miss rate for demand accesses 386system.cpu.icache.overall_miss_rate::cpu.inst 0.002677 # miss rate for overall accesses 387system.cpu.icache.overall_miss_rate::total 0.002677 # miss rate for overall accesses 388system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10308.635010 # average ReadReq miss latency 389system.cpu.icache.ReadReq_avg_miss_latency::total 10308.635010 # average ReadReq miss latency 390system.cpu.icache.demand_avg_miss_latency::cpu.inst 10308.635010 # average overall miss latency 391system.cpu.icache.demand_avg_miss_latency::total 10308.635010 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::cpu.inst 10308.635010 # average overall miss latency 393system.cpu.icache.overall_avg_miss_latency::total 10308.635010 # average overall miss latency | 513system.cpu.icache.occ_blocks::cpu.inst 1826.273597 # Average occupied blocks per requestor 514system.cpu.icache.occ_percent::cpu.inst 0.891735 # Average percentage of cache occupancy 515system.cpu.icache.occ_percent::total 0.891735 # Average percentage of cache occupancy 516system.cpu.icache.ReadReq_hits::cpu.inst 11903210 # number of ReadReq hits 517system.cpu.icache.ReadReq_hits::total 11903210 # number of ReadReq hits 518system.cpu.icache.demand_hits::cpu.inst 11903210 # number of demand (read+write) hits 519system.cpu.icache.demand_hits::total 11903210 # number of demand (read+write) hits 520system.cpu.icache.overall_hits::cpu.inst 11903210 # number of overall hits 521system.cpu.icache.overall_hits::total 11903210 # number of overall hits 522system.cpu.icache.ReadReq_misses::cpu.inst 32666 # number of ReadReq misses 523system.cpu.icache.ReadReq_misses::total 32666 # number of ReadReq misses 524system.cpu.icache.demand_misses::cpu.inst 32666 # number of demand (read+write) misses 525system.cpu.icache.demand_misses::total 32666 # number of demand (read+write) misses 526system.cpu.icache.overall_misses::cpu.inst 32666 # number of overall misses 527system.cpu.icache.overall_misses::total 32666 # number of overall misses 528system.cpu.icache.ReadReq_miss_latency::cpu.inst 361659000 # number of ReadReq miss cycles 529system.cpu.icache.ReadReq_miss_latency::total 361659000 # number of ReadReq miss cycles 530system.cpu.icache.demand_miss_latency::cpu.inst 361659000 # number of demand (read+write) miss cycles 531system.cpu.icache.demand_miss_latency::total 361659000 # number of demand (read+write) miss cycles 532system.cpu.icache.overall_miss_latency::cpu.inst 361659000 # number of overall miss cycles 533system.cpu.icache.overall_miss_latency::total 361659000 # number of overall miss cycles 534system.cpu.icache.ReadReq_accesses::cpu.inst 11935876 # number of ReadReq accesses(hits+misses) 535system.cpu.icache.ReadReq_accesses::total 11935876 # number of ReadReq accesses(hits+misses) 536system.cpu.icache.demand_accesses::cpu.inst 11935876 # number of demand (read+write) accesses 537system.cpu.icache.demand_accesses::total 11935876 # number of demand (read+write) accesses 538system.cpu.icache.overall_accesses::cpu.inst 11935876 # number of overall (read+write) accesses 539system.cpu.icache.overall_accesses::total 11935876 # number of overall (read+write) accesses 540system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses 541system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses 542system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses 543system.cpu.icache.demand_miss_rate::total 0.002737 # miss rate for demand accesses 544system.cpu.icache.overall_miss_rate::cpu.inst 0.002737 # miss rate for overall accesses 545system.cpu.icache.overall_miss_rate::total 0.002737 # miss rate for overall accesses 546system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11071.419825 # average ReadReq miss latency 547system.cpu.icache.ReadReq_avg_miss_latency::total 11071.419825 # average ReadReq miss latency 548system.cpu.icache.demand_avg_miss_latency::cpu.inst 11071.419825 # average overall miss latency 549system.cpu.icache.demand_avg_miss_latency::total 11071.419825 # average overall miss latency 550system.cpu.icache.overall_avg_miss_latency::cpu.inst 11071.419825 # average overall miss latency 551system.cpu.icache.overall_avg_miss_latency::total 11071.419825 # average overall miss latency |
| 394system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 395system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 399system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 400system.cpu.icache.fast_writes 0 # number of fast writes performed 401system.cpu.icache.cache_copies 0 # number of cache copies performed | 552system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 555system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 557system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu.icache.fast_writes 0 # number of fast writes performed 559system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 402system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1159 # number of ReadReq MSHR hits 403system.cpu.icache.ReadReq_mshr_hits::total 1159 # number of ReadReq MSHR hits 404system.cpu.icache.demand_mshr_hits::cpu.inst 1159 # number of demand (read+write) MSHR hits 405system.cpu.icache.demand_mshr_hits::total 1159 # number of demand (read+write) MSHR hits 406system.cpu.icache.overall_mshr_hits::cpu.inst 1159 # number of overall MSHR hits 407system.cpu.icache.overall_mshr_hits::total 1159 # number of overall MSHR hits 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30746 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 30746 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 30746 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 30746 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 30746 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 30746 # number of overall MSHR misses 414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 238224500 # number of ReadReq MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_latency::total 238224500 # number of ReadReq MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 238224500 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::total 238224500 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 238224500 # number of overall MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::total 238224500 # number of overall MSHR miss cycles 420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for ReadReq accesses 421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002579 # mshr miss rate for ReadReq accesses 422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for demand accesses 423system.cpu.icache.demand_mshr_miss_rate::total 0.002579 # mshr miss rate for demand accesses 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.002579 # mshr miss rate for overall accesses 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7748.146100 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7748.146100 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7748.146100 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 7748.146100 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7748.146100 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 7748.146100 # average overall mshr miss latency | 560system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1048 # number of ReadReq MSHR hits 561system.cpu.icache.ReadReq_mshr_hits::total 1048 # number of ReadReq MSHR hits 562system.cpu.icache.demand_mshr_hits::cpu.inst 1048 # number of demand (read+write) MSHR hits 563system.cpu.icache.demand_mshr_hits::total 1048 # number of demand (read+write) MSHR hits 564system.cpu.icache.overall_mshr_hits::cpu.inst 1048 # number of overall MSHR hits 565system.cpu.icache.overall_mshr_hits::total 1048 # number of overall MSHR hits 566system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31618 # number of ReadReq MSHR misses 567system.cpu.icache.ReadReq_mshr_misses::total 31618 # number of ReadReq MSHR misses 568system.cpu.icache.demand_mshr_misses::cpu.inst 31618 # number of demand (read+write) MSHR misses 569system.cpu.icache.demand_mshr_misses::total 31618 # number of demand (read+write) MSHR misses 570system.cpu.icache.overall_mshr_misses::cpu.inst 31618 # number of overall MSHR misses 571system.cpu.icache.overall_mshr_misses::total 31618 # number of overall MSHR misses 572system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 265572000 # number of ReadReq MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_latency::total 265572000 # number of ReadReq MSHR miss cycles 574system.cpu.icache.demand_mshr_miss_latency::cpu.inst 265572000 # number of demand (read+write) MSHR miss cycles 575system.cpu.icache.demand_mshr_miss_latency::total 265572000 # number of demand (read+write) MSHR miss cycles 576system.cpu.icache.overall_mshr_miss_latency::cpu.inst 265572000 # number of overall MSHR miss cycles 577system.cpu.icache.overall_mshr_miss_latency::total 265572000 # number of overall MSHR miss cycles 578system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses 579system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses 580system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses 581system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses 582system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses 583system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses 584system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8399.392751 # average ReadReq mshr miss latency 585system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8399.392751 # average ReadReq mshr miss latency 586system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8399.392751 # average overall mshr miss latency 587system.cpu.icache.demand_avg_mshr_miss_latency::total 8399.392751 # average overall mshr miss latency 588system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8399.392751 # average overall mshr miss latency 589system.cpu.icache.overall_avg_mshr_miss_latency::total 8399.392751 # average overall mshr miss latency |
| 432system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 590system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 433system.cpu.dcache.replacements 158487 # number of replacements 434system.cpu.dcache.tagsinuse 4072.438439 # Cycle average of tags in use 435system.cpu.dcache.total_refs 44565712 # Total number of references to valid blocks. 436system.cpu.dcache.sampled_refs 162583 # Sample count of references to valid blocks. 437system.cpu.dcache.avg_refs 274.110528 # Average number of references to valid blocks. 438system.cpu.dcache.warmup_cycle 253512000 # Cycle when the warmup percentage was hit. 439system.cpu.dcache.occ_blocks::cpu.data 4072.438439 # Average occupied blocks per requestor 440system.cpu.dcache.occ_percent::cpu.data 0.994248 # Average percentage of cache occupancy 441system.cpu.dcache.occ_percent::total 0.994248 # Average percentage of cache occupancy 442system.cpu.dcache.ReadReq_hits::cpu.data 26240884 # number of ReadReq hits 443system.cpu.dcache.ReadReq_hits::total 26240884 # number of ReadReq hits 444system.cpu.dcache.WriteReq_hits::cpu.data 18285018 # number of WriteReq hits 445system.cpu.dcache.WriteReq_hits::total 18285018 # number of WriteReq hits 446system.cpu.dcache.LoadLockedReq_hits::cpu.data 20455 # number of LoadLockedReq hits 447system.cpu.dcache.LoadLockedReq_hits::total 20455 # number of LoadLockedReq hits 448system.cpu.dcache.StoreCondReq_hits::cpu.data 19255 # number of StoreCondReq hits 449system.cpu.dcache.StoreCondReq_hits::total 19255 # number of StoreCondReq hits 450system.cpu.dcache.demand_hits::cpu.data 44525902 # number of demand (read+write) hits 451system.cpu.dcache.demand_hits::total 44525902 # number of demand (read+write) hits 452system.cpu.dcache.overall_hits::cpu.data 44525902 # number of overall hits 453system.cpu.dcache.overall_hits::total 44525902 # number of overall hits 454system.cpu.dcache.ReadReq_misses::cpu.data 105303 # number of ReadReq misses 455system.cpu.dcache.ReadReq_misses::total 105303 # number of ReadReq misses 456system.cpu.dcache.WriteReq_misses::cpu.data 1564883 # number of WriteReq misses 457system.cpu.dcache.WriteReq_misses::total 1564883 # number of WriteReq misses 458system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses 459system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses 460system.cpu.dcache.demand_misses::cpu.data 1670186 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 1670186 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 1670186 # number of overall misses 463system.cpu.dcache.overall_misses::total 1670186 # number of overall misses 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 2142178000 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 2142178000 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 54165146000 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 54165146000 # number of WriteReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358500 # number of LoadLockedReq miss cycles 469system.cpu.dcache.LoadLockedReq_miss_latency::total 358500 # number of LoadLockedReq miss cycles 470system.cpu.dcache.demand_miss_latency::cpu.data 56307324000 # number of demand (read+write) miss cycles 471system.cpu.dcache.demand_miss_latency::total 56307324000 # number of demand (read+write) miss cycles 472system.cpu.dcache.overall_miss_latency::cpu.data 56307324000 # number of overall miss cycles 473system.cpu.dcache.overall_miss_latency::total 56307324000 # number of overall miss cycles 474system.cpu.dcache.ReadReq_accesses::cpu.data 26346187 # number of ReadReq accesses(hits+misses) 475system.cpu.dcache.ReadReq_accesses::total 26346187 # number of ReadReq accesses(hits+misses) | 591system.cpu.dcache.replacements 158443 # number of replacements 592system.cpu.dcache.tagsinuse 4074.275674 # Cycle average of tags in use 593system.cpu.dcache.total_refs 44571484 # Total number of references to valid blocks. 594system.cpu.dcache.sampled_refs 162539 # Sample count of references to valid blocks. 595system.cpu.dcache.avg_refs 274.220243 # Average number of references to valid blocks. 596system.cpu.dcache.warmup_cycle 222430000 # Cycle when the warmup percentage was hit. 597system.cpu.dcache.occ_blocks::cpu.data 4074.275674 # Average occupied blocks per requestor 598system.cpu.dcache.occ_percent::cpu.data 0.994696 # Average percentage of cache occupancy 599system.cpu.dcache.occ_percent::total 0.994696 # Average percentage of cache occupancy 600system.cpu.dcache.ReadReq_hits::cpu.data 26246493 # number of ReadReq hits 601system.cpu.dcache.ReadReq_hits::total 26246493 # number of ReadReq hits 602system.cpu.dcache.WriteReq_hits::cpu.data 18285066 # number of WriteReq hits 603system.cpu.dcache.WriteReq_hits::total 18285066 # number of WriteReq hits 604system.cpu.dcache.LoadLockedReq_hits::cpu.data 20587 # number of LoadLockedReq hits 605system.cpu.dcache.LoadLockedReq_hits::total 20587 # number of LoadLockedReq hits 606system.cpu.dcache.StoreCondReq_hits::cpu.data 19288 # number of StoreCondReq hits 607system.cpu.dcache.StoreCondReq_hits::total 19288 # number of StoreCondReq hits 608system.cpu.dcache.demand_hits::cpu.data 44531559 # number of demand (read+write) hits 609system.cpu.dcache.demand_hits::total 44531559 # number of demand (read+write) hits 610system.cpu.dcache.overall_hits::cpu.data 44531559 # number of overall hits 611system.cpu.dcache.overall_hits::total 44531559 # number of overall hits 612system.cpu.dcache.ReadReq_misses::cpu.data 105048 # number of ReadReq misses 613system.cpu.dcache.ReadReq_misses::total 105048 # number of ReadReq misses 614system.cpu.dcache.WriteReq_misses::cpu.data 1564835 # number of WriteReq misses 615system.cpu.dcache.WriteReq_misses::total 1564835 # number of WriteReq misses 616system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses 617system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses 618system.cpu.dcache.demand_misses::cpu.data 1669883 # number of demand (read+write) misses 619system.cpu.dcache.demand_misses::total 1669883 # number of demand (read+write) misses 620system.cpu.dcache.overall_misses::cpu.data 1669883 # number of overall misses 621system.cpu.dcache.overall_misses::total 1669883 # number of overall misses 622system.cpu.dcache.ReadReq_miss_latency::cpu.data 2599655000 # number of ReadReq miss cycles 623system.cpu.dcache.ReadReq_miss_latency::total 2599655000 # number of ReadReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::cpu.data 60196218000 # number of WriteReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::total 60196218000 # number of WriteReq miss cycles 626system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 448500 # number of LoadLockedReq miss cycles 627system.cpu.dcache.LoadLockedReq_miss_latency::total 448500 # number of LoadLockedReq miss cycles 628system.cpu.dcache.demand_miss_latency::cpu.data 62795873000 # number of demand (read+write) miss cycles 629system.cpu.dcache.demand_miss_latency::total 62795873000 # number of demand (read+write) miss cycles 630system.cpu.dcache.overall_miss_latency::cpu.data 62795873000 # number of overall miss cycles 631system.cpu.dcache.overall_miss_latency::total 62795873000 # number of overall miss cycles 632system.cpu.dcache.ReadReq_accesses::cpu.data 26351541 # number of ReadReq accesses(hits+misses) 633system.cpu.dcache.ReadReq_accesses::total 26351541 # number of ReadReq accesses(hits+misses) |
| 476system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 477system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) | 634system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 635system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| 478system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20497 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.LoadLockedReq_accesses::total 20497 # number of LoadLockedReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::cpu.data 19255 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.StoreCondReq_accesses::total 19255 # number of StoreCondReq accesses(hits+misses) 482system.cpu.dcache.demand_accesses::cpu.data 46196088 # number of demand (read+write) accesses 483system.cpu.dcache.demand_accesses::total 46196088 # number of demand (read+write) accesses 484system.cpu.dcache.overall_accesses::cpu.data 46196088 # number of overall (read+write) accesses 485system.cpu.dcache.overall_accesses::total 46196088 # number of overall (read+write) accesses 486system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003997 # miss rate for ReadReq accesses 487system.cpu.dcache.ReadReq_miss_rate::total 0.003997 # miss rate for ReadReq accesses 488system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078836 # miss rate for WriteReq accesses 489system.cpu.dcache.WriteReq_miss_rate::total 0.078836 # miss rate for WriteReq accesses 490system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002049 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002049 # miss rate for LoadLockedReq accesses 492system.cpu.dcache.demand_miss_rate::cpu.data 0.036154 # miss rate for demand accesses 493system.cpu.dcache.demand_miss_rate::total 0.036154 # miss rate for demand accesses 494system.cpu.dcache.overall_miss_rate::cpu.data 0.036154 # miss rate for overall accesses 495system.cpu.dcache.overall_miss_rate::total 0.036154 # miss rate for overall accesses 496system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20342.991178 # average ReadReq miss latency 497system.cpu.dcache.ReadReq_avg_miss_latency::total 20342.991178 # average ReadReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34612.904607 # average WriteReq miss latency 499system.cpu.dcache.WriteReq_avg_miss_latency::total 34612.904607 # average WriteReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8535.714286 # average LoadLockedReq miss latency 501system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8535.714286 # average LoadLockedReq miss latency 502system.cpu.dcache.demand_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency 503system.cpu.dcache.demand_avg_miss_latency::total 33713.205595 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::total 33713.205595 # average overall miss latency | 636system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20624 # number of LoadLockedReq accesses(hits+misses) 637system.cpu.dcache.LoadLockedReq_accesses::total 20624 # number of LoadLockedReq accesses(hits+misses) 638system.cpu.dcache.StoreCondReq_accesses::cpu.data 19288 # number of StoreCondReq accesses(hits+misses) 639system.cpu.dcache.StoreCondReq_accesses::total 19288 # number of StoreCondReq accesses(hits+misses) 640system.cpu.dcache.demand_accesses::cpu.data 46201442 # number of demand (read+write) accesses 641system.cpu.dcache.demand_accesses::total 46201442 # number of demand (read+write) accesses 642system.cpu.dcache.overall_accesses::cpu.data 46201442 # number of overall (read+write) accesses 643system.cpu.dcache.overall_accesses::total 46201442 # number of overall (read+write) accesses 644system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003986 # miss rate for ReadReq accesses 645system.cpu.dcache.ReadReq_miss_rate::total 0.003986 # miss rate for ReadReq accesses 646system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078833 # miss rate for WriteReq accesses 647system.cpu.dcache.WriteReq_miss_rate::total 0.078833 # miss rate for WriteReq accesses 648system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001794 # miss rate for LoadLockedReq accesses 649system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001794 # miss rate for LoadLockedReq accesses 650system.cpu.dcache.demand_miss_rate::cpu.data 0.036144 # miss rate for demand accesses 651system.cpu.dcache.demand_miss_rate::total 0.036144 # miss rate for demand accesses 652system.cpu.dcache.overall_miss_rate::cpu.data 0.036144 # miss rate for overall accesses 653system.cpu.dcache.overall_miss_rate::total 0.036144 # miss rate for overall accesses 654system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24747.305993 # average ReadReq miss latency 655system.cpu.dcache.ReadReq_avg_miss_latency::total 24747.305993 # average ReadReq miss latency 656system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38468.092802 # average WriteReq miss latency 657system.cpu.dcache.WriteReq_avg_miss_latency::total 38468.092802 # average WriteReq miss latency 658system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12121.621622 # average LoadLockedReq miss latency 659system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12121.621622 # average LoadLockedReq miss latency 660system.cpu.dcache.demand_avg_miss_latency::cpu.data 37604.953760 # average overall miss latency 661system.cpu.dcache.demand_avg_miss_latency::total 37604.953760 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::cpu.data 37604.953760 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::total 37604.953760 # average overall miss latency |
| 506system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 664system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 507system.cpu.dcache.blocked_cycles::no_targets 394 # number of cycles access was blocked | 665system.cpu.dcache.blocked_cycles::no_targets 149 # number of cycles access was blocked |
| 508system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked | 666system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 509system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked | 667system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked |
| 510system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 668system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 511system.cpu.dcache.avg_blocked_cycles::no_targets 39.400000 # average number of cycles each access was blocked | 669system.cpu.dcache.avg_blocked_cycles::no_targets 16.555556 # average number of cycles each access was blocked |
| 512system.cpu.dcache.fast_writes 0 # number of fast writes performed 513system.cpu.dcache.cache_copies 0 # number of cache copies performed | 670system.cpu.dcache.fast_writes 0 # number of fast writes performed 671system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 514system.cpu.dcache.writebacks::writebacks 128103 # number of writebacks 515system.cpu.dcache.writebacks::total 128103 # number of writebacks 516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49707 # number of ReadReq MSHR hits 517system.cpu.dcache.ReadReq_mshr_hits::total 49707 # number of ReadReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457877 # number of WriteReq MSHR hits 519system.cpu.dcache.WriteReq_mshr_hits::total 1457877 # number of WriteReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits 521system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits 522system.cpu.dcache.demand_mshr_hits::cpu.data 1507584 # number of demand (read+write) MSHR hits 523system.cpu.dcache.demand_mshr_hits::total 1507584 # number of demand (read+write) MSHR hits 524system.cpu.dcache.overall_mshr_hits::cpu.data 1507584 # number of overall MSHR hits 525system.cpu.dcache.overall_mshr_hits::total 1507584 # number of overall MSHR hits 526system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55596 # number of ReadReq MSHR misses 527system.cpu.dcache.ReadReq_mshr_misses::total 55596 # number of ReadReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107006 # number of WriteReq MSHR misses 529system.cpu.dcache.WriteReq_mshr_misses::total 107006 # number of WriteReq MSHR misses 530system.cpu.dcache.demand_mshr_misses::cpu.data 162602 # number of demand (read+write) MSHR misses 531system.cpu.dcache.demand_mshr_misses::total 162602 # number of demand (read+write) MSHR misses 532system.cpu.dcache.overall_mshr_misses::cpu.data 162602 # number of overall MSHR misses 533system.cpu.dcache.overall_mshr_misses::total 162602 # number of overall MSHR misses 534system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 945497500 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.ReadReq_mshr_miss_latency::total 945497500 # number of ReadReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3824998000 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.WriteReq_mshr_miss_latency::total 3824998000 # number of WriteReq MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4770495500 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.demand_mshr_miss_latency::total 4770495500 # number of demand (read+write) MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4770495500 # number of overall MSHR miss cycles 541system.cpu.dcache.overall_mshr_miss_latency::total 4770495500 # number of overall MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002110 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002110 # mshr miss rate for ReadReq accesses | 672system.cpu.dcache.writebacks::writebacks 128088 # number of writebacks 673system.cpu.dcache.writebacks::total 128088 # number of writebacks 674system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49495 # number of ReadReq MSHR hits 675system.cpu.dcache.ReadReq_mshr_hits::total 49495 # number of ReadReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457827 # number of WriteReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::total 1457827 # number of WriteReq MSHR hits 678system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits 679system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits 680system.cpu.dcache.demand_mshr_hits::cpu.data 1507322 # number of demand (read+write) MSHR hits 681system.cpu.dcache.demand_mshr_hits::total 1507322 # number of demand (read+write) MSHR hits 682system.cpu.dcache.overall_mshr_hits::cpu.data 1507322 # number of overall MSHR hits 683system.cpu.dcache.overall_mshr_hits::total 1507322 # number of overall MSHR hits 684system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55553 # number of ReadReq MSHR misses 685system.cpu.dcache.ReadReq_mshr_misses::total 55553 # number of ReadReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107008 # number of WriteReq MSHR misses 687system.cpu.dcache.WriteReq_mshr_misses::total 107008 # number of WriteReq MSHR misses 688system.cpu.dcache.demand_mshr_misses::cpu.data 162561 # number of demand (read+write) MSHR misses 689system.cpu.dcache.demand_mshr_misses::total 162561 # number of demand (read+write) MSHR misses 690system.cpu.dcache.overall_mshr_misses::cpu.data 162561 # number of overall MSHR misses 691system.cpu.dcache.overall_mshr_misses::total 162561 # number of overall MSHR misses 692system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141045500 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.ReadReq_mshr_miss_latency::total 1141045500 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4220015000 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::total 4220015000 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5361060500 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::total 5361060500 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5361060500 # number of overall MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::total 5361060500 # number of overall MSHR miss cycles 700system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002108 # mshr miss rate for ReadReq accesses 701system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002108 # mshr miss rate for ReadReq accesses |
| 544system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005391 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005391 # mshr miss rate for WriteReq accesses | 702system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005391 # mshr miss rate for WriteReq accesses 703system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005391 # mshr miss rate for WriteReq accesses |
| 546system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for demand accesses 547system.cpu.dcache.demand_mshr_miss_rate::total 0.003520 # mshr miss rate for demand accesses 548system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for overall accesses 549system.cpu.dcache.overall_mshr_miss_rate::total 0.003520 # mshr miss rate for overall accesses 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.574214 # average ReadReq mshr miss latency 551system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.574214 # average ReadReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35745.640431 # average WriteReq mshr miss latency 553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35745.640431 # average WriteReq mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29338.479846 # average overall mshr miss latency 555system.cpu.dcache.demand_avg_mshr_miss_latency::total 29338.479846 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29338.479846 # average overall mshr miss latency 557system.cpu.dcache.overall_avg_mshr_miss_latency::total 29338.479846 # average overall mshr miss latency | 704system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003519 # mshr miss rate for demand accesses 705system.cpu.dcache.demand_mshr_miss_rate::total 0.003519 # mshr miss rate for demand accesses 706system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003519 # mshr miss rate for overall accesses 707system.cpu.dcache.overall_mshr_miss_rate::total 0.003519 # mshr miss rate for overall accesses 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20539.763829 # average ReadReq mshr miss latency 709system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20539.763829 # average ReadReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39436.444004 # average WriteReq mshr miss latency 711system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39436.444004 # average WriteReq mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32978.761819 # average overall mshr miss latency 713system.cpu.dcache.demand_avg_mshr_miss_latency::total 32978.761819 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32978.761819 # average overall mshr miss latency 715system.cpu.dcache.overall_avg_mshr_miss_latency::total 32978.761819 # average overall mshr miss latency |
| 558system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 716system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 559system.cpu.l2cache.replacements 97972 # number of replacements 560system.cpu.l2cache.tagsinuse 28672.320506 # Cycle average of tags in use 561system.cpu.l2cache.total_refs 85492 # Total number of references to valid blocks. 562system.cpu.l2cache.sampled_refs 128764 # Sample count of references to valid blocks. 563system.cpu.l2cache.avg_refs 0.663943 # Average number of references to valid blocks. | 717system.cpu.l2cache.replacements 97971 # number of replacements 718system.cpu.l2cache.tagsinuse 28800.701977 # Cycle average of tags in use 719system.cpu.l2cache.total_refs 86327 # Total number of references to valid blocks. 720system.cpu.l2cache.sampled_refs 128762 # Sample count of references to valid blocks. 721system.cpu.l2cache.avg_refs 0.670438 # Average number of references to valid blocks. |
| 564system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 722system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 565system.cpu.l2cache.occ_blocks::writebacks 25877.470214 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.inst 1151.216152 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_blocks::cpu.data 1643.634140 # Average occupied blocks per requestor 568system.cpu.l2cache.occ_percent::writebacks 0.789718 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.inst 0.035132 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::cpu.data 0.050160 # Average percentage of cache occupancy 571system.cpu.l2cache.occ_percent::total 0.875010 # Average percentage of cache occupancy 572system.cpu.l2cache.ReadReq_hits::cpu.inst 25596 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::cpu.data 32355 # number of ReadReq hits 574system.cpu.l2cache.ReadReq_hits::total 57951 # number of ReadReq hits 575system.cpu.l2cache.Writeback_hits::writebacks 128103 # number of Writeback hits 576system.cpu.l2cache.Writeback_hits::total 128103 # number of Writeback hits | 723system.cpu.l2cache.occ_blocks::writebacks 25974.611226 # Average occupied blocks per requestor 724system.cpu.l2cache.occ_blocks::cpu.inst 1154.606563 # Average occupied blocks per requestor 725system.cpu.l2cache.occ_blocks::cpu.data 1671.484188 # Average occupied blocks per requestor 726system.cpu.l2cache.occ_percent::writebacks 0.792682 # Average percentage of cache occupancy 727system.cpu.l2cache.occ_percent::cpu.inst 0.035236 # Average percentage of cache occupancy 728system.cpu.l2cache.occ_percent::cpu.data 0.051010 # Average percentage of cache occupancy 729system.cpu.l2cache.occ_percent::total 0.878928 # Average percentage of cache occupancy 730system.cpu.l2cache.ReadReq_hits::cpu.inst 26463 # number of ReadReq hits 731system.cpu.l2cache.ReadReq_hits::cpu.data 32338 # number of ReadReq hits 732system.cpu.l2cache.ReadReq_hits::total 58801 # number of ReadReq hits 733system.cpu.l2cache.Writeback_hits::writebacks 128088 # number of Writeback hits 734system.cpu.l2cache.Writeback_hits::total 128088 # number of Writeback hits |
| 577system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 578system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits | 735system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 736system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits |
| 579system.cpu.l2cache.ReadExReq_hits::cpu.data 4711 # number of ReadExReq hits 580system.cpu.l2cache.ReadExReq_hits::total 4711 # number of ReadExReq hits 581system.cpu.l2cache.demand_hits::cpu.inst 25596 # number of demand (read+write) hits 582system.cpu.l2cache.demand_hits::cpu.data 37066 # number of demand (read+write) hits 583system.cpu.l2cache.demand_hits::total 62662 # number of demand (read+write) hits 584system.cpu.l2cache.overall_hits::cpu.inst 25596 # number of overall hits 585system.cpu.l2cache.overall_hits::cpu.data 37066 # number of overall hits 586system.cpu.l2cache.overall_hits::total 62662 # number of overall hits 587system.cpu.l2cache.ReadReq_misses::cpu.inst 5128 # number of ReadReq misses 588system.cpu.l2cache.ReadReq_misses::cpu.data 23202 # number of ReadReq misses 589system.cpu.l2cache.ReadReq_misses::total 28330 # number of ReadReq misses 590system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses 591system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses 592system.cpu.l2cache.ReadExReq_misses::cpu.data 102315 # number of ReadExReq misses 593system.cpu.l2cache.ReadExReq_misses::total 102315 # number of ReadExReq misses 594system.cpu.l2cache.demand_misses::cpu.inst 5128 # number of demand (read+write) misses 595system.cpu.l2cache.demand_misses::cpu.data 125517 # number of demand (read+write) misses 596system.cpu.l2cache.demand_misses::total 130645 # number of demand (read+write) misses 597system.cpu.l2cache.overall_misses::cpu.inst 5128 # number of overall misses 598system.cpu.l2cache.overall_misses::cpu.data 125517 # number of overall misses 599system.cpu.l2cache.overall_misses::total 130645 # number of overall misses 600system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181262500 # number of ReadReq miss cycles 601system.cpu.l2cache.ReadReq_miss_latency::cpu.data 852393000 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadReq_miss_latency::total 1033655500 # number of ReadReq miss cycles 603system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3712515000 # number of ReadExReq miss cycles 604system.cpu.l2cache.ReadExReq_miss_latency::total 3712515000 # number of ReadExReq miss cycles 605system.cpu.l2cache.demand_miss_latency::cpu.inst 181262500 # number of demand (read+write) miss cycles 606system.cpu.l2cache.demand_miss_latency::cpu.data 4564908000 # number of demand (read+write) miss cycles 607system.cpu.l2cache.demand_miss_latency::total 4746170500 # number of demand (read+write) miss cycles 608system.cpu.l2cache.overall_miss_latency::cpu.inst 181262500 # number of overall miss cycles 609system.cpu.l2cache.overall_miss_latency::cpu.data 4564908000 # number of overall miss cycles 610system.cpu.l2cache.overall_miss_latency::total 4746170500 # number of overall miss cycles 611system.cpu.l2cache.ReadReq_accesses::cpu.inst 30724 # number of ReadReq accesses(hits+misses) 612system.cpu.l2cache.ReadReq_accesses::cpu.data 55557 # number of ReadReq accesses(hits+misses) 613system.cpu.l2cache.ReadReq_accesses::total 86281 # number of ReadReq accesses(hits+misses) 614system.cpu.l2cache.Writeback_accesses::writebacks 128103 # number of Writeback accesses(hits+misses) 615system.cpu.l2cache.Writeback_accesses::total 128103 # number of Writeback accesses(hits+misses) 616system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses) 617system.cpu.l2cache.UpgradeReq_accesses::total 19 # number of UpgradeReq accesses(hits+misses) 618system.cpu.l2cache.ReadExReq_accesses::cpu.data 107026 # number of ReadExReq accesses(hits+misses) 619system.cpu.l2cache.ReadExReq_accesses::total 107026 # number of ReadExReq accesses(hits+misses) 620system.cpu.l2cache.demand_accesses::cpu.inst 30724 # number of demand (read+write) accesses 621system.cpu.l2cache.demand_accesses::cpu.data 162583 # number of demand (read+write) accesses 622system.cpu.l2cache.demand_accesses::total 193307 # number of demand (read+write) accesses 623system.cpu.l2cache.overall_accesses::cpu.inst 30724 # number of overall (read+write) accesses 624system.cpu.l2cache.overall_accesses::cpu.data 162583 # number of overall (read+write) accesses 625system.cpu.l2cache.overall_accesses::total 193307 # number of overall (read+write) accesses 626system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.166905 # miss rate for ReadReq accesses 627system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.417625 # miss rate for ReadReq accesses 628system.cpu.l2cache.ReadReq_miss_rate::total 0.328346 # miss rate for ReadReq accesses 629system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses 630system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses 631system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955983 # miss rate for ReadExReq accesses 632system.cpu.l2cache.ReadExReq_miss_rate::total 0.955983 # miss rate for ReadExReq accesses 633system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166905 # miss rate for demand accesses 634system.cpu.l2cache.demand_miss_rate::cpu.data 0.772018 # miss rate for demand accesses 635system.cpu.l2cache.demand_miss_rate::total 0.675842 # miss rate for demand accesses 636system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166905 # miss rate for overall accesses 637system.cpu.l2cache.overall_miss_rate::cpu.data 0.772018 # miss rate for overall accesses 638system.cpu.l2cache.overall_miss_rate::total 0.675842 # miss rate for overall accesses 639system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35347.601404 # average ReadReq miss latency 640system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36737.910525 # average ReadReq miss latency 641system.cpu.l2cache.ReadReq_avg_miss_latency::total 36486.251324 # average ReadReq miss latency 642system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36285.148805 # average ReadExReq miss latency 643system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36285.148805 # average ReadExReq miss latency 644system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35347.601404 # average overall miss latency 645system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36368.842468 # average overall miss latency 646system.cpu.l2cache.demand_avg_miss_latency::total 36328.757319 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35347.601404 # average overall miss latency 648system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36368.842468 # average overall miss latency 649system.cpu.l2cache.overall_avg_miss_latency::total 36328.757319 # average overall miss latency | 737system.cpu.l2cache.ReadExReq_hits::cpu.data 4704 # number of ReadExReq hits 738system.cpu.l2cache.ReadExReq_hits::total 4704 # number of ReadExReq hits 739system.cpu.l2cache.demand_hits::cpu.inst 26463 # number of demand (read+write) hits 740system.cpu.l2cache.demand_hits::cpu.data 37042 # number of demand (read+write) hits 741system.cpu.l2cache.demand_hits::total 63505 # number of demand (read+write) hits 742system.cpu.l2cache.overall_hits::cpu.inst 26463 # number of overall hits 743system.cpu.l2cache.overall_hits::cpu.data 37042 # number of overall hits 744system.cpu.l2cache.overall_hits::total 63505 # number of overall hits 745system.cpu.l2cache.ReadReq_misses::cpu.inst 5130 # number of ReadReq misses 746system.cpu.l2cache.ReadReq_misses::cpu.data 23181 # number of ReadReq misses 747system.cpu.l2cache.ReadReq_misses::total 28311 # number of ReadReq misses 748system.cpu.l2cache.UpgradeReq_misses::cpu.data 21 # number of UpgradeReq misses 749system.cpu.l2cache.UpgradeReq_misses::total 21 # number of UpgradeReq misses 750system.cpu.l2cache.ReadExReq_misses::cpu.data 102316 # number of ReadExReq misses 751system.cpu.l2cache.ReadExReq_misses::total 102316 # number of ReadExReq misses 752system.cpu.l2cache.demand_misses::cpu.inst 5130 # number of demand (read+write) misses 753system.cpu.l2cache.demand_misses::cpu.data 125497 # number of demand (read+write) misses 754system.cpu.l2cache.demand_misses::total 130627 # number of demand (read+write) misses 755system.cpu.l2cache.overall_misses::cpu.inst 5130 # number of overall misses 756system.cpu.l2cache.overall_misses::cpu.data 125497 # number of overall misses 757system.cpu.l2cache.overall_misses::total 130627 # number of overall misses 758system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 206891000 # number of ReadReq miss cycles 759system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1047770000 # number of ReadReq miss cycles 760system.cpu.l2cache.ReadReq_miss_latency::total 1254661000 # number of ReadReq miss cycles 761system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108116000 # number of ReadExReq miss cycles 762system.cpu.l2cache.ReadExReq_miss_latency::total 4108116000 # number of ReadExReq miss cycles 763system.cpu.l2cache.demand_miss_latency::cpu.inst 206891000 # number of demand (read+write) miss cycles 764system.cpu.l2cache.demand_miss_latency::cpu.data 5155886000 # number of demand (read+write) miss cycles 765system.cpu.l2cache.demand_miss_latency::total 5362777000 # number of demand (read+write) miss cycles 766system.cpu.l2cache.overall_miss_latency::cpu.inst 206891000 # number of overall miss cycles 767system.cpu.l2cache.overall_miss_latency::cpu.data 5155886000 # number of overall miss cycles 768system.cpu.l2cache.overall_miss_latency::total 5362777000 # number of overall miss cycles 769system.cpu.l2cache.ReadReq_accesses::cpu.inst 31593 # number of ReadReq accesses(hits+misses) 770system.cpu.l2cache.ReadReq_accesses::cpu.data 55519 # number of ReadReq accesses(hits+misses) 771system.cpu.l2cache.ReadReq_accesses::total 87112 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.Writeback_accesses::writebacks 128088 # number of Writeback accesses(hits+misses) 773system.cpu.l2cache.Writeback_accesses::total 128088 # number of Writeback accesses(hits+misses) 774system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) 775system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) 776system.cpu.l2cache.ReadExReq_accesses::cpu.data 107020 # number of ReadExReq accesses(hits+misses) 777system.cpu.l2cache.ReadExReq_accesses::total 107020 # number of ReadExReq accesses(hits+misses) 778system.cpu.l2cache.demand_accesses::cpu.inst 31593 # number of demand (read+write) accesses 779system.cpu.l2cache.demand_accesses::cpu.data 162539 # number of demand (read+write) accesses 780system.cpu.l2cache.demand_accesses::total 194132 # number of demand (read+write) accesses 781system.cpu.l2cache.overall_accesses::cpu.inst 31593 # number of overall (read+write) accesses 782system.cpu.l2cache.overall_accesses::cpu.data 162539 # number of overall (read+write) accesses 783system.cpu.l2cache.overall_accesses::total 194132 # number of overall (read+write) accesses 784system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.162378 # miss rate for ReadReq accesses 785system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.417533 # miss rate for ReadReq accesses 786system.cpu.l2cache.ReadReq_miss_rate::total 0.324995 # miss rate for ReadReq accesses 787system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.954545 # miss rate for UpgradeReq accesses 788system.cpu.l2cache.UpgradeReq_miss_rate::total 0.954545 # miss rate for UpgradeReq accesses 789system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.956046 # miss rate for ReadExReq accesses 790system.cpu.l2cache.ReadExReq_miss_rate::total 0.956046 # miss rate for ReadExReq accesses 791system.cpu.l2cache.demand_miss_rate::cpu.inst 0.162378 # miss rate for demand accesses 792system.cpu.l2cache.demand_miss_rate::cpu.data 0.772104 # miss rate for demand accesses 793system.cpu.l2cache.demand_miss_rate::total 0.672877 # miss rate for demand accesses 794system.cpu.l2cache.overall_miss_rate::cpu.inst 0.162378 # miss rate for overall accesses 795system.cpu.l2cache.overall_miss_rate::cpu.data 0.772104 # miss rate for overall accesses 796system.cpu.l2cache.overall_miss_rate::total 0.672877 # miss rate for overall accesses 797system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 40329.629630 # average ReadReq miss latency 798system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45199.516846 # average ReadReq miss latency 799system.cpu.l2cache.ReadReq_avg_miss_latency::total 44317.085232 # average ReadReq miss latency 800system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 40151.256890 # average ReadExReq miss latency 801system.cpu.l2cache.ReadExReq_avg_miss_latency::total 40151.256890 # average ReadExReq miss latency 802system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 40329.629630 # average overall miss latency 803system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41083.739054 # average overall miss latency 804system.cpu.l2cache.demand_avg_miss_latency::total 41054.123573 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 40329.629630 # average overall miss latency 806system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41083.739054 # average overall miss latency 807system.cpu.l2cache.overall_avg_miss_latency::total 41054.123573 # average overall miss latency |
| 650system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.l2cache.fast_writes 0 # number of fast writes performed 657system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 808system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 811system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 812system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 813system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 814system.cpu.l2cache.fast_writes 0 # number of fast writes performed 815system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 658system.cpu.l2cache.writebacks::writebacks 84652 # number of writebacks 659system.cpu.l2cache.writebacks::total 84652 # number of writebacks 660system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 36 # number of ReadReq MSHR hits 661system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits 662system.cpu.l2cache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits 663system.cpu.l2cache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits 664system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits 665system.cpu.l2cache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits 666system.cpu.l2cache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits 667system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits 668system.cpu.l2cache.overall_mshr_hits::total 100 # number of overall MSHR hits 669system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5092 # number of ReadReq MSHR misses 670system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23138 # number of ReadReq MSHR misses 671system.cpu.l2cache.ReadReq_mshr_misses::total 28230 # number of ReadReq MSHR misses 672system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses 673system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses 674system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102315 # number of ReadExReq MSHR misses 675system.cpu.l2cache.ReadExReq_mshr_misses::total 102315 # number of ReadExReq MSHR misses 676system.cpu.l2cache.demand_mshr_misses::cpu.inst 5092 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.demand_mshr_misses::cpu.data 125453 # number of demand (read+write) MSHR misses 678system.cpu.l2cache.demand_mshr_misses::total 130545 # number of demand (read+write) MSHR misses 679system.cpu.l2cache.overall_mshr_misses::cpu.inst 5092 # number of overall MSHR misses 680system.cpu.l2cache.overall_mshr_misses::cpu.data 125453 # number of overall MSHR misses 681system.cpu.l2cache.overall_mshr_misses::total 130545 # number of overall MSHR misses 682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164482000 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 778171500 # number of ReadReq MSHR miss cycles 684system.cpu.l2cache.ReadReq_mshr_miss_latency::total 942653500 # number of ReadReq MSHR miss cycles 685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 567000 # number of UpgradeReq MSHR miss cycles 686system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 567000 # number of UpgradeReq MSHR miss cycles 687system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3395437000 # number of ReadExReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3395437000 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164482000 # number of demand (read+write) MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4173608500 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::total 4338090500 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164482000 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4173608500 # number of overall MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::total 4338090500 # number of overall MSHR miss cycles 695system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416473 # mshr miss rate for ReadReq accesses 697system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.327187 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses 699system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses 700system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955983 # mshr miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955983 # mshr miss rate for ReadExReq accesses 702system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for demand accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771624 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::total 0.675325 # mshr miss rate for demand accesses 705system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for overall accesses 706system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771624 # mshr miss rate for overall accesses 707system.cpu.l2cache.overall_mshr_miss_rate::total 0.675325 # mshr miss rate for overall accesses 708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32302.042419 # average ReadReq mshr miss latency 709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33631.752960 # average ReadReq mshr miss latency 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33391.905774 # average ReadReq mshr miss latency 711system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31500 # average UpgradeReq mshr miss latency 712system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31500 # average UpgradeReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33186.111518 # average ReadExReq mshr miss latency 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33186.111518 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32302.042419 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33268.303668 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33230.613965 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32302.042419 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33268.303668 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33230.613965 # average overall mshr miss latency | 816system.cpu.l2cache.writebacks::writebacks 84647 # number of writebacks 817system.cpu.l2cache.writebacks::total 84647 # number of writebacks 818system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits 819system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits 820system.cpu.l2cache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 821system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits 822system.cpu.l2cache.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits 823system.cpu.l2cache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits 824system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits 825system.cpu.l2cache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits 826system.cpu.l2cache.overall_mshr_hits::total 83 # number of overall MSHR hits 827system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5106 # number of ReadReq MSHR misses 828system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23122 # number of ReadReq MSHR misses 829system.cpu.l2cache.ReadReq_mshr_misses::total 28228 # number of ReadReq MSHR misses 830system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 21 # number of UpgradeReq MSHR misses 831system.cpu.l2cache.UpgradeReq_mshr_misses::total 21 # number of UpgradeReq MSHR misses 832system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102316 # number of ReadExReq MSHR misses 833system.cpu.l2cache.ReadExReq_mshr_misses::total 102316 # number of ReadExReq MSHR misses 834system.cpu.l2cache.demand_mshr_misses::cpu.inst 5106 # number of demand (read+write) MSHR misses 835system.cpu.l2cache.demand_mshr_misses::cpu.data 125438 # number of demand (read+write) MSHR misses 836system.cpu.l2cache.demand_mshr_misses::total 130544 # number of demand (read+write) MSHR misses 837system.cpu.l2cache.overall_mshr_misses::cpu.inst 5106 # number of overall MSHR misses 838system.cpu.l2cache.overall_mshr_misses::cpu.data 125438 # number of overall MSHR misses 839system.cpu.l2cache.overall_mshr_misses::total 130544 # number of overall MSHR misses 840system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187620086 # number of ReadReq MSHR miss cycles 841system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 964824313 # number of ReadReq MSHR miss cycles 842system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1152444399 # number of ReadReq MSHR miss cycles 843system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 21021 # number of UpgradeReq MSHR miss cycles 844system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 21021 # number of UpgradeReq MSHR miss cycles 845system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3752861945 # number of ReadExReq MSHR miss cycles 846system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3752861945 # number of ReadExReq MSHR miss cycles 847system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187620086 # number of demand (read+write) MSHR miss cycles 848system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4717686258 # number of demand (read+write) MSHR miss cycles 849system.cpu.l2cache.demand_mshr_miss_latency::total 4905306344 # number of demand (read+write) MSHR miss cycles 850system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187620086 # number of overall MSHR miss cycles 851system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4717686258 # number of overall MSHR miss cycles 852system.cpu.l2cache.overall_mshr_miss_latency::total 4905306344 # number of overall MSHR miss cycles 853system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.161618 # mshr miss rate for ReadReq accesses 854system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416470 # mshr miss rate for ReadReq accesses 855system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.324043 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.954545 # mshr miss rate for UpgradeReq accesses 857system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.954545 # mshr miss rate for UpgradeReq accesses 858system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956046 # mshr miss rate for ReadExReq accesses 859system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956046 # mshr miss rate for ReadExReq accesses 860system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.161618 # mshr miss rate for demand accesses 861system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771741 # mshr miss rate for demand accesses 862system.cpu.l2cache.demand_mshr_miss_rate::total 0.672450 # mshr miss rate for demand accesses 863system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.161618 # mshr miss rate for overall accesses 864system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771741 # mshr miss rate for overall accesses 865system.cpu.l2cache.overall_mshr_miss_rate::total 0.672450 # mshr miss rate for overall accesses 866system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36745.022718 # average ReadReq mshr miss latency 867system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41727.545757 # average ReadReq mshr miss latency 868system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40826.285922 # average ReadReq mshr miss latency 869system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency 870system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency 871system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36679.130781 # average ReadExReq mshr miss latency 872system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36679.130781 # average ReadExReq mshr miss latency 873system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36745.022718 # average overall mshr miss latency 874system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37609.705655 # average overall mshr miss latency 875system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37575.885096 # average overall mshr miss latency 876system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36745.022718 # average overall mshr miss latency 877system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37609.705655 # average overall mshr miss latency 878system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37575.885096 # average overall mshr miss latency |
| 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 722 723---------- End Simulation Statistics ---------- | 879system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 880 881---------- End Simulation Statistics ---------- |