| stats.txt (9265:8fe936e937bd) | stats.txt (9285:9901180cd573) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.024261 # Number of seconds simulated 4sim_ticks 24260940500 # Number of ticks simulated 5final_tick 24260940500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.023747 # Number of seconds simulated 4sim_ticks 23747395500 # Number of ticks simulated 5final_tick 23747395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 115016 # Simulator instruction rate (inst/s) 8host_op_rate 163211 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39343372 # Simulator tick rate (ticks/s) 10host_mem_usage 237732 # Number of bytes of host memory used 11host_seconds 616.65 # Real time elapsed on the host 12sim_insts 70924159 # Number of instructions simulated 13sim_ops 100643406 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 327680 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 327680 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 327680 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5417600 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5417600 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 5120 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 84650 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 84650 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 13506484 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 330903577 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 344410061 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 13506484 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 13506484 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 223305440 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 223305440 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 223305440 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 13506484 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 330903577 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 567715501 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 107822 # Simulator instruction rate (inst/s) 8host_op_rate 153002 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36101670 # Simulator tick rate (ticks/s) 10host_mem_usage 242616 # Number of bytes of host memory used 11host_seconds 657.79 # Real time elapsed on the host 12sim_insts 70924309 # Number of instructions simulated 13sim_ops 100643556 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 325888 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8028992 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8354880 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 325888 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 325888 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5417728 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5417728 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 5092 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125453 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 130545 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 84652 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 84652 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 13723105 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 338099898 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 351823003 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 13723105 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 13723105 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 228139882 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 228139882 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 228139882 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 13723105 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 338099898 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 579962885 # Total bandwidth to/from this memory (bytes/s) |
| 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 1946 # Number of system calls | 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 80system.cpu.numCycles 48521882 # number of cpu cycles simulated | 80system.cpu.numCycles 47494792 # number of cpu cycles simulated |
| 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 83system.cpu.BPredUnit.lookups 16966170 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 12979168 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 675165 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 11674119 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 7996673 # Number of BTB hits | 83system.cpu.BPredUnit.lookups 16945853 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 12976600 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 671047 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 11791616 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 7980415 # Number of BTB hits |
| 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 89system.cpu.BPredUnit.usedRAS 1849293 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 114426 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 12701255 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 86893403 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 16966170 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 9845966 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 21627617 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 2635386 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 10974011 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 407 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 11950097 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 196542 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 47237958 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.575337 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.329156 # Number of instructions fetched each cycle (Total) | 89system.cpu.BPredUnit.usedRAS 1850372 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 114214 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 12555295 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 86800259 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 16945853 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 9830787 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 21603869 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 2612787 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 10088905 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 11920379 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 192164 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 46165707 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.632126 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.343505 # Number of instructions fetched each cycle (Total) |
| 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 106system.cpu.fetch.rateDist::0 25631712 54.26% 54.26% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 2165185 4.58% 58.84% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 2027432 4.29% 63.14% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 2093511 4.43% 67.57% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 1492717 3.16% 70.73% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 1413949 2.99% 73.72% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 984209 2.08% 75.80% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 1226744 2.60% 78.40% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 10202499 21.60% 100.00% # Number of instructions fetched each cycle (Total) | 106system.cpu.fetch.rateDist::0 24583523 53.25% 53.25% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 2172032 4.70% 57.96% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 2013449 4.36% 62.32% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 2091121 4.53% 66.85% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 1494392 3.24% 70.08% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 1411801 3.06% 73.14% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 982905 2.13% 75.27% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 1224192 2.65% 77.92% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 10192292 22.08% 100.00% # Number of instructions fetched each cycle (Total) |
| 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 118system.cpu.fetch.rateDist::total 47237958 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.349660 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.790809 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 14870883 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 9280138 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 19842641 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 1415670 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 1828626 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 3426061 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 108157 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 118947297 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 370581 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 1828626 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 16604946 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 2957626 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 761420 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 19440844 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 5644496 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 116783060 # Number of instructions processed by rename 137system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full 138system.cpu.rename.IQFullEvents 12596 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 4803591 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 254 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 117118920 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 537771429 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 537766148 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 5281 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 17959800 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 25743 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 25726 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 13145883 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 29944086 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 22669898 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 3682577 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 4376453 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 112886356 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 41706 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 108196580 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 320650 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 12119727 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 28466628 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 4614 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 47237958 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 2.290458 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.991605 # Number of insts issued each cycle | 118system.cpu.fetch.rateDist::total 46165707 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.356794 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.827574 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 14647959 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 8470510 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 19858799 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 1377235 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 1811204 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 3409264 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 108749 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 118806925 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 370081 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 1811204 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 16375618 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 2381141 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 742521 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 19461585 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 5393638 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 116666793 # Number of instructions processed by rename 137system.cpu.rename.ROBFullEvents 61 # Number of times rename has blocked due to ROB full 138system.cpu.rename.IQFullEvents 9401 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 4563999 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 255 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 117035573 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 537232740 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 537225721 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 7019 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 99159360 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 17876213 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 25291 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 25289 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 12820996 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 29922759 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 22636012 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 3511140 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 4209388 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 112770529 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 41465 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 108119060 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 319934 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 12017924 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 28288746 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 4343 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 46165707 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 2.341978 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.993843 # Number of insts issued each cycle |
| 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 165system.cpu.iq.issued_per_cycle::0 11517306 24.38% 24.38% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 8382479 17.75% 42.13% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 7488515 15.85% 57.98% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 7167095 15.17% 73.15% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 5452995 11.54% 84.70% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 3887775 8.23% 92.93% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 1886175 3.99% 96.92% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 877063 1.86% 98.78% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 578555 1.22% 100.00% # Number of insts issued each cycle | 165system.cpu.iq.issued_per_cycle::0 10763393 23.31% 23.31% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 8065577 17.47% 40.79% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 7395154 16.02% 56.80% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 7189034 15.57% 72.38% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 5495666 11.90% 84.28% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 3896907 8.44% 92.72% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 1882413 4.08% 96.80% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 886108 1.92% 98.72% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 591455 1.28% 100.00% # Number of insts issued each cycle |
| 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 177system.cpu.iq.issued_per_cycle::total 47237958 # Number of insts issued each cycle | 177system.cpu.iq.issued_per_cycle::total 46165707 # Number of insts issued each cycle |
| 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 179system.cpu.iq.fu_full::IntAlu 110786 4.40% 4.40% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 1390381 55.25% 59.65% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 1015261 40.35% 100.00% # attempts to use FU when none available | 179system.cpu.iq.fu_full::IntAlu 111137 4.37% 4.37% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 1401194 55.04% 59.40% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 1033519 40.60% 100.00% # attempts to use FU when none available |
| 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 213system.cpu.iq.FU_type_0::IntAlu 57217754 52.88% 52.88% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 91589 0.08% 52.97% # Type of FU issued 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatAdd 191 0.00% 52.97% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.97% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.97% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.97% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.97% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.97% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.97% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.97% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.97% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.97% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.97% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.97% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.97% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.97% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.97% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.97% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.97% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.97% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.97% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued 242system.cpu.iq.FU_type_0::MemRead 29118364 26.91% 79.88% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 21768675 20.12% 100.00% # Type of FU issued | 213system.cpu.iq.FU_type_0::IntAlu 57171551 52.88% 52.88% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 91476 0.08% 52.96% # Type of FU issued 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.96% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatAdd 254 0.00% 52.96% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.96% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.96% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.96% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.96% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.96% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.96% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.96% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.96% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.96% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.96% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.96% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.96% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.96% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.96% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.96% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.96% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.96% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.96% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.96% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.96% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.96% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.96% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.96% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.96% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.96% # Type of FU issued 242system.cpu.iq.FU_type_0::MemRead 29115621 26.93% 79.89% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 21740151 20.11% 100.00% # Type of FU issued |
| 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 246system.cpu.iq.FU_type_0::total 108196580 # Type of FU issued 247system.cpu.iq.rate 2.229851 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 2516428 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.023258 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 266467665 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 125074926 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 106294504 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 531 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 794 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 110712739 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 269 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 2177452 # Number of loads that had data forwarded from stores | 246system.cpu.iq.FU_type_0::total 108119060 # Type of FU issued 247system.cpu.iq.rate 2.276440 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 2545850 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.023547 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 265268953 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 124855497 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 106214423 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 658 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 1042 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 198 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 110664579 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 331 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 2183386 # Number of loads that had data forwarded from stores |
| 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 260system.cpu.iew.lsq.thread0.squashedLoads 2633672 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 7610 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 29131 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 2110854 # Number of stores squashed | 260system.cpu.iew.lsq.thread0.squashedLoads 2612315 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 8134 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 27815 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 2076938 # Number of stores squashed |
| 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 266system.cpu.iew.lsq.thread0.rescheduledLoads 45 # Number of loads that were rescheduled | 266system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled |
| 267system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 267system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 269system.cpu.iew.iewSquashCycles 1828626 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 932107 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 39617 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 112937916 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 341621 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 29944086 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 22669898 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 25185 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 2553 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 3723 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 29131 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 450221 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 202626 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 652847 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 107016957 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 28768203 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 1179623 # Number of squashed instructions skipped in execute | 269system.cpu.iew.iewSquashCycles 1811204 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 969930 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 37593 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 112821828 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 344750 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 29922759 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 22636012 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 24938 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 1077 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 4742 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 27815 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 448633 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 200270 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 648903 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 106941825 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 28766464 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 1177235 # Number of squashed instructions skipped in execute |
| 286system.cpu.iew.exec_swp 0 # number of swp insts executed | 286system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 287system.cpu.iew.exec_nop 9854 # number of nop insts executed 288system.cpu.iew.exec_refs 50224831 # number of memory reference insts executed 289system.cpu.iew.exec_branches 14719282 # Number of branches executed 290system.cpu.iew.exec_stores 21456628 # Number of stores executed 291system.cpu.iew.exec_rate 2.205540 # Inst execution rate 292system.cpu.iew.wb_sent 106535697 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 106294668 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 53446146 # num instructions producing a value 295system.cpu.iew.wb_consumers 103592779 # num instructions consuming a value | 287system.cpu.iew.exec_nop 9834 # number of nop insts executed 288system.cpu.iew.exec_refs 50197967 # number of memory reference insts executed 289system.cpu.iew.exec_branches 14707935 # Number of branches executed 290system.cpu.iew.exec_stores 21431503 # Number of stores executed 291system.cpu.iew.exec_rate 2.251654 # Inst execution rate 292system.cpu.iew.wb_sent 106459563 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 106214621 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 53551409 # num instructions producing a value 295system.cpu.iew.wb_consumers 103987749 # num instructions consuming a value |
| 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 297system.cpu.iew.wb_rate 2.190654 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.515925 # average fanout of values written-back | 297system.cpu.iew.wb_rate 2.236342 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.514978 # average fanout of values written-back |
| 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 300system.cpu.commit.commitSquashedInsts 12289679 # The number of squashed insts skipped by commit 301system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards 302system.cpu.commit.branchMispredicts 569161 # The number of times a branch was mispredicted 303system.cpu.commit.committed_per_cycle::samples 45409333 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::mean 2.216482 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::stdev 2.738259 # Number of insts commited each cycle | 300system.cpu.commit.commitSquashedInsts 12173182 # The number of squashed insts skipped by commit 301system.cpu.commit.commitNonSpecStalls 37122 # The number of times commit has been forced to stall to communicate backwards 302system.cpu.commit.branchMispredicts 565028 # The number of times a branch was mispredicted 303system.cpu.commit.committed_per_cycle::samples 44354504 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::mean 2.269197 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::stdev 2.754788 # Number of insts commited each cycle |
| 306system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 306system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 307system.cpu.commit.committed_per_cycle::0 15949772 35.12% 35.12% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::1 11950425 26.32% 61.44% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::2 3594230 7.92% 69.36% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::3 2920439 6.43% 75.79% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::4 1880725 4.14% 79.93% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::5 1913412 4.21% 84.14% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::6 683428 1.51% 85.65% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::7 576988 1.27% 86.92% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::8 5939914 13.08% 100.00% # Number of insts commited each cycle | 307system.cpu.commit.committed_per_cycle::0 15099779 34.04% 34.04% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::1 11755524 26.50% 60.55% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::2 3528202 7.95% 68.50% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::3 2907503 6.56% 75.06% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::4 1884478 4.25% 79.31% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::5 1967896 4.44% 83.74% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::6 685684 1.55% 85.29% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::7 580329 1.31% 86.60% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::8 5945109 13.40% 100.00% # Number of insts commited each cycle |
| 316system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 316system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 319system.cpu.commit.committed_per_cycle::total 45409333 # Number of insts commited each cycle 320system.cpu.commit.committedInsts 70929711 # Number of instructions committed 321system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed | 319system.cpu.commit.committed_per_cycle::total 44354504 # Number of insts commited each cycle 320system.cpu.commit.committedInsts 70929861 # Number of instructions committed 321system.cpu.commit.committedOps 100649108 # Number of ops (including micro ops) committed |
| 322system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 322system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 323system.cpu.commit.refs 47869458 # Number of memory references committed 324system.cpu.commit.loads 27310414 # Number of loads committed | 323system.cpu.commit.refs 47869518 # Number of memory references committed 324system.cpu.commit.loads 27310444 # Number of loads committed |
| 325system.cpu.commit.membars 15920 # Number of memory barriers committed | 325system.cpu.commit.membars 15920 # Number of memory barriers committed |
| 326system.cpu.commit.branches 13744811 # Number of branches committed | 326system.cpu.commit.branches 13744841 # Number of branches committed |
| 327system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. | 327system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. |
| 328system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. | 328system.cpu.commit.int_insts 91486123 # Number of committed integer instructions. |
| 329system.cpu.commit.function_calls 1679850 # Number of function calls committed. | 329system.cpu.commit.function_calls 1679850 # Number of function calls committed. |
| 330system.cpu.commit.bw_lim_events 5939914 # number cycles where commit BW limit reached | 330system.cpu.commit.bw_lim_events 5945109 # number cycles where commit BW limit reached |
| 331system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 331system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 332system.cpu.rob.rob_reads 152382757 # The number of ROB reads 333system.cpu.rob.rob_writes 227716793 # The number of ROB writes 334system.cpu.timesIdled 52521 # Number of times that the entire CPU went into an idle state and unscheduled itself 335system.cpu.idleCycles 1283924 # Total number of cycles that the CPU has spent unscheduled due to idling 336system.cpu.committedInsts 70924159 # Number of Instructions Simulated 337system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated 338system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated 339system.cpu.cpi 0.684138 # CPI: Cycles Per Instruction 340system.cpu.cpi_total 0.684138 # CPI: Total CPI of All Threads 341system.cpu.ipc 1.461694 # IPC: Instructions Per Cycle 342system.cpu.ipc_total 1.461694 # IPC: Total IPC of All Threads 343system.cpu.int_regfile_reads 515060291 # number of integer regfile reads 344system.cpu.int_regfile_writes 104149739 # number of integer regfile writes 345system.cpu.fp_regfile_reads 734 # number of floating regfile reads 346system.cpu.fp_regfile_writes 618 # number of floating regfile writes 347system.cpu.misc_regfile_reads 145340198 # number of misc regfile reads 348system.cpu.misc_regfile_writes 38452 # number of misc regfile writes 349system.cpu.icache.replacements 30556 # number of replacements 350system.cpu.icache.tagsinuse 1813.467317 # Cycle average of tags in use 351system.cpu.icache.total_refs 11916104 # Total number of references to valid blocks. 352system.cpu.icache.sampled_refs 32594 # Sample count of references to valid blocks. 353system.cpu.icache.avg_refs 365.591949 # Average number of references to valid blocks. | 332system.cpu.rob.rob_reads 151206386 # The number of ROB reads 333system.cpu.rob.rob_writes 227466743 # The number of ROB writes 334system.cpu.timesIdled 61795 # Number of times that the entire CPU went into an idle state and unscheduled itself 335system.cpu.idleCycles 1329085 # Total number of cycles that the CPU has spent unscheduled due to idling 336system.cpu.committedInsts 70924309 # Number of Instructions Simulated 337system.cpu.committedOps 100643556 # Number of Ops (including micro ops) Simulated 338system.cpu.committedInsts_total 70924309 # Number of Instructions Simulated 339system.cpu.cpi 0.669655 # CPI: Cycles Per Instruction 340system.cpu.cpi_total 0.669655 # CPI: Total CPI of All Threads 341system.cpu.ipc 1.493307 # IPC: Instructions Per Cycle 342system.cpu.ipc_total 1.493307 # IPC: Total IPC of All Threads 343system.cpu.int_regfile_reads 514746035 # number of integer regfile reads 344system.cpu.int_regfile_writes 104090442 # number of integer regfile writes 345system.cpu.fp_regfile_reads 1004 # number of floating regfile reads 346system.cpu.fp_regfile_writes 868 # number of floating regfile writes 347system.cpu.misc_regfile_reads 145207051 # number of misc regfile reads 348system.cpu.misc_regfile_writes 38512 # number of misc regfile writes 349system.cpu.icache.replacements 28686 # number of replacements 350system.cpu.icache.tagsinuse 1815.800680 # Cycle average of tags in use 351system.cpu.icache.total_refs 11888473 # Total number of references to valid blocks. 352system.cpu.icache.sampled_refs 30726 # Sample count of references to valid blocks. 353system.cpu.icache.avg_refs 386.918994 # Average number of references to valid blocks. |
| 354system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 354system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 355system.cpu.icache.occ_blocks::cpu.inst 1813.467317 # Average occupied blocks per requestor 356system.cpu.icache.occ_percent::cpu.inst 0.885482 # Average percentage of cache occupancy 357system.cpu.icache.occ_percent::total 0.885482 # Average percentage of cache occupancy 358system.cpu.icache.ReadReq_hits::cpu.inst 11916104 # number of ReadReq hits 359system.cpu.icache.ReadReq_hits::total 11916104 # number of ReadReq hits 360system.cpu.icache.demand_hits::cpu.inst 11916104 # number of demand (read+write) hits 361system.cpu.icache.demand_hits::total 11916104 # number of demand (read+write) hits 362system.cpu.icache.overall_hits::cpu.inst 11916104 # number of overall hits 363system.cpu.icache.overall_hits::total 11916104 # number of overall hits 364system.cpu.icache.ReadReq_misses::cpu.inst 33993 # number of ReadReq misses 365system.cpu.icache.ReadReq_misses::total 33993 # number of ReadReq misses 366system.cpu.icache.demand_misses::cpu.inst 33993 # number of demand (read+write) misses 367system.cpu.icache.demand_misses::total 33993 # number of demand (read+write) misses 368system.cpu.icache.overall_misses::cpu.inst 33993 # number of overall misses 369system.cpu.icache.overall_misses::total 33993 # number of overall misses 370system.cpu.icache.ReadReq_miss_latency::cpu.inst 409410000 # number of ReadReq miss cycles 371system.cpu.icache.ReadReq_miss_latency::total 409410000 # number of ReadReq miss cycles 372system.cpu.icache.demand_miss_latency::cpu.inst 409410000 # number of demand (read+write) miss cycles 373system.cpu.icache.demand_miss_latency::total 409410000 # number of demand (read+write) miss cycles 374system.cpu.icache.overall_miss_latency::cpu.inst 409410000 # number of overall miss cycles 375system.cpu.icache.overall_miss_latency::total 409410000 # number of overall miss cycles 376system.cpu.icache.ReadReq_accesses::cpu.inst 11950097 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.ReadReq_accesses::total 11950097 # number of ReadReq accesses(hits+misses) 378system.cpu.icache.demand_accesses::cpu.inst 11950097 # number of demand (read+write) accesses 379system.cpu.icache.demand_accesses::total 11950097 # number of demand (read+write) accesses 380system.cpu.icache.overall_accesses::cpu.inst 11950097 # number of overall (read+write) accesses 381system.cpu.icache.overall_accesses::total 11950097 # number of overall (read+write) accesses 382system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002845 # miss rate for ReadReq accesses 383system.cpu.icache.ReadReq_miss_rate::total 0.002845 # miss rate for ReadReq accesses 384system.cpu.icache.demand_miss_rate::cpu.inst 0.002845 # miss rate for demand accesses 385system.cpu.icache.demand_miss_rate::total 0.002845 # miss rate for demand accesses 386system.cpu.icache.overall_miss_rate::cpu.inst 0.002845 # miss rate for overall accesses 387system.cpu.icache.overall_miss_rate::total 0.002845 # miss rate for overall accesses 388system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12043.950225 # average ReadReq miss latency 389system.cpu.icache.ReadReq_avg_miss_latency::total 12043.950225 # average ReadReq miss latency 390system.cpu.icache.demand_avg_miss_latency::cpu.inst 12043.950225 # average overall miss latency 391system.cpu.icache.demand_avg_miss_latency::total 12043.950225 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::cpu.inst 12043.950225 # average overall miss latency 393system.cpu.icache.overall_avg_miss_latency::total 12043.950225 # average overall miss latency | 355system.cpu.icache.occ_blocks::cpu.inst 1815.800680 # Average occupied blocks per requestor 356system.cpu.icache.occ_percent::cpu.inst 0.886621 # Average percentage of cache occupancy 357system.cpu.icache.occ_percent::total 0.886621 # Average percentage of cache occupancy 358system.cpu.icache.ReadReq_hits::cpu.inst 11888474 # number of ReadReq hits 359system.cpu.icache.ReadReq_hits::total 11888474 # number of ReadReq hits 360system.cpu.icache.demand_hits::cpu.inst 11888474 # number of demand (read+write) hits 361system.cpu.icache.demand_hits::total 11888474 # number of demand (read+write) hits 362system.cpu.icache.overall_hits::cpu.inst 11888474 # number of overall hits 363system.cpu.icache.overall_hits::total 11888474 # number of overall hits 364system.cpu.icache.ReadReq_misses::cpu.inst 31905 # number of ReadReq misses 365system.cpu.icache.ReadReq_misses::total 31905 # number of ReadReq misses 366system.cpu.icache.demand_misses::cpu.inst 31905 # number of demand (read+write) misses 367system.cpu.icache.demand_misses::total 31905 # number of demand (read+write) misses 368system.cpu.icache.overall_misses::cpu.inst 31905 # number of overall misses 369system.cpu.icache.overall_misses::total 31905 # number of overall misses 370system.cpu.icache.ReadReq_miss_latency::cpu.inst 328897000 # number of ReadReq miss cycles 371system.cpu.icache.ReadReq_miss_latency::total 328897000 # number of ReadReq miss cycles 372system.cpu.icache.demand_miss_latency::cpu.inst 328897000 # number of demand (read+write) miss cycles 373system.cpu.icache.demand_miss_latency::total 328897000 # number of demand (read+write) miss cycles 374system.cpu.icache.overall_miss_latency::cpu.inst 328897000 # number of overall miss cycles 375system.cpu.icache.overall_miss_latency::total 328897000 # number of overall miss cycles 376system.cpu.icache.ReadReq_accesses::cpu.inst 11920379 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.ReadReq_accesses::total 11920379 # number of ReadReq accesses(hits+misses) 378system.cpu.icache.demand_accesses::cpu.inst 11920379 # number of demand (read+write) accesses 379system.cpu.icache.demand_accesses::total 11920379 # number of demand (read+write) accesses 380system.cpu.icache.overall_accesses::cpu.inst 11920379 # number of overall (read+write) accesses 381system.cpu.icache.overall_accesses::total 11920379 # number of overall (read+write) accesses 382system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002677 # miss rate for ReadReq accesses 383system.cpu.icache.ReadReq_miss_rate::total 0.002677 # miss rate for ReadReq accesses 384system.cpu.icache.demand_miss_rate::cpu.inst 0.002677 # miss rate for demand accesses 385system.cpu.icache.demand_miss_rate::total 0.002677 # miss rate for demand accesses 386system.cpu.icache.overall_miss_rate::cpu.inst 0.002677 # miss rate for overall accesses 387system.cpu.icache.overall_miss_rate::total 0.002677 # miss rate for overall accesses 388system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10308.635010 # average ReadReq miss latency 389system.cpu.icache.ReadReq_avg_miss_latency::total 10308.635010 # average ReadReq miss latency 390system.cpu.icache.demand_avg_miss_latency::cpu.inst 10308.635010 # average overall miss latency 391system.cpu.icache.demand_avg_miss_latency::total 10308.635010 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::cpu.inst 10308.635010 # average overall miss latency 393system.cpu.icache.overall_avg_miss_latency::total 10308.635010 # average overall miss latency |
| 394system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 395system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 399system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 400system.cpu.icache.fast_writes 0 # number of fast writes performed 401system.cpu.icache.cache_copies 0 # number of cache copies performed | 394system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 395system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 399system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 400system.cpu.icache.fast_writes 0 # number of fast writes performed 401system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 402system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1348 # number of ReadReq MSHR hits 403system.cpu.icache.ReadReq_mshr_hits::total 1348 # number of ReadReq MSHR hits 404system.cpu.icache.demand_mshr_hits::cpu.inst 1348 # number of demand (read+write) MSHR hits 405system.cpu.icache.demand_mshr_hits::total 1348 # number of demand (read+write) MSHR hits 406system.cpu.icache.overall_mshr_hits::cpu.inst 1348 # number of overall MSHR hits 407system.cpu.icache.overall_mshr_hits::total 1348 # number of overall MSHR hits 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32645 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 32645 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 32645 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 32645 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 32645 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 32645 # number of overall MSHR misses 414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275574000 # number of ReadReq MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_latency::total 275574000 # number of ReadReq MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275574000 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::total 275574000 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275574000 # number of overall MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::total 275574000 # number of overall MSHR miss cycles 420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002732 # mshr miss rate for ReadReq accesses 421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002732 # mshr miss rate for ReadReq accesses 422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002732 # mshr miss rate for demand accesses 423system.cpu.icache.demand_mshr_miss_rate::total 0.002732 # mshr miss rate for demand accesses 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002732 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.002732 # mshr miss rate for overall accesses 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8441.537755 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8441.537755 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8441.537755 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 8441.537755 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8441.537755 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 8441.537755 # average overall mshr miss latency | 402system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1159 # number of ReadReq MSHR hits 403system.cpu.icache.ReadReq_mshr_hits::total 1159 # number of ReadReq MSHR hits 404system.cpu.icache.demand_mshr_hits::cpu.inst 1159 # number of demand (read+write) MSHR hits 405system.cpu.icache.demand_mshr_hits::total 1159 # number of demand (read+write) MSHR hits 406system.cpu.icache.overall_mshr_hits::cpu.inst 1159 # number of overall MSHR hits 407system.cpu.icache.overall_mshr_hits::total 1159 # number of overall MSHR hits 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30746 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 30746 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 30746 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 30746 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 30746 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 30746 # number of overall MSHR misses 414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 238224500 # number of ReadReq MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_latency::total 238224500 # number of ReadReq MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 238224500 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::total 238224500 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 238224500 # number of overall MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::total 238224500 # number of overall MSHR miss cycles 420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for ReadReq accesses 421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002579 # mshr miss rate for ReadReq accesses 422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for demand accesses 423system.cpu.icache.demand_mshr_miss_rate::total 0.002579 # mshr miss rate for demand accesses 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.002579 # mshr miss rate for overall accesses 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7748.146100 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7748.146100 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7748.146100 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 7748.146100 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7748.146100 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 7748.146100 # average overall mshr miss latency |
| 432system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 432system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 433system.cpu.dcache.replacements 158553 # number of replacements 434system.cpu.dcache.tagsinuse 4072.119478 # Cycle average of tags in use 435system.cpu.dcache.total_refs 44571992 # Total number of references to valid blocks. 436system.cpu.dcache.sampled_refs 162649 # Sample count of references to valid blocks. 437system.cpu.dcache.avg_refs 274.037910 # Average number of references to valid blocks. 438system.cpu.dcache.warmup_cycle 270825000 # Cycle when the warmup percentage was hit. 439system.cpu.dcache.occ_blocks::cpu.data 4072.119478 # Average occupied blocks per requestor 440system.cpu.dcache.occ_percent::cpu.data 0.994170 # Average percentage of cache occupancy 441system.cpu.dcache.occ_percent::total 0.994170 # Average percentage of cache occupancy 442system.cpu.dcache.ReadReq_hits::cpu.data 26246711 # number of ReadReq hits 443system.cpu.dcache.ReadReq_hits::total 26246711 # number of ReadReq hits 444system.cpu.dcache.WriteReq_hits::cpu.data 18285374 # number of WriteReq hits 445system.cpu.dcache.WriteReq_hits::total 18285374 # number of WriteReq hits 446system.cpu.dcache.LoadLockedReq_hits::cpu.data 20492 # number of LoadLockedReq hits 447system.cpu.dcache.LoadLockedReq_hits::total 20492 # number of LoadLockedReq hits 448system.cpu.dcache.StoreCondReq_hits::cpu.data 19225 # number of StoreCondReq hits 449system.cpu.dcache.StoreCondReq_hits::total 19225 # number of StoreCondReq hits 450system.cpu.dcache.demand_hits::cpu.data 44532085 # number of demand (read+write) hits 451system.cpu.dcache.demand_hits::total 44532085 # number of demand (read+write) hits 452system.cpu.dcache.overall_hits::cpu.data 44532085 # number of overall hits 453system.cpu.dcache.overall_hits::total 44532085 # number of overall hits 454system.cpu.dcache.ReadReq_misses::cpu.data 107182 # number of ReadReq misses 455system.cpu.dcache.ReadReq_misses::total 107182 # number of ReadReq misses 456system.cpu.dcache.WriteReq_misses::cpu.data 1564527 # number of WriteReq misses 457system.cpu.dcache.WriteReq_misses::total 1564527 # number of WriteReq misses 458system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses 459system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses 460system.cpu.dcache.demand_misses::cpu.data 1671709 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 1671709 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 1671709 # number of overall misses 463system.cpu.dcache.overall_misses::total 1671709 # number of overall misses 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 2591609000 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 2591609000 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 63424341000 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 63424341000 # number of WriteReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 645500 # number of LoadLockedReq miss cycles 469system.cpu.dcache.LoadLockedReq_miss_latency::total 645500 # number of LoadLockedReq miss cycles 470system.cpu.dcache.demand_miss_latency::cpu.data 66015950000 # number of demand (read+write) miss cycles 471system.cpu.dcache.demand_miss_latency::total 66015950000 # number of demand (read+write) miss cycles 472system.cpu.dcache.overall_miss_latency::cpu.data 66015950000 # number of overall miss cycles 473system.cpu.dcache.overall_miss_latency::total 66015950000 # number of overall miss cycles 474system.cpu.dcache.ReadReq_accesses::cpu.data 26353893 # number of ReadReq accesses(hits+misses) 475system.cpu.dcache.ReadReq_accesses::total 26353893 # number of ReadReq accesses(hits+misses) | 433system.cpu.dcache.replacements 158487 # number of replacements 434system.cpu.dcache.tagsinuse 4072.438439 # Cycle average of tags in use 435system.cpu.dcache.total_refs 44565712 # Total number of references to valid blocks. 436system.cpu.dcache.sampled_refs 162583 # Sample count of references to valid blocks. 437system.cpu.dcache.avg_refs 274.110528 # Average number of references to valid blocks. 438system.cpu.dcache.warmup_cycle 253512000 # Cycle when the warmup percentage was hit. 439system.cpu.dcache.occ_blocks::cpu.data 4072.438439 # Average occupied blocks per requestor 440system.cpu.dcache.occ_percent::cpu.data 0.994248 # Average percentage of cache occupancy 441system.cpu.dcache.occ_percent::total 0.994248 # Average percentage of cache occupancy 442system.cpu.dcache.ReadReq_hits::cpu.data 26240884 # number of ReadReq hits 443system.cpu.dcache.ReadReq_hits::total 26240884 # number of ReadReq hits 444system.cpu.dcache.WriteReq_hits::cpu.data 18285018 # number of WriteReq hits 445system.cpu.dcache.WriteReq_hits::total 18285018 # number of WriteReq hits 446system.cpu.dcache.LoadLockedReq_hits::cpu.data 20455 # number of LoadLockedReq hits 447system.cpu.dcache.LoadLockedReq_hits::total 20455 # number of LoadLockedReq hits 448system.cpu.dcache.StoreCondReq_hits::cpu.data 19255 # number of StoreCondReq hits 449system.cpu.dcache.StoreCondReq_hits::total 19255 # number of StoreCondReq hits 450system.cpu.dcache.demand_hits::cpu.data 44525902 # number of demand (read+write) hits 451system.cpu.dcache.demand_hits::total 44525902 # number of demand (read+write) hits 452system.cpu.dcache.overall_hits::cpu.data 44525902 # number of overall hits 453system.cpu.dcache.overall_hits::total 44525902 # number of overall hits 454system.cpu.dcache.ReadReq_misses::cpu.data 105303 # number of ReadReq misses 455system.cpu.dcache.ReadReq_misses::total 105303 # number of ReadReq misses 456system.cpu.dcache.WriteReq_misses::cpu.data 1564883 # number of WriteReq misses 457system.cpu.dcache.WriteReq_misses::total 1564883 # number of WriteReq misses 458system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses 459system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses 460system.cpu.dcache.demand_misses::cpu.data 1670186 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 1670186 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 1670186 # number of overall misses 463system.cpu.dcache.overall_misses::total 1670186 # number of overall misses 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 2142178000 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 2142178000 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 54165146000 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 54165146000 # number of WriteReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358500 # number of LoadLockedReq miss cycles 469system.cpu.dcache.LoadLockedReq_miss_latency::total 358500 # number of LoadLockedReq miss cycles 470system.cpu.dcache.demand_miss_latency::cpu.data 56307324000 # number of demand (read+write) miss cycles 471system.cpu.dcache.demand_miss_latency::total 56307324000 # number of demand (read+write) miss cycles 472system.cpu.dcache.overall_miss_latency::cpu.data 56307324000 # number of overall miss cycles 473system.cpu.dcache.overall_miss_latency::total 56307324000 # number of overall miss cycles 474system.cpu.dcache.ReadReq_accesses::cpu.data 26346187 # number of ReadReq accesses(hits+misses) 475system.cpu.dcache.ReadReq_accesses::total 26346187 # number of ReadReq accesses(hits+misses) |
| 476system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 477system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) | 476system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 477system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| 478system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20537 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.LoadLockedReq_accesses::total 20537 # number of LoadLockedReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.StoreCondReq_accesses::total 19225 # number of StoreCondReq accesses(hits+misses) 482system.cpu.dcache.demand_accesses::cpu.data 46203794 # number of demand (read+write) accesses 483system.cpu.dcache.demand_accesses::total 46203794 # number of demand (read+write) accesses 484system.cpu.dcache.overall_accesses::cpu.data 46203794 # number of overall (read+write) accesses 485system.cpu.dcache.overall_accesses::total 46203794 # number of overall (read+write) accesses 486system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004067 # miss rate for ReadReq accesses 487system.cpu.dcache.ReadReq_miss_rate::total 0.004067 # miss rate for ReadReq accesses 488system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078818 # miss rate for WriteReq accesses 489system.cpu.dcache.WriteReq_miss_rate::total 0.078818 # miss rate for WriteReq accesses 490system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002191 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002191 # miss rate for LoadLockedReq accesses 492system.cpu.dcache.demand_miss_rate::cpu.data 0.036181 # miss rate for demand accesses 493system.cpu.dcache.demand_miss_rate::total 0.036181 # miss rate for demand accesses 494system.cpu.dcache.overall_miss_rate::cpu.data 0.036181 # miss rate for overall accesses 495system.cpu.dcache.overall_miss_rate::total 0.036181 # miss rate for overall accesses 496system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24179.517083 # average ReadReq miss latency 497system.cpu.dcache.ReadReq_avg_miss_latency::total 24179.517083 # average ReadReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40538.987822 # average WriteReq miss latency 499system.cpu.dcache.WriteReq_avg_miss_latency::total 40538.987822 # average WriteReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14344.444444 # average LoadLockedReq miss latency 501system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14344.444444 # average LoadLockedReq miss latency 502system.cpu.dcache.demand_avg_miss_latency::cpu.data 39490.096662 # average overall miss latency 503system.cpu.dcache.demand_avg_miss_latency::total 39490.096662 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::cpu.data 39490.096662 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::total 39490.096662 # average overall miss latency | 478system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20497 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.LoadLockedReq_accesses::total 20497 # number of LoadLockedReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::cpu.data 19255 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.StoreCondReq_accesses::total 19255 # number of StoreCondReq accesses(hits+misses) 482system.cpu.dcache.demand_accesses::cpu.data 46196088 # number of demand (read+write) accesses 483system.cpu.dcache.demand_accesses::total 46196088 # number of demand (read+write) accesses 484system.cpu.dcache.overall_accesses::cpu.data 46196088 # number of overall (read+write) accesses 485system.cpu.dcache.overall_accesses::total 46196088 # number of overall (read+write) accesses 486system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003997 # miss rate for ReadReq accesses 487system.cpu.dcache.ReadReq_miss_rate::total 0.003997 # miss rate for ReadReq accesses 488system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078836 # miss rate for WriteReq accesses 489system.cpu.dcache.WriteReq_miss_rate::total 0.078836 # miss rate for WriteReq accesses 490system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002049 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002049 # miss rate for LoadLockedReq accesses 492system.cpu.dcache.demand_miss_rate::cpu.data 0.036154 # miss rate for demand accesses 493system.cpu.dcache.demand_miss_rate::total 0.036154 # miss rate for demand accesses 494system.cpu.dcache.overall_miss_rate::cpu.data 0.036154 # miss rate for overall accesses 495system.cpu.dcache.overall_miss_rate::total 0.036154 # miss rate for overall accesses 496system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20342.991178 # average ReadReq miss latency 497system.cpu.dcache.ReadReq_avg_miss_latency::total 20342.991178 # average ReadReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34612.904607 # average WriteReq miss latency 499system.cpu.dcache.WriteReq_avg_miss_latency::total 34612.904607 # average WriteReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8535.714286 # average LoadLockedReq miss latency 501system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8535.714286 # average LoadLockedReq miss latency 502system.cpu.dcache.demand_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency 503system.cpu.dcache.demand_avg_miss_latency::total 33713.205595 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::total 33713.205595 # average overall miss latency |
| 506system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 506system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 507system.cpu.dcache.blocked_cycles::no_targets 209500 # number of cycles access was blocked | 507system.cpu.dcache.blocked_cycles::no_targets 197000 # number of cycles access was blocked |
| 508system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked | 508system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 509system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked | 509system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked |
| 510system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 510system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 511system.cpu.dcache.avg_blocked_cycles::no_targets 19045.454545 # average number of cycles each access was blocked | 511system.cpu.dcache.avg_blocked_cycles::no_targets 19700 # average number of cycles each access was blocked |
| 512system.cpu.dcache.fast_writes 0 # number of fast writes performed 513system.cpu.dcache.cache_copies 0 # number of cache copies performed | 512system.cpu.dcache.fast_writes 0 # number of fast writes performed 513system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 514system.cpu.dcache.writebacks::writebacks 128129 # number of writebacks 515system.cpu.dcache.writebacks::total 128129 # number of writebacks 516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51511 # number of ReadReq MSHR hits 517system.cpu.dcache.ReadReq_mshr_hits::total 51511 # number of ReadReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457497 # number of WriteReq MSHR hits 519system.cpu.dcache.WriteReq_mshr_hits::total 1457497 # number of WriteReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits 521system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits 522system.cpu.dcache.demand_mshr_hits::cpu.data 1509008 # number of demand (read+write) MSHR hits 523system.cpu.dcache.demand_mshr_hits::total 1509008 # number of demand (read+write) MSHR hits 524system.cpu.dcache.overall_mshr_hits::cpu.data 1509008 # number of overall MSHR hits 525system.cpu.dcache.overall_mshr_hits::total 1509008 # number of overall MSHR hits 526system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55671 # number of ReadReq MSHR misses 527system.cpu.dcache.ReadReq_mshr_misses::total 55671 # number of ReadReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses 529system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses 530system.cpu.dcache.demand_mshr_misses::cpu.data 162701 # number of demand (read+write) MSHR misses 531system.cpu.dcache.demand_mshr_misses::total 162701 # number of demand (read+write) MSHR misses 532system.cpu.dcache.overall_mshr_misses::cpu.data 162701 # number of overall MSHR misses 533system.cpu.dcache.overall_mshr_misses::total 162701 # number of overall MSHR misses 534system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 988702000 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.ReadReq_mshr_miss_latency::total 988702000 # number of ReadReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3843974500 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.WriteReq_mshr_miss_latency::total 3843974500 # number of WriteReq MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4832676500 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.demand_mshr_miss_latency::total 4832676500 # number of demand (read+write) MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4832676500 # number of overall MSHR miss cycles 541system.cpu.dcache.overall_mshr_miss_latency::total 4832676500 # number of overall MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses 544system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 546system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for demand accesses 547system.cpu.dcache.demand_mshr_miss_rate::total 0.003521 # mshr miss rate for demand accesses 548system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for overall accesses 549system.cpu.dcache.overall_mshr_miss_rate::total 0.003521 # mshr miss rate for overall accesses 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17759.731278 # average ReadReq mshr miss latency 551system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17759.731278 # average ReadReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35914.925722 # average WriteReq mshr miss latency 553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35914.925722 # average WriteReq mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29702.807604 # average overall mshr miss latency 555system.cpu.dcache.demand_avg_mshr_miss_latency::total 29702.807604 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29702.807604 # average overall mshr miss latency 557system.cpu.dcache.overall_avg_mshr_miss_latency::total 29702.807604 # average overall mshr miss latency | 514system.cpu.dcache.writebacks::writebacks 128103 # number of writebacks 515system.cpu.dcache.writebacks::total 128103 # number of writebacks 516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49707 # number of ReadReq MSHR hits 517system.cpu.dcache.ReadReq_mshr_hits::total 49707 # number of ReadReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457877 # number of WriteReq MSHR hits 519system.cpu.dcache.WriteReq_mshr_hits::total 1457877 # number of WriteReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits 521system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits 522system.cpu.dcache.demand_mshr_hits::cpu.data 1507584 # number of demand (read+write) MSHR hits 523system.cpu.dcache.demand_mshr_hits::total 1507584 # number of demand (read+write) MSHR hits 524system.cpu.dcache.overall_mshr_hits::cpu.data 1507584 # number of overall MSHR hits 525system.cpu.dcache.overall_mshr_hits::total 1507584 # number of overall MSHR hits 526system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55596 # number of ReadReq MSHR misses 527system.cpu.dcache.ReadReq_mshr_misses::total 55596 # number of ReadReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107006 # number of WriteReq MSHR misses 529system.cpu.dcache.WriteReq_mshr_misses::total 107006 # number of WriteReq MSHR misses 530system.cpu.dcache.demand_mshr_misses::cpu.data 162602 # number of demand (read+write) MSHR misses 531system.cpu.dcache.demand_mshr_misses::total 162602 # number of demand (read+write) MSHR misses 532system.cpu.dcache.overall_mshr_misses::cpu.data 162602 # number of overall MSHR misses 533system.cpu.dcache.overall_mshr_misses::total 162602 # number of overall MSHR misses 534system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 945497500 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.ReadReq_mshr_miss_latency::total 945497500 # number of ReadReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3824998000 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.WriteReq_mshr_miss_latency::total 3824998000 # number of WriteReq MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4770495500 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.demand_mshr_miss_latency::total 4770495500 # number of demand (read+write) MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4770495500 # number of overall MSHR miss cycles 541system.cpu.dcache.overall_mshr_miss_latency::total 4770495500 # number of overall MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002110 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002110 # mshr miss rate for ReadReq accesses 544system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005391 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005391 # mshr miss rate for WriteReq accesses 546system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for demand accesses 547system.cpu.dcache.demand_mshr_miss_rate::total 0.003520 # mshr miss rate for demand accesses 548system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for overall accesses 549system.cpu.dcache.overall_mshr_miss_rate::total 0.003520 # mshr miss rate for overall accesses 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.574214 # average ReadReq mshr miss latency 551system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.574214 # average ReadReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35745.640431 # average WriteReq mshr miss latency 553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35745.640431 # average WriteReq mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29338.479846 # average overall mshr miss latency 555system.cpu.dcache.demand_avg_mshr_miss_latency::total 29338.479846 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29338.479846 # average overall mshr miss latency 557system.cpu.dcache.overall_avg_mshr_miss_latency::total 29338.479846 # average overall mshr miss latency |
| 558system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 558system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 559system.cpu.l2cache.replacements 97977 # number of replacements 560system.cpu.l2cache.tagsinuse 28615.045992 # Cycle average of tags in use 561system.cpu.l2cache.total_refs 87467 # Total number of references to valid blocks. 562system.cpu.l2cache.sampled_refs 128770 # Sample count of references to valid blocks. 563system.cpu.l2cache.avg_refs 0.679250 # Average number of references to valid blocks. | 559system.cpu.l2cache.replacements 97972 # number of replacements 560system.cpu.l2cache.tagsinuse 28672.320506 # Cycle average of tags in use 561system.cpu.l2cache.total_refs 85492 # Total number of references to valid blocks. 562system.cpu.l2cache.sampled_refs 128764 # Sample count of references to valid blocks. 563system.cpu.l2cache.avg_refs 0.663943 # Average number of references to valid blocks. |
| 564system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 564system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 565system.cpu.l2cache.occ_blocks::writebacks 25802.945299 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.inst 1156.360964 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_blocks::cpu.data 1655.739728 # Average occupied blocks per requestor 568system.cpu.l2cache.occ_percent::writebacks 0.787443 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.inst 0.035289 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::cpu.data 0.050529 # Average percentage of cache occupancy 571system.cpu.l2cache.occ_percent::total 0.873262 # Average percentage of cache occupancy 572system.cpu.l2cache.ReadReq_hits::cpu.inst 27442 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::cpu.data 32454 # number of ReadReq hits 574system.cpu.l2cache.ReadReq_hits::total 59896 # number of ReadReq hits 575system.cpu.l2cache.Writeback_hits::writebacks 128129 # number of Writeback hits 576system.cpu.l2cache.Writeback_hits::total 128129 # number of Writeback hits 577system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits 578system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits 579system.cpu.l2cache.ReadExReq_hits::cpu.data 4696 # number of ReadExReq hits 580system.cpu.l2cache.ReadExReq_hits::total 4696 # number of ReadExReq hits 581system.cpu.l2cache.demand_hits::cpu.inst 27442 # number of demand (read+write) hits 582system.cpu.l2cache.demand_hits::cpu.data 37150 # number of demand (read+write) hits 583system.cpu.l2cache.demand_hits::total 64592 # number of demand (read+write) hits 584system.cpu.l2cache.overall_hits::cpu.inst 27442 # number of overall hits 585system.cpu.l2cache.overall_hits::cpu.data 37150 # number of overall hits 586system.cpu.l2cache.overall_hits::total 64592 # number of overall hits 587system.cpu.l2cache.ReadReq_misses::cpu.inst 5147 # number of ReadReq misses 588system.cpu.l2cache.ReadReq_misses::cpu.data 23181 # number of ReadReq misses 589system.cpu.l2cache.ReadReq_misses::total 28328 # number of ReadReq misses 590system.cpu.l2cache.UpgradeReq_misses::cpu.data 36 # number of UpgradeReq misses 591system.cpu.l2cache.UpgradeReq_misses::total 36 # number of UpgradeReq misses 592system.cpu.l2cache.ReadExReq_misses::cpu.data 102318 # number of ReadExReq misses 593system.cpu.l2cache.ReadExReq_misses::total 102318 # number of ReadExReq misses 594system.cpu.l2cache.demand_misses::cpu.inst 5147 # number of demand (read+write) misses 595system.cpu.l2cache.demand_misses::cpu.data 125499 # number of demand (read+write) misses 596system.cpu.l2cache.demand_misses::total 130646 # number of demand (read+write) misses 597system.cpu.l2cache.overall_misses::cpu.inst 5147 # number of overall misses 598system.cpu.l2cache.overall_misses::cpu.data 125499 # number of overall misses 599system.cpu.l2cache.overall_misses::total 130646 # number of overall misses 600system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 180862000 # number of ReadReq miss cycles 601system.cpu.l2cache.ReadReq_miss_latency::cpu.data 832773500 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadReq_miss_latency::total 1013635500 # number of ReadReq miss cycles 603system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3563699000 # number of ReadExReq miss cycles 604system.cpu.l2cache.ReadExReq_miss_latency::total 3563699000 # number of ReadExReq miss cycles 605system.cpu.l2cache.demand_miss_latency::cpu.inst 180862000 # number of demand (read+write) miss cycles 606system.cpu.l2cache.demand_miss_latency::cpu.data 4396472500 # number of demand (read+write) miss cycles 607system.cpu.l2cache.demand_miss_latency::total 4577334500 # number of demand (read+write) miss cycles 608system.cpu.l2cache.overall_miss_latency::cpu.inst 180862000 # number of overall miss cycles 609system.cpu.l2cache.overall_miss_latency::cpu.data 4396472500 # number of overall miss cycles 610system.cpu.l2cache.overall_miss_latency::total 4577334500 # number of overall miss cycles 611system.cpu.l2cache.ReadReq_accesses::cpu.inst 32589 # number of ReadReq accesses(hits+misses) 612system.cpu.l2cache.ReadReq_accesses::cpu.data 55635 # number of ReadReq accesses(hits+misses) 613system.cpu.l2cache.ReadReq_accesses::total 88224 # number of ReadReq accesses(hits+misses) 614system.cpu.l2cache.Writeback_accesses::writebacks 128129 # number of Writeback accesses(hits+misses) 615system.cpu.l2cache.Writeback_accesses::total 128129 # number of Writeback accesses(hits+misses) 616system.cpu.l2cache.UpgradeReq_accesses::cpu.data 52 # number of UpgradeReq accesses(hits+misses) 617system.cpu.l2cache.UpgradeReq_accesses::total 52 # number of UpgradeReq accesses(hits+misses) 618system.cpu.l2cache.ReadExReq_accesses::cpu.data 107014 # number of ReadExReq accesses(hits+misses) 619system.cpu.l2cache.ReadExReq_accesses::total 107014 # number of ReadExReq accesses(hits+misses) 620system.cpu.l2cache.demand_accesses::cpu.inst 32589 # number of demand (read+write) accesses 621system.cpu.l2cache.demand_accesses::cpu.data 162649 # number of demand (read+write) accesses 622system.cpu.l2cache.demand_accesses::total 195238 # number of demand (read+write) accesses 623system.cpu.l2cache.overall_accesses::cpu.inst 32589 # number of overall (read+write) accesses 624system.cpu.l2cache.overall_accesses::cpu.data 162649 # number of overall (read+write) accesses 625system.cpu.l2cache.overall_accesses::total 195238 # number of overall (read+write) accesses 626system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.157937 # miss rate for ReadReq accesses 627system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.416662 # miss rate for ReadReq accesses 628system.cpu.l2cache.ReadReq_miss_rate::total 0.321092 # miss rate for ReadReq accesses 629system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.692308 # miss rate for UpgradeReq accesses 630system.cpu.l2cache.UpgradeReq_miss_rate::total 0.692308 # miss rate for UpgradeReq accesses 631system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.956118 # miss rate for ReadExReq accesses 632system.cpu.l2cache.ReadExReq_miss_rate::total 0.956118 # miss rate for ReadExReq accesses 633system.cpu.l2cache.demand_miss_rate::cpu.inst 0.157937 # miss rate for demand accesses 634system.cpu.l2cache.demand_miss_rate::cpu.data 0.771594 # miss rate for demand accesses 635system.cpu.l2cache.demand_miss_rate::total 0.669163 # miss rate for demand accesses 636system.cpu.l2cache.overall_miss_rate::cpu.inst 0.157937 # miss rate for overall accesses 637system.cpu.l2cache.overall_miss_rate::cpu.data 0.771594 # miss rate for overall accesses 638system.cpu.l2cache.overall_miss_rate::total 0.669163 # miss rate for overall accesses 639system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35139.304449 # average ReadReq miss latency 640system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35924.830680 # average ReadReq miss latency 641system.cpu.l2cache.ReadReq_avg_miss_latency::total 35782.106043 # average ReadReq miss latency 642system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34829.638969 # average ReadExReq miss latency 643system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34829.638969 # average ReadExReq miss latency 644system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35139.304449 # average overall miss latency 645system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35031.932525 # average overall miss latency 646system.cpu.l2cache.demand_avg_miss_latency::total 35036.162607 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35139.304449 # average overall miss latency 648system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35031.932525 # average overall miss latency 649system.cpu.l2cache.overall_avg_miss_latency::total 35036.162607 # average overall miss latency | 565system.cpu.l2cache.occ_blocks::writebacks 25877.470214 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.inst 1151.216152 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_blocks::cpu.data 1643.634140 # Average occupied blocks per requestor 568system.cpu.l2cache.occ_percent::writebacks 0.789718 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.inst 0.035132 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::cpu.data 0.050160 # Average percentage of cache occupancy 571system.cpu.l2cache.occ_percent::total 0.875010 # Average percentage of cache occupancy 572system.cpu.l2cache.ReadReq_hits::cpu.inst 25596 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::cpu.data 32355 # number of ReadReq hits 574system.cpu.l2cache.ReadReq_hits::total 57951 # number of ReadReq hits 575system.cpu.l2cache.Writeback_hits::writebacks 128103 # number of Writeback hits 576system.cpu.l2cache.Writeback_hits::total 128103 # number of Writeback hits 577system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 578system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 579system.cpu.l2cache.ReadExReq_hits::cpu.data 4711 # number of ReadExReq hits 580system.cpu.l2cache.ReadExReq_hits::total 4711 # number of ReadExReq hits 581system.cpu.l2cache.demand_hits::cpu.inst 25596 # number of demand (read+write) hits 582system.cpu.l2cache.demand_hits::cpu.data 37066 # number of demand (read+write) hits 583system.cpu.l2cache.demand_hits::total 62662 # number of demand (read+write) hits 584system.cpu.l2cache.overall_hits::cpu.inst 25596 # number of overall hits 585system.cpu.l2cache.overall_hits::cpu.data 37066 # number of overall hits 586system.cpu.l2cache.overall_hits::total 62662 # number of overall hits 587system.cpu.l2cache.ReadReq_misses::cpu.inst 5128 # number of ReadReq misses 588system.cpu.l2cache.ReadReq_misses::cpu.data 23202 # number of ReadReq misses 589system.cpu.l2cache.ReadReq_misses::total 28330 # number of ReadReq misses 590system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses 591system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses 592system.cpu.l2cache.ReadExReq_misses::cpu.data 102315 # number of ReadExReq misses 593system.cpu.l2cache.ReadExReq_misses::total 102315 # number of ReadExReq misses 594system.cpu.l2cache.demand_misses::cpu.inst 5128 # number of demand (read+write) misses 595system.cpu.l2cache.demand_misses::cpu.data 125517 # number of demand (read+write) misses 596system.cpu.l2cache.demand_misses::total 130645 # number of demand (read+write) misses 597system.cpu.l2cache.overall_misses::cpu.inst 5128 # number of overall misses 598system.cpu.l2cache.overall_misses::cpu.data 125517 # number of overall misses 599system.cpu.l2cache.overall_misses::total 130645 # number of overall misses 600system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181262500 # number of ReadReq miss cycles 601system.cpu.l2cache.ReadReq_miss_latency::cpu.data 852393000 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadReq_miss_latency::total 1033655500 # number of ReadReq miss cycles 603system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3712515000 # number of ReadExReq miss cycles 604system.cpu.l2cache.ReadExReq_miss_latency::total 3712515000 # number of ReadExReq miss cycles 605system.cpu.l2cache.demand_miss_latency::cpu.inst 181262500 # number of demand (read+write) miss cycles 606system.cpu.l2cache.demand_miss_latency::cpu.data 4564908000 # number of demand (read+write) miss cycles 607system.cpu.l2cache.demand_miss_latency::total 4746170500 # number of demand (read+write) miss cycles 608system.cpu.l2cache.overall_miss_latency::cpu.inst 181262500 # number of overall miss cycles 609system.cpu.l2cache.overall_miss_latency::cpu.data 4564908000 # number of overall miss cycles 610system.cpu.l2cache.overall_miss_latency::total 4746170500 # number of overall miss cycles 611system.cpu.l2cache.ReadReq_accesses::cpu.inst 30724 # number of ReadReq accesses(hits+misses) 612system.cpu.l2cache.ReadReq_accesses::cpu.data 55557 # number of ReadReq accesses(hits+misses) 613system.cpu.l2cache.ReadReq_accesses::total 86281 # number of ReadReq accesses(hits+misses) 614system.cpu.l2cache.Writeback_accesses::writebacks 128103 # number of Writeback accesses(hits+misses) 615system.cpu.l2cache.Writeback_accesses::total 128103 # number of Writeback accesses(hits+misses) 616system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses) 617system.cpu.l2cache.UpgradeReq_accesses::total 19 # number of UpgradeReq accesses(hits+misses) 618system.cpu.l2cache.ReadExReq_accesses::cpu.data 107026 # number of ReadExReq accesses(hits+misses) 619system.cpu.l2cache.ReadExReq_accesses::total 107026 # number of ReadExReq accesses(hits+misses) 620system.cpu.l2cache.demand_accesses::cpu.inst 30724 # number of demand (read+write) accesses 621system.cpu.l2cache.demand_accesses::cpu.data 162583 # number of demand (read+write) accesses 622system.cpu.l2cache.demand_accesses::total 193307 # number of demand (read+write) accesses 623system.cpu.l2cache.overall_accesses::cpu.inst 30724 # number of overall (read+write) accesses 624system.cpu.l2cache.overall_accesses::cpu.data 162583 # number of overall (read+write) accesses 625system.cpu.l2cache.overall_accesses::total 193307 # number of overall (read+write) accesses 626system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.166905 # miss rate for ReadReq accesses 627system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.417625 # miss rate for ReadReq accesses 628system.cpu.l2cache.ReadReq_miss_rate::total 0.328346 # miss rate for ReadReq accesses 629system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses 630system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses 631system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955983 # miss rate for ReadExReq accesses 632system.cpu.l2cache.ReadExReq_miss_rate::total 0.955983 # miss rate for ReadExReq accesses 633system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166905 # miss rate for demand accesses 634system.cpu.l2cache.demand_miss_rate::cpu.data 0.772018 # miss rate for demand accesses 635system.cpu.l2cache.demand_miss_rate::total 0.675842 # miss rate for demand accesses 636system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166905 # miss rate for overall accesses 637system.cpu.l2cache.overall_miss_rate::cpu.data 0.772018 # miss rate for overall accesses 638system.cpu.l2cache.overall_miss_rate::total 0.675842 # miss rate for overall accesses 639system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35347.601404 # average ReadReq miss latency 640system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36737.910525 # average ReadReq miss latency 641system.cpu.l2cache.ReadReq_avg_miss_latency::total 36486.251324 # average ReadReq miss latency 642system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36285.148805 # average ReadExReq miss latency 643system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36285.148805 # average ReadExReq miss latency 644system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35347.601404 # average overall miss latency 645system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36368.842468 # average overall miss latency 646system.cpu.l2cache.demand_avg_miss_latency::total 36328.757319 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35347.601404 # average overall miss latency 648system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36368.842468 # average overall miss latency 649system.cpu.l2cache.overall_avg_miss_latency::total 36328.757319 # average overall miss latency |
| 650system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.l2cache.fast_writes 0 # number of fast writes performed 657system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 650system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.l2cache.fast_writes 0 # number of fast writes performed 657system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 658system.cpu.l2cache.writebacks::writebacks 84650 # number of writebacks 659system.cpu.l2cache.writebacks::total 84650 # number of writebacks 660system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 27 # number of ReadReq MSHR hits 661system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits 662system.cpu.l2cache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits 663system.cpu.l2cache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits 664system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits 665system.cpu.l2cache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits 666system.cpu.l2cache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits 667system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits 668system.cpu.l2cache.overall_mshr_hits::total 88 # number of overall MSHR hits 669system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5120 # number of ReadReq MSHR misses 670system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23120 # number of ReadReq MSHR misses 671system.cpu.l2cache.ReadReq_mshr_misses::total 28240 # number of ReadReq MSHR misses 672system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses 673system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses 674system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102318 # number of ReadExReq MSHR misses 675system.cpu.l2cache.ReadExReq_mshr_misses::total 102318 # number of ReadExReq MSHR misses 676system.cpu.l2cache.demand_mshr_misses::cpu.inst 5120 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.demand_mshr_misses::cpu.data 125438 # number of demand (read+write) MSHR misses 678system.cpu.l2cache.demand_mshr_misses::total 130558 # number of demand (read+write) MSHR misses 679system.cpu.l2cache.overall_mshr_misses::cpu.inst 5120 # number of overall MSHR misses 680system.cpu.l2cache.overall_mshr_misses::cpu.data 125438 # number of overall MSHR misses 681system.cpu.l2cache.overall_mshr_misses::total 130558 # number of overall MSHR misses 682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164141000 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 758230000 # number of ReadReq MSHR miss cycles 684system.cpu.l2cache.ReadReq_mshr_miss_latency::total 922371000 # number of ReadReq MSHR miss cycles 685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1129000 # number of UpgradeReq MSHR miss cycles 686system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1129000 # number of UpgradeReq MSHR miss cycles 687system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3246844000 # number of ReadExReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3246844000 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164141000 # number of demand (read+write) MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4005074000 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::total 4169215000 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164141000 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4005074000 # number of overall MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::total 4169215000 # number of overall MSHR miss cycles 695system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415566 # mshr miss rate for ReadReq accesses 697system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320094 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.692308 # mshr miss rate for UpgradeReq accesses 699system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.692308 # mshr miss rate for UpgradeReq accesses 700system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956118 # mshr miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956118 # mshr miss rate for ReadExReq accesses 702system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for demand accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771219 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::total 0.668712 # mshr miss rate for demand accesses 705system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for overall accesses 706system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771219 # mshr miss rate for overall accesses 707system.cpu.l2cache.overall_mshr_miss_rate::total 0.668712 # mshr miss rate for overall accesses 708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32058.789062 # average ReadReq mshr miss latency 709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32795.415225 # average ReadReq mshr miss latency 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32661.862606 # average ReadReq mshr miss latency 711system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31361.111111 # average UpgradeReq mshr miss latency 712system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31361.111111 # average UpgradeReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31732.872026 # average ReadExReq mshr miss latency 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31732.872026 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32058.789062 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31928.713787 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31933.814856 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32058.789062 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31928.713787 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31933.814856 # average overall mshr miss latency | 658system.cpu.l2cache.writebacks::writebacks 84652 # number of writebacks 659system.cpu.l2cache.writebacks::total 84652 # number of writebacks 660system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 36 # number of ReadReq MSHR hits 661system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits 662system.cpu.l2cache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits 663system.cpu.l2cache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits 664system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits 665system.cpu.l2cache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits 666system.cpu.l2cache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits 667system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits 668system.cpu.l2cache.overall_mshr_hits::total 100 # number of overall MSHR hits 669system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5092 # number of ReadReq MSHR misses 670system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23138 # number of ReadReq MSHR misses 671system.cpu.l2cache.ReadReq_mshr_misses::total 28230 # number of ReadReq MSHR misses 672system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses 673system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses 674system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102315 # number of ReadExReq MSHR misses 675system.cpu.l2cache.ReadExReq_mshr_misses::total 102315 # number of ReadExReq MSHR misses 676system.cpu.l2cache.demand_mshr_misses::cpu.inst 5092 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.demand_mshr_misses::cpu.data 125453 # number of demand (read+write) MSHR misses 678system.cpu.l2cache.demand_mshr_misses::total 130545 # number of demand (read+write) MSHR misses 679system.cpu.l2cache.overall_mshr_misses::cpu.inst 5092 # number of overall MSHR misses 680system.cpu.l2cache.overall_mshr_misses::cpu.data 125453 # number of overall MSHR misses 681system.cpu.l2cache.overall_mshr_misses::total 130545 # number of overall MSHR misses 682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164482000 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 778171500 # number of ReadReq MSHR miss cycles 684system.cpu.l2cache.ReadReq_mshr_miss_latency::total 942653500 # number of ReadReq MSHR miss cycles 685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 567000 # number of UpgradeReq MSHR miss cycles 686system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 567000 # number of UpgradeReq MSHR miss cycles 687system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3395437000 # number of ReadExReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3395437000 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164482000 # number of demand (read+write) MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4173608500 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::total 4338090500 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164482000 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4173608500 # number of overall MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::total 4338090500 # number of overall MSHR miss cycles 695system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416473 # mshr miss rate for ReadReq accesses 697system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.327187 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses 699system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses 700system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955983 # mshr miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955983 # mshr miss rate for ReadExReq accesses 702system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for demand accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771624 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::total 0.675325 # mshr miss rate for demand accesses 705system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for overall accesses 706system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771624 # mshr miss rate for overall accesses 707system.cpu.l2cache.overall_mshr_miss_rate::total 0.675325 # mshr miss rate for overall accesses 708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32302.042419 # average ReadReq mshr miss latency 709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33631.752960 # average ReadReq mshr miss latency 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33391.905774 # average ReadReq mshr miss latency 711system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31500 # average UpgradeReq mshr miss latency 712system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31500 # average UpgradeReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33186.111518 # average ReadExReq mshr miss latency 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33186.111518 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32302.042419 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33268.303668 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33230.613965 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32302.042419 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33268.303668 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33230.613965 # average overall mshr miss latency |
| 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 722 723---------- End Simulation Statistics ---------- | 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 722 723---------- End Simulation Statistics ---------- |