| stats.txt (9223:be1c1059438b) | stats.txt (9229:65f927bda74d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.024460 # Number of seconds simulated 4sim_ticks 24460150500 # Number of ticks simulated 5final_tick 24460150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.024450 # Number of seconds simulated 4sim_ticks 24450292500 # Number of ticks simulated 5final_tick 24450292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 167024 # Simulator instruction rate (inst/s) 8host_op_rate 237012 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57603012 # Simulator tick rate (ticks/s) 10host_mem_usage 242500 # Number of bytes of host memory used 11host_seconds 424.63 # Real time elapsed on the host 12sim_insts 70923824 # Number of instructions simulated 13sim_ops 100643071 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8028736 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5417152 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5417152 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125449 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 84643 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 84643 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 13367702 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 328237392 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 341605094 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 13367702 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 13367702 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 221468466 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 221468466 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 221468466 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 13367702 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 328237392 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 563073559 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 166577 # Simulator instruction rate (inst/s) 8host_op_rate 236377 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57425524 # Simulator tick rate (ticks/s) 10host_mem_usage 242552 # Number of bytes of host memory used 11host_seconds 425.77 # Real time elapsed on the host 12sim_insts 70924074 # Number of instructions simulated 13sim_ops 100643321 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 328512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8029568 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8358080 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 328512 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 328512 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5417984 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5417984 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 5133 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125462 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 130595 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 84656 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 84656 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 13435913 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 328403760 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 341839673 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 13435913 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 13435913 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 221591787 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 221591787 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 221591787 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 13435913 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 328403760 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 563431460 # Total bandwidth to/from this memory (bytes/s) |
| 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 1946 # Number of system calls | 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 80system.cpu.numCycles 48920302 # number of cpu cycles simulated | 80system.cpu.numCycles 48900586 # number of cpu cycles simulated |
| 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 83system.cpu.BPredUnit.lookups 16960531 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 12985874 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 661473 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 11570513 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 7976664 # Number of BTB hits | 83system.cpu.BPredUnit.lookups 16947895 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 12979317 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 657239 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 11568375 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 7965689 # Number of BTB hits |
| 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 89system.cpu.BPredUnit.usedRAS 1883015 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 115088 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 12843999 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 87580035 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 16960531 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 9859679 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 21787094 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 2782746 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 10982319 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 606 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 12079139 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 221673 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 47647021 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.582724 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.336366 # Number of instructions fetched each cycle (Total) | 89system.cpu.BPredUnit.usedRAS 1878366 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 114401 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 12822432 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 87522774 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 16947895 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 9844055 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 21770954 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 2772902 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 11003856 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 471 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 12059223 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 218909 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 47624951 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.582857 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.336628 # Number of instructions fetched each cycle (Total) |
| 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 106system.cpu.fetch.rateDist::0 25881368 54.32% 54.32% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 2178299 4.57% 58.89% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 2007274 4.21% 63.10% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 2021463 4.24% 67.35% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 1548956 3.25% 70.60% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 1412983 2.97% 73.56% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 995678 2.09% 75.65% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 1240946 2.60% 78.26% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 10360054 21.74% 100.00% # Number of instructions fetched each cycle (Total) | 106system.cpu.fetch.rateDist::0 25875265 54.33% 54.33% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 2171829 4.56% 58.89% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 2001256 4.20% 63.09% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 2024856 4.25% 67.35% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 1547627 3.25% 70.59% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 1411228 2.96% 73.56% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 995461 2.09% 75.65% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 1239299 2.60% 78.25% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 10358130 21.75% 100.00% # Number of instructions fetched each cycle (Total) |
| 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 118system.cpu.fetch.rateDist::total 47647021 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.346697 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.790259 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 15031484 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 9298191 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 19969978 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 1421734 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 1925634 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 3462876 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 109476 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 120212842 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 378015 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 1925634 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 16795731 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 2963104 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 805180 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 19544890 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 5612482 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 117675747 # Number of instructions processed by rename | 118system.cpu.fetch.rateDist::total 47624951 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.346579 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.789810 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 15015037 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 9311189 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 19956662 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 1421851 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 1920212 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 3461414 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 109087 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 120161085 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 377153 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 1920212 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 16781785 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 2961677 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 806772 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 19529075 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 5625430 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 117632333 # Number of instructions processed by rename |
| 137system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full | 137system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full |
| 138system.cpu.rename.IQFullEvents 12709 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 4780104 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 263 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 117787272 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 541948309 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 541940540 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 99158584 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 18628688 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 37002 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 36987 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 13169886 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 30082364 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 22781735 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 3607820 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 4315548 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 113341575 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 51734 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 108469975 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 351751 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 12575588 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 30093615 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 14709 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 47647021 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 2.276532 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.995144 # Number of insts issued each cycle | 138system.cpu.rename.IQFullEvents 12238 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 4786667 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 232 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 117758479 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 541753123 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 541746251 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 6872 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 99158984 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 18599495 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 37350 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 37333 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 13184553 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 30073818 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 22775187 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 3642294 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 4290989 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 113312109 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 51967 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 108452712 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 348423 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 12547190 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 29979206 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 14892 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 47624951 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 2.277225 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.996410 # Number of insts issued each cycle |
| 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 165system.cpu.iq.issued_per_cycle::0 11903537 24.98% 24.98% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 8354851 17.53% 42.52% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 7454693 15.65% 58.16% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 7158692 15.02% 73.19% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 5519097 11.58% 84.77% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 3907609 8.20% 92.97% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 1895733 3.98% 96.95% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 881641 1.85% 98.80% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 571168 1.20% 100.00% # Number of insts issued each cycle | 165system.cpu.iq.issued_per_cycle::0 11905380 25.00% 25.00% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 8338489 17.51% 42.51% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 7455711 15.66% 58.16% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 7146400 15.01% 73.17% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 5525482 11.60% 84.77% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 3896676 8.18% 92.95% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 1895621 3.98% 96.93% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 884969 1.86% 98.79% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 576223 1.21% 100.00% # Number of insts issued each cycle |
| 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 177system.cpu.iq.issued_per_cycle::total 47647021 # Number of insts issued each cycle | 177system.cpu.iq.issued_per_cycle::total 47624951 # Number of insts issued each cycle |
| 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 179system.cpu.iq.fu_full::IntAlu 112989 4.45% 4.45% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 0 0.00% 4.45% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 4.45% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.45% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.45% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.45% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 4.45% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.45% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.45% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.45% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.45% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.45% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.45% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.45% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.45% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 4.45% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.45% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 4.45% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.45% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.45% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.45% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.45% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.45% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.45% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.45% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.45% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.45% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.45% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.45% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 1419251 55.85% 60.30% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 1008989 39.70% 100.00% # attempts to use FU when none available | 179system.cpu.iq.fu_full::IntAlu 113237 4.46% 4.46% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 0 0.00% 4.46% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 4.46% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.46% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.46% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.46% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 4.46% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.46% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.46% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.46% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.46% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.46% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.46% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.46% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.46% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 4.46% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.46% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 4.46% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.46% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.46% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.46% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.46% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.46% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.46% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.46% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.46% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.46% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.46% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.46% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 1413224 55.65% 60.11% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 1012935 39.89% 100.00% # attempts to use FU when none available |
| 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 213system.cpu.iq.FU_type_0::IntAlu 57363382 52.88% 52.88% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 91507 0.08% 52.97% # Type of FU issued | 213system.cpu.iq.FU_type_0::IntAlu 57358153 52.89% 52.89% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 91504 0.08% 52.97% # Type of FU issued |
| 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued | 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued |
| 216system.cpu.iq.FU_type_0::FloatAdd 228 0.00% 52.97% # Type of FU issued | 216system.cpu.iq.FU_type_0::FloatAdd 207 0.00% 52.97% # Type of FU issued |
| 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.97% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.97% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.97% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.97% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.97% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.97% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.97% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.97% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.97% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued | 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.97% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.97% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.97% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.97% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.97% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.97% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.97% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.97% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.97% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued |
| 242system.cpu.iq.FU_type_0::MemRead 29217041 26.94% 79.90% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 21797810 20.10% 100.00% # Type of FU issued | 242system.cpu.iq.FU_type_0::MemRead 29210718 26.93% 79.91% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 21792123 20.09% 100.00% # Type of FU issued |
| 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 246system.cpu.iq.FU_type_0::total 108469975 # Type of FU issued 247system.cpu.iq.rate 2.217279 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 2541231 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.023428 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 267479180 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 125995514 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 106424512 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 773 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 1272 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 111010818 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 388 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 2214998 # Number of loads that had data forwarded from stores | 246system.cpu.iq.FU_type_0::total 108452712 # Type of FU issued 247system.cpu.iq.rate 2.217820 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 2539396 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.023415 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 267417480 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 125938241 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 106420258 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 714 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 1140 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 175 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 110991749 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 359 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 2211393 # Number of loads that had data forwarded from stores |
| 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 260system.cpu.iew.lsq.thread0.squashedLoads 2772017 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 7458 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 29087 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 2222758 # Number of stores squashed | 260system.cpu.iew.lsq.thread0.squashedLoads 2763421 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 7106 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 29349 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 2216160 # Number of stores squashed |
| 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 266system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled | 266system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled |
| 267system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 267system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 269system.cpu.iew.iewSquashCycles 1925634 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 929341 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 37355 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 113473181 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 343640 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 30082364 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 22781735 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 35157 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 2560 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 3541 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 29087 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 428613 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 264355 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 692968 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 107247329 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 28841677 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 1222646 # Number of squashed instructions skipped in execute | 269system.cpu.iew.iewSquashCycles 1920212 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 926920 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 38130 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 113444221 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 341894 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 30073818 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 22775187 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 35362 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 2649 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 29349 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 424803 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 263892 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 688695 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 107241565 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 28837233 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 1211147 # Number of squashed instructions skipped in execute |
| 286system.cpu.iew.exec_swp 0 # number of swp insts executed | 286system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 287system.cpu.iew.exec_nop 79872 # number of nop insts executed 288system.cpu.iew.exec_refs 50315882 # number of memory reference insts executed 289system.cpu.iew.exec_branches 14663606 # Number of branches executed 290system.cpu.iew.exec_stores 21474205 # Number of stores executed 291system.cpu.iew.exec_rate 2.192287 # Inst execution rate 292system.cpu.iew.wb_sent 106761196 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 106424699 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 53424049 # num instructions producing a value 295system.cpu.iew.wb_consumers 103788661 # num instructions consuming a value | 287system.cpu.iew.exec_nop 80145 # number of nop insts executed 288system.cpu.iew.exec_refs 50314250 # number of memory reference insts executed 289system.cpu.iew.exec_branches 14661458 # Number of branches executed 290system.cpu.iew.exec_stores 21477017 # Number of stores executed 291system.cpu.iew.exec_rate 2.193053 # Inst execution rate 292system.cpu.iew.wb_sent 106757510 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 106420433 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 53411369 # num instructions producing a value 295system.cpu.iew.wb_consumers 103767535 # num instructions consuming a value |
| 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 297system.cpu.iew.wb_rate 2.175471 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.514739 # average fanout of values written-back | 297system.cpu.iew.wb_rate 2.176261 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.514721 # average fanout of values written-back |
| 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 300system.cpu.commit.commitSquashedInsts 12825262 # The number of squashed insts skipped by commit 301system.cpu.commit.commitNonSpecStalls 37025 # The number of times commit has been forced to stall to communicate backwards 302system.cpu.commit.branchMispredicts 616891 # The number of times a branch was mispredicted 303system.cpu.commit.committed_per_cycle::samples 45721388 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::mean 2.201347 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::stdev 2.733819 # Number of insts commited each cycle | 300system.cpu.commit.commitSquashedInsts 12796121 # The number of squashed insts skipped by commit 301system.cpu.commit.commitNonSpecStalls 37075 # The number of times commit has been forced to stall to communicate backwards 302system.cpu.commit.branchMispredicts 612942 # The number of times a branch was mispredicted 303system.cpu.commit.committed_per_cycle::samples 45704740 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::mean 2.202154 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::stdev 2.735561 # Number of insts commited each cycle |
| 306system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 306system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 307system.cpu.commit.committed_per_cycle::0 16264410 35.57% 35.57% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::1 11914734 26.06% 61.63% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::2 3626051 7.93% 69.56% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::3 2926022 6.40% 75.96% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::4 1880797 4.11% 80.08% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::5 1911030 4.18% 84.26% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::6 689200 1.51% 85.76% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::7 582969 1.28% 87.04% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::8 5926175 12.96% 100.00% # Number of insts commited each cycle | 307system.cpu.commit.committed_per_cycle::0 16269057 35.60% 35.60% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::1 11908776 26.06% 61.65% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::2 3615674 7.91% 69.56% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::3 2919531 6.39% 75.95% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::4 1872792 4.10% 80.05% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::5 1908851 4.18% 84.22% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::6 687748 1.50% 85.73% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::7 590243 1.29% 87.02% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::8 5932068 12.98% 100.00% # Number of insts commited each cycle |
| 316system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 316system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 319system.cpu.commit.committed_per_cycle::total 45721388 # Number of insts commited each cycle 320system.cpu.commit.committedInsts 70929376 # Number of instructions committed 321system.cpu.commit.committedOps 100648623 # Number of ops (including micro ops) committed | 319system.cpu.commit.committed_per_cycle::total 45704740 # Number of insts commited each cycle 320system.cpu.commit.committedInsts 70929626 # Number of instructions committed 321system.cpu.commit.committedOps 100648873 # Number of ops (including micro ops) committed |
| 322system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 322system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 323system.cpu.commit.refs 47869324 # Number of memory references committed 324system.cpu.commit.loads 27310347 # Number of loads committed | 323system.cpu.commit.refs 47869424 # Number of memory references committed 324system.cpu.commit.loads 27310397 # Number of loads committed |
| 325system.cpu.commit.membars 15920 # Number of memory barriers committed | 325system.cpu.commit.membars 15920 # Number of memory barriers committed |
| 326system.cpu.commit.branches 13671866 # Number of branches committed | 326system.cpu.commit.branches 13671916 # Number of branches committed |
| 327system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. | 327system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. |
| 328system.cpu.commit.int_insts 91485735 # Number of committed integer instructions. | 328system.cpu.commit.int_insts 91485935 # Number of committed integer instructions. |
| 329system.cpu.commit.function_calls 1679850 # Number of function calls committed. | 329system.cpu.commit.function_calls 1679850 # Number of function calls committed. |
| 330system.cpu.commit.bw_lim_events 5926175 # number cycles where commit BW limit reached | 330system.cpu.commit.bw_lim_events 5932068 # number cycles where commit BW limit reached |
| 331system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 331system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 332system.cpu.rob.rob_reads 153243799 # The number of ROB reads 333system.cpu.rob.rob_writes 228884039 # The number of ROB writes 334system.cpu.timesIdled 52429 # Number of times that the entire CPU went into an idle state and unscheduled itself 335system.cpu.idleCycles 1273281 # Total number of cycles that the CPU has spent unscheduled due to idling 336system.cpu.committedInsts 70923824 # Number of Instructions Simulated 337system.cpu.committedOps 100643071 # Number of Ops (including micro ops) Simulated 338system.cpu.committedInsts_total 70923824 # Number of Instructions Simulated 339system.cpu.cpi 0.689758 # CPI: Cycles Per Instruction 340system.cpu.cpi_total 0.689758 # CPI: Total CPI of All Threads 341system.cpu.ipc 1.449783 # IPC: Instructions Per Cycle 342system.cpu.ipc_total 1.449783 # IPC: Total IPC of All Threads 343system.cpu.int_regfile_reads 516242048 # number of integer regfile reads 344system.cpu.int_regfile_writes 104369908 # number of integer regfile writes 345system.cpu.fp_regfile_reads 886 # number of floating regfile reads 346system.cpu.fp_regfile_writes 750 # number of floating regfile writes 347system.cpu.misc_regfile_reads 146091713 # number of misc regfile reads 348system.cpu.misc_regfile_writes 38318 # number of misc regfile writes 349system.cpu.icache.replacements 30244 # number of replacements 350system.cpu.icache.tagsinuse 1815.033473 # Cycle average of tags in use 351system.cpu.icache.total_refs 12045499 # Total number of references to valid blocks. 352system.cpu.icache.sampled_refs 32282 # Sample count of references to valid blocks. 353system.cpu.icache.avg_refs 373.133604 # Average number of references to valid blocks. | 332system.cpu.rob.rob_reads 153192367 # The number of ROB reads 333system.cpu.rob.rob_writes 228820850 # The number of ROB writes 334system.cpu.timesIdled 52344 # Number of times that the entire CPU went into an idle state and unscheduled itself 335system.cpu.idleCycles 1275635 # Total number of cycles that the CPU has spent unscheduled due to idling 336system.cpu.committedInsts 70924074 # Number of Instructions Simulated 337system.cpu.committedOps 100643321 # Number of Ops (including micro ops) Simulated 338system.cpu.committedInsts_total 70924074 # Number of Instructions Simulated 339system.cpu.cpi 0.689478 # CPI: Cycles Per Instruction 340system.cpu.cpi_total 0.689478 # CPI: Total CPI of All Threads 341system.cpu.ipc 1.450373 # IPC: Instructions Per Cycle 342system.cpu.ipc_total 1.450373 # IPC: Total IPC of All Threads 343system.cpu.int_regfile_reads 516213591 # number of integer regfile reads 344system.cpu.int_regfile_writes 104366681 # number of integer regfile writes 345system.cpu.fp_regfile_reads 794 # number of floating regfile reads 346system.cpu.fp_regfile_writes 662 # number of floating regfile writes 347system.cpu.misc_regfile_reads 146023696 # number of misc regfile reads 348system.cpu.misc_regfile_writes 38418 # number of misc regfile writes 349system.cpu.icache.replacements 30034 # number of replacements 350system.cpu.icache.tagsinuse 1814.104659 # Cycle average of tags in use 351system.cpu.icache.total_refs 12025772 # Total number of references to valid blocks. 352system.cpu.icache.sampled_refs 32074 # Sample count of references to valid blocks. 353system.cpu.icache.avg_refs 374.938330 # Average number of references to valid blocks. |
| 354system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 354system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 355system.cpu.icache.occ_blocks::cpu.inst 1815.033473 # Average occupied blocks per requestor 356system.cpu.icache.occ_percent::cpu.inst 0.886247 # Average percentage of cache occupancy 357system.cpu.icache.occ_percent::total 0.886247 # Average percentage of cache occupancy 358system.cpu.icache.ReadReq_hits::cpu.inst 12045501 # number of ReadReq hits 359system.cpu.icache.ReadReq_hits::total 12045501 # number of ReadReq hits 360system.cpu.icache.demand_hits::cpu.inst 12045501 # number of demand (read+write) hits 361system.cpu.icache.demand_hits::total 12045501 # number of demand (read+write) hits 362system.cpu.icache.overall_hits::cpu.inst 12045501 # number of overall hits 363system.cpu.icache.overall_hits::total 12045501 # number of overall hits 364system.cpu.icache.ReadReq_misses::cpu.inst 33638 # number of ReadReq misses 365system.cpu.icache.ReadReq_misses::total 33638 # number of ReadReq misses 366system.cpu.icache.demand_misses::cpu.inst 33638 # number of demand (read+write) misses 367system.cpu.icache.demand_misses::total 33638 # number of demand (read+write) misses 368system.cpu.icache.overall_misses::cpu.inst 33638 # number of overall misses 369system.cpu.icache.overall_misses::total 33638 # number of overall misses 370system.cpu.icache.ReadReq_miss_latency::cpu.inst 406685000 # number of ReadReq miss cycles 371system.cpu.icache.ReadReq_miss_latency::total 406685000 # number of ReadReq miss cycles 372system.cpu.icache.demand_miss_latency::cpu.inst 406685000 # number of demand (read+write) miss cycles 373system.cpu.icache.demand_miss_latency::total 406685000 # number of demand (read+write) miss cycles 374system.cpu.icache.overall_miss_latency::cpu.inst 406685000 # number of overall miss cycles 375system.cpu.icache.overall_miss_latency::total 406685000 # number of overall miss cycles 376system.cpu.icache.ReadReq_accesses::cpu.inst 12079139 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.ReadReq_accesses::total 12079139 # number of ReadReq accesses(hits+misses) 378system.cpu.icache.demand_accesses::cpu.inst 12079139 # number of demand (read+write) accesses 379system.cpu.icache.demand_accesses::total 12079139 # number of demand (read+write) accesses 380system.cpu.icache.overall_accesses::cpu.inst 12079139 # number of overall (read+write) accesses 381system.cpu.icache.overall_accesses::total 12079139 # number of overall (read+write) accesses 382system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002785 # miss rate for ReadReq accesses 383system.cpu.icache.ReadReq_miss_rate::total 0.002785 # miss rate for ReadReq accesses 384system.cpu.icache.demand_miss_rate::cpu.inst 0.002785 # miss rate for demand accesses 385system.cpu.icache.demand_miss_rate::total 0.002785 # miss rate for demand accesses 386system.cpu.icache.overall_miss_rate::cpu.inst 0.002785 # miss rate for overall accesses 387system.cpu.icache.overall_miss_rate::total 0.002785 # miss rate for overall accesses 388system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12090.046971 # average ReadReq miss latency 389system.cpu.icache.ReadReq_avg_miss_latency::total 12090.046971 # average ReadReq miss latency 390system.cpu.icache.demand_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency 391system.cpu.icache.demand_avg_miss_latency::total 12090.046971 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency 393system.cpu.icache.overall_avg_miss_latency::total 12090.046971 # average overall miss latency | 355system.cpu.icache.occ_blocks::cpu.inst 1814.104659 # Average occupied blocks per requestor 356system.cpu.icache.occ_percent::cpu.inst 0.885793 # Average percentage of cache occupancy 357system.cpu.icache.occ_percent::total 0.885793 # Average percentage of cache occupancy 358system.cpu.icache.ReadReq_hits::cpu.inst 12025773 # number of ReadReq hits 359system.cpu.icache.ReadReq_hits::total 12025773 # number of ReadReq hits 360system.cpu.icache.demand_hits::cpu.inst 12025773 # number of demand (read+write) hits 361system.cpu.icache.demand_hits::total 12025773 # number of demand (read+write) hits 362system.cpu.icache.overall_hits::cpu.inst 12025773 # number of overall hits 363system.cpu.icache.overall_hits::total 12025773 # number of overall hits 364system.cpu.icache.ReadReq_misses::cpu.inst 33450 # number of ReadReq misses 365system.cpu.icache.ReadReq_misses::total 33450 # number of ReadReq misses 366system.cpu.icache.demand_misses::cpu.inst 33450 # number of demand (read+write) misses 367system.cpu.icache.demand_misses::total 33450 # number of demand (read+write) misses 368system.cpu.icache.overall_misses::cpu.inst 33450 # number of overall misses 369system.cpu.icache.overall_misses::total 33450 # number of overall misses 370system.cpu.icache.ReadReq_miss_latency::cpu.inst 407167500 # number of ReadReq miss cycles 371system.cpu.icache.ReadReq_miss_latency::total 407167500 # number of ReadReq miss cycles 372system.cpu.icache.demand_miss_latency::cpu.inst 407167500 # number of demand (read+write) miss cycles 373system.cpu.icache.demand_miss_latency::total 407167500 # number of demand (read+write) miss cycles 374system.cpu.icache.overall_miss_latency::cpu.inst 407167500 # number of overall miss cycles 375system.cpu.icache.overall_miss_latency::total 407167500 # number of overall miss cycles 376system.cpu.icache.ReadReq_accesses::cpu.inst 12059223 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.ReadReq_accesses::total 12059223 # number of ReadReq accesses(hits+misses) 378system.cpu.icache.demand_accesses::cpu.inst 12059223 # number of demand (read+write) accesses 379system.cpu.icache.demand_accesses::total 12059223 # number of demand (read+write) accesses 380system.cpu.icache.overall_accesses::cpu.inst 12059223 # number of overall (read+write) accesses 381system.cpu.icache.overall_accesses::total 12059223 # number of overall (read+write) accesses 382system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002774 # miss rate for ReadReq accesses 383system.cpu.icache.ReadReq_miss_rate::total 0.002774 # miss rate for ReadReq accesses 384system.cpu.icache.demand_miss_rate::cpu.inst 0.002774 # miss rate for demand accesses 385system.cpu.icache.demand_miss_rate::total 0.002774 # miss rate for demand accesses 386system.cpu.icache.overall_miss_rate::cpu.inst 0.002774 # miss rate for overall accesses 387system.cpu.icache.overall_miss_rate::total 0.002774 # miss rate for overall accesses 388system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12172.421525 # average ReadReq miss latency 389system.cpu.icache.ReadReq_avg_miss_latency::total 12172.421525 # average ReadReq miss latency 390system.cpu.icache.demand_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency 391system.cpu.icache.demand_avg_miss_latency::total 12172.421525 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency 393system.cpu.icache.overall_avg_miss_latency::total 12172.421525 # average overall miss latency |
| 394system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 395system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 399system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 400system.cpu.icache.fast_writes 0 # number of fast writes performed 401system.cpu.icache.cache_copies 0 # number of cache copies performed | 394system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 395system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 399system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 400system.cpu.icache.fast_writes 0 # number of fast writes performed 401system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 402system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1313 # number of ReadReq MSHR hits 403system.cpu.icache.ReadReq_mshr_hits::total 1313 # number of ReadReq MSHR hits 404system.cpu.icache.demand_mshr_hits::cpu.inst 1313 # number of demand (read+write) MSHR hits 405system.cpu.icache.demand_mshr_hits::total 1313 # number of demand (read+write) MSHR hits 406system.cpu.icache.overall_mshr_hits::cpu.inst 1313 # number of overall MSHR hits 407system.cpu.icache.overall_mshr_hits::total 1313 # number of overall MSHR hits 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32325 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 32325 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 32325 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 32325 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 32325 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 32325 # number of overall MSHR misses 414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 274223500 # number of ReadReq MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_latency::total 274223500 # number of ReadReq MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 274223500 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::total 274223500 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 274223500 # number of overall MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::total 274223500 # number of overall MSHR miss cycles 420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses 421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses 422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses 423system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8483.325599 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8483.325599 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency | 402system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1320 # number of ReadReq MSHR hits 403system.cpu.icache.ReadReq_mshr_hits::total 1320 # number of ReadReq MSHR hits 404system.cpu.icache.demand_mshr_hits::cpu.inst 1320 # number of demand (read+write) MSHR hits 405system.cpu.icache.demand_mshr_hits::total 1320 # number of demand (read+write) MSHR hits 406system.cpu.icache.overall_mshr_hits::cpu.inst 1320 # number of overall MSHR hits 407system.cpu.icache.overall_mshr_hits::total 1320 # number of overall MSHR hits 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32130 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 32130 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 32130 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 32130 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 32130 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 32130 # number of overall MSHR misses 414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275291000 # number of ReadReq MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_latency::total 275291000 # number of ReadReq MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275291000 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::total 275291000 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275291000 # number of overall MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::total 275291000 # number of overall MSHR miss cycles 420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for ReadReq accesses 421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002664 # mshr miss rate for ReadReq accesses 422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for demand accesses 423system.cpu.icache.demand_mshr_miss_rate::total 0.002664 # mshr miss rate for demand accesses 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.002664 # mshr miss rate for overall accesses 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8568.036103 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8568.036103 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency |
| 432system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 432system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 433system.cpu.dcache.replacements 158501 # number of replacements 434system.cpu.dcache.tagsinuse 4071.855185 # Cycle average of tags in use 435system.cpu.dcache.total_refs 44605412 # Total number of references to valid blocks. 436system.cpu.dcache.sampled_refs 162597 # Sample count of references to valid blocks. 437system.cpu.dcache.avg_refs 274.331089 # Average number of references to valid blocks. | 433system.cpu.dcache.replacements 158627 # number of replacements 434system.cpu.dcache.tagsinuse 4071.845451 # Cycle average of tags in use 435system.cpu.dcache.total_refs 44602467 # Total number of references to valid blocks. 436system.cpu.dcache.sampled_refs 162723 # Sample count of references to valid blocks. 437system.cpu.dcache.avg_refs 274.100570 # Average number of references to valid blocks. |
| 438system.cpu.dcache.warmup_cycle 272454000 # Cycle when the warmup percentage was hit. | 438system.cpu.dcache.warmup_cycle 272454000 # Cycle when the warmup percentage was hit. |
| 439system.cpu.dcache.occ_blocks::cpu.data 4071.855185 # Average occupied blocks per requestor 440system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy 441system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy 442system.cpu.dcache.ReadReq_hits::cpu.data 26278291 # number of ReadReq hits 443system.cpu.dcache.ReadReq_hits::total 26278291 # number of ReadReq hits 444system.cpu.dcache.WriteReq_hits::cpu.data 18287500 # number of WriteReq hits 445system.cpu.dcache.WriteReq_hits::total 18287500 # number of WriteReq hits 446system.cpu.dcache.LoadLockedReq_hits::cpu.data 20317 # number of LoadLockedReq hits 447system.cpu.dcache.LoadLockedReq_hits::total 20317 # number of LoadLockedReq hits 448system.cpu.dcache.StoreCondReq_hits::cpu.data 19158 # number of StoreCondReq hits 449system.cpu.dcache.StoreCondReq_hits::total 19158 # number of StoreCondReq hits 450system.cpu.dcache.demand_hits::cpu.data 44565791 # number of demand (read+write) hits 451system.cpu.dcache.demand_hits::total 44565791 # number of demand (read+write) hits 452system.cpu.dcache.overall_hits::cpu.data 44565791 # number of overall hits 453system.cpu.dcache.overall_hits::total 44565791 # number of overall hits 454system.cpu.dcache.ReadReq_misses::cpu.data 106674 # number of ReadReq misses 455system.cpu.dcache.ReadReq_misses::total 106674 # number of ReadReq misses 456system.cpu.dcache.WriteReq_misses::cpu.data 1562401 # number of WriteReq misses 457system.cpu.dcache.WriteReq_misses::total 1562401 # number of WriteReq misses 458system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses 459system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses 460system.cpu.dcache.demand_misses::cpu.data 1669075 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 1669075 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 1669075 # number of overall misses 463system.cpu.dcache.overall_misses::total 1669075 # number of overall misses 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 2574319000 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 2574319000 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 63349260500 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 63349260500 # number of WriteReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 629500 # number of LoadLockedReq miss cycles 469system.cpu.dcache.LoadLockedReq_miss_latency::total 629500 # number of LoadLockedReq miss cycles 470system.cpu.dcache.demand_miss_latency::cpu.data 65923579500 # number of demand (read+write) miss cycles 471system.cpu.dcache.demand_miss_latency::total 65923579500 # number of demand (read+write) miss cycles 472system.cpu.dcache.overall_miss_latency::cpu.data 65923579500 # number of overall miss cycles 473system.cpu.dcache.overall_miss_latency::total 65923579500 # number of overall miss cycles 474system.cpu.dcache.ReadReq_accesses::cpu.data 26384965 # number of ReadReq accesses(hits+misses) 475system.cpu.dcache.ReadReq_accesses::total 26384965 # number of ReadReq accesses(hits+misses) | 439system.cpu.dcache.occ_blocks::cpu.data 4071.845451 # Average occupied blocks per requestor 440system.cpu.dcache.occ_percent::cpu.data 0.994103 # Average percentage of cache occupancy 441system.cpu.dcache.occ_percent::total 0.994103 # Average percentage of cache occupancy 442system.cpu.dcache.ReadReq_hits::cpu.data 26277362 # number of ReadReq hits 443system.cpu.dcache.ReadReq_hits::total 26277362 # number of ReadReq hits 444system.cpu.dcache.WriteReq_hits::cpu.data 18285328 # number of WriteReq hits 445system.cpu.dcache.WriteReq_hits::total 18285328 # number of WriteReq hits 446system.cpu.dcache.LoadLockedReq_hits::cpu.data 20388 # number of LoadLockedReq hits 447system.cpu.dcache.LoadLockedReq_hits::total 20388 # number of LoadLockedReq hits 448system.cpu.dcache.StoreCondReq_hits::cpu.data 19208 # number of StoreCondReq hits 449system.cpu.dcache.StoreCondReq_hits::total 19208 # number of StoreCondReq hits 450system.cpu.dcache.demand_hits::cpu.data 44562690 # number of demand (read+write) hits 451system.cpu.dcache.demand_hits::total 44562690 # number of demand (read+write) hits 452system.cpu.dcache.overall_hits::cpu.data 44562690 # number of overall hits 453system.cpu.dcache.overall_hits::total 44562690 # number of overall hits 454system.cpu.dcache.ReadReq_misses::cpu.data 106921 # number of ReadReq misses 455system.cpu.dcache.ReadReq_misses::total 106921 # number of ReadReq misses 456system.cpu.dcache.WriteReq_misses::cpu.data 1564573 # number of WriteReq misses 457system.cpu.dcache.WriteReq_misses::total 1564573 # number of WriteReq misses 458system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses 459system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses 460system.cpu.dcache.demand_misses::cpu.data 1671494 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 1671494 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 1671494 # number of overall misses 463system.cpu.dcache.overall_misses::total 1671494 # number of overall misses 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 2586655500 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 2586655500 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 63403235500 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 63403235500 # number of WriteReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 586000 # number of LoadLockedReq miss cycles 469system.cpu.dcache.LoadLockedReq_miss_latency::total 586000 # number of LoadLockedReq miss cycles 470system.cpu.dcache.demand_miss_latency::cpu.data 65989891000 # number of demand (read+write) miss cycles 471system.cpu.dcache.demand_miss_latency::total 65989891000 # number of demand (read+write) miss cycles 472system.cpu.dcache.overall_miss_latency::cpu.data 65989891000 # number of overall miss cycles 473system.cpu.dcache.overall_miss_latency::total 65989891000 # number of overall miss cycles 474system.cpu.dcache.ReadReq_accesses::cpu.data 26384283 # number of ReadReq accesses(hits+misses) 475system.cpu.dcache.ReadReq_accesses::total 26384283 # number of ReadReq accesses(hits+misses) |
| 476system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 477system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) | 476system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 477system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| 478system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20360 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.LoadLockedReq_accesses::total 20360 # number of LoadLockedReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::cpu.data 19158 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.StoreCondReq_accesses::total 19158 # number of StoreCondReq accesses(hits+misses) 482system.cpu.dcache.demand_accesses::cpu.data 46234866 # number of demand (read+write) accesses 483system.cpu.dcache.demand_accesses::total 46234866 # number of demand (read+write) accesses 484system.cpu.dcache.overall_accesses::cpu.data 46234866 # number of overall (read+write) accesses 485system.cpu.dcache.overall_accesses::total 46234866 # number of overall (read+write) accesses 486system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004043 # miss rate for ReadReq accesses 487system.cpu.dcache.ReadReq_miss_rate::total 0.004043 # miss rate for ReadReq accesses 488system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078711 # miss rate for WriteReq accesses 489system.cpu.dcache.WriteReq_miss_rate::total 0.078711 # miss rate for WriteReq accesses 490system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002112 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002112 # miss rate for LoadLockedReq accesses 492system.cpu.dcache.demand_miss_rate::cpu.data 0.036100 # miss rate for demand accesses 493system.cpu.dcache.demand_miss_rate::total 0.036100 # miss rate for demand accesses 494system.cpu.dcache.overall_miss_rate::cpu.data 0.036100 # miss rate for overall accesses 495system.cpu.dcache.overall_miss_rate::total 0.036100 # miss rate for overall accesses 496system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24132.581510 # average ReadReq miss latency 497system.cpu.dcache.ReadReq_avg_miss_latency::total 24132.581510 # average ReadReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40546.095721 # average WriteReq miss latency 499system.cpu.dcache.WriteReq_avg_miss_latency::total 40546.095721 # average WriteReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14639.534884 # average LoadLockedReq miss latency 501system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14639.534884 # average LoadLockedReq miss latency 502system.cpu.dcache.demand_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency 503system.cpu.dcache.demand_avg_miss_latency::total 39497.074427 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::total 39497.074427 # average overall miss latency | 478system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20429 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.LoadLockedReq_accesses::total 20429 # number of LoadLockedReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::cpu.data 19208 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.StoreCondReq_accesses::total 19208 # number of StoreCondReq accesses(hits+misses) 482system.cpu.dcache.demand_accesses::cpu.data 46234184 # number of demand (read+write) accesses 483system.cpu.dcache.demand_accesses::total 46234184 # number of demand (read+write) accesses 484system.cpu.dcache.overall_accesses::cpu.data 46234184 # number of overall (read+write) accesses 485system.cpu.dcache.overall_accesses::total 46234184 # number of overall (read+write) accesses 486system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004052 # miss rate for ReadReq accesses 487system.cpu.dcache.ReadReq_miss_rate::total 0.004052 # miss rate for ReadReq accesses 488system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078820 # miss rate for WriteReq accesses 489system.cpu.dcache.WriteReq_miss_rate::total 0.078820 # miss rate for WriteReq accesses 490system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002007 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002007 # miss rate for LoadLockedReq accesses 492system.cpu.dcache.demand_miss_rate::cpu.data 0.036153 # miss rate for demand accesses 493system.cpu.dcache.demand_miss_rate::total 0.036153 # miss rate for demand accesses 494system.cpu.dcache.overall_miss_rate::cpu.data 0.036153 # miss rate for overall accesses 495system.cpu.dcache.overall_miss_rate::total 0.036153 # miss rate for overall accesses 496system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24192.212007 # average ReadReq miss latency 497system.cpu.dcache.ReadReq_avg_miss_latency::total 24192.212007 # average ReadReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40524.306312 # average WriteReq miss latency 499system.cpu.dcache.WriteReq_avg_miss_latency::total 40524.306312 # average WriteReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14292.682927 # average LoadLockedReq miss latency 501system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14292.682927 # average LoadLockedReq miss latency 502system.cpu.dcache.demand_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency 503system.cpu.dcache.demand_avg_miss_latency::total 39479.585927 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::total 39479.585927 # average overall miss latency |
| 506system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 506system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 507system.cpu.dcache.blocked_cycles::no_targets 202500 # number of cycles access was blocked | 507system.cpu.dcache.blocked_cycles::no_targets 210000 # number of cycles access was blocked |
| 508system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 509system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked 510system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 508system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 509system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked 510system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 511system.cpu.dcache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked | 511system.cpu.dcache.avg_blocked_cycles::no_targets 19090.909091 # average number of cycles each access was blocked |
| 512system.cpu.dcache.fast_writes 0 # number of fast writes performed 513system.cpu.dcache.cache_copies 0 # number of cache copies performed | 512system.cpu.dcache.fast_writes 0 # number of fast writes performed 513system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 514system.cpu.dcache.writebacks::writebacks 128059 # number of writebacks 515system.cpu.dcache.writebacks::total 128059 # number of writebacks 516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51068 # number of ReadReq MSHR hits 517system.cpu.dcache.ReadReq_mshr_hits::total 51068 # number of ReadReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1455366 # number of WriteReq MSHR hits 519system.cpu.dcache.WriteReq_mshr_hits::total 1455366 # number of WriteReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits 521system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits 522system.cpu.dcache.demand_mshr_hits::cpu.data 1506434 # number of demand (read+write) MSHR hits 523system.cpu.dcache.demand_mshr_hits::total 1506434 # number of demand (read+write) MSHR hits 524system.cpu.dcache.overall_mshr_hits::cpu.data 1506434 # number of overall MSHR hits 525system.cpu.dcache.overall_mshr_hits::total 1506434 # number of overall MSHR hits 526system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55606 # number of ReadReq MSHR misses 527system.cpu.dcache.ReadReq_mshr_misses::total 55606 # number of ReadReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107035 # number of WriteReq MSHR misses 529system.cpu.dcache.WriteReq_mshr_misses::total 107035 # number of WriteReq MSHR misses 530system.cpu.dcache.demand_mshr_misses::cpu.data 162641 # number of demand (read+write) MSHR misses 531system.cpu.dcache.demand_mshr_misses::total 162641 # number of demand (read+write) MSHR misses 532system.cpu.dcache.overall_mshr_misses::cpu.data 162641 # number of overall MSHR misses 533system.cpu.dcache.overall_mshr_misses::total 162641 # number of overall MSHR misses 534system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 982100000 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.ReadReq_mshr_miss_latency::total 982100000 # number of ReadReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3836030000 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.WriteReq_mshr_miss_latency::total 3836030000 # number of WriteReq MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4818130000 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.demand_mshr_miss_latency::total 4818130000 # number of demand (read+write) MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4818130000 # number of overall MSHR miss cycles 541system.cpu.dcache.overall_mshr_miss_latency::total 4818130000 # number of overall MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002107 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002107 # mshr miss rate for ReadReq accesses 544system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 546system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses 547system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses 548system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses 549system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17661.763119 # average ReadReq mshr miss latency 551system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17661.763119 # average ReadReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35839.024618 # average WriteReq mshr miss latency 553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35839.024618 # average WriteReq mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency 555system.cpu.dcache.demand_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency 557system.cpu.dcache.overall_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency | 514system.cpu.dcache.writebacks::writebacks 128131 # number of writebacks 515system.cpu.dcache.writebacks::total 128131 # number of writebacks 516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51186 # number of ReadReq MSHR hits 517system.cpu.dcache.ReadReq_mshr_hits::total 51186 # number of ReadReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457528 # number of WriteReq MSHR hits 519system.cpu.dcache.WriteReq_mshr_hits::total 1457528 # number of WriteReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits 521system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits 522system.cpu.dcache.demand_mshr_hits::cpu.data 1508714 # number of demand (read+write) MSHR hits 523system.cpu.dcache.demand_mshr_hits::total 1508714 # number of demand (read+write) MSHR hits 524system.cpu.dcache.overall_mshr_hits::cpu.data 1508714 # number of overall MSHR hits 525system.cpu.dcache.overall_mshr_hits::total 1508714 # number of overall MSHR hits 526system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55735 # number of ReadReq MSHR misses 527system.cpu.dcache.ReadReq_mshr_misses::total 55735 # number of ReadReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107045 # number of WriteReq MSHR misses 529system.cpu.dcache.WriteReq_mshr_misses::total 107045 # number of WriteReq MSHR misses 530system.cpu.dcache.demand_mshr_misses::cpu.data 162780 # number of demand (read+write) MSHR misses 531system.cpu.dcache.demand_mshr_misses::total 162780 # number of demand (read+write) MSHR misses 532system.cpu.dcache.overall_mshr_misses::cpu.data 162780 # number of overall MSHR misses 533system.cpu.dcache.overall_mshr_misses::total 162780 # number of overall MSHR misses 534system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 988383500 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.ReadReq_mshr_miss_latency::total 988383500 # number of ReadReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3842536000 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.WriteReq_mshr_miss_latency::total 3842536000 # number of WriteReq MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4830919500 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.demand_mshr_miss_latency::total 4830919500 # number of demand (read+write) MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4830919500 # number of overall MSHR miss cycles 541system.cpu.dcache.overall_mshr_miss_latency::total 4830919500 # number of overall MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses 544system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005393 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005393 # mshr miss rate for WriteReq accesses 546system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for demand accesses 547system.cpu.dcache.demand_mshr_miss_rate::total 0.003521 # mshr miss rate for demand accesses 548system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for overall accesses 549system.cpu.dcache.overall_mshr_miss_rate::total 0.003521 # mshr miss rate for overall accesses 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17733.623396 # average ReadReq mshr miss latency 551system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17733.623396 # average ReadReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35896.454762 # average WriteReq mshr miss latency 553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35896.454762 # average WriteReq mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency 555system.cpu.dcache.demand_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency 557system.cpu.dcache.overall_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency |
| 558system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 558system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 559system.cpu.l2cache.replacements 97988 # number of replacements 560system.cpu.l2cache.tagsinuse 28616.670846 # Cycle average of tags in use 561system.cpu.l2cache.total_refs 87010 # Total number of references to valid blocks. 562system.cpu.l2cache.sampled_refs 128775 # Sample count of references to valid blocks. 563system.cpu.l2cache.avg_refs 0.675675 # Average number of references to valid blocks. | 559system.cpu.l2cache.replacements 98022 # number of replacements 560system.cpu.l2cache.tagsinuse 28617.589348 # Cycle average of tags in use 561system.cpu.l2cache.total_refs 86966 # Total number of references to valid blocks. 562system.cpu.l2cache.sampled_refs 128812 # Sample count of references to valid blocks. 563system.cpu.l2cache.avg_refs 0.675139 # Average number of references to valid blocks. |
| 564system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 564system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 565system.cpu.l2cache.occ_blocks::writebacks 25808.135877 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.inst 1157.314936 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_blocks::cpu.data 1651.220033 # Average occupied blocks per requestor 568system.cpu.l2cache.occ_percent::writebacks 0.787602 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.inst 0.035318 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::cpu.data 0.050391 # Average percentage of cache occupancy 571system.cpu.l2cache.occ_percent::total 0.873311 # Average percentage of cache occupancy 572system.cpu.l2cache.ReadReq_hits::cpu.inst 27137 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::cpu.data 32372 # number of ReadReq hits 574system.cpu.l2cache.ReadReq_hits::total 59509 # number of ReadReq hits 575system.cpu.l2cache.Writeback_hits::writebacks 128059 # number of Writeback hits 576system.cpu.l2cache.Writeback_hits::total 128059 # number of Writeback hits 577system.cpu.l2cache.UpgradeReq_hits::cpu.data 7 # number of UpgradeReq hits 578system.cpu.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits | 565system.cpu.l2cache.occ_blocks::writebacks 25792.429972 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.inst 1163.052716 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_blocks::cpu.data 1662.106660 # Average occupied blocks per requestor 568system.cpu.l2cache.occ_percent::writebacks 0.787122 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.inst 0.035494 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::cpu.data 0.050723 # Average percentage of cache occupancy 571system.cpu.l2cache.occ_percent::total 0.873340 # Average percentage of cache occupancy 572system.cpu.l2cache.ReadReq_hits::cpu.inst 26908 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::cpu.data 32482 # number of ReadReq hits 574system.cpu.l2cache.ReadReq_hits::total 59390 # number of ReadReq hits 575system.cpu.l2cache.Writeback_hits::writebacks 128131 # number of Writeback hits 576system.cpu.l2cache.Writeback_hits::total 128131 # number of Writeback hits 577system.cpu.l2cache.UpgradeReq_hits::cpu.data 11 # number of UpgradeReq hits 578system.cpu.l2cache.UpgradeReq_hits::total 11 # number of UpgradeReq hits |
| 579system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits 580system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits | 579system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits 580system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits |
| 581system.cpu.l2cache.demand_hits::cpu.inst 27137 # number of demand (read+write) hits 582system.cpu.l2cache.demand_hits::cpu.data 37084 # number of demand (read+write) hits 583system.cpu.l2cache.demand_hits::total 64221 # number of demand (read+write) hits 584system.cpu.l2cache.overall_hits::cpu.inst 27137 # number of overall hits 585system.cpu.l2cache.overall_hits::cpu.data 37084 # number of overall hits 586system.cpu.l2cache.overall_hits::total 64221 # number of overall hits 587system.cpu.l2cache.ReadReq_misses::cpu.inst 5137 # number of ReadReq misses 588system.cpu.l2cache.ReadReq_misses::cpu.data 23202 # number of ReadReq misses 589system.cpu.l2cache.ReadReq_misses::total 28339 # number of ReadReq misses 590system.cpu.l2cache.UpgradeReq_misses::cpu.data 37 # number of UpgradeReq misses 591system.cpu.l2cache.UpgradeReq_misses::total 37 # number of UpgradeReq misses | 581system.cpu.l2cache.demand_hits::cpu.inst 26908 # number of demand (read+write) hits 582system.cpu.l2cache.demand_hits::cpu.data 37194 # number of demand (read+write) hits 583system.cpu.l2cache.demand_hits::total 64102 # number of demand (read+write) hits 584system.cpu.l2cache.overall_hits::cpu.inst 26908 # number of overall hits 585system.cpu.l2cache.overall_hits::cpu.data 37194 # number of overall hits 586system.cpu.l2cache.overall_hits::total 64102 # number of overall hits 587system.cpu.l2cache.ReadReq_misses::cpu.inst 5162 # number of ReadReq misses 588system.cpu.l2cache.ReadReq_misses::cpu.data 23218 # number of ReadReq misses 589system.cpu.l2cache.ReadReq_misses::total 28380 # number of ReadReq misses 590system.cpu.l2cache.UpgradeReq_misses::cpu.data 46 # number of UpgradeReq misses 591system.cpu.l2cache.UpgradeReq_misses::total 46 # number of UpgradeReq misses |
| 592system.cpu.l2cache.ReadExReq_misses::cpu.data 102311 # number of ReadExReq misses 593system.cpu.l2cache.ReadExReq_misses::total 102311 # number of ReadExReq misses | 592system.cpu.l2cache.ReadExReq_misses::cpu.data 102311 # number of ReadExReq misses 593system.cpu.l2cache.ReadExReq_misses::total 102311 # number of ReadExReq misses |
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| 618system.cpu.l2cache.ReadExReq_accesses::cpu.data 107023 # number of ReadExReq accesses(hits+misses) 619system.cpu.l2cache.ReadExReq_accesses::total 107023 # number of ReadExReq accesses(hits+misses) | 618system.cpu.l2cache.ReadExReq_accesses::cpu.data 107023 # number of ReadExReq accesses(hits+misses) 619system.cpu.l2cache.ReadExReq_accesses::total 107023 # number of ReadExReq accesses(hits+misses) |
| 620system.cpu.l2cache.demand_accesses::cpu.inst 32274 # number of demand (read+write) accesses 621system.cpu.l2cache.demand_accesses::cpu.data 162597 # number of demand (read+write) accesses 622system.cpu.l2cache.demand_accesses::total 194871 # number of demand (read+write) accesses 623system.cpu.l2cache.overall_accesses::cpu.inst 32274 # number of overall (read+write) accesses 624system.cpu.l2cache.overall_accesses::cpu.data 162597 # number of overall (read+write) accesses 625system.cpu.l2cache.overall_accesses::total 194871 # number of overall (read+write) accesses 626system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.159168 # miss rate for ReadReq accesses 627system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.417497 # miss rate for ReadReq accesses 628system.cpu.l2cache.ReadReq_miss_rate::total 0.322591 # miss rate for ReadReq accesses 629system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.840909 # miss rate for UpgradeReq accesses 630system.cpu.l2cache.UpgradeReq_miss_rate::total 0.840909 # miss rate for UpgradeReq accesses | 620system.cpu.l2cache.demand_accesses::cpu.inst 32070 # number of demand (read+write) accesses 621system.cpu.l2cache.demand_accesses::cpu.data 162723 # number of demand (read+write) accesses 622system.cpu.l2cache.demand_accesses::total 194793 # number of demand (read+write) accesses 623system.cpu.l2cache.overall_accesses::cpu.inst 32070 # number of overall (read+write) accesses 624system.cpu.l2cache.overall_accesses::cpu.data 162723 # number of overall (read+write) accesses 625system.cpu.l2cache.overall_accesses::total 194793 # number of overall (read+write) accesses 626system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.160960 # miss rate for ReadReq accesses 627system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.416840 # miss rate for ReadReq accesses 628system.cpu.l2cache.ReadReq_miss_rate::total 0.323345 # miss rate for ReadReq accesses 629system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807018 # miss rate for UpgradeReq accesses 630system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807018 # miss rate for UpgradeReq accesses |
| 631system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955972 # miss rate for ReadExReq accesses 632system.cpu.l2cache.ReadExReq_miss_rate::total 0.955972 # miss rate for ReadExReq accesses | 631system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955972 # miss rate for ReadExReq accesses 632system.cpu.l2cache.ReadExReq_miss_rate::total 0.955972 # miss rate for ReadExReq accesses |
| 633system.cpu.l2cache.demand_miss_rate::cpu.inst 0.159168 # miss rate for demand accesses 634system.cpu.l2cache.demand_miss_rate::cpu.data 0.771927 # miss rate for demand accesses 635system.cpu.l2cache.demand_miss_rate::total 0.670444 # miss rate for demand accesses 636system.cpu.l2cache.overall_miss_rate::cpu.inst 0.159168 # miss rate for overall accesses 637system.cpu.l2cache.overall_miss_rate::cpu.data 0.771927 # miss rate for overall accesses 638system.cpu.l2cache.overall_miss_rate::total 0.670444 # miss rate for overall accesses 639system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35156.219583 # average ReadReq miss latency 640system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35673.304026 # average ReadReq miss latency 641system.cpu.l2cache.ReadReq_avg_miss_latency::total 35579.572321 # average ReadReq miss latency 642system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34769.917213 # average ReadExReq miss latency 643system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34769.917213 # average ReadExReq miss latency 644system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35156.219583 # average overall miss latency 645system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34936.914901 # average overall miss latency 646system.cpu.l2cache.demand_avg_miss_latency::total 34945.537696 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35156.219583 # average overall miss latency 648system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34936.914901 # average overall miss latency 649system.cpu.l2cache.overall_avg_miss_latency::total 34945.537696 # average overall miss latency | 633system.cpu.l2cache.demand_miss_rate::cpu.inst 0.160960 # miss rate for demand accesses 634system.cpu.l2cache.demand_miss_rate::cpu.data 0.771428 # miss rate for demand accesses 635system.cpu.l2cache.demand_miss_rate::total 0.670922 # miss rate for demand accesses 636system.cpu.l2cache.overall_miss_rate::cpu.inst 0.160960 # miss rate for overall accesses 637system.cpu.l2cache.overall_miss_rate::cpu.data 0.771428 # miss rate for overall accesses 638system.cpu.l2cache.overall_miss_rate::total 0.670922 # miss rate for overall accesses 639system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35141.224332 # average ReadReq miss latency 640system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35903.609269 # average ReadReq miss latency 641system.cpu.l2cache.ReadReq_avg_miss_latency::total 35764.940099 # average ReadReq miss latency 642system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34823.283909 # average ReadExReq miss latency 643system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34823.283909 # average ReadExReq miss latency 644system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35141.224332 # average overall miss latency 645system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35023.102231 # average overall miss latency 646system.cpu.l2cache.demand_avg_miss_latency::total 35027.767788 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35141.224332 # average overall miss latency 648system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35023.102231 # average overall miss latency 649system.cpu.l2cache.overall_avg_miss_latency::total 35027.767788 # average overall miss latency |
| 650system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.l2cache.fast_writes 0 # number of fast writes performed 657system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 650system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.l2cache.fast_writes 0 # number of fast writes performed 657system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
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| 676system.cpu.l2cache.demand_mshr_misses::cpu.inst 5109 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.demand_mshr_misses::cpu.data 125449 # number of demand (read+write) MSHR misses 678system.cpu.l2cache.demand_mshr_misses::total 130558 # number of demand (read+write) MSHR misses 679system.cpu.l2cache.overall_mshr_misses::cpu.inst 5109 # number of overall MSHR misses 680system.cpu.l2cache.overall_mshr_misses::cpu.data 125449 # number of overall MSHR misses 681system.cpu.l2cache.overall_mshr_misses::total 130558 # number of overall MSHR misses 682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163941000 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 752838000 # number of ReadReq MSHR miss cycles 684system.cpu.l2cache.ReadReq_mshr_miss_latency::total 916779000 # number of ReadReq MSHR miss cycles 685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1147000 # number of UpgradeReq MSHR miss cycles 686system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1147000 # number of UpgradeReq MSHR miss cycles 687system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3241185000 # number of ReadExReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3241185000 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163941000 # number of demand (read+write) MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3994023000 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::total 4157964000 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163941000 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3994023000 # number of overall MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::total 4157964000 # number of overall MSHR miss cycles 695system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416346 # mshr miss rate for ReadReq accesses 697system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321544 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.840909 # mshr miss rate for UpgradeReq accesses 699system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.840909 # mshr miss rate for UpgradeReq accesses | 676system.cpu.l2cache.demand_mshr_misses::cpu.inst 5133 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.demand_mshr_misses::cpu.data 125462 # number of demand (read+write) MSHR misses 678system.cpu.l2cache.demand_mshr_misses::total 130595 # number of demand (read+write) MSHR misses 679system.cpu.l2cache.overall_mshr_misses::cpu.inst 5133 # number of overall MSHR misses 680system.cpu.l2cache.overall_mshr_misses::cpu.data 125462 # number of overall MSHR misses 681system.cpu.l2cache.overall_mshr_misses::total 130595 # number of overall MSHR misses 682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164656500 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 758645000 # number of ReadReq MSHR miss cycles 684system.cpu.l2cache.ReadReq_mshr_miss_latency::total 923301500 # number of ReadReq MSHR miss cycles 685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1434000 # number of UpgradeReq MSHR miss cycles 686system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1434000 # number of UpgradeReq MSHR miss cycles 687system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3246125500 # number of ReadExReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3246125500 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164656500 # number of demand (read+write) MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4004770500 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::total 4169427000 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164656500 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4004770500 # number of overall MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::total 4169427000 # number of overall MSHR miss cycles 695system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.160056 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415637 # mshr miss rate for ReadReq accesses 697system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.322251 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807018 # mshr miss rate for UpgradeReq accesses 699system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807018 # mshr miss rate for UpgradeReq accesses |
| 700system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955972 # mshr miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955972 # mshr miss rate for ReadExReq accesses | 700system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955972 # mshr miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955972 # mshr miss rate for ReadExReq accesses |
| 702system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for demand accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771533 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::total 0.669971 # mshr miss rate for demand accesses 705system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for overall accesses 706system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771533 # mshr miss rate for overall accesses 707system.cpu.l2cache.overall_mshr_miss_rate::total 0.669971 # mshr miss rate for overall accesses 708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32088.667058 # average ReadReq mshr miss latency 709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32536.865762 # average ReadReq mshr miss latency 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32455.800616 # average ReadReq mshr miss latency 711system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 712system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31679.731407 # average ReadExReq mshr miss latency 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31679.731407 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency | 702system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.160056 # mshr miss rate for demand accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771016 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::total 0.670430 # mshr miss rate for demand accesses 705system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.160056 # mshr miss rate for overall accesses 706system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771016 # mshr miss rate for overall accesses 707system.cpu.l2cache.overall_mshr_miss_rate::total 0.670430 # mshr miss rate for overall accesses 708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32078.024547 # average ReadReq mshr miss latency 709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32769.426807 # average ReadReq mshr miss latency 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32643.950643 # average ReadReq mshr miss latency 711system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31173.913043 # average UpgradeReq mshr miss latency 712system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31173.913043 # average UpgradeReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31728.020447 # average ReadExReq mshr miss latency 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31728.020447 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32078.024547 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31920.186989 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31926.390750 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32078.024547 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31920.186989 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31926.390750 # average overall mshr miss latency |
| 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 722 723---------- End Simulation Statistics ---------- | 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 722 723---------- End Simulation Statistics ---------- |