| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.037283 # Number of seconds simulated 4sim_ticks 37283333000 # Number of ticks simulated 5final_tick 37283333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.037982 # Number of seconds simulated 4sim_ticks 37982056000 # Number of ticks simulated 5final_tick 37982056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 125888 # Simulator instruction rate (inst/s) 8host_op_rate 160996 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 66191855 # Simulator tick rate (ticks/s) 10host_mem_usage 284264 # Number of bytes of host memory used 11host_seconds 563.26 # Real time elapsed on the host | 7host_inst_rate 105525 # Simulator instruction rate (inst/s) 8host_op_rate 134954 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56525025 # Simulator tick rate (ticks/s) 10host_mem_usage 282344 # Number of bytes of host memory used 11host_seconds 671.95 # Real time elapsed on the host |
| 12sim_insts 70907652 # Number of instructions simulated 13sim_ops 90682607 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 70907652 # Number of instructions simulated 13sim_ops 90682607 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 2379328 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 5690752 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 6174592 # Number of bytes read from this memory 20system.physmem.bytes_read::total 14244672 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 2379328 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 2379328 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 6224768 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6224768 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 37177 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 88918 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 96478 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 222573 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 97262 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 97262 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 63817470 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 152635281 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 165612661 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 382065412 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 63817470 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 63817470 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 166958464 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 166958464 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 166958464 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 63817470 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 152635281 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 165612661 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 549023876 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 222574 # Number of read requests accepted 45system.physmem.writeReqs 97262 # Number of write requests accepted 46system.physmem.readBursts 222574 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 97262 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 14235136 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue 50system.physmem.bytesWritten 6223360 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 14244736 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 6224768 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 2372544 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 5696640 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 6178368 # Number of bytes read from this memory 20system.physmem.bytes_read::total 14247552 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 2372544 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 2372544 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 6227072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6227072 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 37071 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 89010 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 96537 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 222618 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 97298 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 97298 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 62464865 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 149982402 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 162665444 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 375112711 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 62464865 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 62464865 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 163947734 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 163947734 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 163947734 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 62464865 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 149982402 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 162665444 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 539060445 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 222619 # Number of read requests accepted 45system.physmem.writeReqs 97298 # Number of write requests accepted 46system.physmem.readBursts 222619 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 97298 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 14237568 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue 50system.physmem.bytesWritten 6225984 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 14247616 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 6227072 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue |
| 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 9684 # Per bank write bursts 57system.physmem.perBankRdBursts::1 9951 # Per bank write bursts 58system.physmem.perBankRdBursts::2 12571 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25345 # Per bank write bursts 60system.physmem.perBankRdBursts::4 17391 # Per bank write bursts 61system.physmem.perBankRdBursts::5 22070 # Per bank write bursts 62system.physmem.perBankRdBursts::6 11722 # Per bank write bursts 63system.physmem.perBankRdBursts::7 14054 # Per bank write bursts 64system.physmem.perBankRdBursts::8 11726 # Per bank write bursts 65system.physmem.perBankRdBursts::9 15447 # Per bank write bursts 66system.physmem.perBankRdBursts::10 11755 # Per bank write bursts 67system.physmem.perBankRdBursts::11 11322 # Per bank write bursts 68system.physmem.perBankRdBursts::12 9441 # Per bank write bursts 69system.physmem.perBankRdBursts::13 9563 # Per bank write bursts 70system.physmem.perBankRdBursts::14 9879 # Per bank write bursts 71system.physmem.perBankRdBursts::15 20503 # Per bank write bursts 72system.physmem.perBankWrBursts::0 5981 # Per bank write bursts 73system.physmem.perBankWrBursts::1 6205 # Per bank write bursts 74system.physmem.perBankWrBursts::2 6090 # Per bank write bursts 75system.physmem.perBankWrBursts::3 6159 # Per bank write bursts 76system.physmem.perBankWrBursts::4 6110 # Per bank write bursts 77system.physmem.perBankWrBursts::5 6252 # Per bank write bursts 78system.physmem.perBankWrBursts::6 5998 # Per bank write bursts 79system.physmem.perBankWrBursts::7 5984 # Per bank write bursts 80system.physmem.perBankWrBursts::8 5961 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6093 # Per bank write bursts 82system.physmem.perBankWrBursts::10 6222 # Per bank write bursts 83system.physmem.perBankWrBursts::11 5895 # Per bank write bursts 84system.physmem.perBankWrBursts::12 6037 # Per bank write bursts 85system.physmem.perBankWrBursts::13 6052 # Per bank write bursts 86system.physmem.perBankWrBursts::14 6175 # Per bank write bursts 87system.physmem.perBankWrBursts::15 6026 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 9655 # Per bank write bursts 57system.physmem.perBankRdBursts::1 9974 # Per bank write bursts 58system.physmem.perBankRdBursts::2 12579 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25363 # Per bank write bursts 60system.physmem.perBankRdBursts::4 17343 # Per bank write bursts 61system.physmem.perBankRdBursts::5 22132 # Per bank write bursts 62system.physmem.perBankRdBursts::6 11760 # Per bank write bursts 63system.physmem.perBankRdBursts::7 14137 # Per bank write bursts 64system.physmem.perBankRdBursts::8 11660 # Per bank write bursts 65system.physmem.perBankRdBursts::9 15453 # Per bank write bursts 66system.physmem.perBankRdBursts::10 11698 # Per bank write bursts 67system.physmem.perBankRdBursts::11 11338 # Per bank write bursts 68system.physmem.perBankRdBursts::12 9437 # Per bank write bursts 69system.physmem.perBankRdBursts::13 9564 # Per bank write bursts 70system.physmem.perBankRdBursts::14 9858 # Per bank write bursts 71system.physmem.perBankRdBursts::15 20511 # Per bank write bursts 72system.physmem.perBankWrBursts::0 5992 # Per bank write bursts 73system.physmem.perBankWrBursts::1 6239 # Per bank write bursts 74system.physmem.perBankWrBursts::2 6121 # Per bank write bursts 75system.physmem.perBankWrBursts::3 6129 # Per bank write bursts 76system.physmem.perBankWrBursts::4 6098 # Per bank write bursts 77system.physmem.perBankWrBursts::5 6229 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6018 # Per bank write bursts 79system.physmem.perBankWrBursts::7 5980 # Per bank write bursts 80system.physmem.perBankWrBursts::8 5938 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6095 # Per bank write bursts 82system.physmem.perBankWrBursts::10 6202 # Per bank write bursts 83system.physmem.perBankWrBursts::11 5916 # Per bank write bursts 84system.physmem.perBankWrBursts::12 6046 # Per bank write bursts 85system.physmem.perBankWrBursts::13 6090 # Per bank write bursts 86system.physmem.perBankWrBursts::14 6173 # Per bank write bursts 87system.physmem.perBankWrBursts::15 6015 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 90system.physmem.totGap 37283321500 # Total gap between requests | 90system.physmem.totGap 37982044500 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 222574 # Read request sizes (log2) | 97system.physmem.readPktSize::6 222619 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 97262 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 113358 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 61350 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 14014 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 10209 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 5990 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 5097 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 4548 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 4202 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 3541 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 97298 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 111989 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 59707 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 15764 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 10925 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 6262 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 5252 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 4622 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 4266 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 76 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 38 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see |
| 118system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see --- 18 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 118system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see --- 18 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 1119 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 1183 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 1912 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 2549 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 4946 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 5524 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6019 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 6870 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7426 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 7971 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 8650 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 8737 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 7379 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 6528 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 6235 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 181 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 91 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 53 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::15 1089 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 1151 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 1856 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 2518 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 3246 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 4935 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 5530 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6006 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 6447 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 6796 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7367 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 7813 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 8377 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 8639 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 7998 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 6745 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 6258 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 95 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see |
| 177system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see | 177system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see |
| 178system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see | 178system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see |
| 180system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see --- 5 unchanged lines hidden (view full) --- 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 180system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see --- 5 unchanged lines hidden (view full) --- 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 201system.physmem.bytesPerActivate::samples 132565 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 154.319345 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 102.621145 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 210.186270 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 82651 62.35% 62.35% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 32256 24.33% 86.68% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 6354 4.79% 91.47% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 2721 2.05% 93.53% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 1163 0.88% 94.40% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 1002 0.76% 95.16% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 846 0.64% 95.80% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 812 0.61% 96.41% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 4760 3.59% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 132565 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 37.864488 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 211.288279 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 5866 99.86% 99.86% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::512-1023 7 0.12% 99.98% # Reads before turning the bus around for writes | 201system.physmem.bytesPerActivate::samples 132891 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 153.980270 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 102.520664 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 209.589027 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 82855 62.35% 62.35% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 32511 24.46% 86.81% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 6209 4.67% 91.48% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 2728 2.05% 93.54% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 1195 0.90% 94.44% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 994 0.75% 95.18% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 885 0.67% 95.85% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 776 0.58% 96.43% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 4738 3.57% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 132891 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 37.813870 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 211.295819 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 5876 99.88% 99.88% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::512-1023 6 0.10% 99.98% # Reads before turning the bus around for writes |
| 220system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes | 220system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5874 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 16.554307 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 16.512747 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 1.243213 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16 4672 79.54% 79.54% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::17 38 0.65% 80.18% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::18 729 12.41% 92.59% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::19 209 3.56% 96.15% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20 107 1.82% 97.97% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::21 58 0.99% 98.96% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::22 31 0.53% 99.49% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::23 16 0.27% 99.76% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24 11 0.19% 99.95% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::26 2 0.03% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 5874 # Writes before turning the bus around for reads 238system.physmem.totQLat 7261518854 # Total ticks spent queuing 239system.physmem.totMemAccLat 11431968854 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 1112120000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 32647.19 # Average queueing delay per DRAM burst | 221system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 16.535951 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 16.496117 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 1.216118 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16 4707 80.01% 80.01% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::17 47 0.80% 80.81% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::18 703 11.95% 92.76% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::19 205 3.48% 96.24% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20 109 1.85% 98.10% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::21 61 1.04% 99.13% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::22 33 0.56% 99.69% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::23 11 0.19% 99.88% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24 1 0.02% 99.90% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::26 4 0.07% 99.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads 239system.physmem.totQLat 8417974819 # Total ticks spent queuing 240system.physmem.totMemAccLat 12589137319 # Total ticks spent from burst creation until serviced by the DRAM 241system.physmem.totBusLat 1112310000 # Total ticks spent in databus transfers 242system.physmem.avgQLat 37840.06 # Average queueing delay per DRAM burst |
| 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 243system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 243system.physmem.avgMemAccLat 51397.19 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 381.81 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 166.92 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 382.07 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 166.96 # Average system write bandwidth in MiByte/s | 244system.physmem.avgMemAccLat 56590.06 # Average memory access latency per DRAM burst 245system.physmem.avgRdBW 374.85 # Average DRAM read bandwidth in MiByte/s 246system.physmem.avgWrBW 163.92 # Average achieved write bandwidth in MiByte/s 247system.physmem.avgRdBWSys 375.11 # Average system read bandwidth in MiByte/s 248system.physmem.avgWrBWSys 163.95 # Average system write bandwidth in MiByte/s |
| 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 249system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 249system.physmem.busUtil 4.29 # Data bus utilization in percentage 250system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing 254system.physmem.readRowHits 157163 # Number of row buffer hits during reads 255system.physmem.writeRowHits 29925 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 70.66 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 30.77 # Row buffer hit rate for writes 258system.physmem.avgGap 116570.12 # Average gap between requests 259system.physmem.pageHitRate 58.52 # Row buffer hit rate, read and write combined 260system.physmem_0.actEnergy 537077520 # Energy for activate commands per rank (pJ) 261system.physmem_0.preEnergy 293048250 # Energy for precharge commands per rank (pJ) 262system.physmem_0.readEnergy 957496800 # Energy for read commands per rank (pJ) 263system.physmem_0.writeEnergy 315958320 # Energy for write commands per rank (pJ) 264system.physmem_0.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) 265system.physmem_0.actBackEnergy 23206024395 # Energy for active background per rank (pJ) 266system.physmem_0.preBackEnergy 2012333250 # Energy for precharge background per rank (pJ) 267system.physmem_0.totalEnergy 29756923815 # Total energy per rank (pJ) 268system.physmem_0.averagePower 798.183082 # Core power per rank (mW) 269system.physmem_0.memoryStateTime::IDLE 3201879547 # Time in different power states 270system.physmem_0.memoryStateTime::REF 1244880000 # Time in different power states 271system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 272system.physmem_0.memoryStateTime::ACT 32834079203 # Time in different power states 273system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 274system.physmem_1.actEnergy 464871960 # Energy for activate commands per rank (pJ) 275system.physmem_1.preEnergy 253650375 # Energy for precharge commands per rank (pJ) 276system.physmem_1.readEnergy 777051600 # Energy for read commands per rank (pJ) 277system.physmem_1.writeEnergy 313949520 # Energy for write commands per rank (pJ) 278system.physmem_1.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) 279system.physmem_1.actBackEnergy 21592790730 # Energy for active background per rank (pJ) 280system.physmem_1.preBackEnergy 3427453500 # Energy for precharge background per rank (pJ) 281system.physmem_1.totalEnergy 29264752965 # Total energy per rank (pJ) 282system.physmem_1.averagePower 784.981262 # Core power per rank (mW) 283system.physmem_1.memoryStateTime::IDLE 5568954615 # Time in different power states 284system.physmem_1.memoryStateTime::REF 1244880000 # Time in different power states 285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 286system.physmem_1.memoryStateTime::ACT 30467009135 # Time in different power states 287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 288system.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 289system.cpu.branchPred.lookups 17068882 # Number of BP lookups 290system.cpu.branchPred.condPredicted 11456187 # Number of conditional branches predicted 291system.cpu.branchPred.condIncorrect 597693 # Number of conditional branches incorrect 292system.cpu.branchPred.BTBLookups 9279962 # Number of BTB lookups 293system.cpu.branchPred.BTBHits 7373647 # Number of BTB hits | 250system.physmem.busUtil 4.21 # Data bus utilization in percentage 251system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads 252system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes 253system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing 254system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing 255system.physmem.readRowHits 157076 # Number of row buffer hits during reads 256system.physmem.writeRowHits 29766 # Number of row buffer hits during writes 257system.physmem.readRowHitRate 70.61 # Row buffer hit rate for reads 258system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes 259system.physmem.avgGap 118724.68 # Average gap between requests 260system.physmem.pageHitRate 58.43 # Row buffer hit rate, read and write combined 261system.physmem_0.actEnergy 508332300 # Energy for activate commands per rank (pJ) 262system.physmem_0.preEnergy 270162255 # Energy for precharge commands per rank (pJ) 263system.physmem_0.readEnergy 877813020 # Energy for read commands per rank (pJ) 264system.physmem_0.writeEnergy 254767320 # Energy for write commands per rank (pJ) 265system.physmem_0.refreshEnergy 3007433520.000000 # Energy for refresh commands per rank (pJ) 266system.physmem_0.actBackEnergy 2937544590 # Energy for active background per rank (pJ) 267system.physmem_0.preBackEnergy 74566560 # Energy for precharge background per rank (pJ) 268system.physmem_0.actPowerDownEnergy 13007568150 # Energy for active power-down per rank (pJ) 269system.physmem_0.prePowerDownEnergy 1007588640 # Energy for precharge power-down per rank (pJ) 270system.physmem_0.selfRefreshEnergy 71626485 # Energy for self refresh per rank (pJ) 271system.physmem_0.totalEnergy 22017862440 # Total energy per rank (pJ) 272system.physmem_0.averagePower 579.691165 # Core power per rank (mW) 273system.physmem_0.totalIdleTime 31344656336 # Total Idle time Per DRAM Rank 274system.physmem_0.memoryStateTime::IDLE 41004063 # Time in different power states 275system.physmem_0.memoryStateTime::REF 1272480000 # Time in different power states 276system.physmem_0.memoryStateTime::SREF 195565250 # Time in different power states 277system.physmem_0.memoryStateTime::PRE_PDN 2624595348 # Time in different power states 278system.physmem_0.memoryStateTime::ACT 5323818601 # Time in different power states 279system.physmem_0.memoryStateTime::ACT_PDN 28524592738 # Time in different power states 280system.physmem_1.actEnergy 440580840 # Energy for activate commands per rank (pJ) 281system.physmem_1.preEnergy 234159090 # Energy for precharge commands per rank (pJ) 282system.physmem_1.readEnergy 710558520 # Energy for read commands per rank (pJ) 283system.physmem_1.writeEnergy 253039500 # Energy for write commands per rank (pJ) 284system.physmem_1.refreshEnergy 2889422640.000000 # Energy for refresh commands per rank (pJ) 285system.physmem_1.actBackEnergy 2771748120 # Energy for active background per rank (pJ) 286system.physmem_1.preBackEnergy 73304160 # Energy for precharge background per rank (pJ) 287system.physmem_1.actPowerDownEnergy 11932439280 # Energy for active power-down per rank (pJ) 288system.physmem_1.prePowerDownEnergy 1384694400 # Energy for precharge power-down per rank (pJ) 289system.physmem_1.selfRefreshEnergy 508589940 # Energy for self refresh per rank (pJ) 290system.physmem_1.totalEnergy 21198847170 # Total energy per rank (pJ) 291system.physmem_1.averagePower 558.127949 # Core power per rank (mW) 292system.physmem_1.totalIdleTime 31712588164 # Total Idle time Per DRAM Rank 293system.physmem_1.memoryStateTime::IDLE 50452548 # Time in different power states 294system.physmem_1.memoryStateTime::REF 1222746000 # Time in different power states 295system.physmem_1.memoryStateTime::SREF 1938473750 # Time in different power states 296system.physmem_1.memoryStateTime::PRE_PDN 3605935527 # Time in different power states 297system.physmem_1.memoryStateTime::ACT 4996269288 # Time in different power states 298system.physmem_1.memoryStateTime::ACT_PDN 26168178887 # Time in different power states 299system.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 300system.cpu.branchPred.lookups 17071043 # Number of BP lookups 301system.cpu.branchPred.condPredicted 11458506 # Number of conditional branches predicted 302system.cpu.branchPred.condIncorrect 598065 # Number of conditional branches incorrect 303system.cpu.branchPred.BTBLookups 9277652 # Number of BTB lookups 304system.cpu.branchPred.BTBHits 7374059 # Number of BTB hits |
| 294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 305system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 295system.cpu.branchPred.BTBHitPct 79.457728 # BTB Hit Percentage 296system.cpu.branchPred.usedRAS 1854916 # Number of times the RAS was used to get a target. 297system.cpu.branchPred.RASInCorrect 101589 # Number of incorrect RAS predictions. 298system.cpu.branchPred.indirectLookups 233217 # Number of indirect predictor lookups. 299system.cpu.branchPred.indirectHits 195584 # Number of indirect target hits. 300system.cpu.branchPred.indirectMisses 37633 # Number of indirect misses. 301system.cpu.branchPredindirectMispredicted 22185 # Number of mispredicted indirect branches. | 306system.cpu.branchPred.BTBHitPct 79.481953 # BTB Hit Percentage 307system.cpu.branchPred.usedRAS 1854771 # Number of times the RAS was used to get a target. 308system.cpu.branchPred.RASInCorrect 101571 # Number of incorrect RAS predictions. 309system.cpu.branchPred.indirectLookups 233347 # Number of indirect predictor lookups. 310system.cpu.branchPred.indirectHits 194967 # Number of indirect target hits. 311system.cpu.branchPred.indirectMisses 38380 # Number of indirect misses. 312system.cpu.branchPredindirectMispredicted 22266 # Number of mispredicted indirect branches. |
| 302system.cpu_clk_domain.clock 500 # Clock period in ticks | 313system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 303system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states | 314system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states |
| 304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 315system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 336system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 337system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 338system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 339system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 340system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 341system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 342system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 343system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 333system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states | 344system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states |
| 334system.cpu.dtb.walker.walks 0 # Table walker walks requested 335system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.dtb.read_accesses 0 # DTB read accesses 358system.cpu.dtb.write_accesses 0 # DTB write accesses 359system.cpu.dtb.inst_accesses 0 # ITB inst accesses 360system.cpu.dtb.hits 0 # DTB hits 361system.cpu.dtb.misses 0 # DTB misses 362system.cpu.dtb.accesses 0 # DTB accesses | 345system.cpu.dtb.walker.walks 0 # Table walker walks requested 346system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 352system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 366system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 367system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 368system.cpu.dtb.read_accesses 0 # DTB read accesses 369system.cpu.dtb.write_accesses 0 # DTB write accesses 370system.cpu.dtb.inst_accesses 0 # ITB inst accesses 371system.cpu.dtb.hits 0 # DTB hits 372system.cpu.dtb.misses 0 # DTB misses 373system.cpu.dtb.accesses 0 # DTB accesses |
| 363system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states | 374system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states |
| 364system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 385system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 386system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 388system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 389system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 390system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 391system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 392system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 375system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 382system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 396system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 397system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 398system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 399system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 400system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 401system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 402system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 403system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 393system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states | 404system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states |
| 394system.cpu.itb.walker.walks 0 # Table walker walks requested 395system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 416system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu.itb.read_accesses 0 # DTB read accesses 418system.cpu.itb.write_accesses 0 # DTB write accesses 419system.cpu.itb.inst_accesses 0 # ITB inst accesses 420system.cpu.itb.hits 0 # DTB hits 421system.cpu.itb.misses 0 # DTB misses 422system.cpu.itb.accesses 0 # DTB accesses 423system.cpu.workload.num_syscalls 1946 # Number of system calls | 405system.cpu.itb.walker.walks 0 # Table walker walks requested 406system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 409system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 410system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 411system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 412system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 427system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 428system.cpu.itb.read_accesses 0 # DTB read accesses 429system.cpu.itb.write_accesses 0 # DTB write accesses 430system.cpu.itb.inst_accesses 0 # ITB inst accesses 431system.cpu.itb.hits 0 # DTB hits 432system.cpu.itb.misses 0 # DTB misses 433system.cpu.itb.accesses 0 # DTB accesses 434system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 424system.cpu.pwrStateResidencyTicks::ON 37283333000 # Cumulative time (in ticks) in various power states 425system.cpu.numCycles 74566667 # number of cpu cycles simulated | 435system.cpu.pwrStateResidencyTicks::ON 37982056000 # Cumulative time (in ticks) in various power states 436system.cpu.numCycles 75964113 # number of cpu cycles simulated |
| 426system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 427system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 437system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 438system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 428system.cpu.fetch.icacheStallCycles 5541341 # Number of cycles fetch is stalled on an Icache miss 429system.cpu.fetch.Insts 87099155 # Number of instructions fetch has processed 430system.cpu.fetch.Branches 17068882 # Number of branches that fetch encountered 431system.cpu.fetch.predictedBranches 9424147 # Number of branches that fetch has predicted taken 432system.cpu.fetch.Cycles 65038748 # Number of cycles fetch has run and was not squashing or blocked 433system.cpu.fetch.SquashCycles 1222021 # Number of cycles fetch has spent squashing 434system.cpu.fetch.MiscStallCycles 11659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 435system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps 436system.cpu.fetch.IcacheWaitRetryStallCycles 30739 # Number of stall cycles due to full MSHR 437system.cpu.fetch.CacheLines 22432357 # Number of cache lines fetched 438system.cpu.fetch.IcacheSquashes 69340 # Number of outstanding Icache misses that were squashed 439system.cpu.fetch.rateDist::samples 71233545 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::mean 1.545306 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::stdev 1.327706 # Number of instructions fetched each cycle (Total) | 439system.cpu.fetch.icacheStallCycles 5537723 # Number of cycles fetch is stalled on an Icache miss 440system.cpu.fetch.Insts 87105546 # Number of instructions fetch has processed 441system.cpu.fetch.Branches 17071043 # Number of branches that fetch encountered 442system.cpu.fetch.predictedBranches 9423797 # Number of branches that fetch has predicted taken 443system.cpu.fetch.Cycles 66074321 # Number of cycles fetch has run and was not squashing or blocked 444system.cpu.fetch.SquashCycles 1222765 # Number of cycles fetch has spent squashing 445system.cpu.fetch.MiscStallCycles 12043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 446system.cpu.fetch.PendingTrapStallCycles 60 # Number of stall cycles due to pending traps 447system.cpu.fetch.IcacheWaitRetryStallCycles 33616 # Number of stall cycles due to full MSHR 448system.cpu.fetch.CacheLines 22433583 # Number of cache lines fetched 449system.cpu.fetch.IcacheSquashes 69302 # Number of outstanding Icache misses that were squashed 450system.cpu.fetch.rateDist::samples 72269145 # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::mean 1.523281 # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::stdev 1.330897 # Number of instructions fetched each cycle (Total) |
| 442system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 453system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 443system.cpu.fetch.rateDist::0 26059108 36.58% 36.58% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::1 8166381 11.46% 48.05% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::2 9112889 12.79% 60.84% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::3 27895167 39.16% 100.00% # Number of instructions fetched each cycle (Total) | 454system.cpu.fetch.rateDist::0 27092588 37.49% 37.49% # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::1 8164913 11.30% 48.79% # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.rateDist::2 9113637 12.61% 61.40% # Number of instructions fetched each cycle (Total) 457system.cpu.fetch.rateDist::3 27898007 38.60% 100.00% # Number of instructions fetched each cycle (Total) |
| 447system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 458system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 459system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 460system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 450system.cpu.fetch.rateDist::total 71233545 # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.branchRate 0.228908 # Number of branch fetches per cycle 452system.cpu.fetch.rate 1.168071 # Number of inst fetches per cycle 453system.cpu.decode.IdleCycles 8928507 # Number of cycles decode is idle 454system.cpu.decode.BlockedCycles 25221623 # Number of cycles decode is blocked 455system.cpu.decode.RunCycles 30949867 # Number of cycles decode is running 456system.cpu.decode.UnblockCycles 5689167 # Number of cycles decode is unblocking 457system.cpu.decode.SquashCycles 444381 # Number of cycles decode is squashing 458system.cpu.decode.BranchResolved 3134053 # Number of times decode resolved a branch 459system.cpu.decode.BranchMispred 168503 # Number of times decode detected a branch misprediction 460system.cpu.decode.DecodedInsts 100299686 # Number of instructions handled by decode 461system.cpu.decode.SquashedInsts 2798262 # Number of squashed instructions handled by decode 462system.cpu.rename.SquashCycles 444381 # Number of cycles rename is squashing 463system.cpu.rename.IdleCycles 13572247 # Number of cycles rename is idle 464system.cpu.rename.BlockCycles 10675080 # Number of cycles rename is blocking 465system.cpu.rename.serializeStallCycles 842433 # count of cycles rename stalled for serializing inst 466system.cpu.rename.RunCycles 31772787 # Number of cycles rename is running 467system.cpu.rename.UnblockCycles 13926617 # Number of cycles rename is unblocking 468system.cpu.rename.RenamedInsts 98328841 # Number of instructions processed by rename 469system.cpu.rename.SquashedInsts 859440 # Number of squashed instructions processed by rename 470system.cpu.rename.ROBFullEvents 4124148 # Number of times rename has blocked due to ROB full 471system.cpu.rename.IQFullEvents 69439 # Number of times rename has blocked due to IQ full 472system.cpu.rename.LQFullEvents 4596367 # Number of times rename has blocked due to LQ full 473system.cpu.rename.SQFullEvents 5265270 # Number of times rename has blocked due to SQ full 474system.cpu.rename.RenamedOperands 103255092 # Number of destination operands rename has renamed 475system.cpu.rename.RenameLookups 453545884 # Number of register rename lookups that rename has made 476system.cpu.rename.int_rename_lookups 114277398 # Number of integer rename lookups 477system.cpu.rename.fp_rename_lookups 716 # Number of floating rename lookups | 461system.cpu.fetch.rateDist::total 72269145 # Number of instructions fetched each cycle (Total) 462system.cpu.fetch.branchRate 0.224725 # Number of branch fetches per cycle 463system.cpu.fetch.rate 1.146667 # Number of inst fetches per cycle 464system.cpu.decode.IdleCycles 8914938 # Number of cycles decode is idle 465system.cpu.decode.BlockedCycles 26268747 # Number of cycles decode is blocked 466system.cpu.decode.RunCycles 30971085 # Number of cycles decode is running 467system.cpu.decode.UnblockCycles 5669704 # Number of cycles decode is unblocking 468system.cpu.decode.SquashCycles 444671 # Number of cycles decode is squashing 469system.cpu.decode.BranchResolved 3134143 # Number of times decode resolved a branch 470system.cpu.decode.BranchMispred 168562 # Number of times decode detected a branch misprediction 471system.cpu.decode.DecodedInsts 100303161 # Number of instructions handled by decode 472system.cpu.decode.SquashedInsts 2799230 # Number of squashed instructions handled by decode 473system.cpu.rename.SquashCycles 444671 # Number of cycles rename is squashing 474system.cpu.rename.IdleCycles 13550474 # Number of cycles rename is idle 475system.cpu.rename.BlockCycles 11467047 # Number of cycles rename is blocking 476system.cpu.rename.serializeStallCycles 876029 # count of cycles rename stalled for serializing inst 477system.cpu.rename.RunCycles 31784130 # Number of cycles rename is running 478system.cpu.rename.UnblockCycles 14146794 # Number of cycles rename is unblocking 479system.cpu.rename.RenamedInsts 98330583 # Number of instructions processed by rename 480system.cpu.rename.SquashedInsts 860090 # Number of squashed instructions processed by rename 481system.cpu.rename.ROBFullEvents 4210253 # Number of times rename has blocked due to ROB full 482system.cpu.rename.IQFullEvents 70388 # Number of times rename has blocked due to IQ full 483system.cpu.rename.LQFullEvents 4670257 # Number of times rename has blocked due to LQ full 484system.cpu.rename.SQFullEvents 5435231 # Number of times rename has blocked due to SQ full 485system.cpu.rename.RenamedOperands 103259286 # Number of destination operands rename has renamed 486system.cpu.rename.RenameLookups 453553071 # Number of register rename lookups that rename has made 487system.cpu.rename.int_rename_lookups 114279094 # Number of integer rename lookups 488system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups |
| 478system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed | 489system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed |
| 479system.cpu.rename.UndoneMaps 9625723 # Number of HB maps that are undone due to squashing 480system.cpu.rename.serializingInsts 18974 # count of serializing insts renamed 481system.cpu.rename.tempSerializingInsts 19002 # count of temporary serializing insts renamed 482system.cpu.rename.skidInsts 12839389 # count of insts added to the skid buffer 483system.cpu.memDep0.insertedLoads 24155878 # Number of loads inserted to the mem dependence unit. 484system.cpu.memDep0.insertedStores 21759886 # Number of stores inserted to the mem dependence unit. 485system.cpu.memDep0.conflictingLoads 1433320 # Number of conflicting loads. 486system.cpu.memDep0.conflictingStores 2321800 # Number of conflicting stores. 487system.cpu.iq.iqInstsAdded 97398916 # Number of instructions added to the IQ (excludes non-spec) 488system.cpu.iq.iqNonSpecInstsAdded 34841 # Number of non-speculative instructions added to the IQ 489system.cpu.iq.iqInstsIssued 94478155 # Number of instructions issued 490system.cpu.iq.iqSquashedInstsIssued 593843 # Number of squashed instructions issued 491system.cpu.iq.iqSquashedInstsExamined 6751150 # Number of squashed instructions iterated over during squash; mainly for profiling 492system.cpu.iq.iqSquashedOperandsExamined 17960313 # Number of squashed operands that are examined and possibly removed from graph 493system.cpu.iq.iqSquashedNonSpecRemoved 1055 # Number of squashed non-spec instructions that were removed 494system.cpu.iq.issued_per_cycle::samples 71233545 # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::mean 1.326316 # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::stdev 1.168839 # Number of insts issued each cycle | 490system.cpu.rename.UndoneMaps 9629917 # Number of HB maps that are undone due to squashing 491system.cpu.rename.serializingInsts 18998 # count of serializing insts renamed 492system.cpu.rename.tempSerializingInsts 19022 # count of temporary serializing insts renamed 493system.cpu.rename.skidInsts 12803731 # count of insts added to the skid buffer 494system.cpu.memDep0.insertedLoads 24155645 # Number of loads inserted to the mem dependence unit. 495system.cpu.memDep0.insertedStores 21760500 # Number of stores inserted to the mem dependence unit. 496system.cpu.memDep0.conflictingLoads 1435489 # Number of conflicting loads. 497system.cpu.memDep0.conflictingStores 2293932 # Number of conflicting stores. 498system.cpu.iq.iqInstsAdded 97400499 # Number of instructions added to the IQ (excludes non-spec) 499system.cpu.iq.iqNonSpecInstsAdded 34856 # Number of non-speculative instructions added to the IQ 500system.cpu.iq.iqInstsIssued 94484787 # Number of instructions issued 501system.cpu.iq.iqSquashedInstsIssued 595355 # Number of squashed instructions issued 502system.cpu.iq.iqSquashedInstsExamined 6752748 # Number of squashed instructions iterated over during squash; mainly for profiling 503system.cpu.iq.iqSquashedOperandsExamined 17957034 # Number of squashed operands that are examined and possibly removed from graph 504system.cpu.iq.iqSquashedNonSpecRemoved 1070 # Number of squashed non-spec instructions that were removed 505system.cpu.iq.issued_per_cycle::samples 72269145 # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::mean 1.307401 # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::stdev 1.171287 # Number of insts issued each cycle |
| 497system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 508system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 498system.cpu.iq.issued_per_cycle::0 23112455 32.45% 32.45% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::1 17441476 24.48% 56.93% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::2 17040128 23.92% 80.85% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::3 11602976 16.29% 97.14% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::4 2035055 2.86% 100.00% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::5 1455 0.00% 100.00% # Number of insts issued each cycle | 509system.cpu.iq.issued_per_cycle::0 24146655 33.41% 33.41% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::1 17449315 24.14% 57.56% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::2 17027031 23.56% 81.12% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::3 11604628 16.06% 97.18% # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::4 2040054 2.82% 100.00% # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::5 1462 0.00% 100.00% # Number of insts issued each cycle |
| 504system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 515system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 517system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 518system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 519system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 520system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 510system.cpu.iq.issued_per_cycle::total 71233545 # Number of insts issued each cycle | 521system.cpu.iq.issued_per_cycle::total 72269145 # Number of insts issued each cycle |
| 511system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 522system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 512system.cpu.iq.fu_full::IntAlu 6731709 22.63% 22.63% # attempts to use FU when none available 513system.cpu.iq.fu_full::IntMult 38 0.00% 22.63% # attempts to use FU when none available | 523system.cpu.iq.fu_full::IntAlu 6736684 22.63% 22.63% # attempts to use FU when none available 524system.cpu.iq.fu_full::IntMult 37 0.00% 22.63% # attempts to use FU when none available |
| 514system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available 515system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available 516system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available 517system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 533system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.63% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.63% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.63% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.63% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available | 525system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available 526system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available 527system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available 528system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available 529system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available 530system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available 531system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 544system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.63% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.63% # attempts to use FU when none available 546system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.63% # attempts to use FU when none available 547system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.63% # attempts to use FU when none available 548system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # attempts to use FU when none available 549system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available 550system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available 551system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available |
| 541system.cpu.iq.fu_full::MemRead 11081856 37.26% 59.89% # attempts to use FU when none available 542system.cpu.iq.fu_full::MemWrite 11930481 40.11% 100.00% # attempts to use FU when none available | 552system.cpu.iq.fu_full::MemRead 11088474 37.25% 59.89% # attempts to use FU when none available 553system.cpu.iq.fu_full::MemWrite 11940322 40.11% 100.00% # attempts to use FU when none available |
| 543system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 544system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 545system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 554system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 555system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 556system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 546system.cpu.iq.FU_type_0::IntAlu 49303920 52.19% 52.19% # Type of FU issued 547system.cpu.iq.FU_type_0::IntMult 86563 0.09% 52.28% # Type of FU issued | 557system.cpu.iq.FU_type_0::IntAlu 49305598 52.18% 52.18% # Type of FU issued 558system.cpu.iq.FU_type_0::IntMult 86530 0.09% 52.28% # Type of FU issued |
| 548system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued 549system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued 550system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued 551system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.28% # Type of FU issued 552system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.28% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.28% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.28% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.28% # Type of FU issued --- 4 unchanged lines hidden (view full) --- 560system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.28% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.28% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.28% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.28% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued | 559system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued 560system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued 561system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued 562system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.28% # Type of FU issued 563system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.28% # Type of FU issued 564system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.28% # Type of FU issued 565system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.28% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.28% # Type of FU issued --- 4 unchanged lines hidden (view full) --- 571system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.28% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.28% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.28% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.28% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued |
| 568system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.28% # Type of FU issued | 579system.cpu.iq.FU_type_0::SimdFloatCmp 11 0.00% 52.28% # Type of FU issued |
| 569system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued | 580system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued |
| 571system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.28% # Type of FU issued | 582system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 52.28% # Type of FU issued |
| 572system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued | 583system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued 584system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued 585system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued |
| 575system.cpu.iq.FU_type_0::MemRead 23954982 25.36% 77.63% # Type of FU issued 576system.cpu.iq.FU_type_0::MemWrite 21132627 22.37% 100.00% # Type of FU issued | 586system.cpu.iq.FU_type_0::MemRead 23958877 25.36% 77.63% # Type of FU issued 587system.cpu.iq.FU_type_0::MemWrite 21133721 22.37% 100.00% # Type of FU issued |
| 577system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 578system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 588system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 589system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 579system.cpu.iq.FU_type_0::total 94478155 # Type of FU issued 580system.cpu.iq.rate 1.267029 # Inst issue rate 581system.cpu.iq.fu_busy_cnt 29744084 # FU busy when requested 582system.cpu.iq.fu_busy_rate 0.314825 # FU busy rate (busy events/executed inst) 583system.cpu.iq.int_inst_queue_reads 290527434 # Number of integer instruction queue reads 584system.cpu.iq.int_inst_queue_writes 104196109 # Number of integer instruction queue writes 585system.cpu.iq.int_inst_queue_wakeup_accesses 93201296 # Number of integer instruction queue wakeup accesses 586system.cpu.iq.fp_inst_queue_reads 348 # Number of floating instruction queue reads 587system.cpu.iq.fp_inst_queue_writes 616 # Number of floating instruction queue writes 588system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses 589system.cpu.iq.int_alu_accesses 124222040 # Number of integer alu accesses 590system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses 591system.cpu.iew.lsq.thread0.forwLoads 1368179 # Number of loads that had data forwarded from stores | 590system.cpu.iq.FU_type_0::total 94484787 # Type of FU issued 591system.cpu.iq.rate 1.243808 # Inst issue rate 592system.cpu.iq.fu_busy_cnt 29765517 # FU busy when requested 593system.cpu.iq.fu_busy_rate 0.315030 # FU busy rate (busy events/executed inst) 594system.cpu.iq.int_inst_queue_reads 291599265 # Number of integer instruction queue reads 595system.cpu.iq.int_inst_queue_writes 104199326 # Number of integer instruction queue writes 596system.cpu.iq.int_inst_queue_wakeup_accesses 93203450 # Number of integer instruction queue wakeup accesses 597system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads 598system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes 599system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses 600system.cpu.iq.int_alu_accesses 124250121 # Number of integer alu accesses 601system.cpu.iq.fp_alu_accesses 183 # Number of floating point alu accesses 602system.cpu.iew.lsq.thread0.forwLoads 1368397 # Number of loads that had data forwarded from stores |
| 592system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 603system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 593system.cpu.iew.lsq.thread0.squashedLoads 1289616 # Number of loads squashed 594system.cpu.iew.lsq.thread0.ignoredResponses 2048 # Number of memory responses ignored because the instruction is squashed | 604system.cpu.iew.lsq.thread0.squashedLoads 1289383 # Number of loads squashed 605system.cpu.iew.lsq.thread0.ignoredResponses 2091 # Number of memory responses ignored because the instruction is squashed |
| 595system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations | 606system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations |
| 596system.cpu.iew.lsq.thread0.squashedStores 1204148 # Number of stores squashed | 607system.cpu.iew.lsq.thread0.squashedStores 1204762 # Number of stores squashed |
| 597system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 598system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 608system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 609system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 599system.cpu.iew.lsq.thread0.rescheduledLoads 144864 # Number of loads that were rescheduled 600system.cpu.iew.lsq.thread0.cacheBlocked 185613 # Number of times an access to memory failed due to the cache being blocked | 610system.cpu.iew.lsq.thread0.rescheduledLoads 147075 # Number of loads that were rescheduled 611system.cpu.iew.lsq.thread0.cacheBlocked 188044 # Number of times an access to memory failed due to the cache being blocked |
| 601system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 612system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 602system.cpu.iew.iewSquashCycles 444381 # Number of cycles IEW is squashing 603system.cpu.iew.iewBlockCycles 624509 # Number of cycles IEW is blocking 604system.cpu.iew.iewUnblockCycles 1115710 # Number of cycles IEW is unblocking 605system.cpu.iew.iewDispatchedInsts 97447803 # Number of instructions dispatched to IQ | 613system.cpu.iew.iewSquashCycles 444671 # Number of cycles IEW is squashing 614system.cpu.iew.iewBlockCycles 622988 # Number of cycles IEW is blocking 615system.cpu.iew.iewUnblockCycles 1195662 # Number of cycles IEW is unblocking 616system.cpu.iew.iewDispatchedInsts 97449431 # Number of instructions dispatched to IQ |
| 606system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 617system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 607system.cpu.iew.iewDispLoadInsts 24155878 # Number of dispatched load instructions 608system.cpu.iew.iewDispStoreInsts 21759886 # Number of dispatched store instructions 609system.cpu.iew.iewDispNonSpecInsts 18921 # Number of dispatched non-speculative instructions 610system.cpu.iew.iewIQFullEvents 1617 # Number of times the IQ has become full, causing a stall 611system.cpu.iew.iewLSQFullEvents 1111435 # Number of times the LSQ has become full, causing a stall | 618system.cpu.iew.iewDispLoadInsts 24155645 # Number of dispatched load instructions 619system.cpu.iew.iewDispStoreInsts 21760500 # Number of dispatched store instructions 620system.cpu.iew.iewDispNonSpecInsts 18936 # Number of dispatched non-speculative instructions 621system.cpu.iew.iewIQFullEvents 1589 # Number of times the IQ has become full, causing a stall 622system.cpu.iew.iewLSQFullEvents 1191442 # Number of times the LSQ has become full, causing a stall |
| 612system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations | 623system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations |
| 613system.cpu.iew.predictedTakenIncorrect 249911 # Number of branches that were predicted taken incorrectly 614system.cpu.iew.predictedNotTakenIncorrect 221890 # Number of branches that were predicted not taken incorrectly 615system.cpu.iew.branchMispredicts 471801 # Number of branch mispredicts detected at execute 616system.cpu.iew.iewExecutedInsts 93685311 # Number of executed instructions 617system.cpu.iew.iewExecLoadInsts 23691817 # Number of load instructions executed 618system.cpu.iew.iewExecSquashedInsts 792844 # Number of squashed instructions skipped in execute | 624system.cpu.iew.predictedTakenIncorrect 249986 # Number of branches that were predicted taken incorrectly 625system.cpu.iew.predictedNotTakenIncorrect 222081 # Number of branches that were predicted not taken incorrectly 626system.cpu.iew.branchMispredicts 472067 # Number of branch mispredicts detected at execute 627system.cpu.iew.iewExecutedInsts 93691189 # Number of executed instructions 628system.cpu.iew.iewExecLoadInsts 23695668 # Number of load instructions executed 629system.cpu.iew.iewExecSquashedInsts 793598 # Number of squashed instructions skipped in execute |
| 619system.cpu.iew.exec_swp 0 # number of swp insts executed | 630system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 620system.cpu.iew.exec_nop 14046 # number of nop insts executed 621system.cpu.iew.exec_refs 44616394 # number of memory reference insts executed 622system.cpu.iew.exec_branches 14207133 # Number of branches executed 623system.cpu.iew.exec_stores 20924577 # Number of stores executed 624system.cpu.iew.exec_rate 1.256397 # Inst execution rate 625system.cpu.iew.wb_sent 93308677 # cumulative count of insts sent to commit 626system.cpu.iew.wb_count 93201392 # cumulative count of insts written-back 627system.cpu.iew.wb_producers 44951021 # num instructions producing a value 628system.cpu.iew.wb_consumers 76633881 # num instructions consuming a value 629system.cpu.iew.wb_rate 1.249907 # insts written-back per cycle 630system.cpu.iew.wb_fanout 0.586569 # average fanout of values written-back 631system.cpu.commit.commitSquashedInsts 5894305 # The number of squashed insts skipped by commit | 631system.cpu.iew.exec_nop 14076 # number of nop insts executed 632system.cpu.iew.exec_refs 44621004 # number of memory reference insts executed 633system.cpu.iew.exec_branches 14207535 # Number of branches executed 634system.cpu.iew.exec_stores 20925336 # Number of stores executed 635system.cpu.iew.exec_rate 1.233361 # Inst execution rate 636system.cpu.iew.wb_sent 93310594 # cumulative count of insts sent to commit 637system.cpu.iew.wb_count 93203542 # cumulative count of insts written-back 638system.cpu.iew.wb_producers 44951761 # num instructions producing a value 639system.cpu.iew.wb_consumers 76639550 # num instructions consuming a value 640system.cpu.iew.wb_rate 1.226942 # insts written-back per cycle 641system.cpu.iew.wb_fanout 0.586535 # average fanout of values written-back 642system.cpu.commit.commitSquashedInsts 5895620 # The number of squashed insts skipped by commit |
| 632system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards | 643system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards |
| 633system.cpu.commit.branchMispredicts 431064 # The number of times a branch was mispredicted 634system.cpu.commit.committed_per_cycle::samples 70277782 # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::mean 1.290424 # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::stdev 2.118209 # Number of insts commited each cycle | 644system.cpu.commit.branchMispredicts 431354 # The number of times a branch was mispredicted 645system.cpu.commit.committed_per_cycle::samples 71312758 # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::mean 1.271696 # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::stdev 2.107515 # Number of insts commited each cycle |
| 637system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 648system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 638system.cpu.commit.committed_per_cycle::0 36842990 52.42% 52.42% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::1 16674938 23.73% 76.15% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::2 4291723 6.11% 82.26% # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::3 4149088 5.90% 88.16% # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::4 1947878 2.77% 90.93% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::5 1240751 1.77% 92.70% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::6 737656 1.05% 93.75% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::7 580756 0.83% 94.58% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::8 3812002 5.42% 100.00% # Number of insts commited each cycle | 649system.cpu.commit.committed_per_cycle::0 37859507 53.09% 53.09% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::1 16683603 23.39% 76.48% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::2 4297164 6.03% 82.51% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::3 4156384 5.83% 88.34% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::4 1956005 2.74% 91.08% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::5 1240140 1.74% 92.82% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::6 732437 1.03% 93.85% # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::7 578410 0.81% 94.66% # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::8 3809108 5.34% 100.00% # Number of insts commited each cycle |
| 647system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 658system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 659system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 660system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 650system.cpu.commit.committed_per_cycle::total 70277782 # Number of insts commited each cycle | 661system.cpu.commit.committed_per_cycle::total 71312758 # Number of insts commited each cycle |
| 651system.cpu.commit.committedInsts 70913204 # Number of instructions committed 652system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed 653system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 654system.cpu.commit.refs 43422000 # Number of memory references committed 655system.cpu.commit.loads 22866262 # Number of loads committed 656system.cpu.commit.membars 15920 # Number of memory barriers committed 657system.cpu.commit.branches 13741468 # Number of branches committed 658system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 688system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 691system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 692system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 693system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 694system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 695system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction | 662system.cpu.commit.committedInsts 70913204 # Number of instructions committed 663system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed 664system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 665system.cpu.commit.refs 43422000 # Number of memory references committed 666system.cpu.commit.loads 22866262 # Number of loads committed 667system.cpu.commit.membars 15920 # Number of memory barriers committed 668system.cpu.commit.branches 13741468 # Number of branches committed 669system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 699system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 700system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 701system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 702system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 703system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 704system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 705system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 706system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction |
| 696system.cpu.commit.bw_lim_events 3812002 # number cycles where commit BW limit reached 697system.cpu.rob.rob_reads 163022945 # The number of ROB reads 698system.cpu.rob.rob_writes 194122181 # The number of ROB writes 699system.cpu.timesIdled 54257 # Number of times that the entire CPU went into an idle state and unscheduled itself 700system.cpu.idleCycles 3333122 # Total number of cycles that the CPU has spent unscheduled due to idling | 707system.cpu.commit.bw_lim_events 3809108 # number cycles where commit BW limit reached 708system.cpu.rob.rob_reads 164062130 # The number of ROB reads 709system.cpu.rob.rob_writes 194125448 # The number of ROB writes 710system.cpu.timesIdled 54252 # Number of times that the entire CPU went into an idle state and unscheduled itself 711system.cpu.idleCycles 3694968 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 701system.cpu.committedInsts 70907652 # Number of Instructions Simulated 702system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated | 712system.cpu.committedInsts 70907652 # Number of Instructions Simulated 713system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated |
| 703system.cpu.cpi 1.051603 # CPI: Cycles Per Instruction 704system.cpu.cpi_total 1.051603 # CPI: Total CPI of All Threads 705system.cpu.ipc 0.950930 # IPC: Instructions Per Cycle 706system.cpu.ipc_total 0.950930 # IPC: Total IPC of All Threads 707system.cpu.int_regfile_reads 101976703 # number of integer regfile reads 708system.cpu.int_regfile_writes 56611271 # number of integer regfile writes 709system.cpu.fp_regfile_reads 60 # number of floating regfile reads 710system.cpu.fp_regfile_writes 48 # number of floating regfile writes 711system.cpu.cc_regfile_reads 345090037 # number of cc regfile reads 712system.cpu.cc_regfile_writes 38758670 # number of cc regfile writes 713system.cpu.misc_regfile_reads 44101489 # number of misc regfile reads | 714system.cpu.cpi 1.071311 # CPI: Cycles Per Instruction 715system.cpu.cpi_total 1.071311 # CPI: Total CPI of All Threads 716system.cpu.ipc 0.933436 # IPC: Instructions Per Cycle 717system.cpu.ipc_total 0.933436 # IPC: Total IPC of All Threads 718system.cpu.int_regfile_reads 101982930 # number of integer regfile reads 719system.cpu.int_regfile_writes 56612163 # number of integer regfile writes 720system.cpu.fp_regfile_reads 58 # number of floating regfile reads 721system.cpu.fp_regfile_writes 45 # number of floating regfile writes 722system.cpu.cc_regfile_reads 345107562 # number of cc regfile reads 723system.cpu.cc_regfile_writes 38759661 # number of cc regfile writes 724system.cpu.misc_regfile_reads 44102170 # number of misc regfile reads |
| 714system.cpu.misc_regfile_writes 31840 # number of misc regfile writes | 725system.cpu.misc_regfile_writes 31840 # number of misc regfile writes |
| 715system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 716system.cpu.dcache.tags.replacements 484862 # number of replacements 717system.cpu.dcache.tags.tagsinuse 510.874566 # Cycle average of tags in use 718system.cpu.dcache.tags.total_refs 40338135 # Total number of references to valid blocks. 719system.cpu.dcache.tags.sampled_refs 485374 # Sample count of references to valid blocks. 720system.cpu.dcache.tags.avg_refs 83.107325 # Average number of references to valid blocks. 721system.cpu.dcache.tags.warmup_cycle 151605500 # Cycle when the warmup percentage was hit. 722system.cpu.dcache.tags.occ_blocks::cpu.data 510.874566 # Average occupied blocks per requestor 723system.cpu.dcache.tags.occ_percent::cpu.data 0.997802 # Average percentage of cache occupancy 724system.cpu.dcache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy | 726system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 727system.cpu.dcache.tags.replacements 484814 # number of replacements 728system.cpu.dcache.tags.tagsinuse 510.868965 # Cycle average of tags in use 729system.cpu.dcache.tags.total_refs 40339815 # Total number of references to valid blocks. 730system.cpu.dcache.tags.sampled_refs 485326 # Sample count of references to valid blocks. 731system.cpu.dcache.tags.avg_refs 83.119007 # Average number of references to valid blocks. 732system.cpu.dcache.tags.warmup_cycle 154595500 # Cycle when the warmup percentage was hit. 733system.cpu.dcache.tags.occ_blocks::cpu.data 510.868965 # Average occupied blocks per requestor 734system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy 735system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy |
| 725system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 726system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 727system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id 728system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 736system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 737system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 738system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id 739system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 729system.cpu.dcache.tags.tag_accesses 84467396 # Number of tag accesses 730system.cpu.dcache.tags.data_accesses 84467396 # Number of data accesses 731system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 732system.cpu.dcache.ReadReq_hits::cpu.data 21414103 # number of ReadReq hits 733system.cpu.dcache.ReadReq_hits::total 21414103 # number of ReadReq hits 734system.cpu.dcache.WriteReq_hits::cpu.data 18832546 # number of WriteReq hits 735system.cpu.dcache.WriteReq_hits::total 18832546 # number of WriteReq hits 736system.cpu.dcache.SoftPFReq_hits::cpu.data 60212 # number of SoftPFReq hits 737system.cpu.dcache.SoftPFReq_hits::total 60212 # number of SoftPFReq hits 738system.cpu.dcache.LoadLockedReq_hits::cpu.data 15310 # number of LoadLockedReq hits 739system.cpu.dcache.LoadLockedReq_hits::total 15310 # number of LoadLockedReq hits | 740system.cpu.dcache.tags.tag_accesses 84466838 # Number of tag accesses 741system.cpu.dcache.tags.data_accesses 84466838 # Number of data accesses 742system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 743system.cpu.dcache.ReadReq_hits::cpu.data 21417711 # number of ReadReq hits 744system.cpu.dcache.ReadReq_hits::total 21417711 # number of ReadReq hits 745system.cpu.dcache.WriteReq_hits::cpu.data 18830642 # number of WriteReq hits 746system.cpu.dcache.WriteReq_hits::total 18830642 # number of WriteReq hits 747system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits 748system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits 749system.cpu.dcache.LoadLockedReq_hits::cpu.data 15309 # number of LoadLockedReq hits 750system.cpu.dcache.LoadLockedReq_hits::total 15309 # number of LoadLockedReq hits |
| 740system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 741system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits | 751system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 752system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| 742system.cpu.dcache.demand_hits::cpu.data 40246649 # number of demand (read+write) hits 743system.cpu.dcache.demand_hits::total 40246649 # number of demand (read+write) hits 744system.cpu.dcache.overall_hits::cpu.data 40306861 # number of overall hits 745system.cpu.dcache.overall_hits::total 40306861 # number of overall hits 746system.cpu.dcache.ReadReq_misses::cpu.data 566310 # number of ReadReq misses 747system.cpu.dcache.ReadReq_misses::total 566310 # number of ReadReq misses 748system.cpu.dcache.WriteReq_misses::cpu.data 1017355 # number of WriteReq misses 749system.cpu.dcache.WriteReq_misses::total 1017355 # number of WriteReq misses 750system.cpu.dcache.SoftPFReq_misses::cpu.data 68643 # number of SoftPFReq misses 751system.cpu.dcache.SoftPFReq_misses::total 68643 # number of SoftPFReq misses 752system.cpu.dcache.LoadLockedReq_misses::cpu.data 613 # number of LoadLockedReq misses 753system.cpu.dcache.LoadLockedReq_misses::total 613 # number of LoadLockedReq misses 754system.cpu.dcache.demand_misses::cpu.data 1583665 # number of demand (read+write) misses 755system.cpu.dcache.demand_misses::total 1583665 # number of demand (read+write) misses 756system.cpu.dcache.overall_misses::cpu.data 1652308 # number of overall misses 757system.cpu.dcache.overall_misses::total 1652308 # number of overall misses 758system.cpu.dcache.ReadReq_miss_latency::cpu.data 13581553500 # number of ReadReq miss cycles 759system.cpu.dcache.ReadReq_miss_latency::total 13581553500 # number of ReadReq miss cycles 760system.cpu.dcache.WriteReq_miss_latency::cpu.data 13903205430 # number of WriteReq miss cycles 761system.cpu.dcache.WriteReq_miss_latency::total 13903205430 # number of WriteReq miss cycles 762system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5738500 # number of LoadLockedReq miss cycles 763system.cpu.dcache.LoadLockedReq_miss_latency::total 5738500 # number of LoadLockedReq miss cycles 764system.cpu.dcache.demand_miss_latency::cpu.data 27484758930 # number of demand (read+write) miss cycles 765system.cpu.dcache.demand_miss_latency::total 27484758930 # number of demand (read+write) miss cycles 766system.cpu.dcache.overall_miss_latency::cpu.data 27484758930 # number of overall miss cycles 767system.cpu.dcache.overall_miss_latency::total 27484758930 # number of overall miss cycles 768system.cpu.dcache.ReadReq_accesses::cpu.data 21980413 # number of ReadReq accesses(hits+misses) 769system.cpu.dcache.ReadReq_accesses::total 21980413 # number of ReadReq accesses(hits+misses) | 753system.cpu.dcache.demand_hits::cpu.data 40248353 # number of demand (read+write) hits 754system.cpu.dcache.demand_hits::total 40248353 # number of demand (read+write) hits 755system.cpu.dcache.overall_hits::cpu.data 40308541 # number of overall hits 756system.cpu.dcache.overall_hits::total 40308541 # number of overall hits 757system.cpu.dcache.ReadReq_misses::cpu.data 562442 # number of ReadReq misses 758system.cpu.dcache.ReadReq_misses::total 562442 # number of ReadReq misses 759system.cpu.dcache.WriteReq_misses::cpu.data 1019259 # number of WriteReq misses 760system.cpu.dcache.WriteReq_misses::total 1019259 # number of WriteReq misses 761system.cpu.dcache.SoftPFReq_misses::cpu.data 68672 # number of SoftPFReq misses 762system.cpu.dcache.SoftPFReq_misses::total 68672 # number of SoftPFReq misses 763system.cpu.dcache.LoadLockedReq_misses::cpu.data 614 # number of LoadLockedReq misses 764system.cpu.dcache.LoadLockedReq_misses::total 614 # number of LoadLockedReq misses 765system.cpu.dcache.demand_misses::cpu.data 1581701 # number of demand (read+write) misses 766system.cpu.dcache.demand_misses::total 1581701 # number of demand (read+write) misses 767system.cpu.dcache.overall_misses::cpu.data 1650373 # number of overall misses 768system.cpu.dcache.overall_misses::total 1650373 # number of overall misses 769system.cpu.dcache.ReadReq_miss_latency::cpu.data 14412910000 # number of ReadReq miss cycles 770system.cpu.dcache.ReadReq_miss_latency::total 14412910000 # number of ReadReq miss cycles 771system.cpu.dcache.WriteReq_miss_latency::cpu.data 14258561428 # number of WriteReq miss cycles 772system.cpu.dcache.WriteReq_miss_latency::total 14258561428 # number of WriteReq miss cycles 773system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5705500 # number of LoadLockedReq miss cycles 774system.cpu.dcache.LoadLockedReq_miss_latency::total 5705500 # number of LoadLockedReq miss cycles 775system.cpu.dcache.demand_miss_latency::cpu.data 28671471428 # number of demand (read+write) miss cycles 776system.cpu.dcache.demand_miss_latency::total 28671471428 # number of demand (read+write) miss cycles 777system.cpu.dcache.overall_miss_latency::cpu.data 28671471428 # number of overall miss cycles 778system.cpu.dcache.overall_miss_latency::total 28671471428 # number of overall miss cycles 779system.cpu.dcache.ReadReq_accesses::cpu.data 21980153 # number of ReadReq accesses(hits+misses) 780system.cpu.dcache.ReadReq_accesses::total 21980153 # number of ReadReq accesses(hits+misses) |
| 770system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 771system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) | 781system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 782system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| 772system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses) 773system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses) | 783system.cpu.dcache.SoftPFReq_accesses::cpu.data 128860 # number of SoftPFReq accesses(hits+misses) 784system.cpu.dcache.SoftPFReq_accesses::total 128860 # number of SoftPFReq accesses(hits+misses) |
| 774system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) 775system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) 776system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 777system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) | 785system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) 786system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) 787system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 788system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| 778system.cpu.dcache.demand_accesses::cpu.data 41830314 # number of demand (read+write) accesses 779system.cpu.dcache.demand_accesses::total 41830314 # number of demand (read+write) accesses 780system.cpu.dcache.overall_accesses::cpu.data 41959169 # number of overall (read+write) accesses 781system.cpu.dcache.overall_accesses::total 41959169 # number of overall (read+write) accesses 782system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025764 # miss rate for ReadReq accesses 783system.cpu.dcache.ReadReq_miss_rate::total 0.025764 # miss rate for ReadReq accesses 784system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051252 # miss rate for WriteReq accesses 785system.cpu.dcache.WriteReq_miss_rate::total 0.051252 # miss rate for WriteReq accesses 786system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532715 # miss rate for SoftPFReq accesses 787system.cpu.dcache.SoftPFReq_miss_rate::total 0.532715 # miss rate for SoftPFReq accesses 788system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038498 # miss rate for LoadLockedReq accesses 789system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038498 # miss rate for LoadLockedReq accesses 790system.cpu.dcache.demand_miss_rate::cpu.data 0.037859 # miss rate for demand accesses 791system.cpu.dcache.demand_miss_rate::total 0.037859 # miss rate for demand accesses 792system.cpu.dcache.overall_miss_rate::cpu.data 0.039379 # miss rate for overall accesses 793system.cpu.dcache.overall_miss_rate::total 0.039379 # miss rate for overall accesses 794system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23982.542247 # average ReadReq miss latency 795system.cpu.dcache.ReadReq_avg_miss_latency::total 23982.542247 # average ReadReq miss latency 796system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13666.031454 # average WriteReq miss latency 797system.cpu.dcache.WriteReq_avg_miss_latency::total 13666.031454 # average WriteReq miss latency 798system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9361.337684 # average LoadLockedReq miss latency 799system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9361.337684 # average LoadLockedReq miss latency 800system.cpu.dcache.demand_avg_miss_latency::cpu.data 17355.159664 # average overall miss latency 801system.cpu.dcache.demand_avg_miss_latency::total 17355.159664 # average overall miss latency 802system.cpu.dcache.overall_avg_miss_latency::cpu.data 16634.161990 # average overall miss latency 803system.cpu.dcache.overall_avg_miss_latency::total 16634.161990 # average overall miss latency 804system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked 805system.cpu.dcache.blocked_cycles::no_targets 2820837 # number of cycles access was blocked 806system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 807system.cpu.dcache.blocked::no_targets 130956 # number of cycles access was blocked 808system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked 809system.cpu.dcache.avg_blocked_cycles::no_targets 21.540342 # average number of cycles each access was blocked 810system.cpu.dcache.writebacks::writebacks 484862 # number of writebacks 811system.cpu.dcache.writebacks::total 484862 # number of writebacks 812system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267183 # number of ReadReq MSHR hits 813system.cpu.dcache.ReadReq_mshr_hits::total 267183 # number of ReadReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868792 # number of WriteReq MSHR hits 815system.cpu.dcache.WriteReq_mshr_hits::total 868792 # number of WriteReq MSHR hits 816system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 613 # number of LoadLockedReq MSHR hits 817system.cpu.dcache.LoadLockedReq_mshr_hits::total 613 # number of LoadLockedReq MSHR hits 818system.cpu.dcache.demand_mshr_hits::cpu.data 1135975 # number of demand (read+write) MSHR hits 819system.cpu.dcache.demand_mshr_hits::total 1135975 # number of demand (read+write) MSHR hits 820system.cpu.dcache.overall_mshr_hits::cpu.data 1135975 # number of overall MSHR hits 821system.cpu.dcache.overall_mshr_hits::total 1135975 # number of overall MSHR hits 822system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299127 # number of ReadReq MSHR misses 823system.cpu.dcache.ReadReq_mshr_misses::total 299127 # number of ReadReq MSHR misses 824system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148563 # number of WriteReq MSHR misses 825system.cpu.dcache.WriteReq_mshr_misses::total 148563 # number of WriteReq MSHR misses 826system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37696 # number of SoftPFReq MSHR misses 827system.cpu.dcache.SoftPFReq_mshr_misses::total 37696 # number of SoftPFReq MSHR misses 828system.cpu.dcache.demand_mshr_misses::cpu.data 447690 # number of demand (read+write) MSHR misses 829system.cpu.dcache.demand_mshr_misses::total 447690 # number of demand (read+write) MSHR misses 830system.cpu.dcache.overall_mshr_misses::cpu.data 485386 # number of overall MSHR misses 831system.cpu.dcache.overall_mshr_misses::total 485386 # number of overall MSHR misses 832system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6671017500 # number of ReadReq MSHR miss cycles 833system.cpu.dcache.ReadReq_mshr_miss_latency::total 6671017500 # number of ReadReq MSHR miss cycles 834system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2276896471 # number of WriteReq MSHR miss cycles 835system.cpu.dcache.WriteReq_mshr_miss_latency::total 2276896471 # number of WriteReq MSHR miss cycles 836system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1910092000 # number of SoftPFReq MSHR miss cycles 837system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1910092000 # number of SoftPFReq MSHR miss cycles 838system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947913971 # number of demand (read+write) MSHR miss cycles 839system.cpu.dcache.demand_mshr_miss_latency::total 8947913971 # number of demand (read+write) MSHR miss cycles 840system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10858005971 # number of overall MSHR miss cycles 841system.cpu.dcache.overall_mshr_miss_latency::total 10858005971 # number of overall MSHR miss cycles 842system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013609 # mshr miss rate for ReadReq accesses 843system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013609 # mshr miss rate for ReadReq accesses | 789system.cpu.dcache.demand_accesses::cpu.data 41830054 # number of demand (read+write) accesses 790system.cpu.dcache.demand_accesses::total 41830054 # number of demand (read+write) accesses 791system.cpu.dcache.overall_accesses::cpu.data 41958914 # number of overall (read+write) accesses 792system.cpu.dcache.overall_accesses::total 41958914 # number of overall (read+write) accesses 793system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025589 # miss rate for ReadReq accesses 794system.cpu.dcache.ReadReq_miss_rate::total 0.025589 # miss rate for ReadReq accesses 795system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051348 # miss rate for WriteReq accesses 796system.cpu.dcache.WriteReq_miss_rate::total 0.051348 # miss rate for WriteReq accesses 797system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532919 # miss rate for SoftPFReq accesses 798system.cpu.dcache.SoftPFReq_miss_rate::total 0.532919 # miss rate for SoftPFReq accesses 799system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038561 # miss rate for LoadLockedReq accesses 800system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038561 # miss rate for LoadLockedReq accesses 801system.cpu.dcache.demand_miss_rate::cpu.data 0.037813 # miss rate for demand accesses 802system.cpu.dcache.demand_miss_rate::total 0.037813 # miss rate for demand accesses 803system.cpu.dcache.overall_miss_rate::cpu.data 0.039333 # miss rate for overall accesses 804system.cpu.dcache.overall_miss_rate::total 0.039333 # miss rate for overall accesses 805system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.593395 # average ReadReq miss latency 806system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.593395 # average ReadReq miss latency 807system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13989.144494 # average WriteReq miss latency 808system.cpu.dcache.WriteReq_avg_miss_latency::total 13989.144494 # average WriteReq miss latency 809system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9292.345277 # average LoadLockedReq miss latency 810system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9292.345277 # average LoadLockedReq miss latency 811system.cpu.dcache.demand_avg_miss_latency::cpu.data 18126.985712 # average overall miss latency 812system.cpu.dcache.demand_avg_miss_latency::total 18126.985712 # average overall miss latency 813system.cpu.dcache.overall_avg_miss_latency::cpu.data 17372.722062 # average overall miss latency 814system.cpu.dcache.overall_avg_miss_latency::total 17372.722062 # average overall miss latency 815system.cpu.dcache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked 816system.cpu.dcache.blocked_cycles::no_targets 2956958 # number of cycles access was blocked 817system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked 818system.cpu.dcache.blocked::no_targets 131265 # number of cycles access was blocked 819system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.666667 # average number of cycles each access was blocked 820system.cpu.dcache.avg_blocked_cycles::no_targets 22.526629 # average number of cycles each access was blocked 821system.cpu.dcache.writebacks::writebacks 484814 # number of writebacks 822system.cpu.dcache.writebacks::total 484814 # number of writebacks 823system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263368 # number of ReadReq MSHR hits 824system.cpu.dcache.ReadReq_mshr_hits::total 263368 # number of ReadReq MSHR hits 825system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870698 # number of WriteReq MSHR hits 826system.cpu.dcache.WriteReq_mshr_hits::total 870698 # number of WriteReq MSHR hits 827system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 614 # number of LoadLockedReq MSHR hits 828system.cpu.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits 829system.cpu.dcache.demand_mshr_hits::cpu.data 1134066 # number of demand (read+write) MSHR hits 830system.cpu.dcache.demand_mshr_hits::total 1134066 # number of demand (read+write) MSHR hits 831system.cpu.dcache.overall_mshr_hits::cpu.data 1134066 # number of overall MSHR hits 832system.cpu.dcache.overall_mshr_hits::total 1134066 # number of overall MSHR hits 833system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299074 # number of ReadReq MSHR misses 834system.cpu.dcache.ReadReq_mshr_misses::total 299074 # number of ReadReq MSHR misses 835system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148561 # number of WriteReq MSHR misses 836system.cpu.dcache.WriteReq_mshr_misses::total 148561 # number of WriteReq MSHR misses 837system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37704 # number of SoftPFReq MSHR misses 838system.cpu.dcache.SoftPFReq_mshr_misses::total 37704 # number of SoftPFReq MSHR misses 839system.cpu.dcache.demand_mshr_misses::cpu.data 447635 # number of demand (read+write) MSHR misses 840system.cpu.dcache.demand_mshr_misses::total 447635 # number of demand (read+write) MSHR misses 841system.cpu.dcache.overall_mshr_misses::cpu.data 485339 # number of overall MSHR misses 842system.cpu.dcache.overall_mshr_misses::total 485339 # number of overall MSHR misses 843system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7124794500 # number of ReadReq MSHR miss cycles 844system.cpu.dcache.ReadReq_mshr_miss_latency::total 7124794500 # number of ReadReq MSHR miss cycles 845system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2343478471 # number of WriteReq MSHR miss cycles 846system.cpu.dcache.WriteReq_mshr_miss_latency::total 2343478471 # number of WriteReq MSHR miss cycles 847system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1981400500 # number of SoftPFReq MSHR miss cycles 848system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1981400500 # number of SoftPFReq MSHR miss cycles 849system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9468272971 # number of demand (read+write) MSHR miss cycles 850system.cpu.dcache.demand_mshr_miss_latency::total 9468272971 # number of demand (read+write) MSHR miss cycles 851system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11449673471 # number of overall MSHR miss cycles 852system.cpu.dcache.overall_mshr_miss_latency::total 11449673471 # number of overall MSHR miss cycles 853system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013607 # mshr miss rate for ReadReq accesses 854system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013607 # mshr miss rate for ReadReq accesses |
| 844system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses 845system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses | 855system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses 856system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses |
| 846system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292546 # mshr miss rate for SoftPFReq accesses 847system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292546 # mshr miss rate for SoftPFReq accesses 848system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010703 # mshr miss rate for demand accesses 849system.cpu.dcache.demand_mshr_miss_rate::total 0.010703 # mshr miss rate for demand accesses 850system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011568 # mshr miss rate for overall accesses 851system.cpu.dcache.overall_mshr_miss_rate::total 0.011568 # mshr miss rate for overall accesses 852system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22301.622722 # average ReadReq mshr miss latency 853system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22301.622722 # average ReadReq mshr miss latency 854system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15326.134172 # average WriteReq mshr miss latency 855system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15326.134172 # average WriteReq mshr miss latency 856system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50670.946520 # average SoftPFReq mshr miss latency 857system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50670.946520 # average SoftPFReq mshr miss latency 858system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19986.852445 # average overall mshr miss latency 859system.cpu.dcache.demand_avg_mshr_miss_latency::total 19986.852445 # average overall mshr miss latency 860system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22369.837554 # average overall mshr miss latency 861system.cpu.dcache.overall_avg_mshr_miss_latency::total 22369.837554 # average overall mshr miss latency 862system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 863system.cpu.icache.tags.replacements 325915 # number of replacements 864system.cpu.icache.tags.tagsinuse 510.404253 # Cycle average of tags in use 865system.cpu.icache.tags.total_refs 22094458 # Total number of references to valid blocks. 866system.cpu.icache.tags.sampled_refs 326427 # Sample count of references to valid blocks. 867system.cpu.icache.tags.avg_refs 67.685755 # Average number of references to valid blocks. 868system.cpu.icache.tags.warmup_cycle 1157973500 # Cycle when the warmup percentage was hit. 869system.cpu.icache.tags.occ_blocks::cpu.inst 510.404253 # Average occupied blocks per requestor 870system.cpu.icache.tags.occ_percent::cpu.inst 0.996883 # Average percentage of cache occupancy 871system.cpu.icache.tags.occ_percent::total 0.996883 # Average percentage of cache occupancy | 857system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292597 # mshr miss rate for SoftPFReq accesses 858system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292597 # mshr miss rate for SoftPFReq accesses 859system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010701 # mshr miss rate for demand accesses 860system.cpu.dcache.demand_mshr_miss_rate::total 0.010701 # mshr miss rate for demand accesses 861system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011567 # mshr miss rate for overall accesses 862system.cpu.dcache.overall_mshr_miss_rate::total 0.011567 # mshr miss rate for overall accesses 863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23822.848191 # average ReadReq mshr miss latency 864system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23822.848191 # average ReadReq mshr miss latency 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15774.520036 # average WriteReq mshr miss latency 866system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15774.520036 # average WriteReq mshr miss latency 867system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52551.466688 # average SoftPFReq mshr miss latency 868system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52551.466688 # average SoftPFReq mshr miss latency 869system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21151.770909 # average overall mshr miss latency 870system.cpu.dcache.demand_avg_mshr_miss_latency::total 21151.770909 # average overall mshr miss latency 871system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23591.084728 # average overall mshr miss latency 872system.cpu.dcache.overall_avg_mshr_miss_latency::total 23591.084728 # average overall mshr miss latency 873system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 874system.cpu.icache.tags.replacements 325639 # number of replacements 875system.cpu.icache.tags.tagsinuse 510.373274 # Cycle average of tags in use 876system.cpu.icache.tags.total_refs 22095836 # Total number of references to valid blocks. 877system.cpu.icache.tags.sampled_refs 326151 # Sample count of references to valid blocks. 878system.cpu.icache.tags.avg_refs 67.747258 # Average number of references to valid blocks. 879system.cpu.icache.tags.warmup_cycle 1176670500 # Cycle when the warmup percentage was hit. 880system.cpu.icache.tags.occ_blocks::cpu.inst 510.373274 # Average occupied blocks per requestor 881system.cpu.icache.tags.occ_percent::cpu.inst 0.996823 # Average percentage of cache occupancy 882system.cpu.icache.tags.occ_percent::total 0.996823 # Average percentage of cache occupancy |
| 872system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 883system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 873system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 874system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 875system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id 876system.cpu.icache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id 877system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id | 884system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id 885system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id 886system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 887system.cpu.icache.tags.age_task_id_blocks_1024::3 328 # Occupied blocks per task id 888system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id |
| 878system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 889system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 879system.cpu.icache.tags.tag_accesses 45190725 # Number of tag accesses 880system.cpu.icache.tags.data_accesses 45190725 # Number of data accesses 881system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 882system.cpu.icache.ReadReq_hits::cpu.inst 22094458 # number of ReadReq hits 883system.cpu.icache.ReadReq_hits::total 22094458 # number of ReadReq hits 884system.cpu.icache.demand_hits::cpu.inst 22094458 # number of demand (read+write) hits 885system.cpu.icache.demand_hits::total 22094458 # number of demand (read+write) hits 886system.cpu.icache.overall_hits::cpu.inst 22094458 # number of overall hits 887system.cpu.icache.overall_hits::total 22094458 # number of overall hits 888system.cpu.icache.ReadReq_misses::cpu.inst 337685 # number of ReadReq misses 889system.cpu.icache.ReadReq_misses::total 337685 # number of ReadReq misses 890system.cpu.icache.demand_misses::cpu.inst 337685 # number of demand (read+write) misses 891system.cpu.icache.demand_misses::total 337685 # number of demand (read+write) misses 892system.cpu.icache.overall_misses::cpu.inst 337685 # number of overall misses 893system.cpu.icache.overall_misses::total 337685 # number of overall misses 894system.cpu.icache.ReadReq_miss_latency::cpu.inst 5566889382 # number of ReadReq miss cycles 895system.cpu.icache.ReadReq_miss_latency::total 5566889382 # number of ReadReq miss cycles 896system.cpu.icache.demand_miss_latency::cpu.inst 5566889382 # number of demand (read+write) miss cycles 897system.cpu.icache.demand_miss_latency::total 5566889382 # number of demand (read+write) miss cycles 898system.cpu.icache.overall_miss_latency::cpu.inst 5566889382 # number of overall miss cycles 899system.cpu.icache.overall_miss_latency::total 5566889382 # number of overall miss cycles 900system.cpu.icache.ReadReq_accesses::cpu.inst 22432143 # number of ReadReq accesses(hits+misses) 901system.cpu.icache.ReadReq_accesses::total 22432143 # number of ReadReq accesses(hits+misses) 902system.cpu.icache.demand_accesses::cpu.inst 22432143 # number of demand (read+write) accesses 903system.cpu.icache.demand_accesses::total 22432143 # number of demand (read+write) accesses 904system.cpu.icache.overall_accesses::cpu.inst 22432143 # number of overall (read+write) accesses 905system.cpu.icache.overall_accesses::total 22432143 # number of overall (read+write) accesses 906system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015054 # miss rate for ReadReq accesses 907system.cpu.icache.ReadReq_miss_rate::total 0.015054 # miss rate for ReadReq accesses 908system.cpu.icache.demand_miss_rate::cpu.inst 0.015054 # miss rate for demand accesses 909system.cpu.icache.demand_miss_rate::total 0.015054 # miss rate for demand accesses 910system.cpu.icache.overall_miss_rate::cpu.inst 0.015054 # miss rate for overall accesses 911system.cpu.icache.overall_miss_rate::total 0.015054 # miss rate for overall accesses 912system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16485.450589 # average ReadReq miss latency 913system.cpu.icache.ReadReq_avg_miss_latency::total 16485.450589 # average ReadReq miss latency 914system.cpu.icache.demand_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency 915system.cpu.icache.demand_avg_miss_latency::total 16485.450589 # average overall miss latency 916system.cpu.icache.overall_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency 917system.cpu.icache.overall_avg_miss_latency::total 16485.450589 # average overall miss latency 918system.cpu.icache.blocked_cycles::no_mshrs 546680 # number of cycles access was blocked 919system.cpu.icache.blocked_cycles::no_targets 53 # number of cycles access was blocked 920system.cpu.icache.blocked::no_mshrs 25668 # number of cycles access was blocked | 890system.cpu.icache.tags.tag_accesses 45192862 # Number of tag accesses 891system.cpu.icache.tags.data_accesses 45192862 # Number of data accesses 892system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 893system.cpu.icache.ReadReq_hits::cpu.inst 22095836 # number of ReadReq hits 894system.cpu.icache.ReadReq_hits::total 22095836 # number of ReadReq hits 895system.cpu.icache.demand_hits::cpu.inst 22095836 # number of demand (read+write) hits 896system.cpu.icache.demand_hits::total 22095836 # number of demand (read+write) hits 897system.cpu.icache.overall_hits::cpu.inst 22095836 # number of overall hits 898system.cpu.icache.overall_hits::total 22095836 # number of overall hits 899system.cpu.icache.ReadReq_misses::cpu.inst 337513 # number of ReadReq misses 900system.cpu.icache.ReadReq_misses::total 337513 # number of ReadReq misses 901system.cpu.icache.demand_misses::cpu.inst 337513 # number of demand (read+write) misses 902system.cpu.icache.demand_misses::total 337513 # number of demand (read+write) misses 903system.cpu.icache.overall_misses::cpu.inst 337513 # number of overall misses 904system.cpu.icache.overall_misses::total 337513 # number of overall misses 905system.cpu.icache.ReadReq_miss_latency::cpu.inst 5817859355 # number of ReadReq miss cycles 906system.cpu.icache.ReadReq_miss_latency::total 5817859355 # number of ReadReq miss cycles 907system.cpu.icache.demand_miss_latency::cpu.inst 5817859355 # number of demand (read+write) miss cycles 908system.cpu.icache.demand_miss_latency::total 5817859355 # number of demand (read+write) miss cycles 909system.cpu.icache.overall_miss_latency::cpu.inst 5817859355 # number of overall miss cycles 910system.cpu.icache.overall_miss_latency::total 5817859355 # number of overall miss cycles 911system.cpu.icache.ReadReq_accesses::cpu.inst 22433349 # number of ReadReq accesses(hits+misses) 912system.cpu.icache.ReadReq_accesses::total 22433349 # number of ReadReq accesses(hits+misses) 913system.cpu.icache.demand_accesses::cpu.inst 22433349 # number of demand (read+write) accesses 914system.cpu.icache.demand_accesses::total 22433349 # number of demand (read+write) accesses 915system.cpu.icache.overall_accesses::cpu.inst 22433349 # number of overall (read+write) accesses 916system.cpu.icache.overall_accesses::total 22433349 # number of overall (read+write) accesses 917system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015045 # miss rate for ReadReq accesses 918system.cpu.icache.ReadReq_miss_rate::total 0.015045 # miss rate for ReadReq accesses 919system.cpu.icache.demand_miss_rate::cpu.inst 0.015045 # miss rate for demand accesses 920system.cpu.icache.demand_miss_rate::total 0.015045 # miss rate for demand accesses 921system.cpu.icache.overall_miss_rate::cpu.inst 0.015045 # miss rate for overall accesses 922system.cpu.icache.overall_miss_rate::total 0.015045 # miss rate for overall accesses 923system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17237.437832 # average ReadReq miss latency 924system.cpu.icache.ReadReq_avg_miss_latency::total 17237.437832 # average ReadReq miss latency 925system.cpu.icache.demand_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency 926system.cpu.icache.demand_avg_miss_latency::total 17237.437832 # average overall miss latency 927system.cpu.icache.overall_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency 928system.cpu.icache.overall_avg_miss_latency::total 17237.437832 # average overall miss latency 929system.cpu.icache.blocked_cycles::no_mshrs 562602 # number of cycles access was blocked 930system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked 931system.cpu.icache.blocked::no_mshrs 26054 # number of cycles access was blocked |
| 921system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked | 932system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked |
| 922system.cpu.icache.avg_blocked_cycles::no_mshrs 21.298114 # average number of cycles each access was blocked 923system.cpu.icache.avg_blocked_cycles::no_targets 26.500000 # average number of cycles each access was blocked 924system.cpu.icache.writebacks::writebacks 325915 # number of writebacks 925system.cpu.icache.writebacks::total 325915 # number of writebacks 926system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11245 # number of ReadReq MSHR hits 927system.cpu.icache.ReadReq_mshr_hits::total 11245 # number of ReadReq MSHR hits 928system.cpu.icache.demand_mshr_hits::cpu.inst 11245 # number of demand (read+write) MSHR hits 929system.cpu.icache.demand_mshr_hits::total 11245 # number of demand (read+write) MSHR hits 930system.cpu.icache.overall_mshr_hits::cpu.inst 11245 # number of overall MSHR hits 931system.cpu.icache.overall_mshr_hits::total 11245 # number of overall MSHR hits 932system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326440 # number of ReadReq MSHR misses 933system.cpu.icache.ReadReq_mshr_misses::total 326440 # number of ReadReq MSHR misses 934system.cpu.icache.demand_mshr_misses::cpu.inst 326440 # number of demand (read+write) MSHR misses 935system.cpu.icache.demand_mshr_misses::total 326440 # number of demand (read+write) MSHR misses 936system.cpu.icache.overall_mshr_misses::cpu.inst 326440 # number of overall MSHR misses 937system.cpu.icache.overall_mshr_misses::total 326440 # number of overall MSHR misses 938system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5156036946 # number of ReadReq MSHR miss cycles 939system.cpu.icache.ReadReq_mshr_miss_latency::total 5156036946 # number of ReadReq MSHR miss cycles 940system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5156036946 # number of demand (read+write) MSHR miss cycles 941system.cpu.icache.demand_mshr_miss_latency::total 5156036946 # number of demand (read+write) MSHR miss cycles 942system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5156036946 # number of overall MSHR miss cycles 943system.cpu.icache.overall_mshr_miss_latency::total 5156036946 # number of overall MSHR miss cycles 944system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for ReadReq accesses 945system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014552 # mshr miss rate for ReadReq accesses 946system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for demand accesses 947system.cpu.icache.demand_mshr_miss_rate::total 0.014552 # mshr miss rate for demand accesses 948system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for overall accesses 949system.cpu.icache.overall_mshr_miss_rate::total 0.014552 # mshr miss rate for overall accesses 950system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15794.746189 # average ReadReq mshr miss latency 951system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15794.746189 # average ReadReq mshr miss latency 952system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency 953system.cpu.icache.demand_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency 954system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency 955system.cpu.icache.overall_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency 956system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 957system.cpu.l2cache.prefetcher.num_hwpf_issued 822007 # number of hwpf issued 958system.cpu.l2cache.prefetcher.pfIdentified 825699 # number of prefetch candidates identified 959system.cpu.l2cache.prefetcher.pfBufferHit 3235 # number of redundant prefetches already in prefetch queue | 933system.cpu.icache.avg_blocked_cycles::no_mshrs 21.593690 # average number of cycles each access was blocked 934system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked 935system.cpu.icache.writebacks::writebacks 325639 # number of writebacks 936system.cpu.icache.writebacks::total 325639 # number of writebacks 937system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11348 # number of ReadReq MSHR hits 938system.cpu.icache.ReadReq_mshr_hits::total 11348 # number of ReadReq MSHR hits 939system.cpu.icache.demand_mshr_hits::cpu.inst 11348 # number of demand (read+write) MSHR hits 940system.cpu.icache.demand_mshr_hits::total 11348 # number of demand (read+write) MSHR hits 941system.cpu.icache.overall_mshr_hits::cpu.inst 11348 # number of overall MSHR hits 942system.cpu.icache.overall_mshr_hits::total 11348 # number of overall MSHR hits 943system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326165 # number of ReadReq MSHR misses 944system.cpu.icache.ReadReq_mshr_misses::total 326165 # number of ReadReq MSHR misses 945system.cpu.icache.demand_mshr_misses::cpu.inst 326165 # number of demand (read+write) MSHR misses 946system.cpu.icache.demand_mshr_misses::total 326165 # number of demand (read+write) MSHR misses 947system.cpu.icache.overall_mshr_misses::cpu.inst 326165 # number of overall MSHR misses 948system.cpu.icache.overall_mshr_misses::total 326165 # number of overall MSHR misses 949system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5383419413 # number of ReadReq MSHR miss cycles 950system.cpu.icache.ReadReq_mshr_miss_latency::total 5383419413 # number of ReadReq MSHR miss cycles 951system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5383419413 # number of demand (read+write) MSHR miss cycles 952system.cpu.icache.demand_mshr_miss_latency::total 5383419413 # number of demand (read+write) MSHR miss cycles 953system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5383419413 # number of overall MSHR miss cycles 954system.cpu.icache.overall_mshr_miss_latency::total 5383419413 # number of overall MSHR miss cycles 955system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for ReadReq accesses 956system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses 957system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for demand accesses 958system.cpu.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses 959system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for overall accesses 960system.cpu.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses 961system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16505.202621 # average ReadReq mshr miss latency 962system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16505.202621 # average ReadReq mshr miss latency 963system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency 964system.cpu.icache.demand_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency 965system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency 966system.cpu.icache.overall_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency 967system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 968system.cpu.l2cache.prefetcher.num_hwpf_issued 823055 # number of hwpf issued 969system.cpu.l2cache.prefetcher.pfIdentified 826389 # number of prefetch candidates identified 970system.cpu.l2cache.prefetcher.pfBufferHit 2921 # number of redundant prefetches already in prefetch queue |
| 960system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 961system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 971system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 972system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 962system.cpu.l2cache.prefetcher.pfSpanPage 78661 # number of prefetches not generated due to page crossing 963system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 964system.cpu.l2cache.tags.replacements 125486 # number of replacements 965system.cpu.l2cache.tags.tagsinuse 15697.579441 # Cycle average of tags in use 966system.cpu.l2cache.tags.total_refs 682126 # Total number of references to valid blocks. 967system.cpu.l2cache.tags.sampled_refs 141813 # Sample count of references to valid blocks. 968system.cpu.l2cache.tags.avg_refs 4.810039 # Average number of references to valid blocks. | 973system.cpu.l2cache.prefetcher.pfSpanPage 78691 # number of prefetches not generated due to page crossing 974system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 975system.cpu.l2cache.tags.replacements 125520 # number of replacements 976system.cpu.l2cache.tags.tagsinuse 15698.936659 # Cycle average of tags in use 977system.cpu.l2cache.tags.total_refs 681800 # Total number of references to valid blocks. 978system.cpu.l2cache.tags.sampled_refs 141835 # Sample count of references to valid blocks. 979system.cpu.l2cache.tags.avg_refs 4.806994 # Average number of references to valid blocks. |
| 969system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 980system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 970system.cpu.l2cache.tags.occ_blocks::writebacks 15632.148504 # Average occupied blocks per requestor 971system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 65.430937 # Average occupied blocks per requestor 972system.cpu.l2cache.tags.occ_percent::writebacks 0.954111 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003994 # Average percentage of cache occupancy 974system.cpu.l2cache.tags.occ_percent::total 0.958104 # Average percentage of cache occupancy 975system.cpu.l2cache.tags.occ_task_id_blocks::1022 23 # Occupied blocks per task id 976system.cpu.l2cache.tags.occ_task_id_blocks::1024 16304 # Occupied blocks per task id | 981system.cpu.l2cache.tags.occ_blocks::writebacks 15629.036475 # Average occupied blocks per requestor 982system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 69.900184 # Average occupied blocks per requestor 983system.cpu.l2cache.tags.occ_percent::writebacks 0.953921 # Average percentage of cache occupancy 984system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004266 # Average percentage of cache occupancy 985system.cpu.l2cache.tags.occ_percent::total 0.958187 # Average percentage of cache occupancy 986system.cpu.l2cache.tags.occ_task_id_blocks::1022 27 # Occupied blocks per task id 987system.cpu.l2cache.tags.occ_task_id_blocks::1024 16288 # Occupied blocks per task id |
| 977system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id | 988system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id |
| 978system.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1022::3 12 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2745 # Occupied blocks per task id 983system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12082 # Occupied blocks per task id 984system.cpu.l2cache.tags.age_task_id_blocks_1024::3 548 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1024::4 792 # Occupied blocks per task id 986system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001404 # Percentage of cache occupancy per task id 987system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id 988system.cpu.l2cache.tags.tag_accesses 25510486 # Number of tag accesses 989system.cpu.l2cache.tags.data_accesses 25510486 # Number of data accesses 990system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 991system.cpu.l2cache.WritebackDirty_hits::writebacks 254711 # number of WritebackDirty hits 992system.cpu.l2cache.WritebackDirty_hits::total 254711 # number of WritebackDirty hits 993system.cpu.l2cache.WritebackClean_hits::writebacks 476176 # number of WritebackClean hits 994system.cpu.l2cache.WritebackClean_hits::total 476176 # number of WritebackClean hits 995system.cpu.l2cache.ReadExReq_hits::cpu.data 137223 # number of ReadExReq hits 996system.cpu.l2cache.ReadExReq_hits::total 137223 # number of ReadExReq hits 997system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 289219 # number of ReadCleanReq hits 998system.cpu.l2cache.ReadCleanReq_hits::total 289219 # number of ReadCleanReq hits 999system.cpu.l2cache.ReadSharedReq_hits::cpu.data 256138 # number of ReadSharedReq hits 1000system.cpu.l2cache.ReadSharedReq_hits::total 256138 # number of ReadSharedReq hits 1001system.cpu.l2cache.demand_hits::cpu.inst 289219 # number of demand (read+write) hits 1002system.cpu.l2cache.demand_hits::cpu.data 393361 # number of demand (read+write) hits 1003system.cpu.l2cache.demand_hits::total 682580 # number of demand (read+write) hits 1004system.cpu.l2cache.overall_hits::cpu.inst 289219 # number of overall hits 1005system.cpu.l2cache.overall_hits::cpu.data 393361 # number of overall hits 1006system.cpu.l2cache.overall_hits::total 682580 # number of overall hits 1007system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 1008system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 1009system.cpu.l2cache.ReadExReq_misses::cpu.data 11378 # number of ReadExReq misses 1010system.cpu.l2cache.ReadExReq_misses::total 11378 # number of ReadExReq misses 1011system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37206 # number of ReadCleanReq misses 1012system.cpu.l2cache.ReadCleanReq_misses::total 37206 # number of ReadCleanReq misses 1013system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80635 # number of ReadSharedReq misses 1014system.cpu.l2cache.ReadSharedReq_misses::total 80635 # number of ReadSharedReq misses 1015system.cpu.l2cache.demand_misses::cpu.inst 37206 # number of demand (read+write) misses 1016system.cpu.l2cache.demand_misses::cpu.data 92013 # number of demand (read+write) misses 1017system.cpu.l2cache.demand_misses::total 129219 # number of demand (read+write) misses 1018system.cpu.l2cache.overall_misses::cpu.inst 37206 # number of overall misses 1019system.cpu.l2cache.overall_misses::cpu.data 92013 # number of overall misses 1020system.cpu.l2cache.overall_misses::total 129219 # number of overall misses 1021system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1158421000 # number of ReadExReq miss cycles 1022system.cpu.l2cache.ReadExReq_miss_latency::total 1158421000 # number of ReadExReq miss cycles 1023system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2926655500 # number of ReadCleanReq miss cycles 1024system.cpu.l2cache.ReadCleanReq_miss_latency::total 2926655500 # number of ReadCleanReq miss cycles 1025system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6384062000 # number of ReadSharedReq miss cycles 1026system.cpu.l2cache.ReadSharedReq_miss_latency::total 6384062000 # number of ReadSharedReq miss cycles 1027system.cpu.l2cache.demand_miss_latency::cpu.inst 2926655500 # number of demand (read+write) miss cycles 1028system.cpu.l2cache.demand_miss_latency::cpu.data 7542483000 # number of demand (read+write) miss cycles 1029system.cpu.l2cache.demand_miss_latency::total 10469138500 # number of demand (read+write) miss cycles 1030system.cpu.l2cache.overall_miss_latency::cpu.inst 2926655500 # number of overall miss cycles 1031system.cpu.l2cache.overall_miss_latency::cpu.data 7542483000 # number of overall miss cycles 1032system.cpu.l2cache.overall_miss_latency::total 10469138500 # number of overall miss cycles 1033system.cpu.l2cache.WritebackDirty_accesses::writebacks 254711 # number of WritebackDirty accesses(hits+misses) 1034system.cpu.l2cache.WritebackDirty_accesses::total 254711 # number of WritebackDirty accesses(hits+misses) 1035system.cpu.l2cache.WritebackClean_accesses::writebacks 476176 # number of WritebackClean accesses(hits+misses) 1036system.cpu.l2cache.WritebackClean_accesses::total 476176 # number of WritebackClean accesses(hits+misses) 1037system.cpu.l2cache.UpgradeReq_accesses::cpu.data 12 # number of UpgradeReq accesses(hits+misses) 1038system.cpu.l2cache.UpgradeReq_accesses::total 12 # number of UpgradeReq accesses(hits+misses) 1039system.cpu.l2cache.ReadExReq_accesses::cpu.data 148601 # number of ReadExReq accesses(hits+misses) 1040system.cpu.l2cache.ReadExReq_accesses::total 148601 # number of ReadExReq accesses(hits+misses) 1041system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 326425 # number of ReadCleanReq accesses(hits+misses) 1042system.cpu.l2cache.ReadCleanReq_accesses::total 326425 # number of ReadCleanReq accesses(hits+misses) 1043system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336773 # number of ReadSharedReq accesses(hits+misses) 1044system.cpu.l2cache.ReadSharedReq_accesses::total 336773 # number of ReadSharedReq accesses(hits+misses) 1045system.cpu.l2cache.demand_accesses::cpu.inst 326425 # number of demand (read+write) accesses 1046system.cpu.l2cache.demand_accesses::cpu.data 485374 # number of demand (read+write) accesses 1047system.cpu.l2cache.demand_accesses::total 811799 # number of demand (read+write) accesses 1048system.cpu.l2cache.overall_accesses::cpu.inst 326425 # number of overall (read+write) accesses 1049system.cpu.l2cache.overall_accesses::cpu.data 485374 # number of overall (read+write) accesses 1050system.cpu.l2cache.overall_accesses::total 811799 # number of overall (read+write) accesses | 989system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2543 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12218 # Occupied blocks per task id 995system.cpu.l2cache.tags.age_task_id_blocks_1024::3 510 # Occupied blocks per task id 996system.cpu.l2cache.tags.age_task_id_blocks_1024::4 881 # Occupied blocks per task id 997system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001648 # Percentage of cache occupancy per task id 998system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 999system.cpu.l2cache.tags.tag_accesses 25499859 # Number of tag accesses 1000system.cpu.l2cache.tags.data_accesses 25499859 # Number of data accesses 1001system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 1002system.cpu.l2cache.WritebackDirty_hits::writebacks 257633 # number of WritebackDirty hits 1003system.cpu.l2cache.WritebackDirty_hits::total 257633 # number of WritebackDirty hits 1004system.cpu.l2cache.WritebackClean_hits::writebacks 472926 # number of WritebackClean hits 1005system.cpu.l2cache.WritebackClean_hits::total 472926 # number of WritebackClean hits 1006system.cpu.l2cache.ReadExReq_hits::cpu.data 137172 # number of ReadExReq hits 1007system.cpu.l2cache.ReadExReq_hits::total 137172 # number of ReadExReq hits 1008system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 289056 # number of ReadCleanReq hits 1009system.cpu.l2cache.ReadCleanReq_hits::total 289056 # number of ReadCleanReq hits 1010system.cpu.l2cache.ReadSharedReq_hits::cpu.data 255940 # number of ReadSharedReq hits 1011system.cpu.l2cache.ReadSharedReq_hits::total 255940 # number of ReadSharedReq hits 1012system.cpu.l2cache.demand_hits::cpu.inst 289056 # number of demand (read+write) hits 1013system.cpu.l2cache.demand_hits::cpu.data 393112 # number of demand (read+write) hits 1014system.cpu.l2cache.demand_hits::total 682168 # number of demand (read+write) hits 1015system.cpu.l2cache.overall_hits::cpu.inst 289056 # number of overall hits 1016system.cpu.l2cache.overall_hits::cpu.data 393112 # number of overall hits 1017system.cpu.l2cache.overall_hits::total 682168 # number of overall hits 1018system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 1019system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 1020system.cpu.l2cache.ReadExReq_misses::cpu.data 11425 # number of ReadExReq misses 1021system.cpu.l2cache.ReadExReq_misses::total 11425 # number of ReadExReq misses 1022system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37095 # number of ReadCleanReq misses 1023system.cpu.l2cache.ReadCleanReq_misses::total 37095 # number of ReadCleanReq misses 1024system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80789 # number of ReadSharedReq misses 1025system.cpu.l2cache.ReadSharedReq_misses::total 80789 # number of ReadSharedReq misses 1026system.cpu.l2cache.demand_misses::cpu.inst 37095 # number of demand (read+write) misses 1027system.cpu.l2cache.demand_misses::cpu.data 92214 # number of demand (read+write) misses 1028system.cpu.l2cache.demand_misses::total 129309 # number of demand (read+write) misses 1029system.cpu.l2cache.overall_misses::cpu.inst 37095 # number of overall misses 1030system.cpu.l2cache.overall_misses::cpu.data 92214 # number of overall misses 1031system.cpu.l2cache.overall_misses::total 129309 # number of overall misses 1032system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1226064500 # number of ReadExReq miss cycles 1033system.cpu.l2cache.ReadExReq_miss_latency::total 1226064500 # number of ReadExReq miss cycles 1034system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3155473000 # number of ReadCleanReq miss cycles 1035system.cpu.l2cache.ReadCleanReq_miss_latency::total 3155473000 # number of ReadCleanReq miss cycles 1036system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6910815500 # number of ReadSharedReq miss cycles 1037system.cpu.l2cache.ReadSharedReq_miss_latency::total 6910815500 # number of ReadSharedReq miss cycles 1038system.cpu.l2cache.demand_miss_latency::cpu.inst 3155473000 # number of demand (read+write) miss cycles 1039system.cpu.l2cache.demand_miss_latency::cpu.data 8136880000 # number of demand (read+write) miss cycles 1040system.cpu.l2cache.demand_miss_latency::total 11292353000 # number of demand (read+write) miss cycles 1041system.cpu.l2cache.overall_miss_latency::cpu.inst 3155473000 # number of overall miss cycles 1042system.cpu.l2cache.overall_miss_latency::cpu.data 8136880000 # number of overall miss cycles 1043system.cpu.l2cache.overall_miss_latency::total 11292353000 # number of overall miss cycles 1044system.cpu.l2cache.WritebackDirty_accesses::writebacks 257633 # number of WritebackDirty accesses(hits+misses) 1045system.cpu.l2cache.WritebackDirty_accesses::total 257633 # number of WritebackDirty accesses(hits+misses) 1046system.cpu.l2cache.WritebackClean_accesses::writebacks 472926 # number of WritebackClean accesses(hits+misses) 1047system.cpu.l2cache.WritebackClean_accesses::total 472926 # number of WritebackClean accesses(hits+misses) 1048system.cpu.l2cache.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) 1049system.cpu.l2cache.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) 1050system.cpu.l2cache.ReadExReq_accesses::cpu.data 148597 # number of ReadExReq accesses(hits+misses) 1051system.cpu.l2cache.ReadExReq_accesses::total 148597 # number of ReadExReq accesses(hits+misses) 1052system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 326151 # number of ReadCleanReq accesses(hits+misses) 1053system.cpu.l2cache.ReadCleanReq_accesses::total 326151 # number of ReadCleanReq accesses(hits+misses) 1054system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336729 # number of ReadSharedReq accesses(hits+misses) 1055system.cpu.l2cache.ReadSharedReq_accesses::total 336729 # number of ReadSharedReq accesses(hits+misses) 1056system.cpu.l2cache.demand_accesses::cpu.inst 326151 # number of demand (read+write) accesses 1057system.cpu.l2cache.demand_accesses::cpu.data 485326 # number of demand (read+write) accesses 1058system.cpu.l2cache.demand_accesses::total 811477 # number of demand (read+write) accesses 1059system.cpu.l2cache.overall_accesses::cpu.inst 326151 # number of overall (read+write) accesses 1060system.cpu.l2cache.overall_accesses::cpu.data 485326 # number of overall (read+write) accesses 1061system.cpu.l2cache.overall_accesses::total 811477 # number of overall (read+write) accesses |
| 1051system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1052system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 1062system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1063system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 1053system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076567 # miss rate for ReadExReq accesses 1054system.cpu.l2cache.ReadExReq_miss_rate::total 0.076567 # miss rate for ReadExReq accesses 1055system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113980 # miss rate for ReadCleanReq accesses 1056system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113980 # miss rate for ReadCleanReq accesses 1057system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239434 # miss rate for ReadSharedReq accesses 1058system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239434 # miss rate for ReadSharedReq accesses 1059system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113980 # miss rate for demand accesses 1060system.cpu.l2cache.demand_miss_rate::cpu.data 0.189571 # miss rate for demand accesses 1061system.cpu.l2cache.demand_miss_rate::total 0.159176 # miss rate for demand accesses 1062system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113980 # miss rate for overall accesses 1063system.cpu.l2cache.overall_miss_rate::cpu.data 0.189571 # miss rate for overall accesses 1064system.cpu.l2cache.overall_miss_rate::total 0.159176 # miss rate for overall accesses 1065system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101812.357181 # average ReadExReq miss latency 1066system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101812.357181 # average ReadExReq miss latency 1067system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78660.847713 # average ReadCleanReq miss latency 1068system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78660.847713 # average ReadCleanReq miss latency 1069system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79172.344515 # average ReadSharedReq miss latency 1070system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79172.344515 # average ReadSharedReq miss latency 1071system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78660.847713 # average overall miss latency 1072system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81971.927880 # average overall miss latency 1073system.cpu.l2cache.demand_avg_miss_latency::total 81018.569251 # average overall miss latency 1074system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78660.847713 # average overall miss latency 1075system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81971.927880 # average overall miss latency 1076system.cpu.l2cache.overall_avg_miss_latency::total 81018.569251 # average overall miss latency | 1064system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076886 # miss rate for ReadExReq accesses 1065system.cpu.l2cache.ReadExReq_miss_rate::total 0.076886 # miss rate for ReadExReq accesses 1066system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113736 # miss rate for ReadCleanReq accesses 1067system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113736 # miss rate for ReadCleanReq accesses 1068system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239923 # miss rate for ReadSharedReq accesses 1069system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239923 # miss rate for ReadSharedReq accesses 1070system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113736 # miss rate for demand accesses 1071system.cpu.l2cache.demand_miss_rate::cpu.data 0.190004 # miss rate for demand accesses 1072system.cpu.l2cache.demand_miss_rate::total 0.159350 # miss rate for demand accesses 1073system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113736 # miss rate for overall accesses 1074system.cpu.l2cache.overall_miss_rate::cpu.data 0.190004 # miss rate for overall accesses 1075system.cpu.l2cache.overall_miss_rate::total 0.159350 # miss rate for overall accesses 1076system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107314.179431 # average ReadExReq miss latency 1077system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107314.179431 # average ReadExReq miss latency 1078system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85064.644831 # average ReadCleanReq miss latency 1079system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85064.644831 # average ReadCleanReq miss latency 1080system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85541.540309 # average ReadSharedReq miss latency 1081system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85541.540309 # average ReadSharedReq miss latency 1082system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85064.644831 # average overall miss latency 1083system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88239.096016 # average overall miss latency 1084system.cpu.l2cache.demand_avg_miss_latency::total 87328.438082 # average overall miss latency 1085system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85064.644831 # average overall miss latency 1086system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88239.096016 # average overall miss latency 1087system.cpu.l2cache.overall_avg_miss_latency::total 87328.438082 # average overall miss latency |
| 1077system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1078system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1080system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1082system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1088system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1089system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1090system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1091system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1092system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1093system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1083system.cpu.l2cache.unused_prefetches 412 # number of HardPF blocks evicted w/o reference 1084system.cpu.l2cache.writebacks::writebacks 97262 # number of writebacks 1085system.cpu.l2cache.writebacks::total 97262 # number of writebacks 1086system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2980 # number of ReadExReq MSHR hits 1087system.cpu.l2cache.ReadExReq_mshr_hits::total 2980 # number of ReadExReq MSHR hits 1088system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 28 # number of ReadCleanReq MSHR hits 1089system.cpu.l2cache.ReadCleanReq_mshr_hits::total 28 # number of ReadCleanReq MSHR hits 1090system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 115 # number of ReadSharedReq MSHR hits 1091system.cpu.l2cache.ReadSharedReq_mshr_hits::total 115 # number of ReadSharedReq MSHR hits 1092system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits 1093system.cpu.l2cache.demand_mshr_hits::cpu.data 3095 # number of demand (read+write) MSHR hits 1094system.cpu.l2cache.demand_mshr_hits::total 3123 # number of demand (read+write) MSHR hits 1095system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits 1096system.cpu.l2cache.overall_mshr_hits::cpu.data 3095 # number of overall MSHR hits 1097system.cpu.l2cache.overall_mshr_hits::total 3123 # number of overall MSHR hits 1098system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 115252 # number of HardPFReq MSHR misses 1099system.cpu.l2cache.HardPFReq_mshr_misses::total 115252 # number of HardPFReq MSHR misses 1100system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 12 # number of UpgradeReq MSHR misses 1101system.cpu.l2cache.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses 1102system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8398 # number of ReadExReq MSHR misses 1103system.cpu.l2cache.ReadExReq_mshr_misses::total 8398 # number of ReadExReq MSHR misses 1104system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37178 # number of ReadCleanReq MSHR misses 1105system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37178 # number of ReadCleanReq MSHR misses 1106system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80520 # number of ReadSharedReq MSHR misses 1107system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80520 # number of ReadSharedReq MSHR misses 1108system.cpu.l2cache.demand_mshr_misses::cpu.inst 37178 # number of demand (read+write) MSHR misses 1109system.cpu.l2cache.demand_mshr_misses::cpu.data 88918 # number of demand (read+write) MSHR misses 1110system.cpu.l2cache.demand_mshr_misses::total 126096 # number of demand (read+write) MSHR misses 1111system.cpu.l2cache.overall_mshr_misses::cpu.inst 37178 # number of overall MSHR misses 1112system.cpu.l2cache.overall_mshr_misses::cpu.data 88918 # number of overall MSHR misses 1113system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115252 # number of overall MSHR misses 1114system.cpu.l2cache.overall_mshr_misses::total 241348 # number of overall MSHR misses 1115system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 9954483724 # number of HardPFReq MSHR miss cycles 1116system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 9954483724 # number of HardPFReq MSHR miss cycles 1117system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185500 # number of UpgradeReq MSHR miss cycles 1118system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185500 # number of UpgradeReq MSHR miss cycles 1119system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 680267500 # number of ReadExReq MSHR miss cycles 1120system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 680267500 # number of ReadExReq MSHR miss cycles 1121system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2701591500 # number of ReadCleanReq MSHR miss cycles 1122system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2701591500 # number of ReadCleanReq MSHR miss cycles 1123system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5893524000 # number of ReadSharedReq MSHR miss cycles 1124system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5893524000 # number of ReadSharedReq MSHR miss cycles 1125system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2701591500 # number of demand (read+write) MSHR miss cycles 1126system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6573791500 # number of demand (read+write) MSHR miss cycles 1127system.cpu.l2cache.demand_mshr_miss_latency::total 9275383000 # number of demand (read+write) MSHR miss cycles 1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2701591500 # number of overall MSHR miss cycles 1129system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6573791500 # number of overall MSHR miss cycles 1130system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 9954483724 # number of overall MSHR miss cycles 1131system.cpu.l2cache.overall_mshr_miss_latency::total 19229866724 # number of overall MSHR miss cycles | 1094system.cpu.l2cache.unused_prefetches 452 # number of HardPF blocks evicted w/o reference 1095system.cpu.l2cache.writebacks::writebacks 97298 # number of writebacks 1096system.cpu.l2cache.writebacks::total 97298 # number of writebacks 1097system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3085 # number of ReadExReq MSHR hits 1098system.cpu.l2cache.ReadExReq_mshr_hits::total 3085 # number of ReadExReq MSHR hits 1099system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits 1100system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits 1101system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 119 # number of ReadSharedReq MSHR hits 1102system.cpu.l2cache.ReadSharedReq_mshr_hits::total 119 # number of ReadSharedReq MSHR hits 1103system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits 1104system.cpu.l2cache.demand_mshr_hits::cpu.data 3204 # number of demand (read+write) MSHR hits 1105system.cpu.l2cache.demand_mshr_hits::total 3227 # number of demand (read+write) MSHR hits 1106system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits 1107system.cpu.l2cache.overall_mshr_hits::cpu.data 3204 # number of overall MSHR hits 1108system.cpu.l2cache.overall_mshr_hits::total 3227 # number of overall MSHR hits 1109system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 115310 # number of HardPFReq MSHR misses 1110system.cpu.l2cache.HardPFReq_mshr_misses::total 115310 # number of HardPFReq MSHR misses 1111system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 1112system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 1113system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8340 # number of ReadExReq MSHR misses 1114system.cpu.l2cache.ReadExReq_mshr_misses::total 8340 # number of ReadExReq MSHR misses 1115system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37072 # number of ReadCleanReq MSHR misses 1116system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37072 # number of ReadCleanReq MSHR misses 1117system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80670 # number of ReadSharedReq MSHR misses 1118system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80670 # number of ReadSharedReq MSHR misses 1119system.cpu.l2cache.demand_mshr_misses::cpu.inst 37072 # number of demand (read+write) MSHR misses 1120system.cpu.l2cache.demand_mshr_misses::cpu.data 89010 # number of demand (read+write) MSHR misses 1121system.cpu.l2cache.demand_mshr_misses::total 126082 # number of demand (read+write) MSHR misses 1122system.cpu.l2cache.overall_mshr_misses::cpu.inst 37072 # number of overall MSHR misses 1123system.cpu.l2cache.overall_mshr_misses::cpu.data 89010 # number of overall MSHR misses 1124system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115310 # number of overall MSHR misses 1125system.cpu.l2cache.overall_mshr_misses::total 241392 # number of overall MSHR misses 1126system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10321796922 # number of HardPFReq MSHR miss cycles 1127system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10321796922 # number of HardPFReq MSHR miss cycles 1128system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 201500 # number of UpgradeReq MSHR miss cycles 1129system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 201500 # number of UpgradeReq MSHR miss cycles 1130system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 722790000 # number of ReadExReq MSHR miss cycles 1131system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 722790000 # number of ReadExReq MSHR miss cycles 1132system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2931479000 # number of ReadCleanReq MSHR miss cycles 1133system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2931479000 # number of ReadCleanReq MSHR miss cycles 1134system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6418843000 # number of ReadSharedReq MSHR miss cycles 1135system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6418843000 # number of ReadSharedReq MSHR miss cycles 1136system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2931479000 # number of demand (read+write) MSHR miss cycles 1137system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7141633000 # number of demand (read+write) MSHR miss cycles 1138system.cpu.l2cache.demand_mshr_miss_latency::total 10073112000 # number of demand (read+write) MSHR miss cycles 1139system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2931479000 # number of overall MSHR miss cycles 1140system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7141633000 # number of overall MSHR miss cycles 1141system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10321796922 # number of overall MSHR miss cycles 1142system.cpu.l2cache.overall_mshr_miss_latency::total 20394908922 # number of overall MSHR miss cycles |
| 1132system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1133system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1134system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1135system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 1143system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1144system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1145system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1146system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 1136system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056514 # mshr miss rate for ReadExReq accesses 1137system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056514 # mshr miss rate for ReadExReq accesses 1138system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for ReadCleanReq accesses 1139system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113894 # mshr miss rate for ReadCleanReq accesses 1140system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239093 # mshr miss rate for ReadSharedReq accesses 1141system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239093 # mshr miss rate for ReadSharedReq accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for demand accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for demand accesses 1144system.cpu.l2cache.demand_mshr_miss_rate::total 0.155329 # mshr miss rate for demand accesses 1145system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for overall accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for overall accesses | 1147system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056125 # mshr miss rate for ReadExReq accesses 1148system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056125 # mshr miss rate for ReadExReq accesses 1149system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for ReadCleanReq accesses 1150system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113665 # mshr miss rate for ReadCleanReq accesses 1151system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239570 # mshr miss rate for ReadSharedReq accesses 1152system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239570 # mshr miss rate for ReadSharedReq accesses 1153system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for demand accesses 1154system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for demand accesses 1155system.cpu.l2cache.demand_mshr_miss_rate::total 0.155373 # mshr miss rate for demand accesses 1156system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for overall accesses 1157system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for overall accesses |
| 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1158system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1148system.cpu.l2cache.overall_mshr_miss_rate::total 0.297300 # mshr miss rate for overall accesses 1149system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average HardPFReq mshr miss latency 1150system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 86371.461875 # average HardPFReq mshr miss latency 1151system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15458.333333 # average UpgradeReq mshr miss latency 1152system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15458.333333 # average UpgradeReq mshr miss latency 1153system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81003.512741 # average ReadExReq mshr miss latency 1154system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81003.512741 # average ReadExReq mshr miss latency 1155system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72666.402173 # average ReadCleanReq mshr miss latency 1156system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72666.402173 # average ReadCleanReq mshr miss latency 1157system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73193.293592 # average ReadSharedReq mshr miss latency 1158system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73193.293592 # average ReadSharedReq mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73558.106522 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79676.925949 # average overall mshr miss latency 1166system.cpu.toL2Bus.snoop_filter.tot_requests 1622603 # Total number of requests made to the snoop filter. 1167system.cpu.toL2Bus.snoop_filter.hit_single_requests 810817 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1168system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79904 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1169system.cpu.toL2Bus.snoop_filter.tot_snoops 18775 # Total number of snoops made to the snoop filter. 1170system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18774 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1159system.cpu.l2cache.overall_mshr_miss_rate::total 0.297472 # mshr miss rate for overall accesses 1160system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average HardPFReq mshr miss latency 1161system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89513.458694 # average HardPFReq mshr miss latency 1162system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency 1163system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency 1164system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86665.467626 # average ReadExReq mshr miss latency 1165system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86665.467626 # average ReadExReq mshr miss latency 1166system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79075.285930 # average ReadCleanReq mshr miss latency 1167system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79075.285930 # average ReadCleanReq mshr miss latency 1168system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79569.145903 # average ReadSharedReq mshr miss latency 1169system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79569.145903 # average ReadSharedReq mshr miss latency 1170system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency 1171system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency 1172system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79893.339255 # average overall mshr miss latency 1173system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency 1174system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency 1175system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average overall mshr miss latency 1176system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84488.752411 # average overall mshr miss latency 1177system.cpu.toL2Bus.snoop_filter.tot_requests 1621957 # Total number of requests made to the snoop filter. 1178system.cpu.toL2Bus.snoop_filter.hit_single_requests 810494 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1179system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1180system.cpu.toL2Bus.snoop_filter.tot_snoops 18773 # Total number of snoops made to the snoop filter. 1181system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18772 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1171system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1182system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1172system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 1173system.cpu.toL2Bus.trans_dist::ReadResp 663212 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::WritebackDirty 351973 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::WritebackClean 556066 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::CleanEvict 28224 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::HardPFReq 144126 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::ReadExReq 148601 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::ReadExResp 148601 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::ReadCleanReq 326440 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::ReadSharedReq 336773 # Transaction distribution 1184system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 978779 # Packet count per connected master and slave (bytes) 1185system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455634 # Packet count per connected master and slave (bytes) 1186system.cpu.toL2Bus.pkt_count::total 2434413 # Packet count per connected master and slave (bytes) 1187system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41749696 # Cumulative packet size per connected master and slave (bytes) 1188system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62095104 # Cumulative packet size per connected master and slave (bytes) 1189system.cpu.toL2Bus.pkt_size::total 103844800 # Cumulative packet size per connected master and slave (bytes) 1190system.cpu.toL2Bus.snoops 269627 # Total snoops (count) 1191system.cpu.toL2Bus.snoopTraffic 6225728 # Total snoop traffic (bytes) 1192system.cpu.toL2Bus.snoop_fanout::samples 1081438 # Request fanout histogram 1193system.cpu.toL2Bus.snoop_fanout::mean 0.091286 # Request fanout histogram 1194system.cpu.toL2Bus.snoop_fanout::stdev 0.288019 # Request fanout histogram | 1183system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 1184system.cpu.toL2Bus.trans_dist::ReadResp 662893 # Transaction distribution 1185system.cpu.toL2Bus.trans_dist::WritebackDirty 354931 # Transaction distribution 1186system.cpu.toL2Bus.trans_dist::WritebackClean 552820 # Transaction distribution 1187system.cpu.toL2Bus.trans_dist::CleanEvict 28222 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::HardPFReq 146565 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::ReadExReq 148597 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::ReadExResp 148597 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::ReadCleanReq 326165 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::ReadSharedReq 336729 # Transaction distribution 1195system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977954 # Packet count per connected master and slave (bytes) 1196system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455492 # Packet count per connected master and slave (bytes) 1197system.cpu.toL2Bus.pkt_count::total 2433446 # Packet count per connected master and slave (bytes) 1198system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41714496 # Cumulative packet size per connected master and slave (bytes) 1199system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62088960 # Cumulative packet size per connected master and slave (bytes) 1200system.cpu.toL2Bus.pkt_size::total 103803456 # Cumulative packet size per connected master and slave (bytes) 1201system.cpu.toL2Bus.snoops 272099 # Total snoops (count) 1202system.cpu.toL2Bus.snoopTraffic 6227968 # Total snoop traffic (bytes) 1203system.cpu.toL2Bus.snoop_fanout::samples 1083589 # Request fanout histogram 1204system.cpu.toL2Bus.snoop_fanout::mean 0.091107 # Request fanout histogram 1205system.cpu.toL2Bus.snoop_fanout::stdev 0.287765 # Request fanout histogram |
| 1195system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1206system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1196system.cpu.toL2Bus.snoop_fanout::0 982719 90.87% 90.87% # Request fanout histogram 1197system.cpu.toL2Bus.snoop_fanout::1 98718 9.13% 100.00% # Request fanout histogram | 1207system.cpu.toL2Bus.snoop_fanout::0 984867 90.89% 90.89% # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::1 98721 9.11% 100.00% # Request fanout histogram |
| 1198system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1199system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1200system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1201system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1209system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1210system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1202system.cpu.toL2Bus.snoop_fanout::total 1081438 # Request fanout histogram 1203system.cpu.toL2Bus.reqLayer0.occupancy 1622078500 # Layer occupancy (ticks) 1204system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) 1205system.cpu.toL2Bus.respLayer0.occupancy 489794228 # Layer occupancy (ticks) | 1213system.cpu.toL2Bus.snoop_fanout::total 1083589 # Request fanout histogram 1214system.cpu.toL2Bus.reqLayer0.occupancy 1621431500 # Layer occupancy (ticks) 1215system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) 1216system.cpu.toL2Bus.respLayer0.occupancy 489373744 # Layer occupancy (ticks) |
| 1206system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) | 1217system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) |
| 1207system.cpu.toL2Bus.respLayer1.occupancy 728148836 # Layer occupancy (ticks) 1208system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) 1209system.membus.snoop_filter.tot_requests 348072 # Total number of requests made to the snoop filter. 1210system.membus.snoop_filter.hit_single_requests 205263 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1218system.cpu.toL2Bus.respLayer1.occupancy 728066857 # Layer occupancy (ticks) 1219system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) 1220system.membus.snoop_filter.tot_requests 348152 # Total number of requests made to the snoop filter. 1221system.membus.snoop_filter.hit_single_requests 205320 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1211system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1212system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1213system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1214system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1222system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1223system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1224system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1225system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1215system.membus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states 1216system.membus.trans_dist::ReadResp 214175 # Transaction distribution 1217system.membus.trans_dist::WritebackDirty 97262 # Transaction distribution 1218system.membus.trans_dist::CleanEvict 28224 # Transaction distribution 1219system.membus.trans_dist::UpgradeReq 12 # Transaction distribution 1220system.membus.trans_dist::ReadExReq 8398 # Transaction distribution 1221system.membus.trans_dist::ReadExResp 8398 # Transaction distribution 1222system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution 1223system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570645 # Packet count per connected master and slave (bytes) 1224system.membus.pkt_count::total 570645 # Packet count per connected master and slave (bytes) 1225system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20469440 # Cumulative packet size per connected master and slave (bytes) 1226system.membus.pkt_size::total 20469440 # Cumulative packet size per connected master and slave (bytes) | 1226system.membus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states 1227system.membus.trans_dist::ReadResp 214278 # Transaction distribution 1228system.membus.trans_dist::WritebackDirty 97298 # Transaction distribution 1229system.membus.trans_dist::CleanEvict 28222 # Transaction distribution 1230system.membus.trans_dist::UpgradeReq 13 # Transaction distribution 1231system.membus.trans_dist::ReadExReq 8340 # Transaction distribution 1232system.membus.trans_dist::ReadExResp 8340 # Transaction distribution 1233system.membus.trans_dist::ReadSharedReq 214279 # Transaction distribution 1234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570770 # Packet count per connected master and slave (bytes) 1235system.membus.pkt_count::total 570770 # Packet count per connected master and slave (bytes) 1236system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20474624 # Cumulative packet size per connected master and slave (bytes) 1237system.membus.pkt_size::total 20474624 # Cumulative packet size per connected master and slave (bytes) |
| 1227system.membus.snoops 0 # Total snoops (count) 1228system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1238system.membus.snoops 0 # Total snoops (count) 1239system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1229system.membus.snoop_fanout::samples 222586 # Request fanout histogram | 1240system.membus.snoop_fanout::samples 222632 # Request fanout histogram |
| 1230system.membus.snoop_fanout::mean 0 # Request fanout histogram 1231system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1232system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1241system.membus.snoop_fanout::mean 0 # Request fanout histogram 1242system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1243system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1233system.membus.snoop_fanout::0 222586 100.00% 100.00% # Request fanout histogram | 1244system.membus.snoop_fanout::0 222632 100.00% 100.00% # Request fanout histogram |
| 1234system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1235system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1236system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1237system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1245system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1246system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1247system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1248system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1238system.membus.snoop_fanout::total 222586 # Request fanout histogram 1239system.membus.reqLayer0.occupancy 837454269 # Layer occupancy (ticks) | 1249system.membus.snoop_fanout::total 222632 # Request fanout histogram 1250system.membus.reqLayer0.occupancy 835899979 # Layer occupancy (ticks) |
| 1240system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) | 1251system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) |
| 1241system.membus.respLayer1.occupancy 1175863136 # Layer occupancy (ticks) 1242system.membus.respLayer1.utilization 3.2 # Layer utilization (%) | 1252system.membus.respLayer1.occupancy 1175524166 # Layer occupancy (ticks) 1253system.membus.respLayer1.utilization 3.1 # Layer utilization (%) |
| 1243 1244---------- End Simulation Statistics ---------- | 1254 1255---------- End Simulation Statistics ---------- |