| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.033525 # Number of seconds simulated 4sim_ticks 33524756000 # Number of ticks simulated 5final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.033525 # Number of seconds simulated 4sim_ticks 33524756000 # Number of ticks simulated 5final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 145211 # Simulator instruction rate (inst/s) 8host_op_rate 185708 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 68655135 # Simulator tick rate (ticks/s) 10host_mem_usage 282260 # Number of bytes of host memory used 11host_seconds 488.31 # Real time elapsed on the host | 7host_inst_rate 160372 # Simulator instruction rate (inst/s) 8host_op_rate 205097 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 75822829 # Simulator tick rate (ticks/s) 10host_mem_usage 282256 # Number of bytes of host memory used 11host_seconds 442.15 # Real time elapsed on the host |
| 12sim_insts 70907652 # Number of instructions simulated 13sim_ops 90682607 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory --- 771 unchanged lines hidden (view full) --- 791system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216 # average overall miss latency 792system.cpu.dcache.overall_avg_miss_latency::total 14360.403216 # average overall miss latency 793system.cpu.dcache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked 794system.cpu.dcache.blocked_cycles::no_targets 2907482 # number of cycles access was blocked 795system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 796system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked 797system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked 798system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked | 12sim_insts 70907652 # Number of instructions simulated 13sim_ops 90682607 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory --- 771 unchanged lines hidden (view full) --- 791system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216 # average overall miss latency 792system.cpu.dcache.overall_avg_miss_latency::total 14360.403216 # average overall miss latency 793system.cpu.dcache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked 794system.cpu.dcache.blocked_cycles::no_targets 2907482 # number of cycles access was blocked 795system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 796system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked 797system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked 798system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked |
| 799system.cpu.dcache.fast_writes 0 # number of fast writes performed 800system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 801system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks 802system.cpu.dcache.writebacks::total 486293 # number of writebacks 803system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits 804system.cpu.dcache.ReadReq_mshr_hits::total 267392 # number of ReadReq MSHR hits 805system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868636 # number of WriteReq MSHR hits 806system.cpu.dcache.WriteReq_mshr_hits::total 868636 # number of WriteReq MSHR hits 807system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits 808system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 845system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency 846system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency 847system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency 848system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency 849system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency 850system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency 851system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency 852system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency | 799system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks 800system.cpu.dcache.writebacks::total 486293 # number of writebacks 801system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits 802system.cpu.dcache.ReadReq_mshr_hits::total 267392 # number of ReadReq MSHR hits 803system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868636 # number of WriteReq MSHR hits 804system.cpu.dcache.WriteReq_mshr_hits::total 868636 # number of WriteReq MSHR hits 805system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits 806system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 843system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency 844system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency 845system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency 846system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency 847system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency 848system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency 849system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency 850system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency |
| 853system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 854system.cpu.icache.tags.replacements 325000 # number of replacements 855system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use 856system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks. 857system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks. 858system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks. 859system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit. 860system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor 861system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 906system.cpu.icache.overall_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency 907system.cpu.icache.overall_avg_miss_latency::total 10536.290484 # average overall miss latency 908system.cpu.icache.blocked_cycles::no_mshrs 264177 # number of cycles access was blocked 909system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked 910system.cpu.icache.blocked::no_mshrs 16495 # number of cycles access was blocked 911system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 912system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # average number of cycles each access was blocked 913system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked | 851system.cpu.icache.tags.replacements 325000 # number of replacements 852system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use 853system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks. 854system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks. 855system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks. 856system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit. 857system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor 858system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 903system.cpu.icache.overall_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency 904system.cpu.icache.overall_avg_miss_latency::total 10536.290484 # average overall miss latency 905system.cpu.icache.blocked_cycles::no_mshrs 264177 # number of cycles access was blocked 906system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked 907system.cpu.icache.blocked::no_mshrs 16495 # number of cycles access was blocked 908system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 909system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # average number of cycles each access was blocked 910system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked |
| 914system.cpu.icache.fast_writes 0 # number of fast writes performed 915system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 916system.cpu.icache.writebacks::writebacks 325000 # number of writebacks 917system.cpu.icache.writebacks::total 325000 # number of writebacks 918system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9178 # number of ReadReq MSHR hits 919system.cpu.icache.ReadReq_mshr_hits::total 9178 # number of ReadReq MSHR hits 920system.cpu.icache.demand_mshr_hits::cpu.inst 9178 # number of demand (read+write) MSHR hits 921system.cpu.icache.demand_mshr_hits::total 9178 # number of demand (read+write) MSHR hits 922system.cpu.icache.overall_mshr_hits::cpu.inst 9178 # number of overall MSHR hits 923system.cpu.icache.overall_mshr_hits::total 9178 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 940system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for overall accesses 941system.cpu.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses 942system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037 # average ReadReq mshr miss latency 943system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037 # average ReadReq mshr miss latency 944system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency 945system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency 946system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency 947system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency | 911system.cpu.icache.writebacks::writebacks 325000 # number of writebacks 912system.cpu.icache.writebacks::total 325000 # number of writebacks 913system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9178 # number of ReadReq MSHR hits 914system.cpu.icache.ReadReq_mshr_hits::total 9178 # number of ReadReq MSHR hits 915system.cpu.icache.demand_mshr_hits::cpu.inst 9178 # number of demand (read+write) MSHR hits 916system.cpu.icache.demand_mshr_hits::total 9178 # number of demand (read+write) MSHR hits 917system.cpu.icache.overall_mshr_hits::cpu.inst 9178 # number of overall MSHR hits 918system.cpu.icache.overall_mshr_hits::total 9178 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 935system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for overall accesses 936system.cpu.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses 937system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037 # average ReadReq mshr miss latency 938system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037 # average ReadReq mshr miss latency 939system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency 940system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency 941system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency 942system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency |
| 948system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 949system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued 950system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified 951system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue 952system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 953system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 954system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing 955system.cpu.l2cache.tags.replacements 128177 # number of replacements 956system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use --- 108 unchanged lines hidden (view full) --- 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::total 85034.464643 # average overall miss latency 1067system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1068system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1069system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1070system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1071system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1072system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 943system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued 944system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified 945system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue 946system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 947system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 948system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing 949system.cpu.l2cache.tags.replacements 128177 # number of replacements 950system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use --- 108 unchanged lines hidden (view full) --- 1059system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency 1060system.cpu.l2cache.overall_avg_miss_latency::total 85034.464643 # average overall miss latency 1061system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1062system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1063system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1064system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1065system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1066system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1073system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1074system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1075system.cpu.l2cache.unused_prefetches 424 # number of HardPF blocks evicted w/o reference 1076system.cpu.l2cache.writebacks::writebacks 97140 # number of writebacks 1077system.cpu.l2cache.writebacks::total 97140 # number of writebacks 1078system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3182 # number of ReadExReq MSHR hits 1079system.cpu.l2cache.ReadExReq_mshr_hits::total 3182 # number of ReadExReq MSHR hits 1080system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 28 # number of ReadCleanReq MSHR hits 1081system.cpu.l2cache.ReadCleanReq_mshr_hits::total 28 # number of ReadCleanReq MSHR hits 1082system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 100 # number of ReadSharedReq MSHR hits --- 67 unchanged lines hidden (view full) --- 1150system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280 # average ReadSharedReq mshr miss latency 1151system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency 1152system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency 1153system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297 # average overall mshr miss latency 1154system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency 1155system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency 1156system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency 1157system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency | 1067system.cpu.l2cache.unused_prefetches 424 # number of HardPF blocks evicted w/o reference 1068system.cpu.l2cache.writebacks::writebacks 97140 # number of writebacks 1069system.cpu.l2cache.writebacks::total 97140 # number of writebacks 1070system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3182 # number of ReadExReq MSHR hits 1071system.cpu.l2cache.ReadExReq_mshr_hits::total 3182 # number of ReadExReq MSHR hits 1072system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 28 # number of ReadCleanReq MSHR hits 1073system.cpu.l2cache.ReadCleanReq_mshr_hits::total 28 # number of ReadCleanReq MSHR hits 1074system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 100 # number of ReadSharedReq MSHR hits --- 67 unchanged lines hidden (view full) --- 1142system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280 # average ReadSharedReq mshr miss latency 1143system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency 1144system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency 1145system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297 # average overall mshr miss latency 1146system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency 1147system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency 1148system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency |
| 1158system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1159system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter. 1160system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1161system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1162system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. 1163system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1164system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1165system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution --- 61 unchanged lines hidden --- | 1150system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter. 1151system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1152system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1153system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. 1154system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1155system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1156system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution --- 61 unchanged lines hidden --- |