| stats.txt (11214:966091379ded) | stats.txt (11336:b318499f676c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.033788 # Number of seconds simulated 4sim_ticks 33787619000 # Number of ticks simulated 5final_tick 33787619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.033784 # Number of seconds simulated 4sim_ticks 33784139000 # Number of ticks simulated 5final_tick 33784139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 117892 # Simulator instruction rate (inst/s) 8host_op_rate 150770 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56175899 # Simulator tick rate (ticks/s) 10host_mem_usage 326928 # Number of bytes of host memory used 11host_seconds 601.46 # Real time elapsed on the host | 7host_inst_rate 118438 # Simulator instruction rate (inst/s) 8host_op_rate 151468 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56430150 # Simulator tick rate (ticks/s) 10host_mem_usage 329476 # Number of bytes of host memory used 11host_seconds 598.69 # Real time elapsed on the host |
| 12sim_insts 70907630 # Number of instructions simulated 13sim_ops 90682585 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 70907630 # Number of instructions simulated 13sim_ops 90682585 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 736896 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2854400 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 6176576 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9767872 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 736896 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 736896 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6229632 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6229632 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 11514 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 44600 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 96509 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 152623 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 97338 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 97338 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 21809646 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 84480650 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 182805897 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 289096192 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 21809646 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 21809646 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 184376176 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 184376176 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 184376176 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 21809646 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 84480650 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 182805897 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 473472369 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 152624 # Number of read requests accepted 44system.physmem.writeReqs 97338 # Number of write requests accepted 45system.physmem.readBursts 152624 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 97338 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 9758080 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue 49system.physmem.bytesWritten 6227712 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 9767936 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 6229632 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 27837 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 9027 # Per bank write bursts 56system.physmem.perBankRdBursts::1 9355 # Per bank write bursts 57system.physmem.perBankRdBursts::2 9548 # Per bank write bursts 58system.physmem.perBankRdBursts::3 12185 # Per bank write bursts 59system.physmem.perBankRdBursts::4 10599 # Per bank write bursts 60system.physmem.perBankRdBursts::5 10432 # Per bank write bursts 61system.physmem.perBankRdBursts::6 9787 # Per bank write bursts 62system.physmem.perBankRdBursts::7 9285 # Per bank write bursts 63system.physmem.perBankRdBursts::8 9499 # Per bank write bursts 64system.physmem.perBankRdBursts::9 9569 # Per bank write bursts 65system.physmem.perBankRdBursts::10 9134 # Per bank write bursts 66system.physmem.perBankRdBursts::11 8776 # Per bank write bursts 67system.physmem.perBankRdBursts::12 8706 # Per bank write bursts 68system.physmem.perBankRdBursts::13 8772 # Per bank write bursts 69system.physmem.perBankRdBursts::14 8686 # Per bank write bursts 70system.physmem.perBankRdBursts::15 9110 # Per bank write bursts 71system.physmem.perBankWrBursts::0 5979 # Per bank write bursts 72system.physmem.perBankWrBursts::1 6226 # Per bank write bursts 73system.physmem.perBankWrBursts::2 6146 # Per bank write bursts 74system.physmem.perBankWrBursts::3 6158 # Per bank write bursts 75system.physmem.perBankWrBursts::4 6081 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6325 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6021 # Per bank write bursts 78system.physmem.perBankWrBursts::7 5966 # Per bank write bursts 79system.physmem.perBankWrBursts::8 5954 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6102 # Per bank write bursts 81system.physmem.perBankWrBursts::10 6248 # Per bank write bursts 82system.physmem.perBankWrBursts::11 5872 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6030 # Per bank write bursts 84system.physmem.perBankWrBursts::13 6061 # Per bank write bursts 85system.physmem.perBankWrBursts::14 6151 # Per bank write bursts 86system.physmem.perBankWrBursts::15 5988 # Per bank write bursts | 16system.physmem.bytes_read::cpu.inst 781248 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2836288 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 6167232 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9784768 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 781248 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 781248 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6226432 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6226432 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 12207 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 44317 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 96363 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 152887 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 97288 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 97288 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 23124698 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 83953242 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 182548148 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 289626088 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 23124698 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 23124698 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 184300449 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 184300449 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 184300449 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 23124698 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 83953242 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 182548148 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 473926537 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 152888 # Number of read requests accepted 44system.physmem.writeReqs 97288 # Number of write requests accepted 45system.physmem.readBursts 152888 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 97288 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 9777152 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue 49system.physmem.bytesWritten 6224960 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 9784832 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 6226432 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 9124 # Per bank write bursts 56system.physmem.perBankRdBursts::1 9348 # Per bank write bursts 57system.physmem.perBankRdBursts::2 9757 # Per bank write bursts 58system.physmem.perBankRdBursts::3 12566 # Per bank write bursts 59system.physmem.perBankRdBursts::4 10929 # Per bank write bursts 60system.physmem.perBankRdBursts::5 10090 # Per bank write bursts 61system.physmem.perBankRdBursts::6 9786 # Per bank write bursts 62system.physmem.perBankRdBursts::7 8974 # Per bank write bursts 63system.physmem.perBankRdBursts::8 9178 # Per bank write bursts 64system.physmem.perBankRdBursts::9 9832 # Per bank write bursts 65system.physmem.perBankRdBursts::10 9165 # Per bank write bursts 66system.physmem.perBankRdBursts::11 8819 # Per bank write bursts 67system.physmem.perBankRdBursts::12 8693 # Per bank write bursts 68system.physmem.perBankRdBursts::13 8672 # Per bank write bursts 69system.physmem.perBankRdBursts::14 8813 # Per bank write bursts 70system.physmem.perBankRdBursts::15 9022 # Per bank write bursts 71system.physmem.perBankWrBursts::0 5950 # Per bank write bursts 72system.physmem.perBankWrBursts::1 6192 # Per bank write bursts 73system.physmem.perBankWrBursts::2 6162 # Per bank write bursts 74system.physmem.perBankWrBursts::3 6171 # Per bank write bursts 75system.physmem.perBankWrBursts::4 6089 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6262 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6013 # Per bank write bursts 78system.physmem.perBankWrBursts::7 5971 # Per bank write bursts 79system.physmem.perBankWrBursts::8 5978 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6080 # Per bank write bursts 81system.physmem.perBankWrBursts::10 6215 # Per bank write bursts 82system.physmem.perBankWrBursts::11 5915 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6050 # Per bank write bursts 84system.physmem.perBankWrBursts::13 6057 # Per bank write bursts 85system.physmem.perBankWrBursts::14 6142 # Per bank write bursts 86system.physmem.perBankWrBursts::15 6018 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 89system.physmem.totGap 33787609500 # Total gap between requests | 89system.physmem.totGap 33784127500 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 152624 # Read request sizes (log2) | 96system.physmem.readPktSize::6 152888 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 97338 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 49823 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 54272 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 13781 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 10225 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6146 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 5327 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 4741 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4387 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3645 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 35 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 97288 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 50168 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 54297 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 13893 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 10288 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6063 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 5243 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 4693 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4371 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3656 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see |
| 117system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see --- 18 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 117system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see --- 18 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 1238 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1280 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1763 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 2239 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2913 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 3782 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5380 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5915 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 6491 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 6847 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 7521 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8155 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8929 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 9277 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 7693 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6643 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6205 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 192 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see | 151system.physmem.wrQLenPdf::15 1235 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1747 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 2248 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2973 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 3847 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 4816 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5412 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5903 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 6387 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 6879 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 7477 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8147 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8715 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 9142 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 7742 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6712 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 84 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 39 # What write queue length does an incoming req see |
| 172system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see | 172system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see |
| 173system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see | 173system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see |
| 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see --- 5 unchanged lines hidden (view full) --- 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see --- 5 unchanged lines hidden (view full) --- 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 200system.physmem.bytesPerActivate::samples 95484 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 167.396422 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 105.401782 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 235.895158 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 59753 62.58% 62.58% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 22097 23.14% 85.72% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4150 4.35% 90.07% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1579 1.65% 91.72% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 956 1.00% 92.72% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 842 0.88% 93.60% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 589 0.62% 94.22% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 882 0.92% 95.14% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 4636 4.86% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 95484 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5850 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 26.058462 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 198.495488 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-511 5849 99.98% 99.98% # Reads before turning the bus around for writes | 200system.physmem.bytesPerActivate::samples 95539 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 167.474225 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 105.587098 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 235.887781 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 59486 62.26% 62.26% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 22475 23.52% 85.79% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4141 4.33% 90.12% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1560 1.63% 91.76% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 915 0.96% 92.71% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 855 0.89% 93.61% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 603 0.63% 94.24% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 793 0.83% 95.07% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 4711 4.93% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 95539 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5851 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 26.107332 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 198.473486 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-511 5850 99.98% 99.98% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes | 218system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 219system.physmem.rdPerTurnAround::total 5850 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 5850 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.633846 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.583273 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 1.382653 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16 4554 77.85% 77.85% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::17 25 0.43% 78.27% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 781 13.35% 91.62% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::19 204 3.49% 95.11% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20 105 1.79% 96.91% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::21 84 1.44% 98.34% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::22 47 0.80% 99.15% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::23 32 0.55% 99.69% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::24 8 0.14% 99.83% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::25 5 0.09% 99.91% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::26 3 0.05% 99.97% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 5850 # Writes before turning the bus around for reads 238system.physmem.totQLat 6712073801 # Total ticks spent queuing 239system.physmem.totMemAccLat 9570886301 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 762350000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 44022.26 # Average queueing delay per DRAM burst | 219system.physmem.rdPerTurnAround::total 5851 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 5851 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.623654 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.576655 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 1.320793 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16 4551 77.78% 77.78% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::17 30 0.51% 78.29% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 752 12.85% 91.15% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::19 225 3.85% 94.99% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20 138 2.36% 97.35% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::21 80 1.37% 98.72% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::22 45 0.77% 99.49% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::23 22 0.38% 99.86% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::24 8 0.14% 100.00% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::total 5851 # Writes before turning the bus around for reads 234system.physmem.totQLat 6694958033 # Total ticks spent queuing 235system.physmem.totMemAccLat 9559358033 # Total ticks spent from burst creation until serviced by the DRAM 236system.physmem.totBusLat 763840000 # Total ticks spent in databus transfers 237system.physmem.avgQLat 43824.35 # Average queueing delay per DRAM burst |
| 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 238system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 243system.physmem.avgMemAccLat 62772.26 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 288.81 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 184.32 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 289.10 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 184.38 # Average system write bandwidth in MiByte/s | 239system.physmem.avgMemAccLat 62574.35 # Average memory access latency per DRAM burst 240system.physmem.avgRdBW 289.40 # Average DRAM read bandwidth in MiByte/s 241system.physmem.avgWrBW 184.26 # Average achieved write bandwidth in MiByte/s 242system.physmem.avgRdBWSys 289.63 # Average system read bandwidth in MiByte/s 243system.physmem.avgWrBWSys 184.30 # Average system write bandwidth in MiByte/s |
| 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 3.70 # Data bus utilization in percentage 250system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes | 244system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 245system.physmem.busUtil 3.70 # Data bus utilization in percentage 246system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads 247system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes |
| 252system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing 254system.physmem.readRowHits 121004 # Number of row buffer hits during reads 255system.physmem.writeRowHits 33280 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 79.36 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 34.19 # Row buffer hit rate for writes 258system.physmem.avgGap 135170.98 # Average gap between requests 259system.physmem.pageHitRate 61.76 # Row buffer hit rate, read and write combined 260system.physmem_0.actEnergy 375641280 # Energy for activate commands per rank (pJ) 261system.physmem_0.preEnergy 204963000 # Energy for precharge commands per rank (pJ) 262system.physmem_0.readEnergy 625404000 # Energy for read commands per rank (pJ) 263system.physmem_0.writeEnergy 316826640 # Energy for write commands per rank (pJ) 264system.physmem_0.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) 265system.physmem_0.actBackEnergy 15342350850 # Energy for active background per rank (pJ) 266system.physmem_0.preBackEnergy 6812703000 # Energy for precharge background per rank (pJ) 267system.physmem_0.totalEnergy 25884530610 # Total energy per rank (pJ) 268system.physmem_0.averagePower 766.158096 # Core power per rank (mW) 269system.physmem_0.memoryStateTime::IDLE 11227638574 # Time in different power states 270system.physmem_0.memoryStateTime::REF 1128140000 # Time in different power states | 248system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing 249system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing 250system.physmem.readRowHits 121417 # Number of row buffer hits during reads 251system.physmem.writeRowHits 33065 # Number of row buffer hits during writes 252system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads 253system.physmem.writeRowHitRate 33.99 # Row buffer hit rate for writes 254system.physmem.avgGap 135041.44 # Average gap between requests 255system.physmem.pageHitRate 61.78 # Row buffer hit rate, read and write combined 256system.physmem_0.actEnergy 374855040 # Energy for activate commands per rank (pJ) 257system.physmem_0.preEnergy 204534000 # Energy for precharge commands per rank (pJ) 258system.physmem_0.readEnergy 627829800 # Energy for read commands per rank (pJ) 259system.physmem_0.writeEnergy 316068480 # Energy for write commands per rank (pJ) 260system.physmem_0.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) 261system.physmem_0.actBackEnergy 15176758725 # Energy for active background per rank (pJ) 262system.physmem_0.preBackEnergy 6953261250 # Energy for precharge background per rank (pJ) 263system.physmem_0.totalEnergy 25859440575 # Total energy per rank (pJ) 264system.physmem_0.averagePower 765.592889 # Core power per rank (mW) 265system.physmem_0.memoryStateTime::IDLE 11461051997 # Time in different power states 266system.physmem_0.memoryStateTime::REF 1127880000 # Time in different power states |
| 271system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 267system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 272system.physmem_0.memoryStateTime::ACT 21429077176 # Time in different power states | 268system.physmem_0.memoryStateTime::ACT 21188094253 # Time in different power states |
| 273system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 269system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 274system.physmem_1.actEnergy 346043880 # Energy for activate commands per rank (pJ) 275system.physmem_1.preEnergy 188813625 # Energy for precharge commands per rank (pJ) 276system.physmem_1.readEnergy 563401800 # Energy for read commands per rank (pJ) 277system.physmem_1.writeEnergy 313625520 # Energy for write commands per rank (pJ) 278system.physmem_1.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) 279system.physmem_1.actBackEnergy 13705423425 # Energy for active background per rank (pJ) 280system.physmem_1.preBackEnergy 8248614750 # Energy for precharge background per rank (pJ) 281system.physmem_1.totalEnergy 25572564840 # Total energy per rank (pJ) 282system.physmem_1.averagePower 756.923807 # Core power per rank (mW) 283system.physmem_1.memoryStateTime::IDLE 13625050098 # Time in different power states 284system.physmem_1.memoryStateTime::REF 1128140000 # Time in different power states | 270system.physmem_1.actEnergy 346777200 # Energy for activate commands per rank (pJ) 271system.physmem_1.preEnergy 189213750 # Energy for precharge commands per rank (pJ) 272system.physmem_1.readEnergy 562754400 # Energy for read commands per rank (pJ) 273system.physmem_1.writeEnergy 313787520 # Energy for write commands per rank (pJ) 274system.physmem_1.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) 275system.physmem_1.actBackEnergy 13818315060 # Energy for active background per rank (pJ) 276system.physmem_1.preBackEnergy 8144878500 # Energy for precharge background per rank (pJ) 277system.physmem_1.totalEnergy 25581859710 # Total energy per rank (pJ) 278system.physmem_1.averagePower 757.374848 # Core power per rank (mW) 279system.physmem_1.memoryStateTime::IDLE 13453093141 # Time in different power states 280system.physmem_1.memoryStateTime::REF 1127880000 # Time in different power states |
| 285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 281system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 286system.physmem_1.memoryStateTime::ACT 19031683152 # Time in different power states | 282system.physmem_1.memoryStateTime::ACT 19196289859 # Time in different power states |
| 287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 283system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 288system.cpu.branchPred.lookups 17216173 # Number of BP lookups 289system.cpu.branchPred.condPredicted 11524251 # Number of conditional branches predicted 290system.cpu.branchPred.condIncorrect 650211 # Number of conditional branches incorrect 291system.cpu.branchPred.BTBLookups 9349330 # Number of BTB lookups 292system.cpu.branchPred.BTBHits 7678783 # Number of BTB hits | 284system.cpu.branchPred.lookups 17214384 # Number of BP lookups 285system.cpu.branchPred.condPredicted 11522342 # Number of conditional branches predicted 286system.cpu.branchPred.condIncorrect 650449 # Number of conditional branches incorrect 287system.cpu.branchPred.BTBLookups 9351216 # Number of BTB lookups 288system.cpu.branchPred.BTBHits 7679376 # Number of BTB hits |
| 293system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 289system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 294system.cpu.branchPred.BTBHitPct 82.131907 # BTB Hit Percentage 295system.cpu.branchPred.usedRAS 1872954 # Number of times the RAS was used to get a target. 296system.cpu.branchPred.RASInCorrect 101563 # Number of incorrect RAS predictions. | 290system.cpu.branchPred.BTBHitPct 82.121683 # BTB Hit Percentage 291system.cpu.branchPred.usedRAS 1872997 # Number of times the RAS was used to get a target. 292system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. |
| 297system.cpu_clk_domain.clock 500 # Clock period in ticks 298system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 407system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu.itb.read_accesses 0 # DTB read accesses 409system.cpu.itb.write_accesses 0 # DTB write accesses 410system.cpu.itb.inst_accesses 0 # ITB inst accesses 411system.cpu.itb.hits 0 # DTB hits 412system.cpu.itb.misses 0 # DTB misses 413system.cpu.itb.accesses 0 # DTB accesses 414system.cpu.workload.num_syscalls 1946 # Number of system calls | 293system.cpu_clk_domain.clock 500 # Clock period in ticks 294system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 403system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 404system.cpu.itb.read_accesses 0 # DTB read accesses 405system.cpu.itb.write_accesses 0 # DTB write accesses 406system.cpu.itb.inst_accesses 0 # ITB inst accesses 407system.cpu.itb.hits 0 # DTB hits 408system.cpu.itb.misses 0 # DTB misses 409system.cpu.itb.accesses 0 # DTB accesses 410system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 415system.cpu.numCycles 67575239 # number of cpu cycles simulated | 411system.cpu.numCycles 67568279 # number of cpu cycles simulated |
| 416system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 417system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 412system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 413system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 418system.cpu.fetch.icacheStallCycles 5134859 # Number of cycles fetch is stalled on an Icache miss 419system.cpu.fetch.Insts 88248834 # Number of instructions fetch has processed 420system.cpu.fetch.Branches 17216173 # Number of branches that fetch encountered 421system.cpu.fetch.predictedBranches 9551737 # Number of branches that fetch has predicted taken 422system.cpu.fetch.Cycles 60707500 # Number of cycles fetch has run and was not squashing or blocked 423system.cpu.fetch.SquashCycles 1326839 # Number of cycles fetch has spent squashing 424system.cpu.fetch.MiscStallCycles 5350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 414system.cpu.fetch.icacheStallCycles 5160872 # Number of cycles fetch is stalled on an Icache miss 415system.cpu.fetch.Insts 88245051 # Number of instructions fetch has processed 416system.cpu.fetch.Branches 17214384 # Number of branches that fetch encountered 417system.cpu.fetch.predictedBranches 9552373 # Number of branches that fetch has predicted taken 418system.cpu.fetch.Cycles 60651743 # Number of cycles fetch has run and was not squashing or blocked 419system.cpu.fetch.SquashCycles 1327287 # Number of cycles fetch has spent squashing 420system.cpu.fetch.MiscStallCycles 6028 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 425system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps | 421system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps |
| 426system.cpu.fetch.IcacheWaitRetryStallCycles 12635 # Number of stall cycles due to full MSHR 427system.cpu.fetch.CacheLines 22778595 # Number of cache lines fetched 428system.cpu.fetch.IcacheSquashes 70008 # Number of outstanding Icache misses that were squashed 429system.cpu.fetch.rateDist::samples 66523790 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::mean 1.678669 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::stdev 1.300955 # Number of instructions fetched each cycle (Total) | 422system.cpu.fetch.IcacheWaitRetryStallCycles 12780 # Number of stall cycles due to full MSHR 423system.cpu.fetch.CacheLines 22780660 # Number of cache lines fetched 424system.cpu.fetch.IcacheSquashes 69845 # Number of outstanding Icache misses that were squashed 425system.cpu.fetch.rateDist::samples 66495093 # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::mean 1.679326 # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::stdev 1.300807 # Number of instructions fetched each cycle (Total) |
| 432system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 428system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 433system.cpu.fetch.rateDist::0 20715769 31.14% 31.14% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::1 8270385 12.43% 43.57% # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::2 9211836 13.85% 57.42% # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::3 28325800 42.58% 100.00% # Number of instructions fetched each cycle (Total) | 429system.cpu.fetch.rateDist::0 20690371 31.12% 31.12% # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::1 8267529 12.43% 43.55% # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::2 9212157 13.85% 57.40% # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.rateDist::3 28325036 42.60% 100.00% # Number of instructions fetched each cycle (Total) |
| 437system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 433system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 440system.cpu.fetch.rateDist::total 66523790 # Number of instructions fetched each cycle (Total) | 436system.cpu.fetch.rateDist::total 66495093 # Number of instructions fetched each cycle (Total) |
| 441system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle | 437system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle |
| 442system.cpu.fetch.rate 1.305934 # Number of inst fetches per cycle 443system.cpu.decode.IdleCycles 8696241 # Number of cycles decode is idle 444system.cpu.decode.BlockedCycles 20116868 # Number of cycles decode is blocked 445system.cpu.decode.RunCycles 31576119 # Number of cycles decode is running 446system.cpu.decode.UnblockCycles 5641245 # Number of cycles decode is unblocking 447system.cpu.decode.SquashCycles 493317 # Number of cycles decode is squashing 448system.cpu.decode.BranchResolved 3182236 # Number of times decode resolved a branch 449system.cpu.decode.BranchMispred 172097 # Number of times decode detected a branch misprediction 450system.cpu.decode.DecodedInsts 101426011 # Number of instructions handled by decode 451system.cpu.decode.SquashedInsts 3049995 # Number of squashed instructions handled by decode 452system.cpu.rename.SquashCycles 493317 # Number of cycles rename is squashing 453system.cpu.rename.IdleCycles 13462916 # Number of cycles rename is idle 454system.cpu.rename.BlockCycles 5983097 # Number of cycles rename is blocking 455system.cpu.rename.serializeStallCycles 839028 # count of cycles rename stalled for serializing inst 456system.cpu.rename.RunCycles 32232549 # Number of cycles rename is running 457system.cpu.rename.UnblockCycles 13512883 # Number of cycles rename is unblocking 458system.cpu.rename.RenamedInsts 99220100 # Number of instructions processed by rename 459system.cpu.rename.SquashedInsts 979828 # Number of squashed instructions processed by rename 460system.cpu.rename.ROBFullEvents 3816376 # Number of times rename has blocked due to ROB full 461system.cpu.rename.IQFullEvents 66808 # Number of times rename has blocked due to IQ full 462system.cpu.rename.LQFullEvents 4343458 # Number of times rename has blocked due to LQ full 463system.cpu.rename.SQFullEvents 5148151 # Number of times rename has blocked due to SQ full 464system.cpu.rename.RenamedOperands 103925700 # Number of destination operands rename has renamed 465system.cpu.rename.RenameLookups 457807646 # Number of register rename lookups that rename has made 466system.cpu.rename.int_rename_lookups 115438955 # Number of integer rename lookups 467system.cpu.rename.fp_rename_lookups 552 # Number of floating rename lookups | 438system.cpu.fetch.rate 1.306013 # Number of inst fetches per cycle 439system.cpu.decode.IdleCycles 8713541 # Number of cycles decode is idle 440system.cpu.decode.BlockedCycles 20066003 # Number of cycles decode is blocked 441system.cpu.decode.RunCycles 31587262 # Number of cycles decode is running 442system.cpu.decode.UnblockCycles 5634718 # Number of cycles decode is unblocking 443system.cpu.decode.SquashCycles 493569 # Number of cycles decode is squashing 444system.cpu.decode.BranchResolved 3182821 # Number of times decode resolved a branch 445system.cpu.decode.BranchMispred 172049 # Number of times decode detected a branch misprediction 446system.cpu.decode.DecodedInsts 101434518 # Number of instructions handled by decode 447system.cpu.decode.SquashedInsts 3052676 # Number of squashed instructions handled by decode 448system.cpu.rename.SquashCycles 493569 # Number of cycles rename is squashing 449system.cpu.rename.IdleCycles 13478922 # Number of cycles rename is idle 450system.cpu.rename.BlockCycles 5884192 # Number of cycles rename is blocking 451system.cpu.rename.serializeStallCycles 838725 # count of cycles rename stalled for serializing inst 452system.cpu.rename.RunCycles 32239032 # Number of cycles rename is running 453system.cpu.rename.UnblockCycles 13560653 # Number of cycles rename is unblocking 454system.cpu.rename.RenamedInsts 99228097 # Number of instructions processed by rename 455system.cpu.rename.SquashedInsts 981180 # Number of squashed instructions processed by rename 456system.cpu.rename.ROBFullEvents 3845119 # Number of times rename has blocked due to ROB full 457system.cpu.rename.IQFullEvents 69162 # Number of times rename has blocked due to IQ full 458system.cpu.rename.LQFullEvents 4384146 # Number of times rename has blocked due to LQ full 459system.cpu.rename.SQFullEvents 5165586 # Number of times rename has blocked due to SQ full 460system.cpu.rename.RenamedOperands 103939784 # Number of destination operands rename has renamed 461system.cpu.rename.RenameLookups 457840373 # Number of register rename lookups that rename has made 462system.cpu.rename.int_rename_lookups 115445962 # Number of integer rename lookups 463system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups |
| 468system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed | 464system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed |
| 469system.cpu.rename.UndoneMaps 10296474 # Number of HB maps that are undone due to squashing 470system.cpu.rename.serializingInsts 18669 # count of serializing insts renamed | 465system.cpu.rename.UndoneMaps 10310558 # Number of HB maps that are undone due to squashing 466system.cpu.rename.serializingInsts 18670 # count of serializing insts renamed |
| 471system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed | 467system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed |
| 472system.cpu.rename.skidInsts 12740509 # count of insts added to the skid buffer 473system.cpu.memDep0.insertedLoads 24326602 # Number of loads inserted to the mem dependence unit. 474system.cpu.memDep0.insertedStores 22004719 # Number of stores inserted to the mem dependence unit. 475system.cpu.memDep0.conflictingLoads 1418947 # Number of conflicting loads. 476system.cpu.memDep0.conflictingStores 2350394 # Number of conflicting stores. 477system.cpu.iq.iqInstsAdded 98183255 # Number of instructions added to the IQ (excludes non-spec) 478system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ 479system.cpu.iq.iqInstsIssued 94912265 # Number of instructions issued 480system.cpu.iq.iqSquashedInstsIssued 694103 # Number of squashed instructions issued 481system.cpu.iq.iqSquashedInstsExamined 7535192 # Number of squashed instructions iterated over during squash; mainly for profiling 482system.cpu.iq.iqSquashedOperandsExamined 20267739 # Number of squashed operands that are examined and possibly removed from graph 483system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed 484system.cpu.iq.issued_per_cycle::samples 66523790 # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::mean 1.426742 # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::stdev 1.152135 # Number of insts issued each cycle | 468system.cpu.rename.skidInsts 12730367 # count of insts added to the skid buffer 469system.cpu.memDep0.insertedLoads 24327975 # Number of loads inserted to the mem dependence unit. 470system.cpu.memDep0.insertedStores 22005134 # Number of stores inserted to the mem dependence unit. 471system.cpu.memDep0.conflictingLoads 1415958 # Number of conflicting loads. 472system.cpu.memDep0.conflictingStores 2369050 # Number of conflicting stores. 473system.cpu.iq.iqInstsAdded 98190630 # Number of instructions added to the IQ (excludes non-spec) 474system.cpu.iq.iqNonSpecInstsAdded 34517 # Number of non-speculative instructions added to the IQ 475system.cpu.iq.iqInstsIssued 94916965 # Number of instructions issued 476system.cpu.iq.iqSquashedInstsIssued 695759 # Number of squashed instructions issued 477system.cpu.iq.iqSquashedInstsExamined 7542562 # Number of squashed instructions iterated over during squash; mainly for profiling 478system.cpu.iq.iqSquashedOperandsExamined 20296667 # Number of squashed operands that are examined and possibly removed from graph 479system.cpu.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed 480system.cpu.iq.issued_per_cycle::samples 66495093 # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::mean 1.427428 # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::stdev 1.151996 # Number of insts issued each cycle |
| 487system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 483system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 488system.cpu.iq.issued_per_cycle::0 18209770 27.37% 27.37% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::1 17473699 26.27% 53.64% # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::2 17129113 25.75% 79.39% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::3 11665460 17.54% 96.92% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::4 2044780 3.07% 100.00% # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::5 968 0.00% 100.00% # Number of insts issued each cycle | 484system.cpu.iq.issued_per_cycle::0 18174968 27.33% 27.33% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::1 17486428 26.30% 53.63% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::2 17117325 25.74% 79.37% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::3 11670567 17.55% 96.92% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::4 2044839 3.08% 100.00% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::5 966 0.00% 100.00% # Number of insts issued each cycle |
| 494system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 490system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 500system.cpu.iq.issued_per_cycle::total 66523790 # Number of insts issued each cycle | 496system.cpu.iq.issued_per_cycle::total 66495093 # Number of insts issued each cycle |
| 501system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 497system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 502system.cpu.iq.fu_full::IntAlu 6707680 22.40% 22.40% # attempts to use FU when none available 503system.cpu.iq.fu_full::IntMult 41 0.00% 22.40% # attempts to use FU when none available 504system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available 505system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available 506system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available 507system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available 508system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available 509system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available 510system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available 531system.cpu.iq.fu_full::MemRead 11186120 37.35% 59.75% # attempts to use FU when none available 532system.cpu.iq.fu_full::MemWrite 12052780 40.25% 100.00% # attempts to use FU when none available | 498system.cpu.iq.fu_full::IntAlu 6711532 22.43% 22.43% # attempts to use FU when none available 499system.cpu.iq.fu_full::IntMult 41 0.00% 22.43% # attempts to use FU when none available 500system.cpu.iq.fu_full::IntDiv 0 0.00% 22.43% # attempts to use FU when none available 501system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.43% # attempts to use FU when none available 502system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.43% # attempts to use FU when none available 503system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.43% # attempts to use FU when none available 504system.cpu.iq.fu_full::FloatMult 0 0.00% 22.43% # attempts to use FU when none available 505system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.43% # attempts to use FU when none available 506system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.43% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.43% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.43% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.43% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.43% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.43% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.43% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdMult 0 0.00% 22.43% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.43% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdShift 0 0.00% 22.43% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.43% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.43% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.43% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.43% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.43% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.43% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.43% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.43% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.43% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.43% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.43% # attempts to use FU when none available 527system.cpu.iq.fu_full::MemRead 11180045 37.36% 59.79% # attempts to use FU when none available 528system.cpu.iq.fu_full::MemWrite 12034310 40.21% 100.00% # attempts to use FU when none available |
| 533system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 534system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 535system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 529system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 530system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 531system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 536system.cpu.iq.FU_type_0::IntAlu 49503200 52.16% 52.16% # Type of FU issued 537system.cpu.iq.FU_type_0::IntMult 89866 0.09% 52.25% # Type of FU issued | 532system.cpu.iq.FU_type_0::IntAlu 49505832 52.16% 52.16% # Type of FU issued 533system.cpu.iq.FU_type_0::IntMult 89861 0.09% 52.25% # Type of FU issued |
| 538system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued 541system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued 542system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued 543system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued 544system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued --- 4 unchanged lines hidden (view full) --- 550system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued | 534system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued 535system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued 536system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued 537system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued 538system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued --- 4 unchanged lines hidden (view full) --- 546system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued |
| 558system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 52.25% # Type of FU issued | 554system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.25% # Type of FU issued |
| 559system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued | 555system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued |
| 561system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 52.25% # Type of FU issued | 557system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.25% # Type of FU issued |
| 562system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued | 558system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued |
| 565system.cpu.iq.FU_type_0::MemRead 24070106 25.36% 77.61% # Type of FU issued 566system.cpu.iq.FU_type_0::MemWrite 21249051 22.39% 100.00% # Type of FU issued | 561system.cpu.iq.FU_type_0::MemRead 24073706 25.36% 77.61% # Type of FU issued 562system.cpu.iq.FU_type_0::MemWrite 21247526 22.39% 100.00% # Type of FU issued |
| 567system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 568system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 563system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 564system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 569system.cpu.iq.FU_type_0::total 94912265 # Type of FU issued 570system.cpu.iq.rate 1.404542 # Inst issue rate 571system.cpu.iq.fu_busy_cnt 29946621 # FU busy when requested 572system.cpu.iq.fu_busy_rate 0.315519 # FU busy rate (busy events/executed inst) 573system.cpu.iq.int_inst_queue_reads 286988829 # Number of integer instruction queue reads 574system.cpu.iq.int_inst_queue_writes 105764420 # Number of integer instruction queue writes 575system.cpu.iq.int_inst_queue_wakeup_accesses 93479370 # Number of integer instruction queue wakeup accesses 576system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads 577system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes 578system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses 579system.cpu.iq.int_alu_accesses 124858764 # Number of integer alu accesses 580system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses 581system.cpu.iew.lsq.thread0.forwLoads 1365617 # Number of loads that had data forwarded from stores | 565system.cpu.iq.FU_type_0::total 94916965 # Type of FU issued 566system.cpu.iq.rate 1.404756 # Inst issue rate 567system.cpu.iq.fu_busy_cnt 29925928 # FU busy when requested 568system.cpu.iq.fu_busy_rate 0.315285 # FU busy rate (busy events/executed inst) 569system.cpu.iq.int_inst_queue_reads 286950501 # Number of integer instruction queue reads 570system.cpu.iq.int_inst_queue_writes 105779157 # Number of integer instruction queue writes 571system.cpu.iq.int_inst_queue_wakeup_accesses 93480434 # Number of integer instruction queue wakeup accesses 572system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads 573system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes 574system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses 575system.cpu.iq.int_alu_accesses 124842774 # Number of integer alu accesses 576system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses 577system.cpu.iew.lsq.thread0.forwLoads 1366701 # Number of loads that had data forwarded from stores |
| 582system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 578system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 583system.cpu.iew.lsq.thread0.squashedLoads 1460340 # Number of loads squashed 584system.cpu.iew.lsq.thread0.ignoredResponses 2088 # Number of memory responses ignored because the instruction is squashed 585system.cpu.iew.lsq.thread0.memOrderViolation 11950 # Number of memory ordering violations 586system.cpu.iew.lsq.thread0.squashedStores 1448981 # Number of stores squashed | 579system.cpu.iew.lsq.thread0.squashedLoads 1461713 # Number of loads squashed 580system.cpu.iew.lsq.thread0.ignoredResponses 2105 # Number of memory responses ignored because the instruction is squashed 581system.cpu.iew.lsq.thread0.memOrderViolation 11942 # Number of memory ordering violations 582system.cpu.iew.lsq.thread0.squashedStores 1449396 # Number of stores squashed |
| 587system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 588system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 583system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 584system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 589system.cpu.iew.lsq.thread0.rescheduledLoads 137954 # Number of loads that were rescheduled 590system.cpu.iew.lsq.thread0.cacheBlocked 185768 # Number of times an access to memory failed due to the cache being blocked | 585system.cpu.iew.lsq.thread0.rescheduledLoads 140491 # Number of loads that were rescheduled 586system.cpu.iew.lsq.thread0.cacheBlocked 185859 # Number of times an access to memory failed due to the cache being blocked |
| 591system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 587system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 592system.cpu.iew.iewSquashCycles 493317 # Number of cycles IEW is squashing 593system.cpu.iew.iewBlockCycles 628934 # Number of cycles IEW is blocking 594system.cpu.iew.iewUnblockCycles 513918 # Number of cycles IEW is unblocking 595system.cpu.iew.iewDispatchedInsts 98227667 # Number of instructions dispatched to IQ | 588system.cpu.iew.iewSquashCycles 493569 # Number of cycles IEW is squashing 589system.cpu.iew.iewBlockCycles 630289 # Number of cycles IEW is blocking 590system.cpu.iew.iewUnblockCycles 523749 # Number of cycles IEW is unblocking 591system.cpu.iew.iewDispatchedInsts 98235038 # Number of instructions dispatched to IQ |
| 596system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 592system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 597system.cpu.iew.iewDispLoadInsts 24326602 # Number of dispatched load instructions 598system.cpu.iew.iewDispStoreInsts 22004719 # Number of dispatched store instructions 599system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions 600system.cpu.iew.iewIQFullEvents 1669 # Number of times the IQ has become full, causing a stall 601system.cpu.iew.iewLSQFullEvents 509191 # Number of times the LSQ has become full, causing a stall 602system.cpu.iew.memOrderViolationEvents 11950 # Number of memory order violations 603system.cpu.iew.predictedTakenIncorrect 303594 # Number of branches that were predicted taken incorrectly 604system.cpu.iew.predictedNotTakenIncorrect 221648 # Number of branches that were predicted not taken incorrectly 605system.cpu.iew.branchMispredicts 525242 # Number of branch mispredicts detected at execute 606system.cpu.iew.iewExecutedInsts 93991933 # Number of executed instructions 607system.cpu.iew.iewExecLoadInsts 23762441 # Number of load instructions executed 608system.cpu.iew.iewExecSquashedInsts 920332 # Number of squashed instructions skipped in execute | 593system.cpu.iew.iewDispLoadInsts 24327975 # Number of dispatched load instructions 594system.cpu.iew.iewDispStoreInsts 22005134 # Number of dispatched store instructions 595system.cpu.iew.iewDispNonSpecInsts 18597 # Number of dispatched non-speculative instructions 596system.cpu.iew.iewIQFullEvents 1652 # Number of times the IQ has become full, causing a stall 597system.cpu.iew.iewLSQFullEvents 519239 # Number of times the LSQ has become full, causing a stall 598system.cpu.iew.memOrderViolationEvents 11942 # Number of memory order violations 599system.cpu.iew.predictedTakenIncorrect 303965 # Number of branches that were predicted taken incorrectly 600system.cpu.iew.predictedNotTakenIncorrect 221737 # Number of branches that were predicted not taken incorrectly 601system.cpu.iew.branchMispredicts 525702 # Number of branch mispredicts detected at execute 602system.cpu.iew.iewExecutedInsts 93996105 # Number of executed instructions 603system.cpu.iew.iewExecLoadInsts 23765772 # Number of load instructions executed 604system.cpu.iew.iewExecSquashedInsts 920860 # Number of squashed instructions skipped in execute |
| 609system.cpu.iew.exec_swp 0 # number of swp insts executed | 605system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 610system.cpu.iew.exec_nop 9890 # number of nop insts executed 611system.cpu.iew.exec_refs 44753885 # number of memory reference insts executed 612system.cpu.iew.exec_branches 14253415 # Number of branches executed 613system.cpu.iew.exec_stores 20991444 # Number of stores executed 614system.cpu.iew.exec_rate 1.390923 # Inst execution rate 615system.cpu.iew.wb_sent 93601796 # cumulative count of insts sent to commit 616system.cpu.iew.wb_count 93479432 # cumulative count of insts written-back 617system.cpu.iew.wb_producers 44975266 # num instructions producing a value 618system.cpu.iew.wb_consumers 76559860 # num instructions consuming a value 619system.cpu.iew.wb_rate 1.383339 # insts written-back per cycle 620system.cpu.iew.wb_fanout 0.587452 # average fanout of values written-back 621system.cpu.commit.commitSquashedInsts 6553334 # The number of squashed insts skipped by commit | 606system.cpu.iew.exec_nop 9891 # number of nop insts executed 607system.cpu.iew.exec_refs 44755693 # number of memory reference insts executed 608system.cpu.iew.exec_branches 14254152 # Number of branches executed 609system.cpu.iew.exec_stores 20989921 # Number of stores executed 610system.cpu.iew.exec_rate 1.391128 # Inst execution rate 611system.cpu.iew.wb_sent 93602702 # cumulative count of insts sent to commit 612system.cpu.iew.wb_count 93480493 # cumulative count of insts written-back 613system.cpu.iew.wb_producers 44980132 # num instructions producing a value 614system.cpu.iew.wb_consumers 76556790 # num instructions consuming a value 615system.cpu.iew.wb_rate 1.383497 # insts written-back per cycle 616system.cpu.iew.wb_fanout 0.587539 # average fanout of values written-back 617system.cpu.commit.commitSquashedInsts 6559945 # The number of squashed insts skipped by commit |
| 622system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards | 618system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards |
| 623system.cpu.commit.branchMispredicts 480109 # The number of times a branch was mispredicted 624system.cpu.commit.committed_per_cycle::samples 65462437 # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::mean 1.385346 # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::stdev 2.157754 # Number of insts commited each cycle | 619system.cpu.commit.branchMispredicts 480375 # The number of times a branch was mispredicted 620system.cpu.commit.committed_per_cycle::samples 65432608 # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::mean 1.385978 # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::stdev 2.157554 # Number of insts commited each cycle |
| 627system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 623system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 628system.cpu.commit.committed_per_cycle::0 31857215 48.66% 48.66% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::1 16813031 25.68% 74.35% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::2 4347273 6.64% 80.99% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::3 4157866 6.35% 87.34% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::4 1935310 2.96% 90.30% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::5 1259510 1.92% 92.22% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::6 744006 1.14% 93.36% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::7 581672 0.89% 94.25% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::8 3766554 5.75% 100.00% # Number of insts commited each cycle | 624system.cpu.commit.committed_per_cycle::0 31819625 48.63% 48.63% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::1 16816004 25.70% 74.33% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::2 4349451 6.65% 80.98% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::3 4164400 6.36% 87.34% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::4 1932309 2.95% 90.29% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::5 1260445 1.93% 92.22% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::6 747040 1.14% 93.36% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::7 580342 0.89% 94.25% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::8 3762992 5.75% 100.00% # Number of insts commited each cycle |
| 637system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 633system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 640system.cpu.commit.committed_per_cycle::total 65462437 # Number of insts commited each cycle | 636system.cpu.commit.committed_per_cycle::total 65432608 # Number of insts commited each cycle |
| 641system.cpu.commit.committedInsts 70913182 # Number of instructions committed 642system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed 643system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 644system.cpu.commit.refs 43422000 # Number of memory references committed 645system.cpu.commit.loads 22866262 # Number of loads committed 646system.cpu.commit.membars 15920 # Number of memory barriers committed 647system.cpu.commit.branches 13741486 # Number of branches committed 648system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 678system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 681system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 682system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 683system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 684system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction | 637system.cpu.commit.committedInsts 70913182 # Number of instructions committed 638system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed 639system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 640system.cpu.commit.refs 43422000 # Number of memory references committed 641system.cpu.commit.loads 22866262 # Number of loads committed 642system.cpu.commit.membars 15920 # Number of memory barriers committed 643system.cpu.commit.branches 13741486 # Number of branches committed 644system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 674system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 677system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 678system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 679system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 680system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 681system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction |
| 686system.cpu.commit.bw_lim_events 3766554 # number cycles where commit BW limit reached 687system.cpu.rob.rob_reads 158912055 # The number of ROB reads 688system.cpu.rob.rob_writes 195546008 # The number of ROB writes 689system.cpu.timesIdled 28044 # Number of times that the entire CPU went into an idle state and unscheduled itself 690system.cpu.idleCycles 1051449 # Total number of cycles that the CPU has spent unscheduled due to idling | 682system.cpu.commit.bw_lim_events 3762992 # number cycles where commit BW limit reached 683system.cpu.rob.rob_reads 158892399 # The number of ROB reads 684system.cpu.rob.rob_writes 195560325 # The number of ROB writes 685system.cpu.timesIdled 28658 # Number of times that the entire CPU went into an idle state and unscheduled itself 686system.cpu.idleCycles 1073186 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 691system.cpu.committedInsts 70907630 # Number of Instructions Simulated 692system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated | 687system.cpu.committedInsts 70907630 # Number of Instructions Simulated 688system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated |
| 693system.cpu.cpi 0.953004 # CPI: Cycles Per Instruction 694system.cpu.cpi_total 0.953004 # CPI: Total CPI of All Threads 695system.cpu.ipc 1.049314 # IPC: Instructions Per Cycle 696system.cpu.ipc_total 1.049314 # IPC: Total IPC of All Threads 697system.cpu.int_regfile_reads 102290506 # number of integer regfile reads 698system.cpu.int_regfile_writes 56802248 # number of integer regfile writes 699system.cpu.fp_regfile_reads 40 # number of floating regfile reads 700system.cpu.fp_regfile_writes 24 # number of floating regfile writes 701system.cpu.cc_regfile_reads 346154538 # number of cc regfile reads 702system.cpu.cc_regfile_writes 38804906 # number of cc regfile writes 703system.cpu.misc_regfile_reads 44219892 # number of misc regfile reads | 689system.cpu.cpi 0.952906 # CPI: Cycles Per Instruction 690system.cpu.cpi_total 0.952906 # CPI: Total CPI of All Threads 691system.cpu.ipc 1.049422 # IPC: Instructions Per Cycle 692system.cpu.ipc_total 1.049422 # IPC: Total IPC of All Threads 693system.cpu.int_regfile_reads 102292430 # number of integer regfile reads 694system.cpu.int_regfile_writes 56802415 # number of integer regfile writes 695system.cpu.fp_regfile_reads 38 # number of floating regfile reads 696system.cpu.fp_regfile_writes 22 # number of floating regfile writes 697system.cpu.cc_regfile_reads 346166780 # number of cc regfile reads 698system.cpu.cc_regfile_writes 38809001 # number of cc regfile writes 699system.cpu.misc_regfile_reads 44218310 # number of misc regfile reads |
| 704system.cpu.misc_regfile_writes 31840 # number of misc regfile writes | 700system.cpu.misc_regfile_writes 31840 # number of misc regfile writes |
| 705system.cpu.dcache.tags.replacements 485017 # number of replacements 706system.cpu.dcache.tags.tagsinuse 510.752563 # Cycle average of tags in use 707system.cpu.dcache.tags.total_refs 40412566 # Total number of references to valid blocks. 708system.cpu.dcache.tags.sampled_refs 485529 # Sample count of references to valid blocks. 709system.cpu.dcache.tags.avg_refs 83.234093 # Average number of references to valid blocks. | 701system.cpu.dcache.tags.replacements 485025 # number of replacements 702system.cpu.dcache.tags.tagsinuse 510.752435 # Cycle average of tags in use 703system.cpu.dcache.tags.total_refs 40412261 # Total number of references to valid blocks. 704system.cpu.dcache.tags.sampled_refs 485537 # Sample count of references to valid blocks. 705system.cpu.dcache.tags.avg_refs 83.232094 # Average number of references to valid blocks. |
| 710system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. | 706system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. |
| 711system.cpu.dcache.tags.occ_blocks::cpu.data 510.752563 # Average occupied blocks per requestor 712system.cpu.dcache.tags.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy 713system.cpu.dcache.tags.occ_percent::total 0.997564 # Average percentage of cache occupancy | 707system.cpu.dcache.tags.occ_blocks::cpu.data 510.752435 # Average occupied blocks per requestor 708system.cpu.dcache.tags.occ_percent::cpu.data 0.997563 # Average percentage of cache occupancy 709system.cpu.dcache.tags.occ_percent::total 0.997563 # Average percentage of cache occupancy |
| 714system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 710system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 715system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 716system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id | 711system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 712system.cpu.dcache.tags.age_task_id_blocks_1024::1 455 # Occupied blocks per task id |
| 717system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 713system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 718system.cpu.dcache.tags.tag_accesses 84615901 # Number of tag accesses 719system.cpu.dcache.tags.data_accesses 84615901 # Number of data accesses 720system.cpu.dcache.ReadReq_hits::cpu.data 21489624 # number of ReadReq hits 721system.cpu.dcache.ReadReq_hits::total 21489624 # number of ReadReq hits 722system.cpu.dcache.WriteReq_hits::cpu.data 18831353 # number of WriteReq hits 723system.cpu.dcache.WriteReq_hits::total 18831353 # number of WriteReq hits 724system.cpu.dcache.SoftPFReq_hits::cpu.data 60282 # number of SoftPFReq hits 725system.cpu.dcache.SoftPFReq_hits::total 60282 # number of SoftPFReq hits 726system.cpu.dcache.LoadLockedReq_hits::cpu.data 15348 # number of LoadLockedReq hits 727system.cpu.dcache.LoadLockedReq_hits::total 15348 # number of LoadLockedReq hits | 714system.cpu.dcache.tags.tag_accesses 84614979 # Number of tag accesses 715system.cpu.dcache.tags.data_accesses 84614979 # Number of data accesses 716system.cpu.dcache.ReadReq_hits::cpu.data 21489272 # number of ReadReq hits 717system.cpu.dcache.ReadReq_hits::total 21489272 # number of ReadReq hits 718system.cpu.dcache.WriteReq_hits::cpu.data 18831416 # number of WriteReq hits 719system.cpu.dcache.WriteReq_hits::total 18831416 # number of WriteReq hits 720system.cpu.dcache.SoftPFReq_hits::cpu.data 60267 # number of SoftPFReq hits 721system.cpu.dcache.SoftPFReq_hits::total 60267 # number of SoftPFReq hits 722system.cpu.dcache.LoadLockedReq_hits::cpu.data 15347 # number of LoadLockedReq hits 723system.cpu.dcache.LoadLockedReq_hits::total 15347 # number of LoadLockedReq hits |
| 728system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 729system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits | 724system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 725system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| 730system.cpu.dcache.demand_hits::cpu.data 40320977 # number of demand (read+write) hits 731system.cpu.dcache.demand_hits::total 40320977 # number of demand (read+write) hits 732system.cpu.dcache.overall_hits::cpu.data 40381259 # number of overall hits 733system.cpu.dcache.overall_hits::total 40381259 # number of overall hits 734system.cpu.dcache.ReadReq_misses::cpu.data 564963 # number of ReadReq misses 735system.cpu.dcache.ReadReq_misses::total 564963 # number of ReadReq misses 736system.cpu.dcache.WriteReq_misses::cpu.data 1018548 # number of WriteReq misses 737system.cpu.dcache.WriteReq_misses::total 1018548 # number of WriteReq misses 738system.cpu.dcache.SoftPFReq_misses::cpu.data 68572 # number of SoftPFReq misses 739system.cpu.dcache.SoftPFReq_misses::total 68572 # number of SoftPFReq misses 740system.cpu.dcache.LoadLockedReq_misses::cpu.data 577 # number of LoadLockedReq misses 741system.cpu.dcache.LoadLockedReq_misses::total 577 # number of LoadLockedReq misses 742system.cpu.dcache.demand_misses::cpu.data 1583511 # number of demand (read+write) misses 743system.cpu.dcache.demand_misses::total 1583511 # number of demand (read+write) misses 744system.cpu.dcache.overall_misses::cpu.data 1652083 # number of overall misses 745system.cpu.dcache.overall_misses::total 1652083 # number of overall misses 746system.cpu.dcache.ReadReq_miss_latency::cpu.data 9256149500 # number of ReadReq miss cycles 747system.cpu.dcache.ReadReq_miss_latency::total 9256149500 # number of ReadReq miss cycles 748system.cpu.dcache.WriteReq_miss_latency::cpu.data 14245975429 # number of WriteReq miss cycles 749system.cpu.dcache.WriteReq_miss_latency::total 14245975429 # number of WriteReq miss cycles 750system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5465000 # number of LoadLockedReq miss cycles 751system.cpu.dcache.LoadLockedReq_miss_latency::total 5465000 # number of LoadLockedReq miss cycles 752system.cpu.dcache.demand_miss_latency::cpu.data 23502124929 # number of demand (read+write) miss cycles 753system.cpu.dcache.demand_miss_latency::total 23502124929 # number of demand (read+write) miss cycles 754system.cpu.dcache.overall_miss_latency::cpu.data 23502124929 # number of overall miss cycles 755system.cpu.dcache.overall_miss_latency::total 23502124929 # number of overall miss cycles 756system.cpu.dcache.ReadReq_accesses::cpu.data 22054587 # number of ReadReq accesses(hits+misses) 757system.cpu.dcache.ReadReq_accesses::total 22054587 # number of ReadReq accesses(hits+misses) | 726system.cpu.dcache.demand_hits::cpu.data 40320688 # number of demand (read+write) hits 727system.cpu.dcache.demand_hits::total 40320688 # number of demand (read+write) hits 728system.cpu.dcache.overall_hits::cpu.data 40380955 # number of overall hits 729system.cpu.dcache.overall_hits::total 40380955 # number of overall hits 730system.cpu.dcache.ReadReq_misses::cpu.data 564863 # number of ReadReq misses 731system.cpu.dcache.ReadReq_misses::total 564863 # number of ReadReq misses 732system.cpu.dcache.WriteReq_misses::cpu.data 1018485 # number of WriteReq misses 733system.cpu.dcache.WriteReq_misses::total 1018485 # number of WriteReq misses 734system.cpu.dcache.SoftPFReq_misses::cpu.data 68573 # number of SoftPFReq misses 735system.cpu.dcache.SoftPFReq_misses::total 68573 # number of SoftPFReq misses 736system.cpu.dcache.LoadLockedReq_misses::cpu.data 579 # number of LoadLockedReq misses 737system.cpu.dcache.LoadLockedReq_misses::total 579 # number of LoadLockedReq misses 738system.cpu.dcache.demand_misses::cpu.data 1583348 # number of demand (read+write) misses 739system.cpu.dcache.demand_misses::total 1583348 # number of demand (read+write) misses 740system.cpu.dcache.overall_misses::cpu.data 1651921 # number of overall misses 741system.cpu.dcache.overall_misses::total 1651921 # number of overall misses 742system.cpu.dcache.ReadReq_miss_latency::cpu.data 9285321000 # number of ReadReq miss cycles 743system.cpu.dcache.ReadReq_miss_latency::total 9285321000 # number of ReadReq miss cycles 744system.cpu.dcache.WriteReq_miss_latency::cpu.data 14250906929 # number of WriteReq miss cycles 745system.cpu.dcache.WriteReq_miss_latency::total 14250906929 # number of WriteReq miss cycles 746system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5341000 # number of LoadLockedReq miss cycles 747system.cpu.dcache.LoadLockedReq_miss_latency::total 5341000 # number of LoadLockedReq miss cycles 748system.cpu.dcache.demand_miss_latency::cpu.data 23536227929 # number of demand (read+write) miss cycles 749system.cpu.dcache.demand_miss_latency::total 23536227929 # number of demand (read+write) miss cycles 750system.cpu.dcache.overall_miss_latency::cpu.data 23536227929 # number of overall miss cycles 751system.cpu.dcache.overall_miss_latency::total 23536227929 # number of overall miss cycles 752system.cpu.dcache.ReadReq_accesses::cpu.data 22054135 # number of ReadReq accesses(hits+misses) 753system.cpu.dcache.ReadReq_accesses::total 22054135 # number of ReadReq accesses(hits+misses) |
| 758system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 759system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) | 754system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 755system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| 760system.cpu.dcache.SoftPFReq_accesses::cpu.data 128854 # number of SoftPFReq accesses(hits+misses) 761system.cpu.dcache.SoftPFReq_accesses::total 128854 # number of SoftPFReq accesses(hits+misses) 762system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15925 # number of LoadLockedReq accesses(hits+misses) 763system.cpu.dcache.LoadLockedReq_accesses::total 15925 # number of LoadLockedReq accesses(hits+misses) | 756system.cpu.dcache.SoftPFReq_accesses::cpu.data 128840 # number of SoftPFReq accesses(hits+misses) 757system.cpu.dcache.SoftPFReq_accesses::total 128840 # number of SoftPFReq accesses(hits+misses) 758system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) 759system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) |
| 764system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 765system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) | 760system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 761system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| 766system.cpu.dcache.demand_accesses::cpu.data 41904488 # number of demand (read+write) accesses 767system.cpu.dcache.demand_accesses::total 41904488 # number of demand (read+write) accesses 768system.cpu.dcache.overall_accesses::cpu.data 42033342 # number of overall (read+write) accesses 769system.cpu.dcache.overall_accesses::total 42033342 # number of overall (read+write) accesses 770system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025617 # miss rate for ReadReq accesses 771system.cpu.dcache.ReadReq_miss_rate::total 0.025617 # miss rate for ReadReq accesses 772system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051312 # miss rate for WriteReq accesses 773system.cpu.dcache.WriteReq_miss_rate::total 0.051312 # miss rate for WriteReq accesses 774system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532168 # miss rate for SoftPFReq accesses 775system.cpu.dcache.SoftPFReq_miss_rate::total 0.532168 # miss rate for SoftPFReq accesses 776system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036232 # miss rate for LoadLockedReq accesses 777system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036232 # miss rate for LoadLockedReq accesses 778system.cpu.dcache.demand_miss_rate::cpu.data 0.037789 # miss rate for demand accesses 779system.cpu.dcache.demand_miss_rate::total 0.037789 # miss rate for demand accesses 780system.cpu.dcache.overall_miss_rate::cpu.data 0.039304 # miss rate for overall accesses 781system.cpu.dcache.overall_miss_rate::total 0.039304 # miss rate for overall accesses 782system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16383.638398 # average ReadReq miss latency 783system.cpu.dcache.ReadReq_avg_miss_latency::total 16383.638398 # average ReadReq miss latency 784system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13986.552847 # average WriteReq miss latency 785system.cpu.dcache.WriteReq_avg_miss_latency::total 13986.552847 # average WriteReq miss latency 786system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9471.403813 # average LoadLockedReq miss latency 787system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9471.403813 # average LoadLockedReq miss latency 788system.cpu.dcache.demand_avg_miss_latency::cpu.data 14841.781919 # average overall miss latency 789system.cpu.dcache.demand_avg_miss_latency::total 14841.781919 # average overall miss latency 790system.cpu.dcache.overall_avg_miss_latency::cpu.data 14225.753143 # average overall miss latency 791system.cpu.dcache.overall_avg_miss_latency::total 14225.753143 # average overall miss latency 792system.cpu.dcache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked 793system.cpu.dcache.blocked_cycles::no_targets 2896869 # number of cycles access was blocked 794system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked 795system.cpu.dcache.blocked::no_targets 131288 # number of cycles access was blocked 796system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.466667 # average number of cycles each access was blocked 797system.cpu.dcache.avg_blocked_cycles::no_targets 22.064995 # average number of cycles each access was blocked | 762system.cpu.dcache.demand_accesses::cpu.data 41904036 # number of demand (read+write) accesses 763system.cpu.dcache.demand_accesses::total 41904036 # number of demand (read+write) accesses 764system.cpu.dcache.overall_accesses::cpu.data 42032876 # number of overall (read+write) accesses 765system.cpu.dcache.overall_accesses::total 42032876 # number of overall (read+write) accesses 766system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025613 # miss rate for ReadReq accesses 767system.cpu.dcache.ReadReq_miss_rate::total 0.025613 # miss rate for ReadReq accesses 768system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051309 # miss rate for WriteReq accesses 769system.cpu.dcache.WriteReq_miss_rate::total 0.051309 # miss rate for WriteReq accesses 770system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532234 # miss rate for SoftPFReq accesses 771system.cpu.dcache.SoftPFReq_miss_rate::total 0.532234 # miss rate for SoftPFReq accesses 772system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036356 # miss rate for LoadLockedReq accesses 773system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036356 # miss rate for LoadLockedReq accesses 774system.cpu.dcache.demand_miss_rate::cpu.data 0.037785 # miss rate for demand accesses 775system.cpu.dcache.demand_miss_rate::total 0.037785 # miss rate for demand accesses 776system.cpu.dcache.overall_miss_rate::cpu.data 0.039301 # miss rate for overall accesses 777system.cpu.dcache.overall_miss_rate::total 0.039301 # miss rate for overall accesses 778system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16438.182356 # average ReadReq miss latency 779system.cpu.dcache.ReadReq_avg_miss_latency::total 16438.182356 # average ReadReq miss latency 780system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13992.260003 # average WriteReq miss latency 781system.cpu.dcache.WriteReq_avg_miss_latency::total 13992.260003 # average WriteReq miss latency 782system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9224.525043 # average LoadLockedReq miss latency 783system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9224.525043 # average LoadLockedReq miss latency 784system.cpu.dcache.demand_avg_miss_latency::cpu.data 14864.848365 # average overall miss latency 785system.cpu.dcache.demand_avg_miss_latency::total 14864.848365 # average overall miss latency 786system.cpu.dcache.overall_avg_miss_latency::cpu.data 14247.792678 # average overall miss latency 787system.cpu.dcache.overall_avg_miss_latency::total 14247.792678 # average overall miss latency 788system.cpu.dcache.blocked_cycles::no_mshrs 81 # number of cycles access was blocked 789system.cpu.dcache.blocked_cycles::no_targets 2899485 # number of cycles access was blocked 790system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 791system.cpu.dcache.blocked::no_targets 131229 # number of cycles access was blocked 792system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.363636 # average number of cycles each access was blocked 793system.cpu.dcache.avg_blocked_cycles::no_targets 22.094849 # average number of cycles each access was blocked |
| 798system.cpu.dcache.fast_writes 0 # number of fast writes performed 799system.cpu.dcache.cache_copies 0 # number of cache copies performed | 794system.cpu.dcache.fast_writes 0 # number of fast writes performed 795system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 800system.cpu.dcache.writebacks::writebacks 485017 # number of writebacks 801system.cpu.dcache.writebacks::total 485017 # number of writebacks 802system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265550 # number of ReadReq MSHR hits 803system.cpu.dcache.ReadReq_mshr_hits::total 265550 # number of ReadReq MSHR hits 804system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870019 # number of WriteReq MSHR hits 805system.cpu.dcache.WriteReq_mshr_hits::total 870019 # number of WriteReq MSHR hits 806system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 577 # number of LoadLockedReq MSHR hits 807system.cpu.dcache.LoadLockedReq_mshr_hits::total 577 # number of LoadLockedReq MSHR hits 808system.cpu.dcache.demand_mshr_hits::cpu.data 1135569 # number of demand (read+write) MSHR hits 809system.cpu.dcache.demand_mshr_hits::total 1135569 # number of demand (read+write) MSHR hits 810system.cpu.dcache.overall_mshr_hits::cpu.data 1135569 # number of overall MSHR hits 811system.cpu.dcache.overall_mshr_hits::total 1135569 # number of overall MSHR hits 812system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299413 # number of ReadReq MSHR misses 813system.cpu.dcache.ReadReq_mshr_misses::total 299413 # number of ReadReq MSHR misses 814system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148529 # number of WriteReq MSHR misses 815system.cpu.dcache.WriteReq_mshr_misses::total 148529 # number of WriteReq MSHR misses | 796system.cpu.dcache.writebacks::writebacks 485025 # number of writebacks 797system.cpu.dcache.writebacks::total 485025 # number of writebacks 798system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265446 # number of ReadReq MSHR hits 799system.cpu.dcache.ReadReq_mshr_hits::total 265446 # number of ReadReq MSHR hits 800system.cpu.dcache.WriteReq_mshr_hits::cpu.data 869952 # number of WriteReq MSHR hits 801system.cpu.dcache.WriteReq_mshr_hits::total 869952 # number of WriteReq MSHR hits 802system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 579 # number of LoadLockedReq MSHR hits 803system.cpu.dcache.LoadLockedReq_mshr_hits::total 579 # number of LoadLockedReq MSHR hits 804system.cpu.dcache.demand_mshr_hits::cpu.data 1135398 # number of demand (read+write) MSHR hits 805system.cpu.dcache.demand_mshr_hits::total 1135398 # number of demand (read+write) MSHR hits 806system.cpu.dcache.overall_mshr_hits::cpu.data 1135398 # number of overall MSHR hits 807system.cpu.dcache.overall_mshr_hits::total 1135398 # number of overall MSHR hits 808system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299417 # number of ReadReq MSHR misses 809system.cpu.dcache.ReadReq_mshr_misses::total 299417 # number of ReadReq MSHR misses 810system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148533 # number of WriteReq MSHR misses 811system.cpu.dcache.WriteReq_mshr_misses::total 148533 # number of WriteReq MSHR misses |
| 816system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses 817system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses | 812system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses 813system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses |
| 818system.cpu.dcache.demand_mshr_misses::cpu.data 447942 # number of demand (read+write) MSHR misses 819system.cpu.dcache.demand_mshr_misses::total 447942 # number of demand (read+write) MSHR misses 820system.cpu.dcache.overall_mshr_misses::cpu.data 485539 # number of overall MSHR misses 821system.cpu.dcache.overall_mshr_misses::total 485539 # number of overall MSHR misses 822system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3625766000 # number of ReadReq MSHR miss cycles 823system.cpu.dcache.ReadReq_mshr_miss_latency::total 3625766000 # number of ReadReq MSHR miss cycles 824system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2305447971 # number of WriteReq MSHR miss cycles 825system.cpu.dcache.WriteReq_mshr_miss_latency::total 2305447971 # number of WriteReq MSHR miss cycles 826system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1884857000 # number of SoftPFReq MSHR miss cycles 827system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1884857000 # number of SoftPFReq MSHR miss cycles 828system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5931213971 # number of demand (read+write) MSHR miss cycles 829system.cpu.dcache.demand_mshr_miss_latency::total 5931213971 # number of demand (read+write) MSHR miss cycles 830system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816070971 # number of overall MSHR miss cycles 831system.cpu.dcache.overall_mshr_miss_latency::total 7816070971 # number of overall MSHR miss cycles | 814system.cpu.dcache.demand_mshr_misses::cpu.data 447950 # number of demand (read+write) MSHR misses 815system.cpu.dcache.demand_mshr_misses::total 447950 # number of demand (read+write) MSHR misses 816system.cpu.dcache.overall_mshr_misses::cpu.data 485547 # number of overall MSHR misses 817system.cpu.dcache.overall_mshr_misses::total 485547 # number of overall MSHR misses 818system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3589129000 # number of ReadReq MSHR miss cycles 819system.cpu.dcache.ReadReq_mshr_miss_latency::total 3589129000 # number of ReadReq MSHR miss cycles 820system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2306203970 # number of WriteReq MSHR miss cycles 821system.cpu.dcache.WriteReq_mshr_miss_latency::total 2306203970 # number of WriteReq MSHR miss cycles 822system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1890576000 # number of SoftPFReq MSHR miss cycles 823system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1890576000 # number of SoftPFReq MSHR miss cycles 824system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5895332970 # number of demand (read+write) MSHR miss cycles 825system.cpu.dcache.demand_mshr_miss_latency::total 5895332970 # number of demand (read+write) MSHR miss cycles 826system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7785908970 # number of overall MSHR miss cycles 827system.cpu.dcache.overall_mshr_miss_latency::total 7785908970 # number of overall MSHR miss cycles |
| 832system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses 833system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses 834system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses 835system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses | 828system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses 829system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses 830system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses 831system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses |
| 836system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291780 # mshr miss rate for SoftPFReq accesses 837system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291780 # mshr miss rate for SoftPFReq accesses | 832system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291812 # mshr miss rate for SoftPFReq accesses 833system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291812 # mshr miss rate for SoftPFReq accesses |
| 838system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses 839system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses | 834system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses 835system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses |
| 840system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011551 # mshr miss rate for overall accesses 841system.cpu.dcache.overall_mshr_miss_rate::total 0.011551 # mshr miss rate for overall accesses 842system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12109.581080 # average ReadReq mshr miss latency 843system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12109.581080 # average ReadReq mshr miss latency 844system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15521.870954 # average WriteReq mshr miss latency 845system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15521.870954 # average WriteReq mshr miss latency 846system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50133.175519 # average SoftPFReq mshr miss latency 847system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50133.175519 # average SoftPFReq mshr miss latency 848system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13241.031140 # average overall mshr miss latency 849system.cpu.dcache.demand_avg_mshr_miss_latency::total 13241.031140 # average overall mshr miss latency 850system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16097.720206 # average overall mshr miss latency 851system.cpu.dcache.overall_avg_mshr_miss_latency::total 16097.720206 # average overall mshr miss latency | 836system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses 837system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses 838system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11987.058183 # average ReadReq mshr miss latency 839system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11987.058183 # average ReadReq mshr miss latency 840system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15526.542721 # average WriteReq mshr miss latency 841system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15526.542721 # average WriteReq mshr miss latency 842system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50285.288720 # average SoftPFReq mshr miss latency 843system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50285.288720 # average SoftPFReq mshr miss latency 844system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13160.694207 # average overall mshr miss latency 845system.cpu.dcache.demand_avg_mshr_miss_latency::total 13160.694207 # average overall mshr miss latency 846system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16035.335343 # average overall mshr miss latency 847system.cpu.dcache.overall_avg_mshr_miss_latency::total 16035.335343 # average overall mshr miss latency |
| 852system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 848system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 853system.cpu.icache.tags.replacements 323105 # number of replacements 854system.cpu.icache.tags.tagsinuse 510.281102 # Cycle average of tags in use 855system.cpu.icache.tags.total_refs 22444187 # Total number of references to valid blocks. 856system.cpu.icache.tags.sampled_refs 323617 # Sample count of references to valid blocks. 857system.cpu.icache.tags.avg_refs 69.354166 # Average number of references to valid blocks. | 849system.cpu.icache.tags.replacements 323129 # number of replacements 850system.cpu.icache.tags.tagsinuse 510.280955 # Cycle average of tags in use 851system.cpu.icache.tags.total_refs 22445799 # Total number of references to valid blocks. 852system.cpu.icache.tags.sampled_refs 323641 # Sample count of references to valid blocks. 853system.cpu.icache.tags.avg_refs 69.354003 # Average number of references to valid blocks. |
| 858system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit. | 854system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit. |
| 859system.cpu.icache.tags.occ_blocks::cpu.inst 510.281102 # Average occupied blocks per requestor 860system.cpu.icache.tags.occ_percent::cpu.inst 0.996643 # Average percentage of cache occupancy 861system.cpu.icache.tags.occ_percent::total 0.996643 # Average percentage of cache occupancy | 855system.cpu.icache.tags.occ_blocks::cpu.inst 510.280955 # Average occupied blocks per requestor 856system.cpu.icache.tags.occ_percent::cpu.inst 0.996642 # Average percentage of cache occupancy 857system.cpu.icache.tags.occ_percent::total 0.996642 # Average percentage of cache occupancy |
| 862system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 858system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 863system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 864system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id 865system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id 866system.cpu.icache.tags.age_task_id_blocks_1024::3 341 # Occupied blocks per task id | 859system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 860system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 861system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id 862system.cpu.icache.tags.age_task_id_blocks_1024::3 335 # Occupied blocks per task id |
| 867system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 868system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 863system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 864system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 869system.cpu.icache.tags.tag_accesses 45880575 # Number of tag accesses 870system.cpu.icache.tags.data_accesses 45880575 # Number of data accesses 871system.cpu.icache.ReadReq_hits::cpu.inst 22444187 # number of ReadReq hits 872system.cpu.icache.ReadReq_hits::total 22444187 # number of ReadReq hits 873system.cpu.icache.demand_hits::cpu.inst 22444187 # number of demand (read+write) hits 874system.cpu.icache.demand_hits::total 22444187 # number of demand (read+write) hits 875system.cpu.icache.overall_hits::cpu.inst 22444187 # number of overall hits 876system.cpu.icache.overall_hits::total 22444187 # number of overall hits 877system.cpu.icache.ReadReq_misses::cpu.inst 334287 # number of ReadReq misses 878system.cpu.icache.ReadReq_misses::total 334287 # number of ReadReq misses 879system.cpu.icache.demand_misses::cpu.inst 334287 # number of demand (read+write) misses 880system.cpu.icache.demand_misses::total 334287 # number of demand (read+write) misses 881system.cpu.icache.overall_misses::cpu.inst 334287 # number of overall misses 882system.cpu.icache.overall_misses::total 334287 # number of overall misses 883system.cpu.icache.ReadReq_miss_latency::cpu.inst 3550514898 # number of ReadReq miss cycles 884system.cpu.icache.ReadReq_miss_latency::total 3550514898 # number of ReadReq miss cycles 885system.cpu.icache.demand_miss_latency::cpu.inst 3550514898 # number of demand (read+write) miss cycles 886system.cpu.icache.demand_miss_latency::total 3550514898 # number of demand (read+write) miss cycles 887system.cpu.icache.overall_miss_latency::cpu.inst 3550514898 # number of overall miss cycles 888system.cpu.icache.overall_miss_latency::total 3550514898 # number of overall miss cycles 889system.cpu.icache.ReadReq_accesses::cpu.inst 22778474 # number of ReadReq accesses(hits+misses) 890system.cpu.icache.ReadReq_accesses::total 22778474 # number of ReadReq accesses(hits+misses) 891system.cpu.icache.demand_accesses::cpu.inst 22778474 # number of demand (read+write) accesses 892system.cpu.icache.demand_accesses::total 22778474 # number of demand (read+write) accesses 893system.cpu.icache.overall_accesses::cpu.inst 22778474 # number of overall (read+write) accesses 894system.cpu.icache.overall_accesses::total 22778474 # number of overall (read+write) accesses 895system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014676 # miss rate for ReadReq accesses 896system.cpu.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses 897system.cpu.icache.demand_miss_rate::cpu.inst 0.014676 # miss rate for demand accesses 898system.cpu.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses 899system.cpu.icache.overall_miss_rate::cpu.inst 0.014676 # miss rate for overall accesses 900system.cpu.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses 901system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10621.157562 # average ReadReq miss latency 902system.cpu.icache.ReadReq_avg_miss_latency::total 10621.157562 # average ReadReq miss latency 903system.cpu.icache.demand_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency 904system.cpu.icache.demand_avg_miss_latency::total 10621.157562 # average overall miss latency 905system.cpu.icache.overall_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency 906system.cpu.icache.overall_avg_miss_latency::total 10621.157562 # average overall miss latency 907system.cpu.icache.blocked_cycles::no_mshrs 261417 # number of cycles access was blocked | 865system.cpu.icache.tags.tag_accesses 45884745 # Number of tag accesses 866system.cpu.icache.tags.data_accesses 45884745 # Number of data accesses 867system.cpu.icache.ReadReq_hits::cpu.inst 22445799 # number of ReadReq hits 868system.cpu.icache.ReadReq_hits::total 22445799 # number of ReadReq hits 869system.cpu.icache.demand_hits::cpu.inst 22445799 # number of demand (read+write) hits 870system.cpu.icache.demand_hits::total 22445799 # number of demand (read+write) hits 871system.cpu.icache.overall_hits::cpu.inst 22445799 # number of overall hits 872system.cpu.icache.overall_hits::total 22445799 # number of overall hits 873system.cpu.icache.ReadReq_misses::cpu.inst 334748 # number of ReadReq misses 874system.cpu.icache.ReadReq_misses::total 334748 # number of ReadReq misses 875system.cpu.icache.demand_misses::cpu.inst 334748 # number of demand (read+write) misses 876system.cpu.icache.demand_misses::total 334748 # number of demand (read+write) misses 877system.cpu.icache.overall_misses::cpu.inst 334748 # number of overall misses 878system.cpu.icache.overall_misses::total 334748 # number of overall misses 879system.cpu.icache.ReadReq_miss_latency::cpu.inst 3612917411 # number of ReadReq miss cycles 880system.cpu.icache.ReadReq_miss_latency::total 3612917411 # number of ReadReq miss cycles 881system.cpu.icache.demand_miss_latency::cpu.inst 3612917411 # number of demand (read+write) miss cycles 882system.cpu.icache.demand_miss_latency::total 3612917411 # number of demand (read+write) miss cycles 883system.cpu.icache.overall_miss_latency::cpu.inst 3612917411 # number of overall miss cycles 884system.cpu.icache.overall_miss_latency::total 3612917411 # number of overall miss cycles 885system.cpu.icache.ReadReq_accesses::cpu.inst 22780547 # number of ReadReq accesses(hits+misses) 886system.cpu.icache.ReadReq_accesses::total 22780547 # number of ReadReq accesses(hits+misses) 887system.cpu.icache.demand_accesses::cpu.inst 22780547 # number of demand (read+write) accesses 888system.cpu.icache.demand_accesses::total 22780547 # number of demand (read+write) accesses 889system.cpu.icache.overall_accesses::cpu.inst 22780547 # number of overall (read+write) accesses 890system.cpu.icache.overall_accesses::total 22780547 # number of overall (read+write) accesses 891system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014694 # miss rate for ReadReq accesses 892system.cpu.icache.ReadReq_miss_rate::total 0.014694 # miss rate for ReadReq accesses 893system.cpu.icache.demand_miss_rate::cpu.inst 0.014694 # miss rate for demand accesses 894system.cpu.icache.demand_miss_rate::total 0.014694 # miss rate for demand accesses 895system.cpu.icache.overall_miss_rate::cpu.inst 0.014694 # miss rate for overall accesses 896system.cpu.icache.overall_miss_rate::total 0.014694 # miss rate for overall accesses 897system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10792.946966 # average ReadReq miss latency 898system.cpu.icache.ReadReq_avg_miss_latency::total 10792.946966 # average ReadReq miss latency 899system.cpu.icache.demand_avg_miss_latency::cpu.inst 10792.946966 # average overall miss latency 900system.cpu.icache.demand_avg_miss_latency::total 10792.946966 # average overall miss latency 901system.cpu.icache.overall_avg_miss_latency::cpu.inst 10792.946966 # average overall miss latency 902system.cpu.icache.overall_avg_miss_latency::total 10792.946966 # average overall miss latency 903system.cpu.icache.blocked_cycles::no_mshrs 264495 # number of cycles access was blocked |
| 908system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked | 904system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked |
| 909system.cpu.icache.blocked::no_mshrs 16440 # number of cycles access was blocked | 905system.cpu.icache.blocked::no_mshrs 16626 # number of cycles access was blocked |
| 910system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked | 906system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked |
| 911system.cpu.icache.avg_blocked_cycles::no_mshrs 15.901277 # average number of cycles each access was blocked | 907system.cpu.icache.avg_blocked_cycles::no_mshrs 15.908517 # average number of cycles each access was blocked |
| 912system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked 913system.cpu.icache.fast_writes 0 # number of fast writes performed 914system.cpu.icache.cache_copies 0 # number of cache copies performed | 908system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked 909system.cpu.icache.fast_writes 0 # number of fast writes performed 910system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 915system.cpu.icache.writebacks::writebacks 323105 # number of writebacks 916system.cpu.icache.writebacks::total 323105 # number of writebacks 917system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10659 # number of ReadReq MSHR hits 918system.cpu.icache.ReadReq_mshr_hits::total 10659 # number of ReadReq MSHR hits 919system.cpu.icache.demand_mshr_hits::cpu.inst 10659 # number of demand (read+write) MSHR hits 920system.cpu.icache.demand_mshr_hits::total 10659 # number of demand (read+write) MSHR hits 921system.cpu.icache.overall_mshr_hits::cpu.inst 10659 # number of overall MSHR hits 922system.cpu.icache.overall_mshr_hits::total 10659 # number of overall MSHR hits 923system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323628 # number of ReadReq MSHR misses 924system.cpu.icache.ReadReq_mshr_misses::total 323628 # number of ReadReq MSHR misses 925system.cpu.icache.demand_mshr_misses::cpu.inst 323628 # number of demand (read+write) MSHR misses 926system.cpu.icache.demand_mshr_misses::total 323628 # number of demand (read+write) MSHR misses 927system.cpu.icache.overall_mshr_misses::cpu.inst 323628 # number of overall MSHR misses 928system.cpu.icache.overall_mshr_misses::total 323628 # number of overall MSHR misses 929system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3274041434 # number of ReadReq MSHR miss cycles 930system.cpu.icache.ReadReq_mshr_miss_latency::total 3274041434 # number of ReadReq MSHR miss cycles 931system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3274041434 # number of demand (read+write) MSHR miss cycles 932system.cpu.icache.demand_mshr_miss_latency::total 3274041434 # number of demand (read+write) MSHR miss cycles 933system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3274041434 # number of overall MSHR miss cycles 934system.cpu.icache.overall_mshr_miss_latency::total 3274041434 # number of overall MSHR miss cycles 935system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for ReadReq accesses 936system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014208 # mshr miss rate for ReadReq accesses 937system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for demand accesses 938system.cpu.icache.demand_mshr_miss_rate::total 0.014208 # mshr miss rate for demand accesses 939system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for overall accesses 940system.cpu.icache.overall_mshr_miss_rate::total 0.014208 # mshr miss rate for overall accesses 941system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10116.681604 # average ReadReq mshr miss latency 942system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10116.681604 # average ReadReq mshr miss latency 943system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10116.681604 # average overall mshr miss latency 944system.cpu.icache.demand_avg_mshr_miss_latency::total 10116.681604 # average overall mshr miss latency 945system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10116.681604 # average overall mshr miss latency 946system.cpu.icache.overall_avg_mshr_miss_latency::total 10116.681604 # average overall mshr miss latency | 911system.cpu.icache.writebacks::writebacks 323129 # number of writebacks 912system.cpu.icache.writebacks::total 323129 # number of writebacks 913system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11096 # number of ReadReq MSHR hits 914system.cpu.icache.ReadReq_mshr_hits::total 11096 # number of ReadReq MSHR hits 915system.cpu.icache.demand_mshr_hits::cpu.inst 11096 # number of demand (read+write) MSHR hits 916system.cpu.icache.demand_mshr_hits::total 11096 # number of demand (read+write) MSHR hits 917system.cpu.icache.overall_mshr_hits::cpu.inst 11096 # number of overall MSHR hits 918system.cpu.icache.overall_mshr_hits::total 11096 # number of overall MSHR hits 919system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323652 # number of ReadReq MSHR misses 920system.cpu.icache.ReadReq_mshr_misses::total 323652 # number of ReadReq MSHR misses 921system.cpu.icache.demand_mshr_misses::cpu.inst 323652 # number of demand (read+write) MSHR misses 922system.cpu.icache.demand_mshr_misses::total 323652 # number of demand (read+write) MSHR misses 923system.cpu.icache.overall_mshr_misses::cpu.inst 323652 # number of overall MSHR misses 924system.cpu.icache.overall_mshr_misses::total 323652 # number of overall MSHR misses 925system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3313255946 # number of ReadReq MSHR miss cycles 926system.cpu.icache.ReadReq_mshr_miss_latency::total 3313255946 # number of ReadReq MSHR miss cycles 927system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3313255946 # number of demand (read+write) MSHR miss cycles 928system.cpu.icache.demand_mshr_miss_latency::total 3313255946 # number of demand (read+write) MSHR miss cycles 929system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3313255946 # number of overall MSHR miss cycles 930system.cpu.icache.overall_mshr_miss_latency::total 3313255946 # number of overall MSHR miss cycles 931system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for ReadReq accesses 932system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014207 # mshr miss rate for ReadReq accesses 933system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for demand accesses 934system.cpu.icache.demand_mshr_miss_rate::total 0.014207 # mshr miss rate for demand accesses 935system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for overall accesses 936system.cpu.icache.overall_mshr_miss_rate::total 0.014207 # mshr miss rate for overall accesses 937system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10237.093996 # average ReadReq mshr miss latency 938system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10237.093996 # average ReadReq mshr miss latency 939system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10237.093996 # average overall mshr miss latency 940system.cpu.icache.demand_avg_mshr_miss_latency::total 10237.093996 # average overall mshr miss latency 941system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10237.093996 # average overall mshr miss latency 942system.cpu.icache.overall_avg_mshr_miss_latency::total 10237.093996 # average overall mshr miss latency |
| 947system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 943system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 948system.cpu.l2cache.prefetcher.num_hwpf_issued 822385 # number of hwpf issued 949system.cpu.l2cache.prefetcher.pfIdentified 826178 # number of prefetch candidates identified 950system.cpu.l2cache.prefetcher.pfBufferHit 3328 # number of redundant prefetches already in prefetch queue | 944system.cpu.l2cache.prefetcher.num_hwpf_issued 821921 # number of hwpf issued 945system.cpu.l2cache.prefetcher.pfIdentified 825508 # number of prefetch candidates identified 946system.cpu.l2cache.prefetcher.pfBufferHit 3147 # number of redundant prefetches already in prefetch queue |
| 951system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 952system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 947system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 948system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 953system.cpu.l2cache.prefetcher.pfSpanPage 78886 # number of prefetches not generated due to page crossing 954system.cpu.l2cache.tags.replacements 128056 # number of replacements 955system.cpu.l2cache.tags.tagsinuse 15991.461548 # Cycle average of tags in use 956system.cpu.l2cache.tags.total_refs 1186413 # Total number of references to valid blocks. 957system.cpu.l2cache.tags.sampled_refs 144416 # Sample count of references to valid blocks. 958system.cpu.l2cache.tags.avg_refs 8.215246 # Average number of references to valid blocks. | 949system.cpu.l2cache.prefetcher.pfSpanPage 78532 # number of prefetches not generated due to page crossing 950system.cpu.l2cache.tags.replacements 128137 # number of replacements 951system.cpu.l2cache.tags.tagsinuse 15990.250829 # Cycle average of tags in use 952system.cpu.l2cache.tags.total_refs 1182553 # Total number of references to valid blocks. 953system.cpu.l2cache.tags.sampled_refs 144496 # Sample count of references to valid blocks. 954system.cpu.l2cache.tags.avg_refs 8.183984 # Average number of references to valid blocks. |
| 959system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 955system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 960system.cpu.l2cache.tags.occ_blocks::writebacks 15890.954967 # Average occupied blocks per requestor 961system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 100.506581 # Average occupied blocks per requestor 962system.cpu.l2cache.tags.occ_percent::writebacks 0.969907 # Average percentage of cache occupancy 963system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006134 # Average percentage of cache occupancy 964system.cpu.l2cache.tags.occ_percent::total 0.976041 # Average percentage of cache occupancy 965system.cpu.l2cache.tags.occ_task_id_blocks::1022 34 # Occupied blocks per task id | 956system.cpu.l2cache.tags.occ_blocks::writebacks 15899.758864 # Average occupied blocks per requestor 957system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 90.491965 # Average occupied blocks per requestor 958system.cpu.l2cache.tags.occ_percent::writebacks 0.970444 # Average percentage of cache occupancy 959system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005523 # Average percentage of cache occupancy 960system.cpu.l2cache.tags.occ_percent::total 0.975967 # Average percentage of cache occupancy 961system.cpu.l2cache.tags.occ_task_id_blocks::1022 33 # Occupied blocks per task id |
| 966system.cpu.l2cache.tags.occ_task_id_blocks::1024 16326 # Occupied blocks per task id | 962system.cpu.l2cache.tags.occ_task_id_blocks::1024 16326 # Occupied blocks per task id |
| 967system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 968system.cpu.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id 969system.cpu.l2cache.tags.age_task_id_blocks_1022::3 18 # Occupied blocks per task id | 963system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 964system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id 965system.cpu.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id |
| 970system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id | 966system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id |
| 971system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 972system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2702 # Occupied blocks per task id 973system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12111 # Occupied blocks per task id 974system.cpu.l2cache.tags.age_task_id_blocks_1024::3 578 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1024::4 810 # Occupied blocks per task id 976system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002075 # Percentage of cache occupancy per task id | 967system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id 968system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2752 # Occupied blocks per task id 969system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12114 # Occupied blocks per task id 970system.cpu.l2cache.tags.age_task_id_blocks_1024::3 551 # Occupied blocks per task id 971system.cpu.l2cache.tags.age_task_id_blocks_1024::4 772 # Occupied blocks per task id 972system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002014 # Percentage of cache occupancy per task id |
| 977system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996460 # Percentage of cache occupancy per task id | 973system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996460 # Percentage of cache occupancy per task id |
| 978system.cpu.l2cache.tags.tag_accesses 24986640 # Number of tag accesses 979system.cpu.l2cache.tags.data_accesses 24986640 # Number of data accesses 980system.cpu.l2cache.WritebackDirty_hits::writebacks 253426 # number of WritebackDirty hits 981system.cpu.l2cache.WritebackDirty_hits::total 253426 # number of WritebackDirty hits 982system.cpu.l2cache.WritebackClean_hits::writebacks 474834 # number of WritebackClean hits 983system.cpu.l2cache.WritebackClean_hits::total 474834 # number of WritebackClean hits 984system.cpu.l2cache.ReadExReq_hits::cpu.data 137075 # number of ReadExReq hits 985system.cpu.l2cache.ReadExReq_hits::total 137075 # number of ReadExReq hits 986system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 312075 # number of ReadCleanReq hits 987system.cpu.l2cache.ReadCleanReq_hits::total 312075 # number of ReadCleanReq hits 988system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300547 # number of ReadSharedReq hits 989system.cpu.l2cache.ReadSharedReq_hits::total 300547 # number of ReadSharedReq hits 990system.cpu.l2cache.demand_hits::cpu.inst 312075 # number of demand (read+write) hits 991system.cpu.l2cache.demand_hits::cpu.data 437622 # number of demand (read+write) hits 992system.cpu.l2cache.demand_hits::total 749697 # number of demand (read+write) hits 993system.cpu.l2cache.overall_hits::cpu.inst 312075 # number of overall hits 994system.cpu.l2cache.overall_hits::cpu.data 437622 # number of overall hits 995system.cpu.l2cache.overall_hits::total 749697 # number of overall hits | 974system.cpu.l2cache.tags.tag_accesses 24991467 # Number of tag accesses 975system.cpu.l2cache.tags.data_accesses 24991467 # Number of data accesses 976system.cpu.l2cache.WritebackDirty_hits::writebacks 256728 # number of WritebackDirty hits 977system.cpu.l2cache.WritebackDirty_hits::total 256728 # number of WritebackDirty hits 978system.cpu.l2cache.WritebackClean_hits::writebacks 471596 # number of WritebackClean hits 979system.cpu.l2cache.WritebackClean_hits::total 471596 # number of WritebackClean hits 980system.cpu.l2cache.ReadExReq_hits::cpu.data 137032 # number of ReadExReq hits 981system.cpu.l2cache.ReadExReq_hits::total 137032 # number of ReadExReq hits 982system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 311398 # number of ReadCleanReq hits 983system.cpu.l2cache.ReadCleanReq_hits::total 311398 # number of ReadCleanReq hits 984system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300922 # number of ReadSharedReq hits 985system.cpu.l2cache.ReadSharedReq_hits::total 300922 # number of ReadSharedReq hits 986system.cpu.l2cache.demand_hits::cpu.inst 311398 # number of demand (read+write) hits 987system.cpu.l2cache.demand_hits::cpu.data 437954 # number of demand (read+write) hits 988system.cpu.l2cache.demand_hits::total 749352 # number of demand (read+write) hits 989system.cpu.l2cache.overall_hits::cpu.inst 311398 # number of overall hits 990system.cpu.l2cache.overall_hits::cpu.data 437954 # number of overall hits 991system.cpu.l2cache.overall_hits::total 749352 # number of overall hits |
| 996system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses 997system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses | 992system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses 993system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses |
| 998system.cpu.l2cache.ReadExReq_misses::cpu.data 11487 # number of ReadExReq misses 999system.cpu.l2cache.ReadExReq_misses::total 11487 # number of ReadExReq misses 1000system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 11542 # number of ReadCleanReq misses 1001system.cpu.l2cache.ReadCleanReq_misses::total 11542 # number of ReadCleanReq misses 1002system.cpu.l2cache.ReadSharedReq_misses::cpu.data 36420 # number of ReadSharedReq misses 1003system.cpu.l2cache.ReadSharedReq_misses::total 36420 # number of ReadSharedReq misses 1004system.cpu.l2cache.demand_misses::cpu.inst 11542 # number of demand (read+write) misses 1005system.cpu.l2cache.demand_misses::cpu.data 47907 # number of demand (read+write) misses 1006system.cpu.l2cache.demand_misses::total 59449 # number of demand (read+write) misses 1007system.cpu.l2cache.overall_misses::cpu.inst 11542 # number of overall misses 1008system.cpu.l2cache.overall_misses::cpu.data 47907 # number of overall misses 1009system.cpu.l2cache.overall_misses::total 59449 # number of overall misses 1010system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1187801500 # number of ReadExReq miss cycles 1011system.cpu.l2cache.ReadExReq_miss_latency::total 1187801500 # number of ReadExReq miss cycles 1012system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 872329000 # number of ReadCleanReq miss cycles 1013system.cpu.l2cache.ReadCleanReq_miss_latency::total 872329000 # number of ReadCleanReq miss cycles 1014system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3000401500 # number of ReadSharedReq miss cycles 1015system.cpu.l2cache.ReadSharedReq_miss_latency::total 3000401500 # number of ReadSharedReq miss cycles 1016system.cpu.l2cache.demand_miss_latency::cpu.inst 872329000 # number of demand (read+write) miss cycles 1017system.cpu.l2cache.demand_miss_latency::cpu.data 4188203000 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.demand_miss_latency::total 5060532000 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.overall_miss_latency::cpu.inst 872329000 # number of overall miss cycles 1020system.cpu.l2cache.overall_miss_latency::cpu.data 4188203000 # number of overall miss cycles 1021system.cpu.l2cache.overall_miss_latency::total 5060532000 # number of overall miss cycles 1022system.cpu.l2cache.WritebackDirty_accesses::writebacks 253426 # number of WritebackDirty accesses(hits+misses) 1023system.cpu.l2cache.WritebackDirty_accesses::total 253426 # number of WritebackDirty accesses(hits+misses) 1024system.cpu.l2cache.WritebackClean_accesses::writebacks 474834 # number of WritebackClean accesses(hits+misses) 1025system.cpu.l2cache.WritebackClean_accesses::total 474834 # number of WritebackClean accesses(hits+misses) | 994system.cpu.l2cache.ReadExReq_misses::cpu.data 11535 # number of ReadExReq misses 995system.cpu.l2cache.ReadExReq_misses::total 11535 # number of ReadExReq misses 996system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12242 # number of ReadCleanReq misses 997system.cpu.l2cache.ReadCleanReq_misses::total 12242 # number of ReadCleanReq misses 998system.cpu.l2cache.ReadSharedReq_misses::cpu.data 36048 # number of ReadSharedReq misses 999system.cpu.l2cache.ReadSharedReq_misses::total 36048 # number of ReadSharedReq misses 1000system.cpu.l2cache.demand_misses::cpu.inst 12242 # number of demand (read+write) misses 1001system.cpu.l2cache.demand_misses::cpu.data 47583 # number of demand (read+write) misses 1002system.cpu.l2cache.demand_misses::total 59825 # number of demand (read+write) misses 1003system.cpu.l2cache.overall_misses::cpu.inst 12242 # number of overall misses 1004system.cpu.l2cache.overall_misses::cpu.data 47583 # number of overall misses 1005system.cpu.l2cache.overall_misses::total 59825 # number of overall misses 1006system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1188658000 # number of ReadExReq miss cycles 1007system.cpu.l2cache.ReadExReq_miss_latency::total 1188658000 # number of ReadExReq miss cycles 1008system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 916670500 # number of ReadCleanReq miss cycles 1009system.cpu.l2cache.ReadCleanReq_miss_latency::total 916670500 # number of ReadCleanReq miss cycles 1010system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2966913000 # number of ReadSharedReq miss cycles 1011system.cpu.l2cache.ReadSharedReq_miss_latency::total 2966913000 # number of ReadSharedReq miss cycles 1012system.cpu.l2cache.demand_miss_latency::cpu.inst 916670500 # number of demand (read+write) miss cycles 1013system.cpu.l2cache.demand_miss_latency::cpu.data 4155571000 # number of demand (read+write) miss cycles 1014system.cpu.l2cache.demand_miss_latency::total 5072241500 # number of demand (read+write) miss cycles 1015system.cpu.l2cache.overall_miss_latency::cpu.inst 916670500 # number of overall miss cycles 1016system.cpu.l2cache.overall_miss_latency::cpu.data 4155571000 # number of overall miss cycles 1017system.cpu.l2cache.overall_miss_latency::total 5072241500 # number of overall miss cycles 1018system.cpu.l2cache.WritebackDirty_accesses::writebacks 256728 # number of WritebackDirty accesses(hits+misses) 1019system.cpu.l2cache.WritebackDirty_accesses::total 256728 # number of WritebackDirty accesses(hits+misses) 1020system.cpu.l2cache.WritebackClean_accesses::writebacks 471596 # number of WritebackClean accesses(hits+misses) 1021system.cpu.l2cache.WritebackClean_accesses::total 471596 # number of WritebackClean accesses(hits+misses) |
| 1026system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) 1027system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) | 1022system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) 1023system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) |
| 1028system.cpu.l2cache.ReadExReq_accesses::cpu.data 148562 # number of ReadExReq accesses(hits+misses) 1029system.cpu.l2cache.ReadExReq_accesses::total 148562 # number of ReadExReq accesses(hits+misses) 1030system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323617 # number of ReadCleanReq accesses(hits+misses) 1031system.cpu.l2cache.ReadCleanReq_accesses::total 323617 # number of ReadCleanReq accesses(hits+misses) 1032system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336967 # number of ReadSharedReq accesses(hits+misses) 1033system.cpu.l2cache.ReadSharedReq_accesses::total 336967 # number of ReadSharedReq accesses(hits+misses) 1034system.cpu.l2cache.demand_accesses::cpu.inst 323617 # number of demand (read+write) accesses 1035system.cpu.l2cache.demand_accesses::cpu.data 485529 # number of demand (read+write) accesses 1036system.cpu.l2cache.demand_accesses::total 809146 # number of demand (read+write) accesses 1037system.cpu.l2cache.overall_accesses::cpu.inst 323617 # number of overall (read+write) accesses 1038system.cpu.l2cache.overall_accesses::cpu.data 485529 # number of overall (read+write) accesses 1039system.cpu.l2cache.overall_accesses::total 809146 # number of overall (read+write) accesses | 1024system.cpu.l2cache.ReadExReq_accesses::cpu.data 148567 # number of ReadExReq accesses(hits+misses) 1025system.cpu.l2cache.ReadExReq_accesses::total 148567 # number of ReadExReq accesses(hits+misses) 1026system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323640 # number of ReadCleanReq accesses(hits+misses) 1027system.cpu.l2cache.ReadCleanReq_accesses::total 323640 # number of ReadCleanReq accesses(hits+misses) 1028system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336970 # number of ReadSharedReq accesses(hits+misses) 1029system.cpu.l2cache.ReadSharedReq_accesses::total 336970 # number of ReadSharedReq accesses(hits+misses) 1030system.cpu.l2cache.demand_accesses::cpu.inst 323640 # number of demand (read+write) accesses 1031system.cpu.l2cache.demand_accesses::cpu.data 485537 # number of demand (read+write) accesses 1032system.cpu.l2cache.demand_accesses::total 809177 # number of demand (read+write) accesses 1033system.cpu.l2cache.overall_accesses::cpu.inst 323640 # number of overall (read+write) accesses 1034system.cpu.l2cache.overall_accesses::cpu.data 485537 # number of overall (read+write) accesses 1035system.cpu.l2cache.overall_accesses::total 809177 # number of overall (read+write) accesses |
| 1040system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1041system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 1036system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1037system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 1042system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077321 # miss rate for ReadExReq accesses 1043system.cpu.l2cache.ReadExReq_miss_rate::total 0.077321 # miss rate for ReadExReq accesses 1044system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.035666 # miss rate for ReadCleanReq accesses 1045system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.035666 # miss rate for ReadCleanReq accesses 1046system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.108082 # miss rate for ReadSharedReq accesses 1047system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.108082 # miss rate for ReadSharedReq accesses 1048system.cpu.l2cache.demand_miss_rate::cpu.inst 0.035666 # miss rate for demand accesses 1049system.cpu.l2cache.demand_miss_rate::cpu.data 0.098670 # miss rate for demand accesses 1050system.cpu.l2cache.demand_miss_rate::total 0.073471 # miss rate for demand accesses 1051system.cpu.l2cache.overall_miss_rate::cpu.inst 0.035666 # miss rate for overall accesses 1052system.cpu.l2cache.overall_miss_rate::cpu.data 0.098670 # miss rate for overall accesses 1053system.cpu.l2cache.overall_miss_rate::total 0.073471 # miss rate for overall accesses 1054system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103403.978410 # average ReadExReq miss latency 1055system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103403.978410 # average ReadExReq miss latency 1056system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75578.669208 # average ReadCleanReq miss latency 1057system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75578.669208 # average ReadCleanReq miss latency 1058system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82383.347062 # average ReadSharedReq miss latency 1059system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82383.347062 # average ReadSharedReq miss latency 1060system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75578.669208 # average overall miss latency 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87423.612416 # average overall miss latency 1062system.cpu.l2cache.demand_avg_miss_latency::total 85123.921344 # average overall miss latency 1063system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75578.669208 # average overall miss latency 1064system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87423.612416 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::total 85123.921344 # average overall miss latency | 1038system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077642 # miss rate for ReadExReq accesses 1039system.cpu.l2cache.ReadExReq_miss_rate::total 0.077642 # miss rate for ReadExReq accesses 1040system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.037826 # miss rate for ReadCleanReq accesses 1041system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.037826 # miss rate for ReadCleanReq accesses 1042system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.106977 # miss rate for ReadSharedReq accesses 1043system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.106977 # miss rate for ReadSharedReq accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.inst 0.037826 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::cpu.data 0.098001 # miss rate for demand accesses 1046system.cpu.l2cache.demand_miss_rate::total 0.073933 # miss rate for demand accesses 1047system.cpu.l2cache.overall_miss_rate::cpu.inst 0.037826 # miss rate for overall accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.data 0.098001 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::total 0.073933 # miss rate for overall accesses 1050system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103047.941049 # average ReadExReq miss latency 1051system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103047.941049 # average ReadExReq miss latency 1052system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74879.145564 # average ReadCleanReq miss latency 1053system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74879.145564 # average ReadCleanReq miss latency 1054system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82304.510652 # average ReadSharedReq miss latency 1055system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82304.510652 # average ReadSharedReq miss latency 1056system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74879.145564 # average overall miss latency 1057system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87333.102158 # average overall miss latency 1058system.cpu.l2cache.demand_avg_miss_latency::total 84784.646887 # average overall miss latency 1059system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74879.145564 # average overall miss latency 1060system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87333.102158 # average overall miss latency 1061system.cpu.l2cache.overall_avg_miss_latency::total 84784.646887 # average overall miss latency |
| 1066system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1067system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1068system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1069system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1070system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1071system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1072system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1073system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1062system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1063system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1064system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1065system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1066system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1067system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1068system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1069system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1074system.cpu.l2cache.writebacks::writebacks 97338 # number of writebacks 1075system.cpu.l2cache.writebacks::total 97338 # number of writebacks 1076system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3200 # number of ReadExReq MSHR hits 1077system.cpu.l2cache.ReadExReq_mshr_hits::total 3200 # number of ReadExReq MSHR hits 1078system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 27 # number of ReadCleanReq MSHR hits 1079system.cpu.l2cache.ReadCleanReq_mshr_hits::total 27 # number of ReadCleanReq MSHR hits 1080system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 107 # number of ReadSharedReq MSHR hits 1081system.cpu.l2cache.ReadSharedReq_mshr_hits::total 107 # number of ReadSharedReq MSHR hits 1082system.cpu.l2cache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits 1083system.cpu.l2cache.demand_mshr_hits::cpu.data 3307 # number of demand (read+write) MSHR hits 1084system.cpu.l2cache.demand_mshr_hits::total 3334 # number of demand (read+write) MSHR hits 1085system.cpu.l2cache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits 1086system.cpu.l2cache.overall_mshr_hits::cpu.data 3307 # number of overall MSHR hits 1087system.cpu.l2cache.overall_mshr_hits::total 3334 # number of overall MSHR hits 1088system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112837 # number of HardPFReq MSHR misses 1089system.cpu.l2cache.HardPFReq_mshr_misses::total 112837 # number of HardPFReq MSHR misses | 1070system.cpu.l2cache.writebacks::writebacks 97288 # number of writebacks 1071system.cpu.l2cache.writebacks::total 97288 # number of writebacks 1072system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3173 # number of ReadExReq MSHR hits 1073system.cpu.l2cache.ReadExReq_mshr_hits::total 3173 # number of ReadExReq MSHR hits 1074system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 34 # number of ReadCleanReq MSHR hits 1075system.cpu.l2cache.ReadCleanReq_mshr_hits::total 34 # number of ReadCleanReq MSHR hits 1076system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 93 # number of ReadSharedReq MSHR hits 1077system.cpu.l2cache.ReadSharedReq_mshr_hits::total 93 # number of ReadSharedReq MSHR hits 1078system.cpu.l2cache.demand_mshr_hits::cpu.inst 34 # number of demand (read+write) MSHR hits 1079system.cpu.l2cache.demand_mshr_hits::cpu.data 3266 # number of demand (read+write) MSHR hits 1080system.cpu.l2cache.demand_mshr_hits::total 3300 # number of demand (read+write) MSHR hits 1081system.cpu.l2cache.overall_mshr_hits::cpu.inst 34 # number of overall MSHR hits 1082system.cpu.l2cache.overall_mshr_hits::cpu.data 3266 # number of overall MSHR hits 1083system.cpu.l2cache.overall_mshr_hits::total 3300 # number of overall MSHR hits 1084system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112494 # number of HardPFReq MSHR misses 1085system.cpu.l2cache.HardPFReq_mshr_misses::total 112494 # number of HardPFReq MSHR misses |
| 1090system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses 1091system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses | 1086system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses 1087system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses |
| 1092system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8287 # number of ReadExReq MSHR misses 1093system.cpu.l2cache.ReadExReq_mshr_misses::total 8287 # number of ReadExReq MSHR misses 1094system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 11515 # number of ReadCleanReq MSHR misses 1095system.cpu.l2cache.ReadCleanReq_mshr_misses::total 11515 # number of ReadCleanReq MSHR misses 1096system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 36313 # number of ReadSharedReq MSHR misses 1097system.cpu.l2cache.ReadSharedReq_mshr_misses::total 36313 # number of ReadSharedReq MSHR misses 1098system.cpu.l2cache.demand_mshr_misses::cpu.inst 11515 # number of demand (read+write) MSHR misses 1099system.cpu.l2cache.demand_mshr_misses::cpu.data 44600 # number of demand (read+write) MSHR misses 1100system.cpu.l2cache.demand_mshr_misses::total 56115 # number of demand (read+write) MSHR misses 1101system.cpu.l2cache.overall_mshr_misses::cpu.inst 11515 # number of overall MSHR misses 1102system.cpu.l2cache.overall_mshr_misses::cpu.data 44600 # number of overall MSHR misses 1103system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112837 # number of overall MSHR misses 1104system.cpu.l2cache.overall_mshr_misses::total 168952 # number of overall MSHR misses 1105system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10338050198 # number of HardPFReq MSHR miss cycles 1106system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10338050198 # number of HardPFReq MSHR miss cycles 1107system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 173000 # number of UpgradeReq MSHR miss cycles 1108system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 173000 # number of UpgradeReq MSHR miss cycles 1109system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 653811000 # number of ReadExReq MSHR miss cycles 1110system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 653811000 # number of ReadExReq MSHR miss cycles 1111system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 801316000 # number of ReadCleanReq MSHR miss cycles 1112system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 801316000 # number of ReadCleanReq MSHR miss cycles 1113system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2775072500 # number of ReadSharedReq MSHR miss cycles 1114system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2775072500 # number of ReadSharedReq MSHR miss cycles 1115system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 801316000 # number of demand (read+write) MSHR miss cycles 1116system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3428883500 # number of demand (read+write) MSHR miss cycles 1117system.cpu.l2cache.demand_mshr_miss_latency::total 4230199500 # number of demand (read+write) MSHR miss cycles 1118system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 801316000 # number of overall MSHR miss cycles 1119system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3428883500 # number of overall MSHR miss cycles 1120system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10338050198 # number of overall MSHR miss cycles 1121system.cpu.l2cache.overall_mshr_miss_latency::total 14568249698 # number of overall MSHR miss cycles | 1088system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8362 # number of ReadExReq MSHR misses 1089system.cpu.l2cache.ReadExReq_mshr_misses::total 8362 # number of ReadExReq MSHR misses 1090system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12208 # number of ReadCleanReq MSHR misses 1091system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12208 # number of ReadCleanReq MSHR misses 1092system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35955 # number of ReadSharedReq MSHR misses 1093system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35955 # number of ReadSharedReq MSHR misses 1094system.cpu.l2cache.demand_mshr_misses::cpu.inst 12208 # number of demand (read+write) MSHR misses 1095system.cpu.l2cache.demand_mshr_misses::cpu.data 44317 # number of demand (read+write) MSHR misses 1096system.cpu.l2cache.demand_mshr_misses::total 56525 # number of demand (read+write) MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::cpu.inst 12208 # number of overall MSHR misses 1098system.cpu.l2cache.overall_mshr_misses::cpu.data 44317 # number of overall MSHR misses 1099system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112494 # number of overall MSHR misses 1100system.cpu.l2cache.overall_mshr_misses::total 169019 # number of overall MSHR misses 1101system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10322993748 # number of HardPFReq MSHR miss cycles 1102system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10322993748 # number of HardPFReq MSHR miss cycles 1103system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 147000 # number of UpgradeReq MSHR miss cycles 1104system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 147000 # number of UpgradeReq MSHR miss cycles 1105system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 658062000 # number of ReadExReq MSHR miss cycles 1106system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 658062000 # number of ReadExReq MSHR miss cycles 1107system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 841432500 # number of ReadCleanReq MSHR miss cycles 1108system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 841432500 # number of ReadCleanReq MSHR miss cycles 1109system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2745124500 # number of ReadSharedReq MSHR miss cycles 1110system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2745124500 # number of ReadSharedReq MSHR miss cycles 1111system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 841432500 # number of demand (read+write) MSHR miss cycles 1112system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3403186500 # number of demand (read+write) MSHR miss cycles 1113system.cpu.l2cache.demand_mshr_miss_latency::total 4244619000 # number of demand (read+write) MSHR miss cycles 1114system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 841432500 # number of overall MSHR miss cycles 1115system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3403186500 # number of overall MSHR miss cycles 1116system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10322993748 # number of overall MSHR miss cycles 1117system.cpu.l2cache.overall_mshr_miss_latency::total 14567612748 # number of overall MSHR miss cycles |
| 1122system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1123system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1124system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1125system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 1118system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1119system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1120system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1121system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 1126system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055781 # mshr miss rate for ReadExReq accesses 1127system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055781 # mshr miss rate for ReadExReq accesses 1128system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for ReadCleanReq accesses 1129system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.035582 # mshr miss rate for ReadCleanReq accesses 1130system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.107764 # mshr miss rate for ReadSharedReq accesses 1131system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.107764 # mshr miss rate for ReadSharedReq accesses 1132system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for demand accesses 1133system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for demand accesses 1134system.cpu.l2cache.demand_mshr_miss_rate::total 0.069351 # mshr miss rate for demand accesses 1135system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for overall accesses 1136system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for overall accesses | 1122system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056284 # mshr miss rate for ReadExReq accesses 1123system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056284 # mshr miss rate for ReadExReq accesses 1124system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for ReadCleanReq accesses 1125system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037721 # mshr miss rate for ReadCleanReq accesses 1126system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.106701 # mshr miss rate for ReadSharedReq accesses 1127system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.106701 # mshr miss rate for ReadSharedReq accesses 1128system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for demand accesses 1129system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for demand accesses 1130system.cpu.l2cache.demand_mshr_miss_rate::total 0.069855 # mshr miss rate for demand accesses 1131system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for overall accesses 1132system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for overall accesses |
| 1137system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1133system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1138system.cpu.l2cache.overall_mshr_miss_rate::total 0.208803 # mshr miss rate for overall accesses 1139system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average HardPFReq mshr miss latency 1140system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91619.328749 # average HardPFReq mshr miss latency 1141system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17300 # average UpgradeReq mshr miss latency 1142system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300 # average UpgradeReq mshr miss latency 1143system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78895.981658 # average ReadExReq mshr miss latency 1144system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78895.981658 # average ReadExReq mshr miss latency 1145system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69588.884064 # average ReadCleanReq mshr miss latency 1146system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69588.884064 # average ReadCleanReq mshr miss latency 1147system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76420.909867 # average ReadSharedReq mshr miss latency 1148system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76420.909867 # average ReadSharedReq mshr miss latency 1149system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency 1150system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency 1151system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75384.469393 # average overall mshr miss latency 1152system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency 1153system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency 1154system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average overall mshr miss latency 1155system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86227.151487 # average overall mshr miss latency | 1134system.cpu.l2cache.overall_mshr_miss_rate::total 0.208878 # mshr miss rate for overall accesses 1135system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average HardPFReq mshr miss latency 1136system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91764.838551 # average HardPFReq mshr miss latency 1137system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700 # average UpgradeReq mshr miss latency 1138system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700 # average UpgradeReq mshr miss latency 1139system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78696.723272 # average ReadExReq mshr miss latency 1140system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78696.723272 # average ReadExReq mshr miss latency 1141system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68924.680537 # average ReadCleanReq mshr miss latency 1142system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68924.680537 # average ReadCleanReq mshr miss latency 1143system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76348.894451 # average ReadSharedReq mshr miss latency 1144system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76348.894451 # average ReadSharedReq mshr miss latency 1145system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency 1146system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency 1147system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75092.773109 # average overall mshr miss latency 1148system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average overall mshr miss latency 1151system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86189.202090 # average overall mshr miss latency |
| 1156system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1152system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1157system.cpu.toL2Bus.snoop_filter.tot_requests 1617289 # Total number of requests made to the snoop filter. 1158system.cpu.toL2Bus.snoop_filter.hit_single_requests 808162 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1159system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79873 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1160system.cpu.toL2Bus.snoop_filter.tot_snoops 67046 # Total number of snoops made to the snoop filter. 1161system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1162system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10433 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1163system.cpu.toL2Bus.trans_dist::ReadResp 660594 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::WritebackDirty 350764 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::WritebackClean 474834 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::CleanEvict 78545 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::HardPFReq 142478 # Transaction distribution | 1153system.cpu.toL2Bus.snoop_filter.tot_requests 1617353 # Total number of requests made to the snoop filter. 1154system.cpu.toL2Bus.snoop_filter.hit_single_requests 808194 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1155system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79842 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1156system.cpu.toL2Bus.snoop_filter.tot_snoops 67170 # Total number of snoops made to the snoop filter. 1157system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56578 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1158system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10592 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1159system.cpu.toL2Bus.trans_dist::ReadResp 660621 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::WritebackDirty 354016 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::WritebackClean 551426 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::CleanEvict 79011 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::HardPFReq 142034 # Transaction distribution |
| 1168system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution | 1164system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution |
| 1170system.cpu.toL2Bus.trans_dist::ReadExReq 148562 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::ReadExResp 148562 # Transaction distribution 1172system.cpu.toL2Bus.trans_dist::ReadCleanReq 323628 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::ReadSharedReq 336967 # Transaction distribution 1174system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 939793 # Packet count per connected master and slave (bytes) 1175system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406789 # Packet count per connected master and slave (bytes) 1176system.cpu.toL2Bus.pkt_count::total 2346582 # Packet count per connected master and slave (bytes) 1177system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39434560 # Cumulative packet size per connected master and slave (bytes) 1178system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 58959360 # Cumulative packet size per connected master and slave (bytes) 1179system.cpu.toL2Bus.pkt_size::total 98393920 # Cumulative packet size per connected master and slave (bytes) 1180system.cpu.toL2Bus.snoops 318372 # Total snoops (count) 1181system.cpu.toL2Bus.snoop_fanout::samples 1127528 # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::mean 0.139590 # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::stdev 0.372305 # Request fanout histogram | 1166system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::ReadCleanReq 323652 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::ReadSharedReq 336970 # Transaction distribution 1170system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 970420 # Packet count per connected master and slave (bytes) 1171system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1456119 # Packet count per connected master and slave (bytes) 1172system.cpu.toL2Bus.pkt_count::total 2426539 # Packet count per connected master and slave (bytes) 1173system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41393152 # Cumulative packet size per connected master and slave (bytes) 1174system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62115968 # Cumulative packet size per connected master and slave (bytes) 1175system.cpu.toL2Bus.pkt_size::total 103509120 # Cumulative packet size per connected master and slave (bytes) 1176system.cpu.toL2Bus.snoops 318345 # Total snoops (count) 1177system.cpu.toL2Bus.snoop_fanout::samples 1127532 # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::mean 0.139813 # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::stdev 0.372899 # Request fanout histogram |
| 1184system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1180system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1185system.cpu.toL2Bus.snoop_fanout::0 980569 86.97% 86.97% # Request fanout histogram 1186system.cpu.toL2Bus.snoop_fanout::1 136526 12.11% 99.07% # Request fanout histogram 1187system.cpu.toL2Bus.snoop_fanout::2 10433 0.93% 100.00% # Request fanout histogram | 1181system.cpu.toL2Bus.snoop_fanout::0 980480 86.96% 86.96% # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::1 136460 12.10% 99.06% # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::2 10592 0.94% 100.00% # Request fanout histogram |
| 1188system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1189system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1190system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1184system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1185system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1186system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1191system.cpu.toL2Bus.snoop_fanout::total 1127528 # Request fanout histogram 1192system.cpu.toL2Bus.reqLayer0.occupancy 1616766500 # Layer occupancy (ticks) | 1187system.cpu.toL2Bus.snoop_fanout::total 1127532 # Request fanout histogram 1188system.cpu.toL2Bus.reqLayer0.occupancy 1616830500 # Layer occupancy (ticks) |
| 1193system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) | 1189system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) |
| 1194system.cpu.toL2Bus.respLayer0.occupancy 485882115 # Layer occupancy (ticks) | 1190system.cpu.toL2Bus.respLayer0.occupancy 485918614 # Layer occupancy (ticks) |
| 1195system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) | 1191system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) |
| 1196system.cpu.toL2Bus.respLayer1.occupancy 728582930 # Layer occupancy (ticks) | 1192system.cpu.toL2Bus.respLayer1.occupancy 728566986 # Layer occupancy (ticks) |
| 1197system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) | 1193system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) |
| 1198system.membus.trans_dist::ReadResp 144336 # Transaction distribution 1199system.membus.trans_dist::WritebackDirty 97338 # Transaction distribution 1200system.membus.trans_dist::CleanEvict 27827 # Transaction distribution | 1194system.membus.trans_dist::ReadResp 144525 # Transaction distribution 1195system.membus.trans_dist::WritebackDirty 97288 # Transaction distribution 1196system.membus.trans_dist::CleanEvict 27973 # Transaction distribution |
| 1201system.membus.trans_dist::UpgradeReq 10 # Transaction distribution | 1197system.membus.trans_dist::UpgradeReq 10 # Transaction distribution |
| 1202system.membus.trans_dist::UpgradeResp 10 # Transaction distribution 1203system.membus.trans_dist::ReadExReq 8287 # Transaction distribution 1204system.membus.trans_dist::ReadExResp 8287 # Transaction distribution 1205system.membus.trans_dist::ReadSharedReq 144337 # Transaction distribution 1206system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 430432 # Packet count per connected master and slave (bytes) 1207system.membus.pkt_count::total 430432 # Packet count per connected master and slave (bytes) 1208system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15997504 # Cumulative packet size per connected master and slave (bytes) 1209system.membus.pkt_size::total 15997504 # Cumulative packet size per connected master and slave (bytes) | 1198system.membus.trans_dist::ReadExReq 8362 # Transaction distribution 1199system.membus.trans_dist::ReadExResp 8362 # Transaction distribution 1200system.membus.trans_dist::ReadSharedReq 144526 # Transaction distribution 1201system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431046 # Packet count per connected master and slave (bytes) 1202system.membus.pkt_count::total 431046 # Packet count per connected master and slave (bytes) 1203system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16011200 # Cumulative packet size per connected master and slave (bytes) 1204system.membus.pkt_size::total 16011200 # Cumulative packet size per connected master and slave (bytes) |
| 1210system.membus.snoops 0 # Total snoops (count) | 1205system.membus.snoops 0 # Total snoops (count) |
| 1211system.membus.snoop_fanout::samples 277799 # Request fanout histogram | 1206system.membus.snoop_fanout::samples 278159 # Request fanout histogram |
| 1212system.membus.snoop_fanout::mean 0 # Request fanout histogram 1213system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1214system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1207system.membus.snoop_fanout::mean 0 # Request fanout histogram 1208system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1209system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1215system.membus.snoop_fanout::0 277799 100.00% 100.00% # Request fanout histogram | 1210system.membus.snoop_fanout::0 278159 100.00% 100.00% # Request fanout histogram |
| 1216system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1217system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1218system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1219system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1211system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1212system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1213system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1214system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1220system.membus.snoop_fanout::total 277799 # Request fanout histogram 1221system.membus.reqLayer0.occupancy 747949896 # Layer occupancy (ticks) | 1215system.membus.snoop_fanout::total 278159 # Request fanout histogram 1216system.membus.reqLayer0.occupancy 748401121 # Layer occupancy (ticks) |
| 1222system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) | 1217system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) |
| 1223system.membus.respLayer1.occupancy 797228853 # Layer occupancy (ticks) | 1218system.membus.respLayer1.occupancy 798557507 # Layer occupancy (ticks) |
| 1224system.membus.respLayer1.utilization 2.4 # Layer utilization (%) 1225 1226---------- End Simulation Statistics ---------- | 1219system.membus.respLayer1.utilization 2.4 # Layer utilization (%) 1220 1221---------- End Simulation Statistics ---------- |