| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.033359 # Number of seconds simulated 4sim_ticks 33359312000 # Number of ticks simulated 5final_tick 33359312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 125450 # Simulator instruction rate (inst/s) 8host_op_rate 160435 # Simulator op (including micro ops) rate (op/s) --- 673 unchanged lines hidden (view full) --- 682system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 684system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 685system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 687system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 688system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction 689system.cpu.commit.bw_lim_events 3769965 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.033359 # Number of seconds simulated 4sim_ticks 33359312000 # Number of ticks simulated 5final_tick 33359312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 125450 # Simulator instruction rate (inst/s) 8host_op_rate 160435 # Simulator op (including micro ops) rate (op/s) --- 673 unchanged lines hidden (view full) --- 682system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 684system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 685system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 687system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 688system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction 689system.cpu.commit.bw_lim_events 3769965 # number cycles where commit BW limit reached |
| 690system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 691system.cpu.rob.rob_reads 158240550 # The number of ROB reads 692system.cpu.rob.rob_writes 195514428 # The number of ROB writes 693system.cpu.timesIdled 23835 # Number of times that the entire CPU went into an idle state and unscheduled itself 694system.cpu.idleCycles 850743 # Total number of cycles that the CPU has spent unscheduled due to idling 695system.cpu.committedInsts 70907629 # Number of Instructions Simulated 696system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated 697system.cpu.cpi 0.940923 # CPI: Cycles Per Instruction 698system.cpu.cpi_total 0.940923 # CPI: Total CPI of All Threads --- 513 unchanged lines hidden --- | 690system.cpu.rob.rob_reads 158240550 # The number of ROB reads 691system.cpu.rob.rob_writes 195514428 # The number of ROB writes 692system.cpu.timesIdled 23835 # Number of times that the entire CPU went into an idle state and unscheduled itself 693system.cpu.idleCycles 850743 # Total number of cycles that the CPU has spent unscheduled due to idling 694system.cpu.committedInsts 70907629 # Number of Instructions Simulated 695system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated 696system.cpu.cpi 0.940923 # CPI: Cycles Per Instruction 697system.cpu.cpi_total 0.940923 # CPI: Total CPI of All Threads --- 513 unchanged lines hidden --- |