| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.023896 # Number of seconds simulated 4sim_ticks 23896420500 # Number of ticks simulated 5final_tick 23896420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.032615 # Number of seconds simulated 4sim_ticks 32615215000 # Number of ticks simulated 5final_tick 32615215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 105740 # Simulator instruction rate (inst/s) 8host_op_rate 135229 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 35635051 # Simulator tick rate (ticks/s) 10host_mem_usage 262840 # Number of bytes of host memory used 11host_seconds 670.59 # Real time elapsed on the host | 7host_inst_rate 86014 # Simulator instruction rate (inst/s) 8host_op_rate 110001 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39563517 # Simulator tick rate (ticks/s) 10host_mem_usage 333060 # Number of bytes of host memory used 11host_seconds 824.38 # Real time elapsed on the host |
| 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 90682584 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 90682584 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 299392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7936704 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8236096 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 299392 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 299392 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4678 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 124011 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128689 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 12528738 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 332129408 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 344658147 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 12528738 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 12528738 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 224837021 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 224837021 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 224837021 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 12528738 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 332129408 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 569495168 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 128689 # Number of read requests accepted 40system.physmem.writeReqs 83950 # Number of write requests accepted 41system.physmem.readBursts 128689 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 8235648 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue 45system.physmem.bytesWritten 5371072 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 8236096 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 133120 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2337984 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 7506432 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9977536 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 133120 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 133120 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6303424 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6303424 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2080 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 36531 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 117288 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 155899 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 98491 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 98491 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 4081531 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 71683844 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 230151235 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 305916610 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 4081531 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 4081531 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 193266364 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 193266364 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 193266364 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 4081531 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 71683844 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 230151235 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 499182973 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 155899 # Number of read requests accepted 44system.physmem.writeReqs 98491 # Number of write requests accepted 45system.physmem.readBursts 155899 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 98491 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 9968640 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue 49system.physmem.bytesWritten 6301696 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 9977536 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 6303424 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 50system.physmem.neitherReadNorWriteReqs 380 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8141 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8384 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8239 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8150 # Per bank write bursts 55system.physmem.perBankRdBursts::4 8295 # Per bank write bursts 56system.physmem.perBankRdBursts::5 8428 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8074 # Per bank write bursts 58system.physmem.perBankRdBursts::7 7958 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8067 # Per bank write bursts 60system.physmem.perBankRdBursts::9 7598 # Per bank write bursts 61system.physmem.perBankRdBursts::10 7783 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7813 # Per bank write bursts 63system.physmem.perBankRdBursts::12 7877 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7881 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7983 # Per bank write bursts 66system.physmem.perBankRdBursts::15 8011 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5183 # Per bank write bursts 68system.physmem.perBankWrBursts::1 5376 # Per bank write bursts 69system.physmem.perBankWrBursts::2 5289 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5157 # Per bank write bursts 71system.physmem.perBankWrBursts::4 5266 # Per bank write bursts 72system.physmem.perBankWrBursts::5 5517 # Per bank write bursts 73system.physmem.perBankWrBursts::6 5198 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5051 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5029 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5090 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5246 # Per bank write bursts 78system.physmem.perBankWrBursts::11 5140 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5343 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5452 # Per bank write bursts 82system.physmem.perBankWrBursts::15 5223 # Per bank write bursts | 54system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 10106 # Per bank write bursts 56system.physmem.perBankRdBursts::1 10077 # Per bank write bursts 57system.physmem.perBankRdBursts::2 9750 # Per bank write bursts 58system.physmem.perBankRdBursts::3 10345 # Per bank write bursts 59system.physmem.perBankRdBursts::4 10619 # Per bank write bursts 60system.physmem.perBankRdBursts::5 10733 # Per bank write bursts 61system.physmem.perBankRdBursts::6 9548 # Per bank write bursts 62system.physmem.perBankRdBursts::7 9567 # Per bank write bursts 63system.physmem.perBankRdBursts::8 9971 # Per bank write bursts 64system.physmem.perBankRdBursts::9 9445 # Per bank write bursts 65system.physmem.perBankRdBursts::10 9639 # Per bank write bursts 66system.physmem.perBankRdBursts::11 9476 # Per bank write bursts 67system.physmem.perBankRdBursts::12 8930 # Per bank write bursts 68system.physmem.perBankRdBursts::13 9084 # Per bank write bursts 69system.physmem.perBankRdBursts::14 9062 # Per bank write bursts 70system.physmem.perBankRdBursts::15 9408 # Per bank write bursts 71system.physmem.perBankWrBursts::0 6017 # Per bank write bursts 72system.physmem.perBankWrBursts::1 6275 # Per bank write bursts 73system.physmem.perBankWrBursts::2 6171 # Per bank write bursts 74system.physmem.perBankWrBursts::3 6231 # Per bank write bursts 75system.physmem.perBankWrBursts::4 6142 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6389 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6054 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6025 # Per bank write bursts 79system.physmem.perBankWrBursts::8 6057 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6227 # Per bank write bursts 81system.physmem.perBankWrBursts::10 6350 # Per bank write bursts 82system.physmem.perBankWrBursts::11 5949 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6129 # Per bank write bursts 84system.physmem.perBankWrBursts::13 6148 # Per bank write bursts 85system.physmem.perBankWrBursts::14 6212 # Per bank write bursts 86system.physmem.perBankWrBursts::15 6088 # Per bank write bursts |
| 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 23896016500 # Total gap between requests | 89system.physmem.totGap 32615126500 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 128689 # Read request sizes (log2) | 96system.physmem.readPktSize::6 155899 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 99system.physmem.writePktSize::6 83950 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 68784 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 50927 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 6546 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 2414 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 98491 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 46242 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 51007 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 19397 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 10907 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 7160 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 6108 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 5351 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4799 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 4082 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 329 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 161 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 51 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 32 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 22 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 12 # What read queue length does an incoming req see |
| 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 2057 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 3691 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4468 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 4948 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5202 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5301 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5438 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5521 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5545 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5656 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 6068 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5800 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 6220 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5413 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see | 151system.physmem.wrQLenPdf::15 1248 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1291 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1960 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 2723 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 3606 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4588 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5698 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5990 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 6308 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 6755 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 7385 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8090 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8877 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 7957 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 7389 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6799 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6302 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 59 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see |
| 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 37607 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 361.810089 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 217.183531 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 344.455844 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 11970 31.83% 31.83% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 7877 20.95% 52.77% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 3759 10.00% 62.77% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2606 6.93% 69.70% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2473 6.58% 76.28% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1554 4.13% 80.41% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1216 3.23% 83.64% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1043 2.77% 86.41% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 5109 13.59% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 37607 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5143 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 25.009139 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 391.762417 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5141 99.96% 99.96% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5143 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5143 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 16.317908 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 16.294258 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.943897 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 4493 87.36% 87.36% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 13 0.25% 87.61% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 424 8.24% 95.86% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 146 2.84% 98.70% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20 43 0.84% 99.53% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::21 15 0.29% 99.83% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::22 3 0.06% 99.88% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::23 1 0.02% 99.90% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::27 1 0.02% 99.94% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::28 1 0.02% 99.96% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::32 2 0.04% 100.00% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::total 5143 # Writes before turning the bus around for reads 234system.physmem.totQLat 2744774250 # Total ticks spent queuing 235system.physmem.totMemAccLat 5157561750 # Total ticks spent from burst creation until serviced by the DRAM 236system.physmem.totBusLat 643410000 # Total ticks spent in databus transfers 237system.physmem.avgQLat 21329.90 # Average queueing delay per DRAM burst | 200system.physmem.bytesPerActivate::samples 91367 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 178.055709 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 111.660605 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 241.201750 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 53557 58.62% 58.62% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 22743 24.89% 83.51% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4730 5.18% 88.69% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1990 2.18% 90.86% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1303 1.43% 92.29% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 874 0.96% 93.25% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 818 0.90% 94.14% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 792 0.87% 95.01% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 4560 4.99% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 91367 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5918 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 26.315816 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 22.639360 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 186.500180 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 5917 99.98% 99.98% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 5918 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 5918 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 16.638053 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 16.588323 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 1.367969 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16 4586 77.49% 77.49% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::17 35 0.59% 78.08% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18 770 13.01% 91.09% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::19 230 3.89% 94.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::20 141 2.38% 97.36% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::21 69 1.17% 98.53% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::22 46 0.78% 99.31% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::23 20 0.34% 99.65% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::24 12 0.20% 99.85% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::25 3 0.05% 99.90% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::26 5 0.08% 99.98% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 5918 # Writes before turning the bus around for reads 238system.physmem.totQLat 7435933847 # Total ticks spent queuing 239system.physmem.totMemAccLat 10356433847 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 778800000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 47739.69 # Average queueing delay per DRAM burst |
| 238system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 239system.physmem.avgMemAccLat 40079.90 # Average memory access latency per DRAM burst 240system.physmem.avgRdBW 344.64 # Average DRAM read bandwidth in MiByte/s 241system.physmem.avgWrBW 224.76 # Average achieved write bandwidth in MiByte/s 242system.physmem.avgRdBWSys 344.66 # Average system read bandwidth in MiByte/s 243system.physmem.avgWrBWSys 224.84 # Average system write bandwidth in MiByte/s | 243system.physmem.avgMemAccLat 66489.69 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 305.64 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 193.21 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 305.92 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 193.27 # Average system write bandwidth in MiByte/s |
| 244system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 245system.physmem.busUtil 4.45 # Data bus utilization in percentage 246system.physmem.busUtilRead 2.69 # Data bus utilization in percentage for reads 247system.physmem.busUtilWrite 1.76 # Data bus utilization in percentage for writes 248system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing 249system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing 250system.physmem.readRowHits 112874 # Number of row buffer hits during reads 251system.physmem.writeRowHits 62123 # Number of row buffer hits during writes 252system.physmem.readRowHitRate 87.72 # Row buffer hit rate for reads 253system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes 254system.physmem.avgGap 112378.33 # Average gap between requests 255system.physmem.pageHitRate 82.30 # Row buffer hit rate, read and write combined 256system.physmem.memoryStateTime::IDLE 9567571500 # Time in different power states 257system.physmem.memoryStateTime::REF 797940000 # Time in different power states | 249system.physmem.busUtil 3.90 # Data bus utilization in percentage 250system.physmem.busUtilRead 2.39 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 1.51 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing 254system.physmem.readRowHits 126861 # Number of row buffer hits during reads 255system.physmem.writeRowHits 35985 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 81.45 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 36.54 # Row buffer hit rate for writes 258system.physmem.avgGap 128209.15 # Average gap between requests 259system.physmem.pageHitRate 64.05 # Row buffer hit rate, read and write combined 260system.physmem.memoryStateTime::IDLE 11335868113 # Time in different power states 261system.physmem.memoryStateTime::REF 1088880000 # Time in different power states |
| 258system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 262system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 259system.physmem.memoryStateTime::ACT 13530763500 # Time in different power states | 263system.physmem.memoryStateTime::ACT 20184340637 # Time in different power states |
| 260system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 264system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 261system.membus.throughput 569495168 # Throughput (bytes/s) 262system.membus.trans_dist::ReadReq 26431 # Transaction distribution 263system.membus.trans_dist::ReadResp 26431 # Transaction distribution 264system.membus.trans_dist::Writeback 83950 # Transaction distribution 265system.membus.trans_dist::UpgradeReq 380 # Transaction distribution 266system.membus.trans_dist::UpgradeResp 380 # Transaction distribution 267system.membus.trans_dist::ReadExReq 102258 # Transaction distribution 268system.membus.trans_dist::ReadExResp 102258 # Transaction distribution 269system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342088 # Packet count per connected master and slave (bytes) 270system.membus.pkt_count::total 342088 # Packet count per connected master and slave (bytes) 271system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13608896 # Cumulative packet size per connected master and slave (bytes) 272system.membus.tot_pkt_size::total 13608896 # Cumulative packet size per connected master and slave (bytes) 273system.membus.data_through_bus 13608896 # Total data (bytes) 274system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 275system.membus.reqLayer0.occupancy 898146000 # Layer occupancy (ticks) 276system.membus.reqLayer0.utilization 3.8 # Layer utilization (%) 277system.membus.respLayer1.occupancy 1183170872 # Layer occupancy (ticks) 278system.membus.respLayer1.utilization 5.0 # Layer utilization (%) | 265system.membus.trans_dist::ReadReq 149976 # Transaction distribution 266system.membus.trans_dist::ReadResp 149976 # Transaction distribution 267system.membus.trans_dist::Writeback 98491 # Transaction distribution 268system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 269system.membus.trans_dist::UpgradeResp 6 # Transaction distribution 270system.membus.trans_dist::ReadExReq 5923 # Transaction distribution 271system.membus.trans_dist::ReadExResp 5923 # Transaction distribution 272system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 410301 # Packet count per connected master and slave (bytes) 273system.membus.pkt_count::total 410301 # Packet count per connected master and slave (bytes) 274system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16280960 # Cumulative packet size per connected master and slave (bytes) 275system.membus.pkt_size::total 16280960 # Cumulative packet size per connected master and slave (bytes) 276system.membus.snoops 0 # Total snoops (count) 277system.membus.snoop_fanout::samples 254396 # Request fanout histogram 278system.membus.snoop_fanout::mean 0 # Request fanout histogram 279system.membus.snoop_fanout::stdev 0 # Request fanout histogram 280system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 281system.membus.snoop_fanout::0 254396 100.00% 100.00% # Request fanout histogram 282system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 283system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 284system.membus.snoop_fanout::min_value 0 # Request fanout histogram 285system.membus.snoop_fanout::max_value 0 # Request fanout histogram 286system.membus.snoop_fanout::total 254396 # Request fanout histogram 287system.membus.reqLayer0.occupancy 1082237025 # Layer occupancy (ticks) 288system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) 289system.membus.respLayer1.occupancy 1431940683 # Layer occupancy (ticks) 290system.membus.respLayer1.utilization 4.4 # Layer utilization (%) |
| 279system.cpu_clk_domain.clock 500 # Clock period in ticks | 291system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 280system.cpu.branchPred.lookups 17877019 # Number of BP lookups 281system.cpu.branchPred.condPredicted 11927811 # Number of conditional branches predicted 282system.cpu.branchPred.condIncorrect 593439 # Number of conditional branches incorrect 283system.cpu.branchPred.BTBLookups 11204319 # Number of BTB lookups 284system.cpu.branchPred.BTBHits 8313088 # Number of BTB hits | 292system.cpu.branchPred.lookups 17209876 # Number of BP lookups 293system.cpu.branchPred.condPredicted 11519021 # Number of conditional branches predicted 294system.cpu.branchPred.condIncorrect 648079 # Number of conditional branches incorrect 295system.cpu.branchPred.BTBLookups 9339439 # Number of BTB lookups 296system.cpu.branchPred.BTBHits 7675638 # Number of BTB hits |
| 285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 297system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 286system.cpu.branchPred.BTBHitPct 74.195388 # BTB Hit Percentage 287system.cpu.branchPred.usedRAS 1978187 # Number of times the RAS was used to get a target. 288system.cpu.branchPred.RASInCorrect 104069 # Number of incorrect RAS predictions. | 298system.cpu.branchPred.BTBHitPct 82.185215 # BTB Hit Percentage 299system.cpu.branchPred.usedRAS 1872557 # Number of times the RAS was used to get a target. 300system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions. |
| 289system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 290system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 291system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 292system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 293system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 294system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 295system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 296system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 366system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 367system.cpu.itb.read_accesses 0 # DTB read accesses 368system.cpu.itb.write_accesses 0 # DTB write accesses 369system.cpu.itb.inst_accesses 0 # ITB inst accesses 370system.cpu.itb.hits 0 # DTB hits 371system.cpu.itb.misses 0 # DTB misses 372system.cpu.itb.accesses 0 # DTB accesses 373system.cpu.workload.num_syscalls 1946 # Number of system calls | 301system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 302system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 303system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 304system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 305system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 306system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 307system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 308system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 378system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 379system.cpu.itb.read_accesses 0 # DTB read accesses 380system.cpu.itb.write_accesses 0 # DTB write accesses 381system.cpu.itb.inst_accesses 0 # ITB inst accesses 382system.cpu.itb.hits 0 # DTB hits 383system.cpu.itb.misses 0 # DTB misses 384system.cpu.itb.accesses 0 # DTB accesses 385system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 374system.cpu.numCycles 47792842 # number of cpu cycles simulated | 386system.cpu.numCycles 65230431 # number of cpu cycles simulated |
| 375system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 376system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 387system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 388system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 377system.cpu.fetch.icacheStallCycles 13399730 # Number of cycles fetch is stalled on an Icache miss 378system.cpu.fetch.Insts 91818563 # Number of instructions fetch has processed 379system.cpu.fetch.Branches 17877019 # Number of branches that fetch encountered 380system.cpu.fetch.predictedBranches 10291275 # Number of branches that fetch has predicted taken 381system.cpu.fetch.Cycles 33374868 # Number of cycles fetch has run and was not squashing or blocked 382system.cpu.fetch.SquashCycles 1293258 # Number of cycles fetch has spent squashing 383system.cpu.fetch.MiscStallCycles 460 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 384system.cpu.fetch.PendingTrapStallCycles 3119 # Number of stall cycles due to pending traps 385system.cpu.fetch.IcacheWaitRetryStallCycles 70 # Number of stall cycles due to full MSHR 386system.cpu.fetch.CacheLines 12485707 # Number of cache lines fetched 387system.cpu.fetch.IcacheSquashes 222370 # Number of outstanding Icache misses that were squashed 388system.cpu.fetch.rateDist::samples 47424876 # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::mean 2.444936 # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::stdev 3.221090 # Number of instructions fetched each cycle (Total) | 389system.cpu.fetch.icacheStallCycles 4923591 # Number of cycles fetch is stalled on an Icache miss 390system.cpu.fetch.Insts 88199449 # Number of instructions fetch has processed 391system.cpu.fetch.Branches 17209876 # Number of branches that fetch encountered 392system.cpu.fetch.predictedBranches 9548195 # Number of branches that fetch has predicted taken 393system.cpu.fetch.Cycles 59293355 # Number of cycles fetch has run and was not squashing or blocked 394system.cpu.fetch.SquashCycles 1322460 # Number of cycles fetch has spent squashing 395system.cpu.fetch.MiscStallCycles 1971 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 396system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps 397system.cpu.fetch.IcacheWaitRetryStallCycles 4935 # Number of stall cycles due to full MSHR 398system.cpu.fetch.CacheLines 22763618 # Number of cache lines fetched 399system.cpu.fetch.IcacheSquashes 68177 # Number of outstanding Icache misses that were squashed 400system.cpu.fetch.rateDist::samples 64885124 # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::mean 1.720232 # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::stdev 1.289546 # Number of instructions fetched each cycle (Total) |
| 391system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 403system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 392system.cpu.fetch.rateDist::0 25840907 54.49% 54.49% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::1 2398343 5.06% 59.55% # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::2 2102611 4.43% 63.98% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::3 2392037 5.04% 69.02% # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::4 1862029 3.93% 72.95% # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::5 1496992 3.16% 76.11% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::6 1004992 2.12% 78.22% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::7 1407650 2.97% 81.19% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::8 8919315 18.81% 100.00% # Number of instructions fetched each cycle (Total) | 404system.cpu.fetch.rateDist::0 19096390 29.43% 29.43% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::1 8276176 12.76% 42.19% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::2 9196383 14.17% 56.36% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::3 28316175 43.64% 100.00% # Number of instructions fetched each cycle (Total) |
| 401system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) | 408system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) |
| 403system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::total 47424876 # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.branchRate 0.374052 # Number of branch fetches per cycle 406system.cpu.fetch.rate 1.921178 # Number of inst fetches per cycle 407system.cpu.decode.IdleCycles 9991238 # Number of cycles decode is idle 408system.cpu.decode.BlockedCycles 18372924 # Number of cycles decode is blocked 409system.cpu.decode.RunCycles 15962018 # Number of cycles decode is running 410system.cpu.decode.UnblockCycles 2553700 # Number of cycles decode is unblocking 411system.cpu.decode.SquashCycles 544996 # Number of cycles decode is squashing 412system.cpu.decode.BranchResolved 3514191 # Number of times decode resolved a branch 413system.cpu.decode.BranchMispred 104008 # Number of times decode detected a branch misprediction 414system.cpu.decode.DecodedInsts 110994138 # Number of instructions handled by decode 415system.cpu.decode.SquashedInsts 375319 # Number of squashed instructions handled by decode 416system.cpu.rename.SquashCycles 544996 # Number of cycles rename is squashing 417system.cpu.rename.IdleCycles 11354333 # Number of cycles rename is idle 418system.cpu.rename.BlockCycles 2895918 # Number of cycles rename is blocking 419system.cpu.rename.serializeStallCycles 1063087 # count of cycles rename stalled for serializing inst 420system.cpu.rename.RunCycles 17104266 # Number of cycles rename is running 421system.cpu.rename.UnblockCycles 14462276 # Number of cycles rename is unblocking 422system.cpu.rename.RenamedInsts 108881212 # Number of instructions processed by rename 423system.cpu.rename.ROBFullEvents 1310 # Number of times rename has blocked due to ROB full 424system.cpu.rename.IQFullEvents 1983947 # Number of times rename has blocked due to IQ full 425system.cpu.rename.LQFullEvents 2643349 # Number of times rename has blocked due to LQ full 426system.cpu.rename.SQFullEvents 9691184 # Number of times rename has blocked due to SQ full 427system.cpu.rename.RenamedOperands 114456313 # Number of destination operands rename has renamed 428system.cpu.rename.RenameLookups 501643948 # Number of register rename lookups that rename has made 429system.cpu.rename.int_rename_lookups 126478316 # Number of integer rename lookups 430system.cpu.rename.fp_rename_lookups 2998 # Number of floating rename lookups | 410system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::total 64885124 # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.branchRate 0.263832 # Number of branch fetches per cycle 413system.cpu.fetch.rate 1.352121 # Number of inst fetches per cycle 414system.cpu.decode.IdleCycles 8536355 # Number of cycles decode is idle 415system.cpu.decode.BlockedCycles 18658081 # Number of cycles decode is blocked 416system.cpu.decode.RunCycles 31532227 # Number of cycles decode is running 417system.cpu.decode.UnblockCycles 5666329 # Number of cycles decode is unblocking 418system.cpu.decode.SquashCycles 492132 # Number of cycles decode is squashing 419system.cpu.decode.BranchResolved 3179364 # Number of times decode resolved a branch 420system.cpu.decode.BranchMispred 171028 # Number of times decode detected a branch misprediction 421system.cpu.decode.DecodedInsts 101394580 # Number of instructions handled by decode 422system.cpu.decode.SquashedInsts 3046745 # Number of squashed instructions handled by decode 423system.cpu.rename.SquashCycles 492132 # Number of cycles rename is squashing 424system.cpu.rename.IdleCycles 13317145 # Number of cycles rename is idle 425system.cpu.rename.BlockCycles 5269714 # Number of cycles rename is blocking 426system.cpu.rename.serializeStallCycles 677558 # count of cycles rename stalled for serializing inst 427system.cpu.rename.RunCycles 32193664 # Number of cycles rename is running 428system.cpu.rename.UnblockCycles 12934911 # Number of cycles rename is unblocking 429system.cpu.rename.RenamedInsts 99186097 # Number of instructions processed by rename 430system.cpu.rename.SquashedInsts 982635 # Number of squashed instructions processed by rename 431system.cpu.rename.ROBFullEvents 3696460 # Number of times rename has blocked due to ROB full 432system.cpu.rename.IQFullEvents 54484 # Number of times rename has blocked due to IQ full 433system.cpu.rename.LQFullEvents 4041872 # Number of times rename has blocked due to LQ full 434system.cpu.rename.SQFullEvents 4848974 # Number of times rename has blocked due to SQ full 435system.cpu.rename.RenamedOperands 103911408 # Number of destination operands rename has renamed 436system.cpu.rename.RenameLookups 457625717 # Number of register rename lookups that rename has made 437system.cpu.rename.int_rename_lookups 115391737 # Number of integer rename lookups 438system.cpu.rename.fp_rename_lookups 582 # Number of floating rename lookups |
| 431system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed | 439system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed |
| 432system.cpu.rename.UndoneMaps 20827087 # Number of HB maps that are undone due to squashing 433system.cpu.rename.serializingInsts 24787 # count of serializing insts renamed 434system.cpu.rename.tempSerializingInsts 25137 # count of temporary serializing insts renamed 435system.cpu.rename.skidInsts 12915604 # count of insts added to the skid buffer 436system.cpu.memDep0.insertedLoads 25719384 # Number of loads inserted to the mem dependence unit. 437system.cpu.memDep0.insertedStores 23405570 # Number of stores inserted to the mem dependence unit. 438system.cpu.memDep0.conflictingLoads 6651489 # Number of conflicting loads. 439system.cpu.memDep0.conflictingStores 7812944 # Number of conflicting stores. 440system.cpu.iq.iqInstsAdded 105238243 # Number of instructions added to the IQ (excludes non-spec) 441system.cpu.iq.iqNonSpecInstsAdded 38026 # Number of non-speculative instructions added to the IQ 442system.cpu.iq.iqInstsIssued 99646497 # Number of instructions issued 443system.cpu.iq.iqSquashedInstsIssued 159437 # Number of squashed instructions issued 444system.cpu.iq.iqSquashedInstsExamined 14433434 # Number of squashed instructions iterated over during squash; mainly for profiling 445system.cpu.iq.iqSquashedOperandsExamined 35646535 # Number of squashed operands that are examined and possibly removed from graph 446system.cpu.iq.iqSquashedNonSpecRemoved 4240 # Number of squashed non-spec instructions that were removed 447system.cpu.iq.issued_per_cycle::samples 47424876 # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::mean 2.101144 # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::stdev 2.177334 # Number of insts issued each cycle | 440system.cpu.rename.UndoneMaps 10282182 # Number of HB maps that are undone due to squashing 441system.cpu.rename.serializingInsts 18671 # count of serializing insts renamed 442system.cpu.rename.tempSerializingInsts 18658 # count of temporary serializing insts renamed 443system.cpu.rename.skidInsts 12776141 # count of insts added to the skid buffer 444system.cpu.memDep0.insertedLoads 24320792 # Number of loads inserted to the mem dependence unit. 445system.cpu.memDep0.insertedStores 21987717 # Number of stores inserted to the mem dependence unit. 446system.cpu.memDep0.conflictingLoads 1318624 # Number of conflicting loads. 447system.cpu.memDep0.conflictingStores 2218270 # Number of conflicting stores. 448system.cpu.iq.iqInstsAdded 98150566 # Number of instructions added to the IQ (excludes non-spec) 449system.cpu.iq.iqNonSpecInstsAdded 34524 # Number of non-speculative instructions added to the IQ 450system.cpu.iq.iqInstsIssued 94860274 # Number of instructions issued 451system.cpu.iq.iqSquashedInstsIssued 691673 # Number of squashed instructions issued 452system.cpu.iq.iqSquashedInstsExamined 7398751 # Number of squashed instructions iterated over during squash; mainly for profiling 453system.cpu.iq.iqSquashedOperandsExamined 20189182 # Number of squashed operands that are examined and possibly removed from graph 454system.cpu.iq.iqSquashedNonSpecRemoved 738 # Number of squashed non-spec instructions that were removed 455system.cpu.iq.issued_per_cycle::samples 64885124 # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::mean 1.461973 # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::stdev 1.146315 # Number of insts issued each cycle |
| 450system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 458system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 451system.cpu.iq.issued_per_cycle::0 16924239 35.69% 35.69% # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::1 6535440 13.78% 49.47% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::2 6148782 12.97% 62.43% # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::3 5092843 10.74% 73.17% # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::4 5223877 11.02% 84.19% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::5 3271997 6.90% 91.09% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::6 2206801 4.65% 95.74% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::7 1128511 2.38% 98.12% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::8 892386 1.88% 100.00% # Number of insts issued each cycle | 459system.cpu.iq.issued_per_cycle::0 16747153 25.81% 25.81% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::1 17200007 26.51% 52.32% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::2 17188207 26.49% 78.81% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::3 11716155 18.06% 96.87% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::4 2032622 3.13% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::5 980 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle |
| 460system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle | 468system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle |
| 462system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::total 47424876 # Number of insts issued each cycle | 470system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::total 64885124 # Number of insts issued each cycle |
| 464system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 472system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 465system.cpu.iq.fu_full::IntAlu 215167 9.06% 9.06% # attempts to use FU when none available 466system.cpu.iq.fu_full::IntMult 0 0.00% 9.06% # attempts to use FU when none available 467system.cpu.iq.fu_full::IntDiv 0 0.00% 9.06% # attempts to use FU when none available 468system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.06% # attempts to use FU when none available 469system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.06% # attempts to use FU when none available 470system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.06% # attempts to use FU when none available 471system.cpu.iq.fu_full::FloatMult 0 0.00% 9.06% # attempts to use FU when none available 472system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.06% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.06% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.06% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.06% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.06% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.06% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.06% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.06% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdMult 0 0.00% 9.06% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.06% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdShift 0 0.00% 9.06% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.06% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.06% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.06% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.06% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.06% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.06% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.06% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.06% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.06% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.06% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.06% # attempts to use FU when none available 494system.cpu.iq.fu_full::MemRead 1190055 50.09% 59.14% # attempts to use FU when none available 495system.cpu.iq.fu_full::MemWrite 970810 40.86% 100.00% # attempts to use FU when none available | 473system.cpu.iq.fu_full::IntAlu 6675057 22.12% 22.12% # attempts to use FU when none available 474system.cpu.iq.fu_full::IntMult 43 0.00% 22.12% # attempts to use FU when none available 475system.cpu.iq.fu_full::IntDiv 0 0.00% 22.12% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.12% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.12% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.12% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatMult 0 0.00% 22.12% # attempts to use FU when none available 480system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.12% # attempts to use FU when none available 481system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.12% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.12% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.12% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.12% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.12% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.12% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.12% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdMult 0 0.00% 22.12% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.12% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdShift 0 0.00% 22.12% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.12% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.12% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.12% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.12% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.12% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.12% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.12% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.12% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.12% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.12% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.12% # attempts to use FU when none available 502system.cpu.iq.fu_full::MemRead 11293925 37.43% 59.55% # attempts to use FU when none available 503system.cpu.iq.fu_full::MemWrite 12204027 40.45% 100.00% # attempts to use FU when none available |
| 496system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 497system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 498system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 504system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 505system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 506system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 499system.cpu.iq.FU_type_0::IntAlu 51976863 52.16% 52.16% # Type of FU issued 500system.cpu.iq.FU_type_0::IntMult 92995 0.09% 52.25% # Type of FU issued 501system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued 502system.cpu.iq.FU_type_0::FloatAdd 147 0.00% 52.25% # Type of FU issued 503system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued 504system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued 505system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued 506system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued 507system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued 528system.cpu.iq.FU_type_0::MemRead 25513927 25.60% 77.86% # Type of FU issued 529system.cpu.iq.FU_type_0::MemWrite 22062558 22.14% 100.00% # Type of FU issued | 507system.cpu.iq.FU_type_0::IntAlu 49495845 52.18% 52.18% # Type of FU issued 508system.cpu.iq.FU_type_0::IntMult 89880 0.09% 52.27% # Type of FU issued 509system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.27% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued 515system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued 536system.cpu.iq.FU_type_0::MemRead 24035217 25.34% 77.61% # Type of FU issued 537system.cpu.iq.FU_type_0::MemWrite 21239293 22.39% 100.00% # Type of FU issued |
| 530system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 531system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 538system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 539system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 532system.cpu.iq.FU_type_0::total 99646497 # Type of FU issued 533system.cpu.iq.rate 2.084967 # Inst issue rate 534system.cpu.iq.fu_busy_cnt 2376032 # FU busy when requested 535system.cpu.iq.fu_busy_rate 0.023845 # FU busy rate (busy events/executed inst) 536system.cpu.iq.int_inst_queue_reads 249252729 # Number of integer instruction queue reads 537system.cpu.iq.int_inst_queue_writes 119771582 # Number of integer instruction queue writes 538system.cpu.iq.int_inst_queue_wakeup_accesses 97191472 # Number of integer instruction queue wakeup accesses 539system.cpu.iq.fp_inst_queue_reads 610 # Number of floating instruction queue reads 540system.cpu.iq.fp_inst_queue_writes 940 # Number of floating instruction queue writes 541system.cpu.iq.fp_inst_queue_wakeup_accesses 210 # Number of floating instruction queue wakeup accesses 542system.cpu.iq.int_alu_accesses 102022220 # Number of integer alu accesses 543system.cpu.iq.fp_alu_accesses 309 # Number of floating point alu accesses 544system.cpu.iew.lsq.thread0.forwLoads 2232705 # Number of loads that had data forwarded from stores | 540system.cpu.iq.FU_type_0::total 94860274 # Type of FU issued 541system.cpu.iq.rate 1.454233 # Inst issue rate 542system.cpu.iq.fu_busy_cnt 30173052 # FU busy when requested 543system.cpu.iq.fu_busy_rate 0.318079 # FU busy rate (busy events/executed inst) 544system.cpu.iq.int_inst_queue_reads 285470188 # Number of integer instruction queue reads 545system.cpu.iq.int_inst_queue_writes 105595239 # Number of integer instruction queue writes 546system.cpu.iq.int_inst_queue_wakeup_accesses 93464369 # Number of integer instruction queue wakeup accesses 547system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads 548system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes 549system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses 550system.cpu.iq.int_alu_accesses 125033207 # Number of integer alu accesses 551system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses 552system.cpu.iew.lsq.thread0.forwLoads 1351291 # Number of loads that had data forwarded from stores |
| 545system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 553system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 546system.cpu.iew.lsq.thread0.squashedLoads 2853122 # Number of loads squashed 547system.cpu.iew.lsq.thread0.ignoredResponses 4762 # Number of memory responses ignored because the instruction is squashed 548system.cpu.iew.lsq.thread0.memOrderViolation 65666 # Number of memory ordering violations 549system.cpu.iew.lsq.thread0.squashedStores 2849832 # Number of stores squashed | 554system.cpu.iew.lsq.thread0.squashedLoads 1454530 # Number of loads squashed 555system.cpu.iew.lsq.thread0.ignoredResponses 2099 # Number of memory responses ignored because the instruction is squashed 556system.cpu.iew.lsq.thread0.memOrderViolation 11910 # Number of memory ordering violations 557system.cpu.iew.lsq.thread0.squashedStores 1431979 # Number of stores squashed |
| 550system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 551system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 558system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 559system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 552system.cpu.iew.lsq.thread0.rescheduledLoads 726205 # Number of loads that were rescheduled 553system.cpu.iew.lsq.thread0.cacheBlocked 82286 # Number of times an access to memory failed due to the cache being blocked | 560system.cpu.iew.lsq.thread0.rescheduledLoads 120662 # Number of loads that were rescheduled 561system.cpu.iew.lsq.thread0.cacheBlocked 168795 # Number of times an access to memory failed due to the cache being blocked |
| 554system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 562system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 555system.cpu.iew.iewSquashCycles 544996 # Number of cycles IEW is squashing 556system.cpu.iew.iewBlockCycles 1714516 # Number of cycles IEW is blocking 557system.cpu.iew.iewUnblockCycles 834399 # Number of cycles IEW is unblocking 558system.cpu.iew.iewDispatchedInsts 105286702 # Number of instructions dispatched to IQ 559system.cpu.iew.iewDispSquashedInsts 183365 # Number of squashed instructions skipped by dispatch 560system.cpu.iew.iewDispLoadInsts 25719384 # Number of dispatched load instructions 561system.cpu.iew.iewDispStoreInsts 23405570 # Number of dispatched store instructions 562system.cpu.iew.iewDispNonSpecInsts 22106 # Number of dispatched non-speculative instructions 563system.cpu.iew.iewIQFullEvents 17305 # Number of times the IQ has become full, causing a stall 564system.cpu.iew.iewLSQFullEvents 806226 # Number of times the LSQ has become full, causing a stall 565system.cpu.iew.memOrderViolationEvents 65666 # Number of memory order violations 566system.cpu.iew.predictedTakenIncorrect 396732 # Number of branches that were predicted taken incorrectly 567system.cpu.iew.predictedNotTakenIncorrect 182672 # Number of branches that were predicted not taken incorrectly 568system.cpu.iew.branchMispredicts 579404 # Number of branch mispredicts detected at execute 569system.cpu.iew.iewExecutedInsts 98631248 # Number of executed instructions 570system.cpu.iew.iewExecLoadInsts 25214590 # Number of load instructions executed 571system.cpu.iew.iewExecSquashedInsts 1015249 # Number of squashed instructions skipped in execute | 563system.cpu.iew.iewSquashCycles 492132 # Number of cycles IEW is squashing 564system.cpu.iew.iewBlockCycles 622391 # Number of cycles IEW is blocking 565system.cpu.iew.iewUnblockCycles 354812 # Number of cycles IEW is unblocking 566system.cpu.iew.iewDispatchedInsts 98194956 # Number of instructions dispatched to IQ 567system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 568system.cpu.iew.iewDispLoadInsts 24320792 # Number of dispatched load instructions 569system.cpu.iew.iewDispStoreInsts 21987717 # Number of dispatched store instructions 570system.cpu.iew.iewDispNonSpecInsts 18604 # Number of dispatched non-speculative instructions 571system.cpu.iew.iewIQFullEvents 1618 # Number of times the IQ has become full, causing a stall 572system.cpu.iew.iewLSQFullEvents 350368 # Number of times the LSQ has become full, causing a stall 573system.cpu.iew.memOrderViolationEvents 11910 # Number of memory order violations 574system.cpu.iew.predictedTakenIncorrect 302846 # Number of branches that were predicted taken incorrectly 575system.cpu.iew.predictedNotTakenIncorrect 221657 # Number of branches that were predicted not taken incorrectly 576system.cpu.iew.branchMispredicts 524503 # Number of branch mispredicts detected at execute 577system.cpu.iew.iewExecutedInsts 93943274 # Number of executed instructions 578system.cpu.iew.iewExecLoadInsts 23727789 # Number of load instructions executed 579system.cpu.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute |
| 572system.cpu.iew.exec_swp 0 # number of swp insts executed | 580system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 573system.cpu.iew.exec_nop 10433 # number of nop insts executed 574system.cpu.iew.exec_refs 46968385 # number of memory reference insts executed 575system.cpu.iew.exec_branches 14905400 # Number of branches executed 576system.cpu.iew.exec_stores 21753795 # Number of stores executed 577system.cpu.iew.exec_rate 2.063724 # Inst execution rate 578system.cpu.iew.wb_sent 97441036 # cumulative count of insts sent to commit 579system.cpu.iew.wb_count 97191682 # cumulative count of insts written-back 580system.cpu.iew.wb_producers 50912103 # num instructions producing a value 581system.cpu.iew.wb_consumers 98942269 # num instructions consuming a value | 581system.cpu.iew.exec_nop 9866 # number of nop insts executed 582system.cpu.iew.exec_refs 44709300 # number of memory reference insts executed 583system.cpu.iew.exec_branches 14252629 # Number of branches executed 584system.cpu.iew.exec_stores 20981511 # Number of stores executed 585system.cpu.iew.exec_rate 1.440176 # Inst execution rate 586system.cpu.iew.wb_sent 93586002 # cumulative count of insts sent to commit 587system.cpu.iew.wb_count 93464426 # cumulative count of insts written-back 588system.cpu.iew.wb_producers 44933898 # num instructions producing a value 589system.cpu.iew.wb_consumers 76510027 # num instructions consuming a value |
| 582system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 590system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 583system.cpu.iew.wb_rate 2.033603 # insts written-back per cycle 584system.cpu.iew.wb_fanout 0.514564 # average fanout of values written-back | 591system.cpu.iew.wb_rate 1.432835 # insts written-back per cycle 592system.cpu.iew.wb_fanout 0.587294 # average fanout of values written-back |
| 585system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 593system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 586system.cpu.commit.commitSquashedInsts 14604340 # The number of squashed insts skipped by commit | 594system.cpu.commit.commitSquashedInsts 6524705 # The number of squashed insts skipped by commit |
| 587system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards | 595system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards |
| 588system.cpu.commit.branchMispredicts 491808 # The number of times a branch was mispredicted 589system.cpu.commit.committed_per_cycle::samples 45293214 # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::mean 2.002246 # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::stdev 2.787973 # Number of insts commited each cycle | 596system.cpu.commit.branchMispredicts 478981 # The number of times a branch was mispredicted 597system.cpu.commit.committed_per_cycle::samples 63829281 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::mean 1.420792 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::stdev 2.179767 # Number of insts commited each cycle |
| 592system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 600system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 593system.cpu.commit.committed_per_cycle::0 20766641 45.85% 45.85% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::1 9214809 20.34% 66.19% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::2 2670756 5.90% 72.09% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::3 2400198 5.30% 77.39% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::4 2023573 4.47% 81.86% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::5 972100 2.15% 84.00% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::6 768345 1.70% 85.70% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::7 447977 0.99% 86.69% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::8 6028815 13.31% 100.00% # Number of insts commited each cycle | 601system.cpu.commit.committed_per_cycle::0 30376493 47.59% 47.59% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::1 16710378 26.18% 73.77% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::2 4273265 6.69% 80.46% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::3 4126779 6.47% 86.93% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::4 1950134 3.06% 89.99% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::5 1295842 2.03% 92.02% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::6 707155 1.11% 93.12% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::7 585665 0.92% 94.04% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::8 3803570 5.96% 100.00% # Number of insts commited each cycle |
| 602system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 610system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 605system.cpu.commit.committed_per_cycle::total 45293214 # Number of insts commited each cycle | 613system.cpu.commit.committed_per_cycle::total 63829281 # Number of insts commited each cycle |
| 606system.cpu.commit.committedInsts 70913181 # Number of instructions committed 607system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed 608system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 609system.cpu.commit.refs 43422000 # Number of memory references committed 610system.cpu.commit.loads 22866262 # Number of loads committed 611system.cpu.commit.membars 15920 # Number of memory barriers committed 612system.cpu.commit.branches 13741485 # Number of branches committed 613system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 643system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 646system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 647system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 648system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 649system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 650system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction | 614system.cpu.commit.committedInsts 70913181 # Number of instructions committed 615system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed 616system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 617system.cpu.commit.refs 43422000 # Number of memory references committed 618system.cpu.commit.loads 22866262 # Number of loads committed 619system.cpu.commit.membars 15920 # Number of memory barriers committed 620system.cpu.commit.branches 13741485 # Number of branches committed 621system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 651system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 654system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 655system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 657system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 658system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction |
| 651system.cpu.commit.bw_lim_events 6028815 # number cycles where commit BW limit reached | 659system.cpu.commit.bw_lim_events 3803570 # number cycles where commit BW limit reached |
| 652system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 660system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 653system.cpu.rob.rob_reads 144531576 # The number of ROB reads 654system.cpu.rob.rob_writes 212728591 # The number of ROB writes 655system.cpu.timesIdled 10876 # Number of times that the entire CPU went into an idle state and unscheduled itself 656system.cpu.idleCycles 367966 # Total number of cycles that the CPU has spent unscheduled due to idling | 661system.cpu.rob.rob_reads 157213253 # The number of ROB reads 662system.cpu.rob.rob_writes 195483387 # The number of ROB writes 663system.cpu.timesIdled 20301 # Number of times that the entire CPU went into an idle state and unscheduled itself 664system.cpu.idleCycles 345307 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 657system.cpu.committedInsts 70907629 # Number of Instructions Simulated 658system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated | 665system.cpu.committedInsts 70907629 # Number of Instructions Simulated 666system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated |
| 659system.cpu.cpi 0.674016 # CPI: Cycles Per Instruction 660system.cpu.cpi_total 0.674016 # CPI: Total CPI of All Threads 661system.cpu.ipc 1.483645 # IPC: Instructions Per Cycle 662system.cpu.ipc_total 1.483645 # IPC: Total IPC of All Threads 663system.cpu.int_regfile_reads 106842718 # number of integer regfile reads 664system.cpu.int_regfile_writes 59180200 # number of integer regfile writes 665system.cpu.fp_regfile_reads 1084 # number of floating regfile reads 666system.cpu.fp_regfile_writes 924 # number of floating regfile writes 667system.cpu.cc_regfile_reads 361896749 # number of cc regfile reads 668system.cpu.cc_regfile_writes 40174850 # number of cc regfile writes 669system.cpu.misc_regfile_reads 45647350 # number of misc regfile reads | 667system.cpu.cpi 0.919935 # CPI: Cycles Per Instruction 668system.cpu.cpi_total 0.919935 # CPI: Total CPI of All Threads 669system.cpu.ipc 1.087033 # IPC: Instructions Per Cycle 670system.cpu.ipc_total 1.087033 # IPC: Total IPC of All Threads 671system.cpu.int_regfile_reads 102236516 # number of integer regfile reads 672system.cpu.int_regfile_writes 56794814 # number of integer regfile writes 673system.cpu.fp_regfile_reads 36 # number of floating regfile reads 674system.cpu.fp_regfile_writes 21 # number of floating regfile writes 675system.cpu.cc_regfile_reads 346002142 # number of cc regfile reads 676system.cpu.cc_regfile_writes 38804540 # number of cc regfile writes 677system.cpu.misc_regfile_reads 44207937 # number of misc regfile reads |
| 670system.cpu.misc_regfile_writes 31840 # number of misc regfile writes | 678system.cpu.misc_regfile_writes 31840 # number of misc regfile writes |
| 671system.cpu.toL2Bus.throughput 869793867 # Throughput (bytes/s) 672system.cpu.toL2Bus.trans_dist::ReadReq 88682 # Transaction distribution 673system.cpu.toL2Bus.trans_dist::ReadResp 88681 # Transaction distribution 674system.cpu.toL2Bus.trans_dist::Writeback 129104 # Transaction distribution 675system.cpu.toL2Bus.trans_dist::UpgradeReq 425 # Transaction distribution 676system.cpu.toL2Bus.trans_dist::UpgradeResp 425 # Transaction distribution 677system.cpu.toL2Bus.trans_dist::ReadExReq 106980 # Transaction distribution 678system.cpu.toL2Bus.trans_dist::ReadExResp 106980 # Transaction distribution 679system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66417 # Packet count per connected master and slave (bytes) 680system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454340 # Packet count per connected master and slave (bytes) 681system.cpu.toL2Bus.pkt_count::total 520757 # Packet count per connected master and slave (bytes) 682system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2108672 # Cumulative packet size per connected master and slave (bytes) 683system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18643008 # Cumulative packet size per connected master and slave (bytes) 684system.cpu.toL2Bus.tot_pkt_size::total 20751680 # Cumulative packet size per connected master and slave (bytes) 685system.cpu.toL2Bus.data_through_bus 20751680 # Total data (bytes) 686system.cpu.toL2Bus.snoop_data_through_bus 33280 # Total snoop data (bytes) 687system.cpu.toL2Bus.reqLayer0.occupancy 291703993 # Layer occupancy (ticks) 688system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 689system.cpu.toL2Bus.respLayer0.occupancy 50946473 # Layer occupancy (ticks) 690system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 691system.cpu.toL2Bus.respLayer1.occupancy 259533576 # Layer occupancy (ticks) 692system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 693system.cpu.icache.tags.replacements 31122 # number of replacements 694system.cpu.icache.tags.tagsinuse 1801.454521 # Cycle average of tags in use 695system.cpu.icache.tags.total_refs 12448339 # Total number of references to valid blocks. 696system.cpu.icache.tags.sampled_refs 33152 # Sample count of references to valid blocks. 697system.cpu.icache.tags.avg_refs 375.492851 # Average number of references to valid blocks. 698system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 699system.cpu.icache.tags.occ_blocks::cpu.inst 1801.454521 # Average occupied blocks per requestor 700system.cpu.icache.tags.occ_percent::cpu.inst 0.879616 # Average percentage of cache occupancy 701system.cpu.icache.tags.occ_percent::total 0.879616 # Average percentage of cache occupancy 702system.cpu.icache.tags.occ_task_id_blocks::1024 2030 # Occupied blocks per task id 703system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 704system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id 705system.cpu.icache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id 706system.cpu.icache.tags.age_task_id_blocks_1024::4 672 # Occupied blocks per task id 707system.cpu.icache.tags.occ_task_id_percent::1024 0.991211 # Percentage of cache occupancy per task id 708system.cpu.icache.tags.tag_accesses 25004882 # Number of tag accesses 709system.cpu.icache.tags.data_accesses 25004882 # Number of data accesses 710system.cpu.icache.ReadReq_hits::cpu.inst 12448346 # number of ReadReq hits 711system.cpu.icache.ReadReq_hits::total 12448346 # number of ReadReq hits 712system.cpu.icache.demand_hits::cpu.inst 12448346 # number of demand (read+write) hits 713system.cpu.icache.demand_hits::total 12448346 # number of demand (read+write) hits 714system.cpu.icache.overall_hits::cpu.inst 12448346 # number of overall hits 715system.cpu.icache.overall_hits::total 12448346 # number of overall hits 716system.cpu.icache.ReadReq_misses::cpu.inst 37361 # number of ReadReq misses 717system.cpu.icache.ReadReq_misses::total 37361 # number of ReadReq misses 718system.cpu.icache.demand_misses::cpu.inst 37361 # number of demand (read+write) misses 719system.cpu.icache.demand_misses::total 37361 # number of demand (read+write) misses 720system.cpu.icache.overall_misses::cpu.inst 37361 # number of overall misses 721system.cpu.icache.overall_misses::total 37361 # number of overall misses 722system.cpu.icache.ReadReq_miss_latency::cpu.inst 833057215 # number of ReadReq miss cycles 723system.cpu.icache.ReadReq_miss_latency::total 833057215 # number of ReadReq miss cycles 724system.cpu.icache.demand_miss_latency::cpu.inst 833057215 # number of demand (read+write) miss cycles 725system.cpu.icache.demand_miss_latency::total 833057215 # number of demand (read+write) miss cycles 726system.cpu.icache.overall_miss_latency::cpu.inst 833057215 # number of overall miss cycles 727system.cpu.icache.overall_miss_latency::total 833057215 # number of overall miss cycles 728system.cpu.icache.ReadReq_accesses::cpu.inst 12485707 # number of ReadReq accesses(hits+misses) 729system.cpu.icache.ReadReq_accesses::total 12485707 # number of ReadReq accesses(hits+misses) 730system.cpu.icache.demand_accesses::cpu.inst 12485707 # number of demand (read+write) accesses 731system.cpu.icache.demand_accesses::total 12485707 # number of demand (read+write) accesses 732system.cpu.icache.overall_accesses::cpu.inst 12485707 # number of overall (read+write) accesses 733system.cpu.icache.overall_accesses::total 12485707 # number of overall (read+write) accesses 734system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002992 # miss rate for ReadReq accesses 735system.cpu.icache.ReadReq_miss_rate::total 0.002992 # miss rate for ReadReq accesses 736system.cpu.icache.demand_miss_rate::cpu.inst 0.002992 # miss rate for demand accesses 737system.cpu.icache.demand_miss_rate::total 0.002992 # miss rate for demand accesses 738system.cpu.icache.overall_miss_rate::cpu.inst 0.002992 # miss rate for overall accesses 739system.cpu.icache.overall_miss_rate::total 0.002992 # miss rate for overall accesses 740system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22297.508498 # average ReadReq miss latency 741system.cpu.icache.ReadReq_avg_miss_latency::total 22297.508498 # average ReadReq miss latency 742system.cpu.icache.demand_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency 743system.cpu.icache.demand_avg_miss_latency::total 22297.508498 # average overall miss latency 744system.cpu.icache.overall_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency 745system.cpu.icache.overall_avg_miss_latency::total 22297.508498 # average overall miss latency 746system.cpu.icache.blocked_cycles::no_mshrs 1054 # number of cycles access was blocked | 679system.cpu.toL2Bus.trans_dist::ReadReq 661258 # Transaction distribution 680system.cpu.toL2Bus.trans_dist::ReadResp 661257 # Transaction distribution 681system.cpu.toL2Bus.trans_dist::Writeback 256573 # Transaction distribution 682system.cpu.toL2Bus.trans_dist::HardPFReq 261175 # Transaction distribution 683system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution 684system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution 685system.cpu.toL2Bus.trans_dist::ReadExReq 148561 # Transaction distribution 686system.cpu.toL2Bus.trans_dist::ReadExResp 148561 # Transaction distribution 687system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647966 # Packet count per connected master and slave (bytes) 688system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1228253 # Packet count per connected master and slave (bytes) 689system.cpu.toL2Bus.pkt_count::total 1876219 # Packet count per connected master and slave (bytes) 690system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20734528 # Cumulative packet size per connected master and slave (bytes) 691system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47513792 # Cumulative packet size per connected master and slave (bytes) 692system.cpu.toL2Bus.pkt_size::total 68248320 # Cumulative packet size per connected master and slave (bytes) 693system.cpu.toL2Bus.snoops 261186 # Total snoops (count) 694system.cpu.toL2Bus.snoop_fanout::samples 1327591 # Request fanout histogram 695system.cpu.toL2Bus.snoop_fanout::mean 5.196729 # Request fanout histogram 696system.cpu.toL2Bus.snoop_fanout::stdev 0.397525 # Request fanout histogram 697system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 698system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 699system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 700system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 701system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 702system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 703system.cpu.toL2Bus.snoop_fanout::5 1066416 80.33% 80.33% # Request fanout histogram 704system.cpu.toL2Bus.snoop_fanout::6 261175 19.67% 100.00% # Request fanout histogram 705system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 706system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 707system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 708system.cpu.toL2Bus.snoop_fanout::total 1327591 # Request fanout histogram 709system.cpu.toL2Bus.reqLayer0.occupancy 789786488 # Layer occupancy (ticks) 710system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) 711system.cpu.toL2Bus.respLayer0.occupancy 486428945 # Layer occupancy (ticks) 712system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 713system.cpu.toL2Bus.respLayer1.occupancy 733917689 # Layer occupancy (ticks) 714system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 715system.cpu.icache.tags.replacements 323466 # number of replacements 716system.cpu.icache.tags.tagsinuse 510.438944 # Cycle average of tags in use 717system.cpu.icache.tags.total_refs 22431935 # Total number of references to valid blocks. 718system.cpu.icache.tags.sampled_refs 323978 # Sample count of references to valid blocks. 719system.cpu.icache.tags.avg_refs 69.239069 # Average number of references to valid blocks. 720system.cpu.icache.tags.warmup_cycle 1054590000 # Cycle when the warmup percentage was hit. 721system.cpu.icache.tags.occ_blocks::cpu.inst 510.438944 # Average occupied blocks per requestor 722system.cpu.icache.tags.occ_percent::cpu.inst 0.996951 # Average percentage of cache occupancy 723system.cpu.icache.tags.occ_percent::total 0.996951 # Average percentage of cache occupancy 724system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 725system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 726system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id 728system.cpu.icache.tags.age_task_id_blocks_1024::3 267 # Occupied blocks per task id 729system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 730system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 731system.cpu.icache.tags.tag_accesses 45851126 # Number of tag accesses 732system.cpu.icache.tags.data_accesses 45851126 # Number of data accesses 733system.cpu.icache.ReadReq_hits::cpu.inst 22431935 # number of ReadReq hits 734system.cpu.icache.ReadReq_hits::total 22431935 # number of ReadReq hits 735system.cpu.icache.demand_hits::cpu.inst 22431935 # number of demand (read+write) hits 736system.cpu.icache.demand_hits::total 22431935 # number of demand (read+write) hits 737system.cpu.icache.overall_hits::cpu.inst 22431935 # number of overall hits 738system.cpu.icache.overall_hits::total 22431935 # number of overall hits 739system.cpu.icache.ReadReq_misses::cpu.inst 331634 # number of ReadReq misses 740system.cpu.icache.ReadReq_misses::total 331634 # number of ReadReq misses 741system.cpu.icache.demand_misses::cpu.inst 331634 # number of demand (read+write) misses 742system.cpu.icache.demand_misses::total 331634 # number of demand (read+write) misses 743system.cpu.icache.overall_misses::cpu.inst 331634 # number of overall misses 744system.cpu.icache.overall_misses::total 331634 # number of overall misses 745system.cpu.icache.ReadReq_miss_latency::cpu.inst 2861760504 # number of ReadReq miss cycles 746system.cpu.icache.ReadReq_miss_latency::total 2861760504 # number of ReadReq miss cycles 747system.cpu.icache.demand_miss_latency::cpu.inst 2861760504 # number of demand (read+write) miss cycles 748system.cpu.icache.demand_miss_latency::total 2861760504 # number of demand (read+write) miss cycles 749system.cpu.icache.overall_miss_latency::cpu.inst 2861760504 # number of overall miss cycles 750system.cpu.icache.overall_miss_latency::total 2861760504 # number of overall miss cycles 751system.cpu.icache.ReadReq_accesses::cpu.inst 22763569 # number of ReadReq accesses(hits+misses) 752system.cpu.icache.ReadReq_accesses::total 22763569 # number of ReadReq accesses(hits+misses) 753system.cpu.icache.demand_accesses::cpu.inst 22763569 # number of demand (read+write) accesses 754system.cpu.icache.demand_accesses::total 22763569 # number of demand (read+write) accesses 755system.cpu.icache.overall_accesses::cpu.inst 22763569 # number of overall (read+write) accesses 756system.cpu.icache.overall_accesses::total 22763569 # number of overall (read+write) accesses 757system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_miss_rate::total 0.014569 # miss rate for ReadReq accesses 759system.cpu.icache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses 760system.cpu.icache.demand_miss_rate::total 0.014569 # miss rate for demand accesses 761system.cpu.icache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses 762system.cpu.icache.overall_miss_rate::total 0.014569 # miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8629.273549 # average ReadReq miss latency 764system.cpu.icache.ReadReq_avg_miss_latency::total 8629.273549 # average ReadReq miss latency 765system.cpu.icache.demand_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency 766system.cpu.icache.demand_avg_miss_latency::total 8629.273549 # average overall miss latency 767system.cpu.icache.overall_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency 768system.cpu.icache.overall_avg_miss_latency::total 8629.273549 # average overall miss latency 769system.cpu.icache.blocked_cycles::no_mshrs 97738 # number of cycles access was blocked |
| 747system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 770system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 748system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked | 771system.cpu.icache.blocked::no_mshrs 12080 # number of cycles access was blocked |
| 749system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 772system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 750system.cpu.icache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked | 773system.cpu.icache.avg_blocked_cycles::no_mshrs 8.090894 # average number of cycles each access was blocked |
| 751system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 752system.cpu.icache.fast_writes 0 # number of fast writes performed 753system.cpu.icache.cache_copies 0 # number of cache copies performed | 774system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu.icache.fast_writes 0 # number of fast writes performed 776system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 754system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3892 # number of ReadReq MSHR hits 755system.cpu.icache.ReadReq_mshr_hits::total 3892 # number of ReadReq MSHR hits 756system.cpu.icache.demand_mshr_hits::cpu.inst 3892 # number of demand (read+write) MSHR hits 757system.cpu.icache.demand_mshr_hits::total 3892 # number of demand (read+write) MSHR hits 758system.cpu.icache.overall_mshr_hits::cpu.inst 3892 # number of overall MSHR hits 759system.cpu.icache.overall_mshr_hits::total 3892 # number of overall MSHR hits 760system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33469 # number of ReadReq MSHR misses 761system.cpu.icache.ReadReq_mshr_misses::total 33469 # number of ReadReq MSHR misses 762system.cpu.icache.demand_mshr_misses::cpu.inst 33469 # number of demand (read+write) MSHR misses 763system.cpu.icache.demand_mshr_misses::total 33469 # number of demand (read+write) MSHR misses 764system.cpu.icache.overall_mshr_misses::cpu.inst 33469 # number of overall MSHR misses 765system.cpu.icache.overall_mshr_misses::total 33469 # number of overall MSHR misses 766system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 671681027 # number of ReadReq MSHR miss cycles 767system.cpu.icache.ReadReq_mshr_miss_latency::total 671681027 # number of ReadReq MSHR miss cycles 768system.cpu.icache.demand_mshr_miss_latency::cpu.inst 671681027 # number of demand (read+write) MSHR miss cycles 769system.cpu.icache.demand_mshr_miss_latency::total 671681027 # number of demand (read+write) MSHR miss cycles 770system.cpu.icache.overall_mshr_miss_latency::cpu.inst 671681027 # number of overall MSHR miss cycles 771system.cpu.icache.overall_mshr_miss_latency::total 671681027 # number of overall MSHR miss cycles 772system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002681 # mshr miss rate for ReadReq accesses 773system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002681 # mshr miss rate for ReadReq accesses 774system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002681 # mshr miss rate for demand accesses 775system.cpu.icache.demand_mshr_miss_rate::total 0.002681 # mshr miss rate for demand accesses 776system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002681 # mshr miss rate for overall accesses 777system.cpu.icache.overall_mshr_miss_rate::total 0.002681 # mshr miss rate for overall accesses 778system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20068.750993 # average ReadReq mshr miss latency 779system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20068.750993 # average ReadReq mshr miss latency 780system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20068.750993 # average overall mshr miss latency 781system.cpu.icache.demand_avg_mshr_miss_latency::total 20068.750993 # average overall mshr miss latency 782system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20068.750993 # average overall mshr miss latency 783system.cpu.icache.overall_avg_mshr_miss_latency::total 20068.750993 # average overall mshr miss latency | 777system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7645 # number of ReadReq MSHR hits 778system.cpu.icache.ReadReq_mshr_hits::total 7645 # number of ReadReq MSHR hits 779system.cpu.icache.demand_mshr_hits::cpu.inst 7645 # number of demand (read+write) MSHR hits 780system.cpu.icache.demand_mshr_hits::total 7645 # number of demand (read+write) MSHR hits 781system.cpu.icache.overall_mshr_hits::cpu.inst 7645 # number of overall MSHR hits 782system.cpu.icache.overall_mshr_hits::total 7645 # number of overall MSHR hits 783system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323989 # number of ReadReq MSHR misses 784system.cpu.icache.ReadReq_mshr_misses::total 323989 # number of ReadReq MSHR misses 785system.cpu.icache.demand_mshr_misses::cpu.inst 323989 # number of demand (read+write) MSHR misses 786system.cpu.icache.demand_mshr_misses::total 323989 # number of demand (read+write) MSHR misses 787system.cpu.icache.overall_mshr_misses::cpu.inst 323989 # number of overall MSHR misses 788system.cpu.icache.overall_mshr_misses::total 323989 # number of overall MSHR misses 789system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325660123 # number of ReadReq MSHR miss cycles 790system.cpu.icache.ReadReq_mshr_miss_latency::total 2325660123 # number of ReadReq MSHR miss cycles 791system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2325660123 # number of demand (read+write) MSHR miss cycles 792system.cpu.icache.demand_mshr_miss_latency::total 2325660123 # number of demand (read+write) MSHR miss cycles 793system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2325660123 # number of overall MSHR miss cycles 794system.cpu.icache.overall_mshr_miss_latency::total 2325660123 # number of overall MSHR miss cycles 795system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for ReadReq accesses 796system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014233 # mshr miss rate for ReadReq accesses 797system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for demand accesses 798system.cpu.icache.demand_mshr_miss_rate::total 0.014233 # mshr miss rate for demand accesses 799system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for overall accesses 800system.cpu.icache.overall_mshr_miss_rate::total 0.014233 # mshr miss rate for overall accesses 801system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7178.207047 # average ReadReq mshr miss latency 802system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7178.207047 # average ReadReq mshr miss latency 803system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency 804system.cpu.icache.demand_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency 805system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency 806system.cpu.icache.overall_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency |
| 784system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 807system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 785system.cpu.l2cache.tags.replacements 95567 # number of replacements 786system.cpu.l2cache.tags.tagsinuse 29785.869326 # Cycle average of tags in use 787system.cpu.l2cache.tags.total_refs 90467 # Total number of references to valid blocks. 788system.cpu.l2cache.tags.sampled_refs 126676 # Sample count of references to valid blocks. 789system.cpu.l2cache.tags.avg_refs 0.714161 # Average number of references to valid blocks. | 808system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 3266027 # number of hwpf identified 809system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 304781 # number of hwpf that were already in mshr 810system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2719229 # number of hwpf that were already in the cache 811system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 25673 # number of hwpf that were already in the prefetch queue 812system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 813system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 17215 # number of hwpf removed because MSHR allocated 814system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 199121 # number of hwpf issued 815system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 314405 # number of hwpf spanning a virtual page 816system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 817system.cpu.l2cache.tags.replacements 140078 # number of replacements 818system.cpu.l2cache.tags.tagsinuse 16107.104250 # Cycle average of tags in use 819system.cpu.l2cache.tags.total_refs 874451 # Total number of references to valid blocks. 820system.cpu.l2cache.tags.sampled_refs 156393 # Sample count of references to valid blocks. 821system.cpu.l2cache.tags.avg_refs 5.591369 # Average number of references to valid blocks. |
| 790system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 822system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 791system.cpu.l2cache.tags.occ_blocks::writebacks 26681.247493 # Average occupied blocks per requestor 792system.cpu.l2cache.tags.occ_blocks::cpu.inst 1364.251232 # Average occupied blocks per requestor 793system.cpu.l2cache.tags.occ_blocks::cpu.data 1740.370601 # Average occupied blocks per requestor 794system.cpu.l2cache.tags.occ_percent::writebacks 0.814247 # Average percentage of cache occupancy 795system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041634 # Average percentage of cache occupancy 796system.cpu.l2cache.tags.occ_percent::cpu.data 0.053112 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::total 0.908993 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_task_id_blocks::1024 31109 # Occupied blocks per task id 799system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2594 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::2 24318 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3666 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::4 376 # Occupied blocks per task id 804system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949371 # Percentage of cache occupancy per task id 805system.cpu.l2cache.tags.tag_accesses 2831071 # Number of tag accesses 806system.cpu.l2cache.tags.data_accesses 2831071 # Number of data accesses 807system.cpu.l2cache.ReadReq_hits::cpu.inst 28249 # number of ReadReq hits 808system.cpu.l2cache.ReadReq_hits::cpu.data 33410 # number of ReadReq hits 809system.cpu.l2cache.ReadReq_hits::total 61659 # number of ReadReq hits 810system.cpu.l2cache.Writeback_hits::writebacks 129104 # number of Writeback hits 811system.cpu.l2cache.Writeback_hits::total 129104 # number of Writeback hits 812system.cpu.l2cache.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits 813system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits 814system.cpu.l2cache.ReadExReq_hits::cpu.data 4722 # number of ReadExReq hits 815system.cpu.l2cache.ReadExReq_hits::total 4722 # number of ReadExReq hits 816system.cpu.l2cache.demand_hits::cpu.inst 28249 # number of demand (read+write) hits 817system.cpu.l2cache.demand_hits::cpu.data 38132 # number of demand (read+write) hits 818system.cpu.l2cache.demand_hits::total 66381 # number of demand (read+write) hits 819system.cpu.l2cache.overall_hits::cpu.inst 28249 # number of overall hits 820system.cpu.l2cache.overall_hits::cpu.data 38132 # number of overall hits 821system.cpu.l2cache.overall_hits::total 66381 # number of overall hits 822system.cpu.l2cache.ReadReq_misses::cpu.inst 4700 # number of ReadReq misses 823system.cpu.l2cache.ReadReq_misses::cpu.data 21803 # number of ReadReq misses 824system.cpu.l2cache.ReadReq_misses::total 26503 # number of ReadReq misses 825system.cpu.l2cache.UpgradeReq_misses::cpu.data 380 # number of UpgradeReq misses 826system.cpu.l2cache.UpgradeReq_misses::total 380 # number of UpgradeReq misses 827system.cpu.l2cache.ReadExReq_misses::cpu.data 102258 # number of ReadExReq misses 828system.cpu.l2cache.ReadExReq_misses::total 102258 # number of ReadExReq misses 829system.cpu.l2cache.demand_misses::cpu.inst 4700 # number of demand (read+write) misses 830system.cpu.l2cache.demand_misses::cpu.data 124061 # number of demand (read+write) misses 831system.cpu.l2cache.demand_misses::total 128761 # number of demand (read+write) misses 832system.cpu.l2cache.overall_misses::cpu.inst 4700 # number of overall misses 833system.cpu.l2cache.overall_misses::cpu.data 124061 # number of overall misses 834system.cpu.l2cache.overall_misses::total 128761 # number of overall misses 835system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 354760000 # number of ReadReq miss cycles 836system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2021590000 # number of ReadReq miss cycles 837system.cpu.l2cache.ReadReq_miss_latency::total 2376350000 # number of ReadReq miss cycles 838system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 46498 # number of UpgradeReq miss cycles 839system.cpu.l2cache.UpgradeReq_miss_latency::total 46498 # number of UpgradeReq miss cycles 840system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8476574750 # number of ReadExReq miss cycles 841system.cpu.l2cache.ReadExReq_miss_latency::total 8476574750 # number of ReadExReq miss cycles 842system.cpu.l2cache.demand_miss_latency::cpu.inst 354760000 # number of demand (read+write) miss cycles 843system.cpu.l2cache.demand_miss_latency::cpu.data 10498164750 # number of demand (read+write) miss cycles 844system.cpu.l2cache.demand_miss_latency::total 10852924750 # number of demand (read+write) miss cycles 845system.cpu.l2cache.overall_miss_latency::cpu.inst 354760000 # number of overall miss cycles 846system.cpu.l2cache.overall_miss_latency::cpu.data 10498164750 # number of overall miss cycles 847system.cpu.l2cache.overall_miss_latency::total 10852924750 # number of overall miss cycles 848system.cpu.l2cache.ReadReq_accesses::cpu.inst 32949 # number of ReadReq accesses(hits+misses) 849system.cpu.l2cache.ReadReq_accesses::cpu.data 55213 # number of ReadReq accesses(hits+misses) 850system.cpu.l2cache.ReadReq_accesses::total 88162 # number of ReadReq accesses(hits+misses) 851system.cpu.l2cache.Writeback_accesses::writebacks 129104 # number of Writeback accesses(hits+misses) 852system.cpu.l2cache.Writeback_accesses::total 129104 # number of Writeback accesses(hits+misses) 853system.cpu.l2cache.UpgradeReq_accesses::cpu.data 425 # number of UpgradeReq accesses(hits+misses) 854system.cpu.l2cache.UpgradeReq_accesses::total 425 # number of UpgradeReq accesses(hits+misses) 855system.cpu.l2cache.ReadExReq_accesses::cpu.data 106980 # number of ReadExReq accesses(hits+misses) 856system.cpu.l2cache.ReadExReq_accesses::total 106980 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.demand_accesses::cpu.inst 32949 # number of demand (read+write) accesses 858system.cpu.l2cache.demand_accesses::cpu.data 162193 # number of demand (read+write) accesses 859system.cpu.l2cache.demand_accesses::total 195142 # number of demand (read+write) accesses 860system.cpu.l2cache.overall_accesses::cpu.inst 32949 # number of overall (read+write) accesses 861system.cpu.l2cache.overall_accesses::cpu.data 162193 # number of overall (read+write) accesses 862system.cpu.l2cache.overall_accesses::total 195142 # number of overall (read+write) accesses 863system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.142645 # miss rate for ReadReq accesses 864system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.394889 # miss rate for ReadReq accesses 865system.cpu.l2cache.ReadReq_miss_rate::total 0.300617 # miss rate for ReadReq accesses 866system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.894118 # miss rate for UpgradeReq accesses 867system.cpu.l2cache.UpgradeReq_miss_rate::total 0.894118 # miss rate for UpgradeReq accesses 868system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955861 # miss rate for ReadExReq accesses 869system.cpu.l2cache.ReadExReq_miss_rate::total 0.955861 # miss rate for ReadExReq accesses 870system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142645 # miss rate for demand accesses 871system.cpu.l2cache.demand_miss_rate::cpu.data 0.764897 # miss rate for demand accesses 872system.cpu.l2cache.demand_miss_rate::total 0.659832 # miss rate for demand accesses 873system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142645 # miss rate for overall accesses 874system.cpu.l2cache.overall_miss_rate::cpu.data 0.764897 # miss rate for overall accesses 875system.cpu.l2cache.overall_miss_rate::total 0.659832 # miss rate for overall accesses 876system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75480.851064 # average ReadReq miss latency 877system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 92720.726506 # average ReadReq miss latency 878system.cpu.l2cache.ReadReq_avg_miss_latency::total 89663.434328 # average ReadReq miss latency 879system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 122.363158 # average UpgradeReq miss latency 880system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 122.363158 # average UpgradeReq miss latency 881system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82894.000958 # average ReadExReq miss latency 882system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82894.000958 # average ReadExReq miss latency 883system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75480.851064 # average overall miss latency 884system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84620.990884 # average overall miss latency 885system.cpu.l2cache.demand_avg_miss_latency::total 84287.359915 # average overall miss latency 886system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75480.851064 # average overall miss latency 887system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84620.990884 # average overall miss latency 888system.cpu.l2cache.overall_avg_miss_latency::total 84287.359915 # average overall miss latency 889system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 823system.cpu.l2cache.tags.occ_blocks::writebacks 11482.142430 # Average occupied blocks per requestor 824system.cpu.l2cache.tags.occ_blocks::cpu.inst 301.953059 # Average occupied blocks per requestor 825system.cpu.l2cache.tags.occ_blocks::cpu.data 1690.013125 # Average occupied blocks per requestor 826system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2632.995635 # Average occupied blocks per requestor 827system.cpu.l2cache.tags.occ_percent::writebacks 0.700814 # Average percentage of cache occupancy 828system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018430 # Average percentage of cache occupancy 829system.cpu.l2cache.tags.occ_percent::cpu.data 0.103150 # Average percentage of cache occupancy 830system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.160705 # Average percentage of cache occupancy 831system.cpu.l2cache.tags.occ_percent::total 0.983100 # Average percentage of cache occupancy 832system.cpu.l2cache.tags.occ_task_id_blocks::1022 869 # Occupied blocks per task id 833system.cpu.l2cache.tags.occ_task_id_blocks::1024 15446 # Occupied blocks per task id 834system.cpu.l2cache.tags.age_task_id_blocks_1022::0 223 # Occupied blocks per task id 835system.cpu.l2cache.tags.age_task_id_blocks_1022::1 244 # Occupied blocks per task id 836system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id 837system.cpu.l2cache.tags.age_task_id_blocks_1022::3 234 # Occupied blocks per task id 838system.cpu.l2cache.tags.age_task_id_blocks_1022::4 156 # Occupied blocks per task id 839system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 840system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2751 # Occupied blocks per task id 841system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11585 # Occupied blocks per task id 842system.cpu.l2cache.tags.age_task_id_blocks_1024::3 388 # Occupied blocks per task id 843system.cpu.l2cache.tags.age_task_id_blocks_1024::4 623 # Occupied blocks per task id 844system.cpu.l2cache.tags.occ_task_id_percent::1022 0.053040 # Percentage of cache occupancy per task id 845system.cpu.l2cache.tags.occ_task_id_percent::1024 0.942749 # Percentage of cache occupancy per task id 846system.cpu.l2cache.tags.tag_accesses 17367214 # Number of tag accesses 847system.cpu.l2cache.tags.data_accesses 17367214 # Number of data accesses 848system.cpu.l2cache.ReadReq_hits::cpu.inst 320997 # number of ReadReq hits 849system.cpu.l2cache.ReadReq_hits::cpu.data 306363 # number of ReadReq hits 850system.cpu.l2cache.ReadReq_hits::total 627360 # number of ReadReq hits 851system.cpu.l2cache.Writeback_hits::writebacks 256573 # number of Writeback hits 852system.cpu.l2cache.Writeback_hits::total 256573 # number of Writeback hits 853system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 854system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 855system.cpu.l2cache.ReadExReq_hits::cpu.data 139690 # number of ReadExReq hits 856system.cpu.l2cache.ReadExReq_hits::total 139690 # number of ReadExReq hits 857system.cpu.l2cache.demand_hits::cpu.inst 320997 # number of demand (read+write) hits 858system.cpu.l2cache.demand_hits::cpu.data 446053 # number of demand (read+write) hits 859system.cpu.l2cache.demand_hits::total 767050 # number of demand (read+write) hits 860system.cpu.l2cache.overall_hits::cpu.inst 320997 # number of overall hits 861system.cpu.l2cache.overall_hits::cpu.data 446053 # number of overall hits 862system.cpu.l2cache.overall_hits::total 767050 # number of overall hits 863system.cpu.l2cache.ReadReq_misses::cpu.inst 2981 # number of ReadReq misses 864system.cpu.l2cache.ReadReq_misses::cpu.data 30906 # number of ReadReq misses 865system.cpu.l2cache.ReadReq_misses::total 33887 # number of ReadReq misses 866system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 867system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 868system.cpu.l2cache.ReadExReq_misses::cpu.data 8871 # number of ReadExReq misses 869system.cpu.l2cache.ReadExReq_misses::total 8871 # number of ReadExReq misses 870system.cpu.l2cache.demand_misses::cpu.inst 2981 # number of demand (read+write) misses 871system.cpu.l2cache.demand_misses::cpu.data 39777 # number of demand (read+write) misses 872system.cpu.l2cache.demand_misses::total 42758 # number of demand (read+write) misses 873system.cpu.l2cache.overall_misses::cpu.inst 2981 # number of overall misses 874system.cpu.l2cache.overall_misses::cpu.data 39777 # number of overall misses 875system.cpu.l2cache.overall_misses::total 42758 # number of overall misses 876system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232061970 # number of ReadReq miss cycles 877system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2519217993 # number of ReadReq miss cycles 878system.cpu.l2cache.ReadReq_miss_latency::total 2751279963 # number of ReadReq miss cycles 879system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 950040000 # number of ReadExReq miss cycles 880system.cpu.l2cache.ReadExReq_miss_latency::total 950040000 # number of ReadExReq miss cycles 881system.cpu.l2cache.demand_miss_latency::cpu.inst 232061970 # number of demand (read+write) miss cycles 882system.cpu.l2cache.demand_miss_latency::cpu.data 3469257993 # number of demand (read+write) miss cycles 883system.cpu.l2cache.demand_miss_latency::total 3701319963 # number of demand (read+write) miss cycles 884system.cpu.l2cache.overall_miss_latency::cpu.inst 232061970 # number of overall miss cycles 885system.cpu.l2cache.overall_miss_latency::cpu.data 3469257993 # number of overall miss cycles 886system.cpu.l2cache.overall_miss_latency::total 3701319963 # number of overall miss cycles 887system.cpu.l2cache.ReadReq_accesses::cpu.inst 323978 # number of ReadReq accesses(hits+misses) 888system.cpu.l2cache.ReadReq_accesses::cpu.data 337269 # number of ReadReq accesses(hits+misses) 889system.cpu.l2cache.ReadReq_accesses::total 661247 # number of ReadReq accesses(hits+misses) 890system.cpu.l2cache.Writeback_accesses::writebacks 256573 # number of Writeback accesses(hits+misses) 891system.cpu.l2cache.Writeback_accesses::total 256573 # number of Writeback accesses(hits+misses) 892system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) 893system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) 894system.cpu.l2cache.ReadExReq_accesses::cpu.data 148561 # number of ReadExReq accesses(hits+misses) 895system.cpu.l2cache.ReadExReq_accesses::total 148561 # number of ReadExReq accesses(hits+misses) 896system.cpu.l2cache.demand_accesses::cpu.inst 323978 # number of demand (read+write) accesses 897system.cpu.l2cache.demand_accesses::cpu.data 485830 # number of demand (read+write) accesses 898system.cpu.l2cache.demand_accesses::total 809808 # number of demand (read+write) accesses 899system.cpu.l2cache.overall_accesses::cpu.inst 323978 # number of overall (read+write) accesses 900system.cpu.l2cache.overall_accesses::cpu.data 485830 # number of overall (read+write) accesses 901system.cpu.l2cache.overall_accesses::total 809808 # number of overall (read+write) accesses 902system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.009201 # miss rate for ReadReq accesses 903system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.091636 # miss rate for ReadReq accesses 904system.cpu.l2cache.ReadReq_miss_rate::total 0.051247 # miss rate for ReadReq accesses 905system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses 906system.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses 907system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.059713 # miss rate for ReadExReq accesses 908system.cpu.l2cache.ReadExReq_miss_rate::total 0.059713 # miss rate for ReadExReq accesses 909system.cpu.l2cache.demand_miss_rate::cpu.inst 0.009201 # miss rate for demand accesses 910system.cpu.l2cache.demand_miss_rate::cpu.data 0.081874 # miss rate for demand accesses 911system.cpu.l2cache.demand_miss_rate::total 0.052800 # miss rate for demand accesses 912system.cpu.l2cache.overall_miss_rate::cpu.inst 0.009201 # miss rate for overall accesses 913system.cpu.l2cache.overall_miss_rate::cpu.data 0.081874 # miss rate for overall accesses 914system.cpu.l2cache.overall_miss_rate::total 0.052800 # miss rate for overall accesses 915system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77847.021134 # average ReadReq miss latency 916system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81512.262765 # average ReadReq miss latency 917system.cpu.l2cache.ReadReq_avg_miss_latency::total 81189.835719 # average ReadReq miss latency 918system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107095.028745 # average ReadExReq miss latency 919system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107095.028745 # average ReadExReq miss latency 920system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77847.021134 # average overall miss latency 921system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87217.688438 # average overall miss latency 922system.cpu.l2cache.demand_avg_miss_latency::total 86564.384747 # average overall miss latency 923system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77847.021134 # average overall miss latency 924system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87217.688438 # average overall miss latency 925system.cpu.l2cache.overall_avg_miss_latency::total 86564.384747 # average overall miss latency 926system.cpu.l2cache.blocked_cycles::no_mshrs 3458 # number of cycles access was blocked |
| 890system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 927system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 891system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked | 928system.cpu.l2cache.blocked::no_mshrs 119 # number of cycles access was blocked |
| 892system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 929system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 893system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 930system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.058824 # average number of cycles each access was blocked |
| 894system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu.l2cache.fast_writes 0 # number of fast writes performed 896system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 931system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 932system.cpu.l2cache.fast_writes 0 # number of fast writes performed 933system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 897system.cpu.l2cache.writebacks::writebacks 83950 # number of writebacks 898system.cpu.l2cache.writebacks::total 83950 # number of writebacks 899system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 21 # number of ReadReq MSHR hits 900system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 50 # number of ReadReq MSHR hits 901system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 902system.cpu.l2cache.demand_mshr_hits::cpu.inst 21 # number of demand (read+write) MSHR hits 903system.cpu.l2cache.demand_mshr_hits::cpu.data 50 # number of demand (read+write) MSHR hits 904system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 905system.cpu.l2cache.overall_mshr_hits::cpu.inst 21 # number of overall MSHR hits 906system.cpu.l2cache.overall_mshr_hits::cpu.data 50 # number of overall MSHR hits 907system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits 908system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4679 # number of ReadReq MSHR misses 909system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21753 # number of ReadReq MSHR misses 910system.cpu.l2cache.ReadReq_mshr_misses::total 26432 # number of ReadReq MSHR misses 911system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 380 # number of UpgradeReq MSHR misses 912system.cpu.l2cache.UpgradeReq_mshr_misses::total 380 # number of UpgradeReq MSHR misses 913system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102258 # number of ReadExReq MSHR misses 914system.cpu.l2cache.ReadExReq_mshr_misses::total 102258 # number of ReadExReq MSHR misses 915system.cpu.l2cache.demand_mshr_misses::cpu.inst 4679 # number of demand (read+write) MSHR misses 916system.cpu.l2cache.demand_mshr_misses::cpu.data 124011 # number of demand (read+write) MSHR misses 917system.cpu.l2cache.demand_mshr_misses::total 128690 # number of demand (read+write) MSHR misses 918system.cpu.l2cache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses 919system.cpu.l2cache.overall_mshr_misses::cpu.data 124011 # number of overall MSHR misses 920system.cpu.l2cache.overall_mshr_misses::total 128690 # number of overall MSHR misses 921system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 294843250 # number of ReadReq MSHR miss cycles 922system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1751098750 # number of ReadReq MSHR miss cycles 923system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2045942000 # number of ReadReq MSHR miss cycles 924system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3814378 # number of UpgradeReq MSHR miss cycles 925system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3814378 # number of UpgradeReq MSHR miss cycles 926system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7217032750 # number of ReadExReq MSHR miss cycles 927system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7217032750 # number of ReadExReq MSHR miss cycles 928system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 294843250 # number of demand (read+write) MSHR miss cycles 929system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8968131500 # number of demand (read+write) MSHR miss cycles 930system.cpu.l2cache.demand_mshr_miss_latency::total 9262974750 # number of demand (read+write) MSHR miss cycles 931system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294843250 # number of overall MSHR miss cycles 932system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8968131500 # number of overall MSHR miss cycles 933system.cpu.l2cache.overall_mshr_miss_latency::total 9262974750 # number of overall MSHR miss cycles 934system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.142007 # mshr miss rate for ReadReq accesses 935system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.393983 # mshr miss rate for ReadReq accesses 936system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299812 # mshr miss rate for ReadReq accesses 937system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.894118 # mshr miss rate for UpgradeReq accesses 938system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.894118 # mshr miss rate for UpgradeReq accesses 939system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955861 # mshr miss rate for ReadExReq accesses 940system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955861 # mshr miss rate for ReadExReq accesses 941system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142007 # mshr miss rate for demand accesses 942system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764589 # mshr miss rate for demand accesses 943system.cpu.l2cache.demand_mshr_miss_rate::total 0.659468 # mshr miss rate for demand accesses 944system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142007 # mshr miss rate for overall accesses 945system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764589 # mshr miss rate for overall accesses 946system.cpu.l2cache.overall_mshr_miss_rate::total 0.659468 # mshr miss rate for overall accesses 947system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63014.159008 # average ReadReq mshr miss latency 948system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 80499.184021 # average ReadReq mshr miss latency 949system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77403.980024 # average ReadReq mshr miss latency 950system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.836842 # average UpgradeReq mshr miss latency 951system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.836842 # average UpgradeReq mshr miss latency 952system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70576.705490 # average ReadExReq mshr miss latency 953system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70576.705490 # average ReadExReq mshr miss latency 954system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63014.159008 # average overall mshr miss latency 955system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72317.225891 # average overall mshr miss latency 956system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71978.978553 # average overall mshr miss latency 957system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63014.159008 # average overall mshr miss latency 958system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72317.225891 # average overall mshr miss latency 959system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71978.978553 # average overall mshr miss latency | 934system.cpu.l2cache.writebacks::writebacks 98491 # number of writebacks 935system.cpu.l2cache.writebacks::total 98491 # number of writebacks 936system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 910 # number of ReadReq MSHR hits 937system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 298 # number of ReadReq MSHR hits 938system.cpu.l2cache.ReadReq_mshr_hits::total 1208 # number of ReadReq MSHR hits 939system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2953 # number of ReadExReq MSHR hits 940system.cpu.l2cache.ReadExReq_mshr_hits::total 2953 # number of ReadExReq MSHR hits 941system.cpu.l2cache.demand_mshr_hits::cpu.inst 910 # number of demand (read+write) MSHR hits 942system.cpu.l2cache.demand_mshr_hits::cpu.data 3251 # number of demand (read+write) MSHR hits 943system.cpu.l2cache.demand_mshr_hits::total 4161 # number of demand (read+write) MSHR hits 944system.cpu.l2cache.overall_mshr_hits::cpu.inst 910 # number of overall MSHR hits 945system.cpu.l2cache.overall_mshr_hits::cpu.data 3251 # number of overall MSHR hits 946system.cpu.l2cache.overall_mshr_hits::total 4161 # number of overall MSHR hits 947system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2071 # number of ReadReq MSHR misses 948system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30608 # number of ReadReq MSHR misses 949system.cpu.l2cache.ReadReq_mshr_misses::total 32679 # number of ReadReq MSHR misses 950system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 199121 # number of HardPFReq MSHR misses 951system.cpu.l2cache.HardPFReq_mshr_misses::total 199121 # number of HardPFReq MSHR misses 952system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 953system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 954system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 5918 # number of ReadExReq MSHR misses 955system.cpu.l2cache.ReadExReq_mshr_misses::total 5918 # number of ReadExReq MSHR misses 956system.cpu.l2cache.demand_mshr_misses::cpu.inst 2071 # number of demand (read+write) MSHR misses 957system.cpu.l2cache.demand_mshr_misses::cpu.data 36526 # number of demand (read+write) MSHR misses 958system.cpu.l2cache.demand_mshr_misses::total 38597 # number of demand (read+write) MSHR misses 959system.cpu.l2cache.overall_mshr_misses::cpu.inst 2071 # number of overall MSHR misses 960system.cpu.l2cache.overall_mshr_misses::cpu.data 36526 # number of overall MSHR misses 961system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 199121 # number of overall MSHR misses 962system.cpu.l2cache.overall_mshr_misses::total 237718 # number of overall MSHR misses 963system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159067500 # number of ReadReq MSHR miss cycles 964system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2245450503 # number of ReadReq MSHR miss cycles 965system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2404518003 # number of ReadReq MSHR miss cycles 966system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of HardPFReq MSHR miss cycles 967system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 12215795775 # number of HardPFReq MSHR miss cycles 968system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 36006 # number of UpgradeReq MSHR miss cycles 969system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 36006 # number of UpgradeReq MSHR miss cycles 970system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 395713000 # number of ReadExReq MSHR miss cycles 971system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 395713000 # number of ReadExReq MSHR miss cycles 972system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159067500 # number of demand (read+write) MSHR miss cycles 973system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2641163503 # number of demand (read+write) MSHR miss cycles 974system.cpu.l2cache.demand_mshr_miss_latency::total 2800231003 # number of demand (read+write) MSHR miss cycles 975system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159067500 # number of overall MSHR miss cycles 976system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2641163503 # number of overall MSHR miss cycles 977system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of overall MSHR miss cycles 978system.cpu.l2cache.overall_mshr_miss_latency::total 15016026778 # number of overall MSHR miss cycles 979system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for ReadReq accesses 980system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.090752 # mshr miss rate for ReadReq accesses 981system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.049420 # mshr miss rate for ReadReq accesses 982system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 983system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 984system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses 985system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses 986system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.039835 # mshr miss rate for ReadExReq accesses 987system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.039835 # mshr miss rate for ReadExReq accesses 988system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for demand accesses 989system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for demand accesses 990system.cpu.l2cache.demand_mshr_miss_rate::total 0.047662 # mshr miss rate for demand accesses 991system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for overall accesses 992system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for overall accesses 993system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 994system.cpu.l2cache.overall_mshr_miss_rate::total 0.293549 # mshr miss rate for overall accesses 995system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 76807.098020 # average ReadReq mshr miss latency 996system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73361.555900 # average ReadReq mshr miss latency 997system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73579.913798 # average ReadReq mshr miss latency 998system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average HardPFReq mshr miss latency 999system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61348.605998 # average HardPFReq mshr miss latency 1000system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 1001system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency 1002system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66866.002028 # average ReadExReq mshr miss latency 1003system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66866.002028 # average ReadExReq mshr miss latency 1004system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency 1005system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency 1006system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72550.483276 # average overall mshr miss latency 1007system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency 1008system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency 1009system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average overall mshr miss latency 1010system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63167.394888 # average overall mshr miss latency |
| 960system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1011system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 961system.cpu.dcache.tags.replacements 158097 # number of replacements 962system.cpu.dcache.tags.tagsinuse 4066.697393 # Cycle average of tags in use 963system.cpu.dcache.tags.total_refs 40254845 # Total number of references to valid blocks. 964system.cpu.dcache.tags.sampled_refs 162193 # Sample count of references to valid blocks. 965system.cpu.dcache.tags.avg_refs 248.191013 # Average number of references to valid blocks. 966system.cpu.dcache.tags.warmup_cycle 349035000 # Cycle when the warmup percentage was hit. 967system.cpu.dcache.tags.occ_blocks::cpu.data 4066.697393 # Average occupied blocks per requestor 968system.cpu.dcache.tags.occ_percent::cpu.data 0.992846 # Average percentage of cache occupancy 969system.cpu.dcache.tags.occ_percent::total 0.992846 # Average percentage of cache occupancy 970system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 971system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 972system.cpu.dcache.tags.age_task_id_blocks_1024::1 2487 # Occupied blocks per task id 973system.cpu.dcache.tags.age_task_id_blocks_1024::2 1534 # Occupied blocks per task id | 1012system.cpu.dcache.tags.replacements 485318 # number of replacements 1013system.cpu.dcache.tags.tagsinuse 510.841997 # Cycle average of tags in use 1014system.cpu.dcache.tags.total_refs 40443714 # Total number of references to valid blocks. 1015system.cpu.dcache.tags.sampled_refs 485830 # Sample count of references to valid blocks. 1016system.cpu.dcache.tags.avg_refs 83.246638 # Average number of references to valid blocks. 1017system.cpu.dcache.tags.warmup_cycle 139928000 # Cycle when the warmup percentage was hit. 1018system.cpu.dcache.tags.occ_blocks::cpu.data 510.841997 # Average occupied blocks per requestor 1019system.cpu.dcache.tags.occ_percent::cpu.data 0.997738 # Average percentage of cache occupancy 1020system.cpu.dcache.tags.occ_percent::total 0.997738 # Average percentage of cache occupancy 1021system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1022system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 1023system.cpu.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id |
| 974system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1024system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 975system.cpu.dcache.tags.tag_accesses 84282165 # Number of tag accesses 976system.cpu.dcache.tags.data_accesses 84282165 # Number of data accesses 977system.cpu.dcache.ReadReq_hits::cpu.data 21874674 # number of ReadReq hits 978system.cpu.dcache.ReadReq_hits::total 21874674 # number of ReadReq hits 979system.cpu.dcache.WriteReq_hits::cpu.data 18263658 # number of WriteReq hits 980system.cpu.dcache.WriteReq_hits::total 18263658 # number of WriteReq hits 981system.cpu.dcache.SoftPFReq_hits::cpu.data 83481 # number of SoftPFReq hits 982system.cpu.dcache.SoftPFReq_hits::total 83481 # number of SoftPFReq hits 983system.cpu.dcache.LoadLockedReq_hits::cpu.data 15983 # number of LoadLockedReq hits 984system.cpu.dcache.LoadLockedReq_hits::total 15983 # number of LoadLockedReq hits | 1025system.cpu.dcache.tags.tag_accesses 84640426 # Number of tag accesses 1026system.cpu.dcache.tags.data_accesses 84640426 # Number of data accesses 1027system.cpu.dcache.ReadReq_hits::cpu.data 21515343 # number of ReadReq hits 1028system.cpu.dcache.ReadReq_hits::total 21515343 # number of ReadReq hits 1029system.cpu.dcache.WriteReq_hits::cpu.data 18834765 # number of WriteReq hits 1030system.cpu.dcache.WriteReq_hits::total 18834765 # number of WriteReq hits 1031system.cpu.dcache.SoftPFReq_hits::cpu.data 62288 # number of SoftPFReq hits 1032system.cpu.dcache.SoftPFReq_hits::total 62288 # number of SoftPFReq hits 1033system.cpu.dcache.LoadLockedReq_hits::cpu.data 15377 # number of LoadLockedReq hits 1034system.cpu.dcache.LoadLockedReq_hits::total 15377 # number of LoadLockedReq hits |
| 985system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 986system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits | 1035system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 1036system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| 987system.cpu.dcache.demand_hits::cpu.data 40138332 # number of demand (read+write) hits 988system.cpu.dcache.demand_hits::total 40138332 # number of demand (read+write) hits 989system.cpu.dcache.overall_hits::cpu.data 40221813 # number of overall hits 990system.cpu.dcache.overall_hits::total 40221813 # number of overall hits 991system.cpu.dcache.ReadReq_misses::cpu.data 172724 # number of ReadReq misses 992system.cpu.dcache.ReadReq_misses::total 172724 # number of ReadReq misses 993system.cpu.dcache.WriteReq_misses::cpu.data 1586243 # number of WriteReq misses 994system.cpu.dcache.WriteReq_misses::total 1586243 # number of WriteReq misses 995system.cpu.dcache.SoftPFReq_misses::cpu.data 47266 # number of SoftPFReq misses 996system.cpu.dcache.SoftPFReq_misses::total 47266 # number of SoftPFReq misses 997system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses 998system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses 999system.cpu.dcache.demand_misses::cpu.data 1758967 # number of demand (read+write) misses 1000system.cpu.dcache.demand_misses::total 1758967 # number of demand (read+write) misses 1001system.cpu.dcache.overall_misses::cpu.data 1806233 # number of overall misses 1002system.cpu.dcache.overall_misses::total 1806233 # number of overall misses 1003system.cpu.dcache.ReadReq_miss_latency::cpu.data 5001907368 # number of ReadReq miss cycles 1004system.cpu.dcache.ReadReq_miss_latency::total 5001907368 # number of ReadReq miss cycles 1005system.cpu.dcache.WriteReq_miss_latency::cpu.data 128651444042 # number of WriteReq miss cycles 1006system.cpu.dcache.WriteReq_miss_latency::total 128651444042 # number of WriteReq miss cycles 1007system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1064000 # number of LoadLockedReq miss cycles 1008system.cpu.dcache.LoadLockedReq_miss_latency::total 1064000 # number of LoadLockedReq miss cycles 1009system.cpu.dcache.demand_miss_latency::cpu.data 133653351410 # number of demand (read+write) miss cycles 1010system.cpu.dcache.demand_miss_latency::total 133653351410 # number of demand (read+write) miss cycles 1011system.cpu.dcache.overall_miss_latency::cpu.data 133653351410 # number of overall miss cycles 1012system.cpu.dcache.overall_miss_latency::total 133653351410 # number of overall miss cycles 1013system.cpu.dcache.ReadReq_accesses::cpu.data 22047398 # number of ReadReq accesses(hits+misses) 1014system.cpu.dcache.ReadReq_accesses::total 22047398 # number of ReadReq accesses(hits+misses) | 1037system.cpu.dcache.demand_hits::cpu.data 40350108 # number of demand (read+write) hits 1038system.cpu.dcache.demand_hits::total 40350108 # number of demand (read+write) hits 1039system.cpu.dcache.overall_hits::cpu.data 40412396 # number of overall hits 1040system.cpu.dcache.overall_hits::total 40412396 # number of overall hits 1041system.cpu.dcache.ReadReq_misses::cpu.data 551365 # number of ReadReq misses 1042system.cpu.dcache.ReadReq_misses::total 551365 # number of ReadReq misses 1043system.cpu.dcache.WriteReq_misses::cpu.data 1015136 # number of WriteReq misses 1044system.cpu.dcache.WriteReq_misses::total 1015136 # number of WriteReq misses 1045system.cpu.dcache.SoftPFReq_misses::cpu.data 66556 # number of SoftPFReq misses 1046system.cpu.dcache.SoftPFReq_misses::total 66556 # number of SoftPFReq misses 1047system.cpu.dcache.LoadLockedReq_misses::cpu.data 549 # number of LoadLockedReq misses 1048system.cpu.dcache.LoadLockedReq_misses::total 549 # number of LoadLockedReq misses 1049system.cpu.dcache.demand_misses::cpu.data 1566501 # number of demand (read+write) misses 1050system.cpu.dcache.demand_misses::total 1566501 # number of demand (read+write) misses 1051system.cpu.dcache.overall_misses::cpu.data 1633057 # number of overall misses 1052system.cpu.dcache.overall_misses::total 1633057 # number of overall misses 1053system.cpu.dcache.ReadReq_miss_latency::cpu.data 8548612161 # number of ReadReq miss cycles 1054system.cpu.dcache.ReadReq_miss_latency::total 8548612161 # number of ReadReq miss cycles 1055system.cpu.dcache.WriteReq_miss_latency::cpu.data 13150540915 # number of WriteReq miss cycles 1056system.cpu.dcache.WriteReq_miss_latency::total 13150540915 # number of WriteReq miss cycles 1057system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5021750 # number of LoadLockedReq miss cycles 1058system.cpu.dcache.LoadLockedReq_miss_latency::total 5021750 # number of LoadLockedReq miss cycles 1059system.cpu.dcache.demand_miss_latency::cpu.data 21699153076 # number of demand (read+write) miss cycles 1060system.cpu.dcache.demand_miss_latency::total 21699153076 # number of demand (read+write) miss cycles 1061system.cpu.dcache.overall_miss_latency::cpu.data 21699153076 # number of overall miss cycles 1062system.cpu.dcache.overall_miss_latency::total 21699153076 # number of overall miss cycles 1063system.cpu.dcache.ReadReq_accesses::cpu.data 22066708 # number of ReadReq accesses(hits+misses) 1064system.cpu.dcache.ReadReq_accesses::total 22066708 # number of ReadReq accesses(hits+misses) |
| 1015system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 1016system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) | 1065system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 1066system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| 1017system.cpu.dcache.SoftPFReq_accesses::cpu.data 130747 # number of SoftPFReq accesses(hits+misses) 1018system.cpu.dcache.SoftPFReq_accesses::total 130747 # number of SoftPFReq accesses(hits+misses) 1019system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16021 # number of LoadLockedReq accesses(hits+misses) 1020system.cpu.dcache.LoadLockedReq_accesses::total 16021 # number of LoadLockedReq accesses(hits+misses) | 1067system.cpu.dcache.SoftPFReq_accesses::cpu.data 128844 # number of SoftPFReq accesses(hits+misses) 1068system.cpu.dcache.SoftPFReq_accesses::total 128844 # number of SoftPFReq accesses(hits+misses) 1069system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) 1070system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) |
| 1021system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 1022system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) | 1071system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 1072system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| 1023system.cpu.dcache.demand_accesses::cpu.data 41897299 # number of demand (read+write) accesses 1024system.cpu.dcache.demand_accesses::total 41897299 # number of demand (read+write) accesses 1025system.cpu.dcache.overall_accesses::cpu.data 42028046 # number of overall (read+write) accesses 1026system.cpu.dcache.overall_accesses::total 42028046 # number of overall (read+write) accesses 1027system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007834 # miss rate for ReadReq accesses 1028system.cpu.dcache.ReadReq_miss_rate::total 0.007834 # miss rate for ReadReq accesses 1029system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079912 # miss rate for WriteReq accesses 1030system.cpu.dcache.WriteReq_miss_rate::total 0.079912 # miss rate for WriteReq accesses 1031system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.361507 # miss rate for SoftPFReq accesses 1032system.cpu.dcache.SoftPFReq_miss_rate::total 0.361507 # miss rate for SoftPFReq accesses 1033system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002372 # miss rate for LoadLockedReq accesses 1034system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002372 # miss rate for LoadLockedReq accesses 1035system.cpu.dcache.demand_miss_rate::cpu.data 0.041983 # miss rate for demand accesses 1036system.cpu.dcache.demand_miss_rate::total 0.041983 # miss rate for demand accesses 1037system.cpu.dcache.overall_miss_rate::cpu.data 0.042977 # miss rate for overall accesses 1038system.cpu.dcache.overall_miss_rate::total 0.042977 # miss rate for overall accesses 1039system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.959774 # average ReadReq miss latency 1040system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.959774 # average ReadReq miss latency 1041system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81104.499148 # average WriteReq miss latency 1042system.cpu.dcache.WriteReq_avg_miss_latency::total 81104.499148 # average WriteReq miss latency 1043system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28000 # average LoadLockedReq miss latency 1044system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28000 # average LoadLockedReq miss latency 1045system.cpu.dcache.demand_avg_miss_latency::cpu.data 75984.001638 # average overall miss latency 1046system.cpu.dcache.demand_avg_miss_latency::total 75984.001638 # average overall miss latency 1047system.cpu.dcache.overall_avg_miss_latency::cpu.data 73995.631466 # average overall miss latency 1048system.cpu.dcache.overall_avg_miss_latency::total 73995.631466 # average overall miss latency 1049system.cpu.dcache.blocked_cycles::no_mshrs 911565 # number of cycles access was blocked 1050system.cpu.dcache.blocked_cycles::no_targets 1622 # number of cycles access was blocked 1051system.cpu.dcache.blocked::no_mshrs 13218 # number of cycles access was blocked 1052system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked 1053system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.963913 # average number of cycles each access was blocked 1054system.cpu.dcache.avg_blocked_cycles::no_targets 108.133333 # average number of cycles each access was blocked | 1073system.cpu.dcache.demand_accesses::cpu.data 41916609 # number of demand (read+write) accesses 1074system.cpu.dcache.demand_accesses::total 41916609 # number of demand (read+write) accesses 1075system.cpu.dcache.overall_accesses::cpu.data 42045453 # number of overall (read+write) accesses 1076system.cpu.dcache.overall_accesses::total 42045453 # number of overall (read+write) accesses 1077system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024986 # miss rate for ReadReq accesses 1078system.cpu.dcache.ReadReq_miss_rate::total 0.024986 # miss rate for ReadReq accesses 1079system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051141 # miss rate for WriteReq accesses 1080system.cpu.dcache.WriteReq_miss_rate::total 0.051141 # miss rate for WriteReq accesses 1081system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516563 # miss rate for SoftPFReq accesses 1082system.cpu.dcache.SoftPFReq_miss_rate::total 0.516563 # miss rate for SoftPFReq accesses 1083system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034472 # miss rate for LoadLockedReq accesses 1084system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034472 # miss rate for LoadLockedReq accesses 1085system.cpu.dcache.demand_miss_rate::cpu.data 0.037372 # miss rate for demand accesses 1086system.cpu.dcache.demand_miss_rate::total 0.037372 # miss rate for demand accesses 1087system.cpu.dcache.overall_miss_rate::cpu.data 0.038840 # miss rate for overall accesses 1088system.cpu.dcache.overall_miss_rate::total 0.038840 # miss rate for overall accesses 1089system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15504.451971 # average ReadReq miss latency 1090system.cpu.dcache.ReadReq_avg_miss_latency::total 15504.451971 # average ReadReq miss latency 1091system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12954.462176 # average WriteReq miss latency 1092system.cpu.dcache.WriteReq_avg_miss_latency::total 12954.462176 # average WriteReq miss latency 1093system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9147.085610 # average LoadLockedReq miss latency 1094system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9147.085610 # average LoadLockedReq miss latency 1095system.cpu.dcache.demand_avg_miss_latency::cpu.data 13851.988014 # average overall miss latency 1096system.cpu.dcache.demand_avg_miss_latency::total 13851.988014 # average overall miss latency 1097system.cpu.dcache.overall_avg_miss_latency::cpu.data 13287.443779 # average overall miss latency 1098system.cpu.dcache.overall_avg_miss_latency::total 13287.443779 # average overall miss latency 1099system.cpu.dcache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked 1100system.cpu.dcache.blocked_cycles::no_targets 2567726 # number of cycles access was blocked 1101system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked 1102system.cpu.dcache.blocked::no_targets 127351 # number of cycles access was blocked 1103system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.214286 # average number of cycles each access was blocked 1104system.cpu.dcache.avg_blocked_cycles::no_targets 20.162590 # average number of cycles each access was blocked |
| 1055system.cpu.dcache.fast_writes 0 # number of fast writes performed 1056system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1105system.cpu.dcache.fast_writes 0 # number of fast writes performed 1106system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1057system.cpu.dcache.writebacks::writebacks 129104 # number of writebacks 1058system.cpu.dcache.writebacks::total 129104 # number of writebacks 1059system.cpu.dcache.ReadReq_mshr_hits::cpu.data 141550 # number of ReadReq MSHR hits 1060system.cpu.dcache.ReadReq_mshr_hits::total 141550 # number of ReadReq MSHR hits 1061system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1478910 # number of WriteReq MSHR hits 1062system.cpu.dcache.WriteReq_mshr_hits::total 1478910 # number of WriteReq MSHR hits 1063system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits 1064system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits 1065system.cpu.dcache.demand_mshr_hits::cpu.data 1620460 # number of demand (read+write) MSHR hits 1066system.cpu.dcache.demand_mshr_hits::total 1620460 # number of demand (read+write) MSHR hits 1067system.cpu.dcache.overall_mshr_hits::cpu.data 1620460 # number of overall MSHR hits 1068system.cpu.dcache.overall_mshr_hits::total 1620460 # number of overall MSHR hits 1069system.cpu.dcache.ReadReq_mshr_misses::cpu.data 31174 # number of ReadReq MSHR misses 1070system.cpu.dcache.ReadReq_mshr_misses::total 31174 # number of ReadReq MSHR misses 1071system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107333 # number of WriteReq MSHR misses 1072system.cpu.dcache.WriteReq_mshr_misses::total 107333 # number of WriteReq MSHR misses 1073system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24111 # number of SoftPFReq MSHR misses 1074system.cpu.dcache.SoftPFReq_mshr_misses::total 24111 # number of SoftPFReq MSHR misses 1075system.cpu.dcache.demand_mshr_misses::cpu.data 138507 # number of demand (read+write) MSHR misses 1076system.cpu.dcache.demand_mshr_misses::total 138507 # number of demand (read+write) MSHR misses 1077system.cpu.dcache.overall_mshr_misses::cpu.data 162618 # number of overall MSHR misses 1078system.cpu.dcache.overall_mshr_misses::total 162618 # number of overall MSHR misses 1079system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 566566801 # number of ReadReq MSHR miss cycles 1080system.cpu.dcache.ReadReq_mshr_miss_latency::total 566566801 # number of ReadReq MSHR miss cycles 1081system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8639740111 # number of WriteReq MSHR miss cycles 1082system.cpu.dcache.WriteReq_mshr_miss_latency::total 8639740111 # number of WriteReq MSHR miss cycles 1083system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1848458500 # number of SoftPFReq MSHR miss cycles 1084system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1848458500 # number of SoftPFReq MSHR miss cycles 1085system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9206306912 # number of demand (read+write) MSHR miss cycles 1086system.cpu.dcache.demand_mshr_miss_latency::total 9206306912 # number of demand (read+write) MSHR miss cycles 1087system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11054765412 # number of overall MSHR miss cycles 1088system.cpu.dcache.overall_mshr_miss_latency::total 11054765412 # number of overall MSHR miss cycles 1089system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001414 # mshr miss rate for ReadReq accesses 1090system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001414 # mshr miss rate for ReadReq accesses 1091system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses 1092system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses 1093system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.184410 # mshr miss rate for SoftPFReq accesses 1094system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.184410 # mshr miss rate for SoftPFReq accesses 1095system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003306 # mshr miss rate for demand accesses 1096system.cpu.dcache.demand_mshr_miss_rate::total 0.003306 # mshr miss rate for demand accesses 1097system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003869 # mshr miss rate for overall accesses 1098system.cpu.dcache.overall_mshr_miss_rate::total 0.003869 # mshr miss rate for overall accesses 1099system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18174.337621 # average ReadReq mshr miss latency 1100system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18174.337621 # average ReadReq mshr miss latency 1101system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80494.723067 # average WriteReq mshr miss latency 1102system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80494.723067 # average WriteReq mshr miss latency 1103system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76664.530712 # average SoftPFReq mshr miss latency 1104system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76664.530712 # average SoftPFReq mshr miss latency 1105system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66468.170648 # average overall mshr miss latency 1106system.cpu.dcache.demand_avg_mshr_miss_latency::total 66468.170648 # average overall mshr miss latency 1107system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67979.961702 # average overall mshr miss latency 1108system.cpu.dcache.overall_avg_mshr_miss_latency::total 67979.961702 # average overall mshr miss latency | 1107system.cpu.dcache.writebacks::writebacks 256573 # number of writebacks 1108system.cpu.dcache.writebacks::total 256573 # number of writebacks 1109system.cpu.dcache.ReadReq_mshr_hits::cpu.data 251643 # number of ReadReq MSHR hits 1110system.cpu.dcache.ReadReq_mshr_hits::total 251643 # number of ReadReq MSHR hits 1111system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866615 # number of WriteReq MSHR hits 1112system.cpu.dcache.WriteReq_mshr_hits::total 866615 # number of WriteReq MSHR hits 1113system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 549 # number of LoadLockedReq MSHR hits 1114system.cpu.dcache.LoadLockedReq_mshr_hits::total 549 # number of LoadLockedReq MSHR hits 1115system.cpu.dcache.demand_mshr_hits::cpu.data 1118258 # number of demand (read+write) MSHR hits 1116system.cpu.dcache.demand_mshr_hits::total 1118258 # number of demand (read+write) MSHR hits 1117system.cpu.dcache.overall_mshr_hits::cpu.data 1118258 # number of overall MSHR hits 1118system.cpu.dcache.overall_mshr_hits::total 1118258 # number of overall MSHR hits 1119system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299722 # number of ReadReq MSHR misses 1120system.cpu.dcache.ReadReq_mshr_misses::total 299722 # number of ReadReq MSHR misses 1121system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148521 # number of WriteReq MSHR misses 1122system.cpu.dcache.WriteReq_mshr_misses::total 148521 # number of WriteReq MSHR misses 1123system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses 1124system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses 1125system.cpu.dcache.demand_mshr_misses::cpu.data 448243 # number of demand (read+write) MSHR misses 1126system.cpu.dcache.demand_mshr_misses::total 448243 # number of demand (read+write) MSHR misses 1127system.cpu.dcache.overall_mshr_misses::cpu.data 485840 # number of overall MSHR misses 1128system.cpu.dcache.overall_mshr_misses::total 485840 # number of overall MSHR misses 1129system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2813681816 # number of ReadReq MSHR miss cycles 1130system.cpu.dcache.ReadReq_mshr_miss_latency::total 2813681816 # number of ReadReq MSHR miss cycles 1131system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1950344957 # number of WriteReq MSHR miss cycles 1132system.cpu.dcache.WriteReq_mshr_miss_latency::total 1950344957 # number of WriteReq MSHR miss cycles 1133system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1901549750 # number of SoftPFReq MSHR miss cycles 1134system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1901549750 # number of SoftPFReq MSHR miss cycles 1135system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4764026773 # number of demand (read+write) MSHR miss cycles 1136system.cpu.dcache.demand_mshr_miss_latency::total 4764026773 # number of demand (read+write) MSHR miss cycles 1137system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6665576523 # number of overall MSHR miss cycles 1138system.cpu.dcache.overall_mshr_miss_latency::total 6665576523 # number of overall MSHR miss cycles 1139system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013583 # mshr miss rate for ReadReq accesses 1140system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013583 # mshr miss rate for ReadReq accesses 1141system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses 1142system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses 1143system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291802 # mshr miss rate for SoftPFReq accesses 1144system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291802 # mshr miss rate for SoftPFReq accesses 1145system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010694 # mshr miss rate for demand accesses 1146system.cpu.dcache.demand_mshr_miss_rate::total 0.010694 # mshr miss rate for demand accesses 1147system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses 1148system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses 1149system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9387.638598 # average ReadReq mshr miss latency 1150system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9387.638598 # average ReadReq mshr miss latency 1151system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13131.779055 # average WriteReq mshr miss latency 1152system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13131.779055 # average WriteReq mshr miss latency 1153system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50577.167061 # average SoftPFReq mshr miss latency 1154system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50577.167061 # average SoftPFReq mshr miss latency 1155system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10628.223470 # average overall mshr miss latency 1156system.cpu.dcache.demand_avg_mshr_miss_latency::total 10628.223470 # average overall mshr miss latency 1157system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13719.694803 # average overall mshr miss latency 1158system.cpu.dcache.overall_avg_mshr_miss_latency::total 13719.694803 # average overall mshr miss latency |
| 1109system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1110 1111---------- End Simulation Statistics ---------- | 1159system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1160 1161---------- End Simulation Statistics ---------- |