| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.024561 # Number of seconds simulated 4sim_ticks 24560764000 # Number of ticks simulated 5final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 104807 # Simulator instruction rate (inst/s) 8host_op_rate 148726 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36296181 # Simulator tick rate (ticks/s) 10host_mem_usage 240672 # Number of bytes of host memory used 11host_seconds 676.68 # Real time elapsed on the host |
| 12sim_insts 70920072 # Number of instructions simulated 13sim_ops 100639320 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 367552 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8319680 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8687232 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 367552 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 367552 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5661632 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5661632 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 5743 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 129995 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 135738 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 88463 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 88463 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 14965007 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 338738648 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 353703655 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 14965007 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 14965007 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 230515305 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 230515305 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 230515305 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 14965007 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 338738648 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 584218960 # Total bandwidth to/from this memory (bytes/s) |
| 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 332 unchanged lines hidden (view full) --- 377system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles 378system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses) 379system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses) 380system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses 381system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses 382system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses 383system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses 384system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses |
| 385system.cpu.icache.ReadReq_miss_rate::total 0.002824 # miss rate for ReadReq accesses |
| 386system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses |
| 387system.cpu.icache.demand_miss_rate::total 0.002824 # miss rate for demand accesses |
| 388system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses |
| 389system.cpu.icache.overall_miss_rate::total 0.002824 # miss rate for overall accesses |
| 390system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency |
| 391system.cpu.icache.ReadReq_avg_miss_latency::total 11568.616839 # average ReadReq miss latency |
| 392system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency |
| 393system.cpu.icache.demand_avg_miss_latency::total 11568.616839 # average overall miss latency |
| 394system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency |
| 395system.cpu.icache.overall_avg_miss_latency::total 11568.616839 # average overall miss latency |
| 396system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 400system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 401system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.cpu.icache.fast_writes 0 # number of fast writes performed 403system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 415system.cpu.icache.overall_mshr_misses::total 33634 # number of overall MSHR misses 416system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268782500 # number of ReadReq MSHR miss cycles 417system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles 418system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles 422system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses |
| 423system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002705 # mshr miss rate for ReadReq accesses |
| 424system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses |
| 425system.cpu.icache.demand_mshr_miss_rate::total 0.002705 # mshr miss rate for demand accesses |
| 426system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses |
| 427system.cpu.icache.overall_mshr_miss_rate::total 0.002705 # mshr miss rate for overall accesses |
| 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency |
| 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7991.392638 # average ReadReq mshr miss latency |
| 430system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency |
| 431system.cpu.icache.demand_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency |
| 432system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency |
| 433system.cpu.icache.overall_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency |
| 434system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 435system.cpu.dcache.replacements 158907 # number of replacements 436system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use 437system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks. 438system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks. 439system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks. 440system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit. 441system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor --- 39 unchanged lines hidden (view full) --- 481system.cpu.dcache.LoadLockedReq_accesses::total 19679 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.StoreCondReq_accesses::cpu.data 18406 # number of StoreCondReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::total 18406 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses 485system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses 486system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses 487system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses 488system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses |
| 489system.cpu.dcache.ReadReq_miss_rate::total 0.004158 # miss rate for ReadReq accesses |
| 490system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses |
| 491system.cpu.dcache.WriteReq_miss_rate::total 0.077587 # miss rate for WriteReq accesses |
| 492system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses |
| 493system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001779 # miss rate for LoadLockedReq accesses |
| 494system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses |
| 495system.cpu.dcache.demand_miss_rate::total 0.035602 # miss rate for demand accesses |
| 496system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses |
| 497system.cpu.dcache.overall_miss_rate::total 0.035602 # miss rate for overall accesses |
| 498system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency |
| 499system.cpu.dcache.ReadReq_avg_miss_latency::total 22097.370069 # average ReadReq miss latency |
| 500system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency |
| 501system.cpu.dcache.WriteReq_avg_miss_latency::total 34105.131348 # average WriteReq miss latency |
| 502system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency |
| 503system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12142.857143 # average LoadLockedReq miss latency |
| 504system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency |
| 505system.cpu.dcache.demand_avg_miss_latency::total 33303.352734 # average overall miss latency |
| 506system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency |
| 507system.cpu.dcache.overall_avg_miss_latency::total 33303.352734 # average overall miss latency |
| 508system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 509system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked 510system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 511system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked 512system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 513system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked 514system.cpu.dcache.fast_writes 0 # number of fast writes performed 515system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 537system.cpu.dcache.ReadReq_mshr_miss_latency::total 1049489500 # number of ReadReq MSHR miss cycles 538system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3666942000 # number of WriteReq MSHR miss cycles 539system.cpu.dcache.WriteReq_mshr_miss_latency::total 3666942000 # number of WriteReq MSHR miss cycles 540system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4716431500 # number of demand (read+write) MSHR miss cycles 541system.cpu.dcache.demand_mshr_miss_latency::total 4716431500 # number of demand (read+write) MSHR miss cycles 542system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4716431500 # number of overall MSHR miss cycles 543system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles 544system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses |
| 545system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses |
| 546system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses |
| 547system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005388 # mshr miss rate for WriteReq accesses |
| 548system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses |
| 549system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses |
| 550system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses |
| 551system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses |
| 552system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency |
| 553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18700.810763 # average ReadReq mshr miss latency |
| 554system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency |
| 555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34284.263770 # average WriteReq mshr miss latency |
| 556system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency |
| 557system.cpu.dcache.demand_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency |
| 558system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency |
| 559system.cpu.dcache.overall_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency |
| 560system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 561system.cpu.l2cache.replacements 115487 # number of replacements 562system.cpu.l2cache.tagsinuse 18346.494934 # Cycle average of tags in use 563system.cpu.l2cache.total_refs 78611 # Total number of references to valid blocks. 564system.cpu.l2cache.sampled_refs 134352 # Sample count of references to valid blocks. 565system.cpu.l2cache.avg_refs 0.585112 # Average number of references to valid blocks. 566system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 567system.cpu.l2cache.occ_blocks::writebacks 15851.533035 # Average occupied blocks per requestor --- 56 unchanged lines hidden (view full) --- 624system.cpu.l2cache.demand_accesses::cpu.inst 33555 # number of demand (read+write) accesses 625system.cpu.l2cache.demand_accesses::cpu.data 163003 # number of demand (read+write) accesses 626system.cpu.l2cache.demand_accesses::total 196558 # number of demand (read+write) accesses 627system.cpu.l2cache.overall_accesses::cpu.inst 33555 # number of overall (read+write) accesses 628system.cpu.l2cache.overall_accesses::cpu.data 163003 # number of overall (read+write) accesses 629system.cpu.l2cache.overall_accesses::total 196558 # number of overall (read+write) accesses 630system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171927 # miss rate for ReadReq accesses 631system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.489855 # miss rate for ReadReq accesses |
| 632system.cpu.l2cache.ReadReq_miss_rate::total 0.370843 # miss rate for ReadReq accesses |
| 633system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.851351 # miss rate for UpgradeReq accesses |
| 634system.cpu.l2cache.UpgradeReq_miss_rate::total 0.851351 # miss rate for UpgradeReq accesses |
| 635system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959483 # miss rate for ReadExReq accesses |
| 636system.cpu.l2cache.ReadExReq_miss_rate::total 0.959483 # miss rate for ReadExReq accesses |
| 637system.cpu.l2cache.demand_miss_rate::cpu.inst 0.171927 # miss rate for demand accesses 638system.cpu.l2cache.demand_miss_rate::cpu.data 0.797899 # miss rate for demand accesses |
| 639system.cpu.l2cache.demand_miss_rate::total 0.691038 # miss rate for demand accesses |
| 640system.cpu.l2cache.overall_miss_rate::cpu.inst 0.171927 # miss rate for overall accesses 641system.cpu.l2cache.overall_miss_rate::cpu.data 0.797899 # miss rate for overall accesses |
| 642system.cpu.l2cache.overall_miss_rate::total 0.691038 # miss rate for overall accesses |
| 643system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34232.535968 # average ReadReq miss latency 644system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34238.943690 # average ReadReq miss latency |
| 645system.cpu.l2cache.ReadReq_avg_miss_latency::total 34237.831659 # average ReadReq miss latency |
| 646system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 547.619048 # average UpgradeReq miss latency |
| 647system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 547.619048 # average UpgradeReq miss latency |
| 648system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.620761 # average ReadExReq miss latency |
| 649system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34314.620761 # average ReadExReq miss latency |
| 650system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency 651system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency |
| 652system.cpu.l2cache.demand_avg_miss_latency::total 34295.827842 # average overall miss latency |
| 653system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency 654system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency |
| 655system.cpu.l2cache.overall_avg_miss_latency::total 34295.827842 # average overall miss latency |
| 656system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 657system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 659system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 660system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 661system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 662system.cpu.l2cache.fast_writes 0 # number of fast writes performed 663system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 31 unchanged lines hidden (view full) --- 695system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178439000 # number of demand (read+write) MSHR miss cycles 696system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4047027000 # number of demand (read+write) MSHR miss cycles 697system.cpu.l2cache.demand_mshr_miss_latency::total 4225466000 # number of demand (read+write) MSHR miss cycles 698system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178439000 # number of overall MSHR miss cycles 699system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4047027000 # number of overall MSHR miss cycles 700system.cpu.l2cache.overall_mshr_miss_latency::total 4225466000 # number of overall MSHR miss cycles 701system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for ReadReq accesses 702system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488696 # mshr miss rate for ReadReq accesses |
| 703system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.369828 # mshr miss rate for ReadReq accesses |
| 704system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.851351 # mshr miss rate for UpgradeReq accesses |
| 705system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.851351 # mshr miss rate for UpgradeReq accesses |
| 706system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959483 # mshr miss rate for ReadExReq accesses |
| 707system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.959483 # mshr miss rate for ReadExReq accesses |
| 708system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for demand accesses 709system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for demand accesses |
| 710system.cpu.l2cache.demand_mshr_miss_rate::total 0.690575 # mshr miss rate for demand accesses |
| 711system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for overall accesses 712system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for overall accesses |
| 713system.cpu.l2cache.overall_mshr_miss_rate::total 0.690575 # mshr miss rate for overall accesses |
| 714system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759 # average ReadReq mshr miss latency 715system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004 # average ReadReq mshr miss latency |
| 716system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.421315 # average ReadReq mshr miss latency |
| 717system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032 # average UpgradeReq mshr miss latency |
| 718system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.746032 # average UpgradeReq mshr miss latency |
| 719system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency |
| 720system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31144.487118 # average ReadExReq mshr miss latency |
| 721system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency 722system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency |
| 723system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency |
| 724system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency 725system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency |
| 726system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency |
| 727system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 728 729---------- End Simulation Statistics ---------- |