4,5c4,5
< sim_ticks 25577832000 # Number of ticks simulated
< final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 25578307500 # Number of ticks simulated
> final_tick 25578307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 133487 # Simulator instruction rate (inst/s)
< host_op_rate 189436 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 48151664 # Simulator tick rate (ticks/s)
< host_mem_usage 268312 # Number of bytes of host memory used
< host_seconds 531.19 # Real time elapsed on the host
---
> host_inst_rate 122516 # Simulator instruction rate (inst/s)
> host_op_rate 173866 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 44194830 # Simulator tick rate (ticks/s)
> host_mem_usage 267056 # Number of bytes of host memory used
> host_seconds 578.76 # Real time elapsed on the host
14,43c14,43
< system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory
< system.physmem.bytes_read::total 8241856 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 5372416 # Number of bytes written to this memory
< system.physmem.bytes_written::total 5372416 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 128779 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 83944 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 83944 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 11662599 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 310563929 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 322226528 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 11662599 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 11662599 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 210041883 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 210041883 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 210041883 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 11662599 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 310563929 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 532268411 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 128779 # Total number of read requests seen
< system.physmem.writeReqs 83944 # Total number of write requests seen
< system.physmem.cpureqs 213035 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 8241856 # Total number of bytes read from memory
< system.physmem.bytesWritten 5372416 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 8241856 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 5372416 # bytesWritten derated as per pkt->getSize()
---
> system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory
> system.physmem.bytes_read::total 8241536 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 5372288 # Number of bytes written to this memory
> system.physmem.bytes_written::total 5372288 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 128774 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 83942 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 83942 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 11654876 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 310553151 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 322208027 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 11654876 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 11654876 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 210032974 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 210032974 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 210032974 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 11654876 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 310553151 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 532241001 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 128775 # Total number of read requests seen
> system.physmem.writeReqs 83942 # Total number of write requests seen
> system.physmem.cpureqs 213036 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 8241536 # Total number of bytes read from memory
> system.physmem.bytesWritten 5372288 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 8241536 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 5372288 # bytesWritten derated as per pkt->getSize()
45,51c45,51
< system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 7976 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 8188 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 8062 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 8171 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis
---
> system.physmem.neitherReadNorWrite 319 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 7977 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 8191 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 8064 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 8161 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 8170 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 8108 # Track reads on a per bank basis
54,60c54,60
< system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 7991 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 7993 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 8127 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 8038 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 7985 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::8 7996 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 7987 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 8126 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 8035 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 7981 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 7987 # Track reads on a per bank basis
62c62
< system.physmem.perBankWrReqs::0 5141 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::0 5142 # Track writes on a per bank basis
67c67
< system.physmem.perBankWrReqs::5 5371 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::5 5372 # Track writes on a per bank basis
70,71c70,71
< system.physmem.perBankWrReqs::8 5263 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 5277 # Track writes on a per bank basis
73c73
< system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::11 5350 # Track writes on a per bank basis
75,77c75,77
< system.physmem.perBankWrReqs::13 5125 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 5133 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 5152 # Track writes on a per bank basis
80c80
< system.physmem.totGap 25577735000 # Total gap between requests
---
> system.physmem.totGap 25578289000 # Total gap between requests
87c87
< system.physmem.readPktSize::6 128779 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 128775 # Categorize read packet sizes
94,99c94,99
< system.physmem.writePktSize::6 83944 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 83942 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 70073 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 56517 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 2103 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
127,128c127,128
< system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 3546 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 3640 # What write queue length does an incoming req see
130,131c130,131
< system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::3 3648 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see
142,143c142,143
< system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see
150,151c150,151
< system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::23 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see
153,154c153,154
< system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
159,164c159,164
< system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests
< system.physmem.totBusLat 643885000 # Total cycles spent in databus access
< system.physmem.totBankLat 1400217500 # Total cycles spent in bank access
< system.physmem.avgQLat 24884.85 # Average queueing delay per request
< system.physmem.avgBankLat 10873.20 # Average bank access latency per request
---
> system.physmem.totQLat 3208033250 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 5250782000 # Sum of mem lat for all requests
> system.physmem.totBusLat 643865000 # Total cycles spent in databus access
> system.physmem.totBankLat 1398883750 # Total cycles spent in bank access
> system.physmem.avgQLat 24912.31 # Average queueing delay per request
> system.physmem.avgBankLat 10863.18 # Average bank access latency per request
166,170c166,170
< system.physmem.avgMemAccLat 40758.05 # Average memory access latency
< system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 210.04 # Average consumed write bandwidth in MB/s
---
> system.physmem.avgMemAccLat 40775.49 # Average memory access latency
> system.physmem.avgRdBW 322.21 # Average achieved read bandwidth in MB/s
> system.physmem.avgWrBW 210.03 # Average achieved write bandwidth in MB/s
> system.physmem.avgConsumedRdBW 322.21 # Average consumed read bandwidth in MB/s
> system.physmem.avgConsumedWrBW 210.03 # Average consumed write bandwidth in MB/s
174,176c174,176
< system.physmem.avgWrQLen 9.73 # Average write queue length over time
< system.physmem.readRowHits 116758 # Number of row buffer hits during reads
< system.physmem.writeRowHits 52879 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 9.59 # Average write queue length over time
> system.physmem.readRowHits 116753 # Number of row buffer hits during reads
> system.physmem.writeRowHits 52875 # Number of row buffer hits during writes
179,184c179,184
< system.physmem.avgGap 120239.63 # Average gap between requests
< system.cpu.branchPred.lookups 16629564 # Number of BP lookups
< system.cpu.branchPred.condPredicted 12762911 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 603280 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 10503277 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 7769578 # Number of BTB hits
---
> system.physmem.avgGap 120245.63 # Average gap between requests
> system.cpu.branchPred.lookups 16623364 # Number of BP lookups
> system.cpu.branchPred.condPredicted 12760071 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 602765 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 10462695 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 7764975 # Number of BTB hits
186,188c186,188
< system.cpu.branchPred.BTBHitPct 73.972894 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1825196 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 113459 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 74.215821 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1825729 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 113390 # Number of incorrect RAS predictions.
232c232
< system.cpu.numCycles 51155665 # number of cpu cycles simulated
---
> system.cpu.numCycles 51156616 # number of cpu cycles simulated
235,249c235,249
< system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 12528030 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 85177625 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 16623364 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 9590704 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 21186632 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 2363015 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 10581483 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 556 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 11675113 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 179601 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 46030680 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.591102 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.335075 # Number of instructions fetched each cycle (Total)
251,259c251,259
< system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 1466538 3.19% 70.53% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 1380808 3.00% 73.53% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 959441 2.08% 75.61% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1192836 2.59% 78.21% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 24864286 54.02% 54.02% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2136700 4.64% 58.66% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 1964680 4.27% 62.93% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 2042011 4.44% 67.36% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 1465176 3.18% 70.55% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 1378812 3.00% 73.54% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 958023 2.08% 75.62% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1192746 2.59% 78.21% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 10028246 21.79% 100.00% # Number of instructions fetched each cycle (Total)
263,289c263,289
< system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 46030680 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.324950 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.665036 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 14611647 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 8930047 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 19464619 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 1393461 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 1630906 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 3329793 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 104768 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 116826129 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 364020 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 1630906 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 16323488 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 2561901 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 880060 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 19095828 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 5538497 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 114955733 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 140 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 16360 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 4684188 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 269 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 115265758 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 529627924 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 529622592 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 5332 # Number of floating rename lookups
291,308c291,308
< system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 274406 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 16133086 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 20210 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 20206 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13085457 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 29620481 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 22434207 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 3897313 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 4409985 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 111515856 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 35838 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 107234062 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 271666 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 10778201 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 25823888 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 2052 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 46030680 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.329622 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.987561 # Number of insts issued each cycle
310,318c310,318
< system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10772740 23.40% 23.40% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 8089543 17.57% 40.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 7436956 16.16% 57.13% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 7132439 15.49% 72.63% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 5411666 11.76% 84.39% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 3908589 8.49% 92.88% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1839107 4.00% 96.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 868081 1.89% 98.76% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 571559 1.24% 100.00% # Number of insts issued each cycle
322c322
< system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 46030680 # Number of insts issued each cycle
324,354c324,354
< system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 112263 4.55% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 1357458 55.03% 59.58% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 996979 40.42% 100.00% # attempts to use FU when none available
358,359c358,359
< system.cpu.iq.FU_type_0::IntAlu 56638968 52.80% 52.80% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 91700 0.09% 52.89% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 56624593 52.80% 52.80% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 91608 0.09% 52.89% # Type of FU issued
361c361
< system.cpu.iq.FU_type_0::FloatAdd 212 0.00% 52.89% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatAdd 187 0.00% 52.89% # Type of FU issued
387,388c387,388
< system.cpu.iq.FU_type_0::MemRead 28903478 26.95% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 21630689 20.17% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 28897959 26.95% 79.84% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 21619708 20.16% 100.00% # Type of FU issued
391,403c391,403
< system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued
< system.cpu.iq.rate 2.096836 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 107234062 # Type of FU issued
> system.cpu.iq.rate 2.096191 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 2466700 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.023003 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 263236655 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 122357738 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 105553758 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 515 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 109700502 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 2179129 # Number of loads that had data forwarded from stores
405,408c405,408
< system.cpu.iew.lsq.thread0.squashedLoads 2321749 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 6850 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 30026 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1892744 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 2313373 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 29813 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1878469 # Number of stores squashed
411,412c411,412
< system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 507 # Number of times an access to memory failed due to the cache being blocked
414,430c414,430
< system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 1630906 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 1049242 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 45608 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 111561445 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 293593 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 29620481 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 22434207 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 19918 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 6795 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 5249 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 29813 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 391440 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 181697 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 573137 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 106207608 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 28598944 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1026454 # Number of squashed instructions skipped in execute
432,440c432,440
< system.cpu.iew.exec_nop 9761 # number of nop insts executed
< system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed
< system.cpu.iew.exec_branches 14602542 # Number of branches executed
< system.cpu.iew.exec_stores 21344564 # Number of stores executed
< system.cpu.iew.exec_rate 2.076700 # Inst execution rate
< system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 53282087 # num instructions producing a value
< system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 9751 # number of nop insts executed
> system.cpu.iew.exec_refs 49933957 # number of memory reference insts executed
> system.cpu.iew.exec_branches 14599960 # Number of branches executed
> system.cpu.iew.exec_stores 21335013 # Number of stores executed
> system.cpu.iew.exec_rate 2.076127 # Inst execution rate
> system.cpu.iew.wb_sent 105772826 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 105553928 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 53290488 # num instructions producing a value
> system.cpu.iew.wb_consumers 103570522 # num instructions consuming a value
442,443c442,443
< system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 2.063349 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.514533 # average fanout of values written-back
445c445
< system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 10929916 # The number of squashed insts skipped by commit
447,450c447,450
< system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 499809 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 44399774 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 2.266508 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.764024 # Number of insts commited each cycle
452,460c452,460
< system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 15322992 34.51% 34.51% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 11640164 26.22% 60.73% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 3466305 7.81% 68.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 2879897 6.49% 75.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1880990 4.24% 79.26% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1948005 4.39% 83.65% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 685170 1.54% 85.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 565050 1.27% 86.46% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 6011201 13.54% 100.00% # Number of insts commited each cycle
464c464
< system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 44399774 # Number of insts commited each cycle
471c471
< system.cpu.commit.branches 13741505 # Number of branches committed
---
> system.cpu.commit.branches 13741485 # Number of branches committed
475c475
< system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 6011201 # number cycles where commit BW limit reached
477,480c477,480
< system.cpu.rob.rob_reads 149959530 # The number of ROB reads
< system.cpu.rob.rob_writes 224865260 # The number of ROB writes
< system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 149925618 # The number of ROB reads
> system.cpu.rob.rob_writes 224764611 # The number of ROB writes
> system.cpu.timesIdled 74074 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 5125936 # Total number of cycles that the CPU has spent unscheduled due to idling
484,492c484,492
< system.cpu.cpi 0.721441 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 511661173 # number of integer regfile reads
< system.cpu.int_regfile_writes 103341311 # number of integer regfile writes
< system.cpu.fp_regfile_reads 804 # number of floating regfile reads
< system.cpu.fp_regfile_writes 688 # number of floating regfile writes
< system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads
---
> system.cpu.cpi 0.721454 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.721454 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.386089 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.386089 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 511542927 # number of integer regfile reads
> system.cpu.int_regfile_writes 103323311 # number of integer regfile writes
> system.cpu.fp_regfile_reads 788 # number of floating regfile reads
> system.cpu.fp_regfile_writes 660 # number of floating regfile writes
> system.cpu.misc_regfile_reads 49174075 # number of misc regfile reads
494,498c494,498
< system.cpu.icache.replacements 28586 # number of replacements
< system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use
< system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks.
---
> system.cpu.icache.replacements 28620 # number of replacements
> system.cpu.icache.tagsinuse 1814.212486 # Cycle average of tags in use
> system.cpu.icache.total_refs 11640356 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 30656 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 379.708899 # Average number of references to valid blocks.
500,539c500,539
< system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 11645446 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 11645446 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 11645446 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 11645446 # number of overall hits
< system.cpu.icache.overall_hits::total 11645446 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 34686 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 34686 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 34686 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses
< system.cpu.icache.overall_misses::total 34686 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 11680132 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 11680132 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 11680132 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002970 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.002970 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked
---
> system.cpu.icache.occ_blocks::cpu.inst 1814.212486 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.885846 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.885846 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 11640361 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 11640361 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 11640361 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 11640361 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 11640361 # number of overall hits
> system.cpu.icache.overall_hits::total 11640361 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 34752 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 34752 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 34752 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 34752 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 34752 # number of overall misses
> system.cpu.icache.overall_misses::total 34752 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 732057000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 732057000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 732057000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 732057000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 732057000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 732057000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 11675113 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 11675113 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 11675113 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 11675113 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 11675113 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 11675113 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002977 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.002977 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.002977 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.002977 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.002977 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.002977 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21065.176105 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 21065.176105 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 21065.176105 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 21065.176105 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 21065.176105 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 21065.176105 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 767 # number of cycles access was blocked
541c541
< system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked
543c543
< system.cpu.icache.avg_blocked_cycles::no_mshrs 30.440000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 31.958333 # average number of cycles each access was blocked
547,576c547,576
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3741 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 3741 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 3741 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 3741 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 3741 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 3741 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30945 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 30945 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 30945 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3763 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 3763 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 3763 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 3763 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 3763 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 3763 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30989 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 30989 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 30989 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 30989 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 30989 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 30989 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 594458000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 594458000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 594458000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 594458000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 594458000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 594458000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002654 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.002654 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.002654 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19182.871341 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19182.871341 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19182.871341 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19182.871341 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19182.871341 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19182.871341 # average overall mshr miss latency
578,582c578,582
< system.cpu.l2cache.replacements 95649 # number of replacements
< system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 88124 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 126758 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 0.695215 # Average number of references to valid blocks.
---
> system.cpu.l2cache.replacements 95644 # number of replacements
> system.cpu.l2cache.tagsinuse 30089.524370 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 88146 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 126756 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 0.695399 # Average number of references to valid blocks.
584,610c584,610
< system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.822011 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.inst 0.041948 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.054317 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.918275 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 25825 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 33460 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 59285 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 129109 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 129109 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 4785 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 4785 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 25825 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 38245 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 64070 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 25825 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 38245 # number of overall hits
< system.cpu.l2cache.overall_hits::total 64070 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 4676 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 21922 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 26598 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 312 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 312 # number of UpgradeReq misses
---
> system.cpu.l2cache.occ_blocks::writebacks 26934.597461 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 1374.602931 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 1780.323979 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.821979 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.041950 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.054331 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.918259 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 25863 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 33463 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 59326 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 129088 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 129088 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 19 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 19 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 4769 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 4769 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 25863 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 38232 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 64095 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 25863 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 38232 # number of overall hits
> system.cpu.l2cache.overall_hits::total 64095 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 4674 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 21921 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 26595 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 319 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 319 # number of UpgradeReq misses
613,621c613,621
< system.cpu.l2cache.demand_misses::cpu.inst 4676 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 124179 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 128855 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 4676 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 124179 # number of overall misses
< system.cpu.l2cache.overall_misses::total 128855 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.demand_misses::cpu.inst 4674 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 124178 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 128852 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 4674 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 124178 # number of overall misses
> system.cpu.l2cache.overall_misses::total 128852 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 304002000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1479409000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1783411000 # number of ReadReq miss cycles
624,672c624,672
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6641217500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 30501 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 55382 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 85883 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 129109 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 129109 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 332 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 332 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 107042 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 107042 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 30501 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 162424 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 192925 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 30501 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 162424 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 192925 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.153306 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395833 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.309700 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.939759 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.939759 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955298 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.955298 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153306 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.764536 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.667902 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153306 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.764536 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.667902 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.717949 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.717949 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6653931500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6653931500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 304002000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8133340500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8437342500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 304002000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8133340500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8437342500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 30537 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 55384 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 85921 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 129088 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 129088 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 338 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 338 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 107026 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 107026 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 30537 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 162410 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 192947 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 30537 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 162410 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 192947 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.153060 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395800 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.309529 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.943787 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.943787 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955441 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.955441 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153060 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.764596 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.667810 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153060 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.764596 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.667810 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65041.078306 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67488.207655 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 67058.131228 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 72.100313 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 72.100313 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65070.669979 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65070.669979 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65041.078306 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65497.435133 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 65480.881166 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65041.078306 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65497.435133 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 65480.881166 # average overall miss latency
681,682c681,682
< system.cpu.l2cache.writebacks::writebacks 83944 # number of writebacks
< system.cpu.l2cache.writebacks::total 83944 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 83942 # number of writebacks
> system.cpu.l2cache.writebacks::total 83942 # number of writebacks
684,685c684,685
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
687,688c687,688
< system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
690,696c690,696
< system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21861 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 26522 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 312 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 312 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4659 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21859 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 26518 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 319 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 319 # number of UpgradeReq MSHR misses
699,743c699,743
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 128779 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251555285 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461018603 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5385248857 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.939759 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.939759 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955298 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955298 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 4659 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 124116 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 128775 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 4659 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 124116 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 128775 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 245046791 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1206365816 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1451412607 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3199316 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3199316 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5398042204 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5398042204 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245046791 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6604408020 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6849454811 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245046791 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6604408020 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6849454811 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394681 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308632 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.943787 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.943787 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955441 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955441 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764214 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.667411 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764214 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.667411 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52596.435072 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55188.518047 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54733.109850 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.203762 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.203762 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52788.974877 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52788.974877 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52596.435072 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53211.576429 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53189.320994 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52596.435072 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53211.576429 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53189.320994 # average overall mshr miss latency
745,749c745,749
< system.cpu.dcache.replacements 158328 # number of replacements
< system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use
< system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks.
---
> system.cpu.dcache.replacements 158314 # number of replacements
> system.cpu.dcache.tagsinuse 4072.315596 # Cycle average of tags in use
> system.cpu.dcache.total_refs 44364658 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 162410 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 273.164571 # Average number of references to valid blocks.
751c751
< system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor
---
> system.cpu.dcache.occ_blocks::cpu.data 4072.315596 # Average occupied blocks per requestor
754,759c754,759
< system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 26064858 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 26064858 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18267205 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18267205 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits
762,769c762,769
< system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits
< system.cpu.dcache.overall_hits::total 44337915 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 44332063 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 44332063 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 44332063 # number of overall hits
> system.cpu.dcache.overall_hits::total 44332063 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 124444 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 124444 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1582696 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1582696 # number of WriteReq misses
772,787c772,787
< system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses
< system.cpu.dcache.overall_misses::total 1707154 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4246899000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 1707140 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1707140 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1707140 # number of overall misses
> system.cpu.dcache.overall_misses::total 1707140 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 4243660500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 4243660500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 98452063982 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 98452063982 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1297000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 1297000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 102695724482 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 102695724482 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 102695724482 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 102695724482 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 26189302 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 26189302 # number of ReadReq accesses(hits+misses)
790,791c790,791
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16026 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 16026 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16031 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 16031 # number of LoadLockedReq accesses(hits+misses)
794,797c794,797
< system.cpu.dcache.demand_accesses::cpu.data 46045069 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 46045069 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 46045069 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 46045069 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 46039203 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 46039203 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 46039203 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 46039203 # number of overall (read+write) accesses
800,818c800,818
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079732 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.079732 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002808 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002808 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079733 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.079733 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002807 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002807 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.037080 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.037080 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.037080 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.037080 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34100.965093 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34100.965093 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62205.290202 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62205.290202 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28822.222222 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28822.222222 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 60156.592009 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 60156.592009 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 5240 # number of cycles access was blocked
820c820
< system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 121 # number of cycles access was blocked
822c822
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.352459 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.305785 # average number of cycles each access was blocked
826,831c826,831
< system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks
< system.cpu.dcache.writebacks::total 129109 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 129088 # number of writebacks
> system.cpu.dcache.writebacks::total 129088 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69028 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 69028 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475364 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1475364 # number of WriteReq MSHR hits
834,857c834,857
< system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 107343 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 162756 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 1544392 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1544392 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1544392 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1544392 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55416 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 55416 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 162748 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 162748 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 162748 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 162748 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1874890000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 1874890000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6816019991 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6816019991 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8690909991 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8690909991 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8690909991 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8690909991 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses
862,869c862,869
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33833.008517 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33833.008517 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63504.080712 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63504.080712 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency