7,11c7,11
< host_inst_rate 153227 # Simulator instruction rate (inst/s)
< host_op_rate 217448 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 55271946 # Simulator tick rate (ticks/s)
< host_mem_usage 270340 # Number of bytes of host memory used
< host_seconds 462.76 # Real time elapsed on the host
---
> host_inst_rate 133487 # Simulator instruction rate (inst/s)
> host_op_rate 189436 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 48151664 # Simulator tick rate (ticks/s)
> host_mem_usage 268312 # Number of bytes of host memory used
> host_seconds 531.19 # Real time elapsed on the host
88,110c88,97
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 83944 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 312 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
< system.physmem.rdQLenPdf::0 70134 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 56500 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 2062 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 83944 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see
140,141c127
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
< system.physmem.wrQLenPdf::0 3542 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see
164c150
< system.physmem.wrQLenPdf::23 108 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see
173,175c159,160
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 3204614448 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 5248634448 # Sum of mem lat for all requests
---
> system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests
177,179c162,164
< system.physmem.totBankLat 1400135000 # Total cycles spent in bank access
< system.physmem.avgQLat 24884.99 # Average queueing delay per request
< system.physmem.avgBankLat 10872.55 # Average bank access latency per request
---
> system.physmem.totBankLat 1400217500 # Total cycles spent in bank access
> system.physmem.avgQLat 24884.85 # Average queueing delay per request
> system.physmem.avgBankLat 10873.20 # Average bank access latency per request
181c166
< system.physmem.avgMemAccLat 40757.55 # Average memory access latency
---
> system.physmem.avgMemAccLat 40758.05 # Average memory access latency
250c235
< system.cpu.fetch.icacheStallCycles 12532709 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss
256c241
< system.cpu.fetch.BlockedCycles 10561174 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked
261,264c246,249
< system.cpu.fetch.IcacheSquashes 179650 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 46029302 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.592220 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.335381 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total)
266c251
< system.cpu.fetch.rateDist::0 24855702 54.00% 54.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total)
278c263
< system.cpu.fetch.rateDist::total 46029302 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total)
281,284c266,269
< system.cpu.decode.IdleCycles 14615111 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 8910636 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 19475070 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 1390460 # Number of cycles decode is unblocking
---
> system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking
288c273
< system.cpu.decode.DecodedInsts 116875392 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode
291,296c276,281
< system.cpu.rename.IdleCycles 16327930 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 2553995 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 876400 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 19102314 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 5530638 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 115006216 # Number of instructions processed by rename
---
> system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename
299c284
< system.cpu.rename.LSQFullEvents 4672566 # Number of times rename has blocked due to LSQ full
---
> system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full
301,303c286,288
< system.cpu.rename.RenamedOperands 115315088 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 529845526 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 529838425 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups
306c291
< system.cpu.rename.UndoneMaps 16182416 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing
309c294
< system.cpu.rename.skidInsts 13070329 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer
313c298
< system.cpu.memDep0.conflictingStores 4365711 # Number of conflicting stores.
---
> system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores.
321,323c306,308
< system.cpu.iq.issued_per_cycle::samples 46029302 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.330365 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.988633 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle
325,331c310,316
< system.cpu.iq.issued_per_cycle::0 10776543 23.41% 23.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 8085599 17.57% 40.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 7427656 16.14% 57.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 7135117 15.50% 72.62% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 5408591 11.75% 84.37% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 3911102 8.50% 92.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1839411 4.00% 96.86% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle
337c322
< system.cpu.iq.issued_per_cycle::total 46029302 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle
369c354
< system.cpu.iq.fu_full::MemWrite 1003479 40.72% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available
408,410c393,395
< system.cpu.iq.fu_busy_cnt 2464043 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.022972 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 263297262 # Number of integer instruction queue reads
---
> system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads
412c397
< system.cpu.iq.int_inst_queue_wakeup_accesses 105577839 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses
416c401
< system.cpu.iq.int_alu_accesses 109728805 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses
430,431c415,416
< system.cpu.iew.iewBlockCycles 1048423 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 45681 # Number of cycles IEW is unblocking
---
> system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking
438c423
< system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall
443c428
< system.cpu.iew.iewExecutedInsts 106234972 # Number of executed instructions
---
> system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions
445c430
< system.cpu.iew.iewExecSquashedInsts 1030082 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute
452,453c437,438
< system.cpu.iew.wb_sent 105797759 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 105578008 # cumulative count of insts written-back
---
> system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back
455c440
< system.cpu.iew.wb_consumers 103565148 # num instructions consuming a value
---
> system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value
463,465c448,450
< system.cpu.commit.committed_per_cycle::samples 44391277 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 2.266941 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.764740 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle
467,469c452,454
< system.cpu.commit.committed_per_cycle::0 15317735 34.51% 34.51% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 11646185 26.24% 60.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 3462928 7.80% 68.54% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle
471,475c456,460
< system.cpu.commit.committed_per_cycle::4 1875712 4.23% 79.24% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1949355 4.39% 83.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 685853 1.55% 85.18% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 564106 1.27% 86.45% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 6015739 13.55% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle
479c464
< system.cpu.commit.committed_per_cycle::total 44391277 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle
490c475
< system.cpu.commit.bw_lim_events 6015739 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached
492c477
< system.cpu.rob.rob_reads 149959303 # The number of ROB reads
---
> system.cpu.rob.rob_reads 149959530 # The number of ROB reads
494,495c479,480
< system.cpu.timesIdled 74068 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 5126363 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling
503,504c488,489
< system.cpu.int_regfile_reads 511661177 # number of integer regfile reads
< system.cpu.int_regfile_writes 103341315 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 511661173 # number of integer regfile reads
> system.cpu.int_regfile_writes 103341311 # number of integer regfile writes
510c495
< system.cpu.icache.tagsinuse 1814.278230 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use
515c500
< system.cpu.icache.occ_blocks::cpu.inst 1814.278230 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor
530,535c515,520
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 739119000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 739119000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 739119000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 739119000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 739119000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 739119000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles
548,553c533,538
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21308.856599 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 21308.856599 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 21308.856599 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 21308.856599 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency
574,579c559,564
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600341000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 600341000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600341000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 600341000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600341000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 600341000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles
586,591c571,576
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19400.258523 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19400.258523 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
594c579
< system.cpu.l2cache.tagsinuse 30090.049168 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use
599,601c584,586
< system.cpu.l2cache.occ_blocks::writebacks 26935.644891 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 1374.538058 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 1779.866218 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor
634,636c619,621
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310311500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482845500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1793157000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles
639,646c624,631
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6640773000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6640773000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 310311500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8123618500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 8433930000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 310311500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8123618500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 8433930000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6641217500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles
675,677c660,662
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66362.596236 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67641.889426 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 67416.986240 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency
680,687c665,672
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64941.989301 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64941.989301 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 65452.873385 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 65452.873385 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency
720,722c705,707
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251333698 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209966181 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461299879 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251555285 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461018603 # number of ReadReq MSHR miss cycles
725,732c710,717
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5384861495 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5384861495 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251333698 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594827676 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6846161374 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251333698 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594827676 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 6846161374 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5385248857 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles
746,748c731,733
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53922.698563 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55348.162527 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55097.650215 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency
751,758c736,743
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52660.077012 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52660.077012 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
761,762c746,747
< system.cpu.dcache.tagsinuse 4072.315266 # Cycle average of tags in use
< system.cpu.dcache.total_refs 44370475 # Total number of references to valid blocks.
---
> system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use
> system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks.
764c749
< system.cpu.dcache.avg_refs 273.176840 # Average number of references to valid blocks.
---
> system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks.
766c751
< system.cpu.dcache.occ_blocks::cpu.data 4072.315266 # Average occupied blocks per requestor
---
> system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor
769,770c754,755
< system.cpu.dcache.ReadReq_hits::cpu.data 26070698 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 26070698 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits
777,782c762,767
< system.cpu.dcache.demand_hits::cpu.data 44337922 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 44337922 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 44337922 # number of overall hits
< system.cpu.dcache.overall_hits::total 44337922 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 124470 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 124470 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits
> system.cpu.dcache.overall_hits::total 44337915 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses
787,794c772,779
< system.cpu.dcache.demand_misses::cpu.data 1707147 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1707147 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1707147 # number of overall misses
< system.cpu.dcache.overall_misses::total 1707147 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247957000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4247957000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 98254010480 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 98254010480 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses
> system.cpu.dcache.overall_misses::total 1707154 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 4246899000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles
797,800c782,785
< system.cpu.dcache.demand_miss_latency::cpu.data 102501967480 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 102501967480 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 102501967480 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 102501967480 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles
823,826c808,811
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34128.360247 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34128.360247 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62080.898680 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62080.898680 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency
829,832c814,817
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 60042.847792 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 60042.847792 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency
843,844c828,829
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69057 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 69057 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits
849,852c834,837
< system.cpu.dcache.demand_mshr_hits::cpu.data 1544391 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1544391 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1544391 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1544391 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits
861,868c846,853
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878248000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878248000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6802862990 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6802862990 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681110990 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8681110990 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681110990 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8681110990 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles
877,884c862,869
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33895.439698 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33895.439698 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63375.003400 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63375.003400 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
< host_inst_rate 153227 # Simulator instruction rate (inst/s)
< host_op_rate 217448 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 55271946 # Simulator tick rate (ticks/s)
< host_mem_usage 270340 # Number of bytes of host memory used
< host_seconds 462.76 # Real time elapsed on the host
---
> host_inst_rate 133487 # Simulator instruction rate (inst/s)
> host_op_rate 189436 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 48151664 # Simulator tick rate (ticks/s)
> host_mem_usage 268312 # Number of bytes of host memory used
> host_seconds 531.19 # Real time elapsed on the host
88,110c88,97
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 83944 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 312 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
< system.physmem.rdQLenPdf::0 70134 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 56500 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 2062 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 83944 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see
140,141c127
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
< system.physmem.wrQLenPdf::0 3542 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see
164c150
< system.physmem.wrQLenPdf::23 108 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see
173,175c159,160
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 3204614448 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 5248634448 # Sum of mem lat for all requests
---
> system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests
177,179c162,164
< system.physmem.totBankLat 1400135000 # Total cycles spent in bank access
< system.physmem.avgQLat 24884.99 # Average queueing delay per request
< system.physmem.avgBankLat 10872.55 # Average bank access latency per request
---
> system.physmem.totBankLat 1400217500 # Total cycles spent in bank access
> system.physmem.avgQLat 24884.85 # Average queueing delay per request
> system.physmem.avgBankLat 10873.20 # Average bank access latency per request
181c166
< system.physmem.avgMemAccLat 40757.55 # Average memory access latency
---
> system.physmem.avgMemAccLat 40758.05 # Average memory access latency
250c235
< system.cpu.fetch.icacheStallCycles 12532709 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss
256c241
< system.cpu.fetch.BlockedCycles 10561174 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked
261,264c246,249
< system.cpu.fetch.IcacheSquashes 179650 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 46029302 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.592220 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.335381 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total)
266c251
< system.cpu.fetch.rateDist::0 24855702 54.00% 54.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total)
278c263
< system.cpu.fetch.rateDist::total 46029302 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total)
281,284c266,269
< system.cpu.decode.IdleCycles 14615111 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 8910636 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 19475070 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 1390460 # Number of cycles decode is unblocking
---
> system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking
288c273
< system.cpu.decode.DecodedInsts 116875392 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode
291,296c276,281
< system.cpu.rename.IdleCycles 16327930 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 2553995 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 876400 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 19102314 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 5530638 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 115006216 # Number of instructions processed by rename
---
> system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename
299c284
< system.cpu.rename.LSQFullEvents 4672566 # Number of times rename has blocked due to LSQ full
---
> system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full
301,303c286,288
< system.cpu.rename.RenamedOperands 115315088 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 529845526 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 529838425 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups
306c291
< system.cpu.rename.UndoneMaps 16182416 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing
309c294
< system.cpu.rename.skidInsts 13070329 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer
313c298
< system.cpu.memDep0.conflictingStores 4365711 # Number of conflicting stores.
---
> system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores.
321,323c306,308
< system.cpu.iq.issued_per_cycle::samples 46029302 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.330365 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.988633 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle
325,331c310,316
< system.cpu.iq.issued_per_cycle::0 10776543 23.41% 23.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 8085599 17.57% 40.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 7427656 16.14% 57.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 7135117 15.50% 72.62% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 5408591 11.75% 84.37% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 3911102 8.50% 92.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1839411 4.00% 96.86% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle
337c322
< system.cpu.iq.issued_per_cycle::total 46029302 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle
369c354
< system.cpu.iq.fu_full::MemWrite 1003479 40.72% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available
408,410c393,395
< system.cpu.iq.fu_busy_cnt 2464043 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.022972 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 263297262 # Number of integer instruction queue reads
---
> system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads
412c397
< system.cpu.iq.int_inst_queue_wakeup_accesses 105577839 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses
416c401
< system.cpu.iq.int_alu_accesses 109728805 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses
430,431c415,416
< system.cpu.iew.iewBlockCycles 1048423 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 45681 # Number of cycles IEW is unblocking
---
> system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking
438c423
< system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall
443c428
< system.cpu.iew.iewExecutedInsts 106234972 # Number of executed instructions
---
> system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions
445c430
< system.cpu.iew.iewExecSquashedInsts 1030082 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute
452,453c437,438
< system.cpu.iew.wb_sent 105797759 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 105578008 # cumulative count of insts written-back
---
> system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back
455c440
< system.cpu.iew.wb_consumers 103565148 # num instructions consuming a value
---
> system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value
463,465c448,450
< system.cpu.commit.committed_per_cycle::samples 44391277 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 2.266941 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.764740 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle
467,469c452,454
< system.cpu.commit.committed_per_cycle::0 15317735 34.51% 34.51% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 11646185 26.24% 60.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 3462928 7.80% 68.54% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle
471,475c456,460
< system.cpu.commit.committed_per_cycle::4 1875712 4.23% 79.24% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1949355 4.39% 83.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 685853 1.55% 85.18% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 564106 1.27% 86.45% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 6015739 13.55% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle
479c464
< system.cpu.commit.committed_per_cycle::total 44391277 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle
490c475
< system.cpu.commit.bw_lim_events 6015739 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached
492c477
< system.cpu.rob.rob_reads 149959303 # The number of ROB reads
---
> system.cpu.rob.rob_reads 149959530 # The number of ROB reads
494,495c479,480
< system.cpu.timesIdled 74068 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 5126363 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling
503,504c488,489
< system.cpu.int_regfile_reads 511661177 # number of integer regfile reads
< system.cpu.int_regfile_writes 103341315 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 511661173 # number of integer regfile reads
> system.cpu.int_regfile_writes 103341311 # number of integer regfile writes
510c495
< system.cpu.icache.tagsinuse 1814.278230 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use
515c500
< system.cpu.icache.occ_blocks::cpu.inst 1814.278230 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor
530,535c515,520
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 739119000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 739119000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 739119000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 739119000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 739119000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 739119000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles
548,553c533,538
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21308.856599 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 21308.856599 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 21308.856599 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 21308.856599 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency
574,579c559,564
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600341000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 600341000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600341000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 600341000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600341000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 600341000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles
586,591c571,576
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19400.258523 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19400.258523 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
594c579
< system.cpu.l2cache.tagsinuse 30090.049168 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use
599,601c584,586
< system.cpu.l2cache.occ_blocks::writebacks 26935.644891 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 1374.538058 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 1779.866218 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor
634,636c619,621
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310311500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482845500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1793157000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles
639,646c624,631
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6640773000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6640773000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 310311500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8123618500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 8433930000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 310311500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8123618500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 8433930000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6641217500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles
675,677c660,662
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66362.596236 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67641.889426 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 67416.986240 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency
680,687c665,672
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64941.989301 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64941.989301 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 65452.873385 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 65452.873385 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency
720,722c705,707
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251333698 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209966181 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461299879 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251555285 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461018603 # number of ReadReq MSHR miss cycles
725,732c710,717
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5384861495 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5384861495 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251333698 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594827676 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6846161374 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251333698 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594827676 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 6846161374 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5385248857 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles
746,748c731,733
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53922.698563 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55348.162527 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55097.650215 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency
751,758c736,743
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52660.077012 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52660.077012 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
761,762c746,747
< system.cpu.dcache.tagsinuse 4072.315266 # Cycle average of tags in use
< system.cpu.dcache.total_refs 44370475 # Total number of references to valid blocks.
---
> system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use
> system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks.
764c749
< system.cpu.dcache.avg_refs 273.176840 # Average number of references to valid blocks.
---
> system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks.
766c751
< system.cpu.dcache.occ_blocks::cpu.data 4072.315266 # Average occupied blocks per requestor
---
> system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor
769,770c754,755
< system.cpu.dcache.ReadReq_hits::cpu.data 26070698 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 26070698 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits
777,782c762,767
< system.cpu.dcache.demand_hits::cpu.data 44337922 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 44337922 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 44337922 # number of overall hits
< system.cpu.dcache.overall_hits::total 44337922 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 124470 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 124470 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits
> system.cpu.dcache.overall_hits::total 44337915 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses
787,794c772,779
< system.cpu.dcache.demand_misses::cpu.data 1707147 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1707147 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1707147 # number of overall misses
< system.cpu.dcache.overall_misses::total 1707147 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247957000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4247957000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 98254010480 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 98254010480 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses
> system.cpu.dcache.overall_misses::total 1707154 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 4246899000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles
797,800c782,785
< system.cpu.dcache.demand_miss_latency::cpu.data 102501967480 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 102501967480 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 102501967480 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 102501967480 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles
823,826c808,811
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34128.360247 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 34128.360247 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62080.898680 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62080.898680 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency
829,832c814,817
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 60042.847792 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 60042.847792 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency
843,844c828,829
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69057 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 69057 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits
849,852c834,837
< system.cpu.dcache.demand_mshr_hits::cpu.data 1544391 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1544391 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1544391 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1544391 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits
861,868c846,853
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878248000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878248000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6802862990 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6802862990 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681110990 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8681110990 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681110990 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8681110990 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles
877,884c862,869
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33895.439698 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33895.439698 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63375.003400 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63375.003400 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency