7,11c7,11
< host_inst_rate 139577 # Simulator instruction rate (inst/s)
< host_op_rate 198063 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 51742306 # Simulator tick rate (ticks/s)
< host_mem_usage 305460 # Number of bytes of host memory used
< host_seconds 508.14 # Real time elapsed on the host
---
> host_inst_rate 43892 # Simulator instruction rate (inst/s)
> host_op_rate 62284 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 16271073 # Simulator tick rate (ticks/s)
> host_mem_usage 263196 # Number of bytes of host memory used
> host_seconds 1615.90 # Real time elapsed on the host
80c80
< system.physmem.totGap 26292446500 # Total gap between requests
---
> system.physmem.totGap 26292447500 # Total gap between requests
174,175c174,175
< system.physmem.totQLat 4868161034 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 6756433034 # Sum of mem lat for all requests
---
> system.physmem.totQLat 4868163034 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 6756435034 # Sum of mem lat for all requests
178c178
< system.physmem.avgQLat 37803.91 # Average queueing delay per request
---
> system.physmem.avgQLat 37803.93 # Average queueing delay per request
181c181
< system.physmem.avgMemAccLat 52467.37 # Average memory access latency
---
> system.physmem.avgMemAccLat 52467.38 # Average memory access latency
249c249
< system.cpu.fetch.icacheStallCycles 12549160 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 12549163 # Number of cycles fetch is stalled on an Icache miss
255,256c255,256
< system.cpu.fetch.BlockedCycles 10606958 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.BlockedCycles 10606959 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
259,262c259,262
< system.cpu.fetch.CacheLines 11672224 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 180779 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 46048900 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.587178 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 11672225 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 180780 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 46048903 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.587177 # Number of instructions fetched each cycle (Total)
265c265
< system.cpu.fetch.rateDist::0 24897026 54.07% 54.07% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 24897029 54.07% 54.07% # Number of instructions fetched each cycle (Total)
277c277
< system.cpu.fetch.rateDist::total 46048900 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 46048903 # Number of instructions fetched each cycle (Total)
281c281
< system.cpu.decode.BlockedCycles 8956467 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 8956470 # Number of cycles decode is blocked
292,293c292,293
< system.cpu.rename.serializeStallCycles 926852 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 19086495 # Number of cycles rename is running
---
> system.cpu.rename.serializeStallCycles 926854 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 19086496 # Number of cycles rename is running
295c295
< system.cpu.rename.RenamedInsts 114852318 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 114852319 # Number of instructions processed by rename
300,302c300,302
< system.cpu.rename.RenamedOperands 115176508 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 529186359 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 529181674 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 115176509 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 529186363 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 529181678 # Number of integer rename lookups
305c305
< system.cpu.rename.UndoneMaps 16015892 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 16015893 # Number of HB maps that are undone due to squashing
320c320
< system.cpu.iq.issued_per_cycle::samples 46048900 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 46048903 # Number of insts issued each cycle
324c324
< system.cpu.iq.issued_per_cycle::0 10795987 23.44% 23.44% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10795990 23.44% 23.44% # Number of insts issued each cycle
336c336
< system.cpu.iq.issued_per_cycle::total 46048900 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 46048903 # Number of insts issued each cycle
409c409
< system.cpu.iq.int_inst_queue_reads 263189734 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 263189737 # Number of integer instruction queue reads
432c432
< system.cpu.iew.iewDispSquashedInsts 290951 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 290952 # Number of squashed instructions skipped by dispatch
462c462
< system.cpu.commit.committed_per_cycle::samples 44431401 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 44431403 # Number of insts commited each cycle
466c466
< system.cpu.commit.committed_per_cycle::0 15343377 34.53% 34.53% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 15343379 34.53% 34.53% # Number of insts commited each cycle
478c478
< system.cpu.commit.committed_per_cycle::total 44431401 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 44431403 # Number of insts commited each cycle
491c491
< system.cpu.rob.rob_reads 149890854 # The number of ROB reads
---
> system.cpu.rob.rob_reads 149890856 # The number of ROB reads
494c494
< system.cpu.idleCycles 6536033 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 6536030 # Total number of cycles that the CPU has spent unscheduled due to idling
509c509
< system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 1820.333458 # Cycle average of tags in use
514c514
< system.cpu.icache.occ_blocks::cpu.inst 1820.333452 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 1820.333458 # Average occupied blocks per requestor
523,540c523,540
< system.cpu.icache.ReadReq_misses::cpu.inst 36657 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 36657 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 36657 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 36657 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 36657 # number of overall misses
< system.cpu.icache.overall_misses::total 36657 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 709011999 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 709011999 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 709011999 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 709011999 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 709011999 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 709011999 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 11672224 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 11672224 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 11672224 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 11672224 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 11672224 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 11672224 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 36658 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 36658 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 36658 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 36658 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 36658 # number of overall misses
> system.cpu.icache.overall_misses::total 36658 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 709083999 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 709083999 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 709083999 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 709083999 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 709083999 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 709083999 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 11672225 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 11672225 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 11672225 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 11672225 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 11672225 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 11672225 # number of overall (read+write) accesses
547,552c547,552
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19341.790081 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19341.790081 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19341.790081 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19341.790081 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19343.226554 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 19343.226554 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 19343.226554 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 19343.226554 # average overall miss latency
561,566c561,566
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits
573,578c573,578
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580604499 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 580604499 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580604499 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 580604499 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580604499 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 580604499 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580605499 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 580605499 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580605499 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 580605499 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580605499 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 580605499 # number of overall MSHR miss cycles
585,590c585,590
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.139734 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.139734 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.170144 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.170144 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency
592,717d591
< system.cpu.dcache.replacements 158306 # number of replacements
< system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use
< system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
< system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
< system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
< system.cpu.dcache.writebacks::total 129052 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
719c593
< system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 30136.955699 # Cycle average of tags in use
725,726c599,600
< system.cpu.l2cache.occ_blocks::cpu.inst 1379.489976 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 1876.569805 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 1379.489982 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 1876.569807 # Average occupied blocks per requestor
759,761c633,635
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269870000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664898500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1934768500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269871000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664900000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1934771000 # number of ReadReq miss cycles
766,771c640,645
< system.cpu.l2cache.demand_miss_latency::cpu.inst 269870000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9756860500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10026730500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 269870000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9756860500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10026730500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 269871000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9756862000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 10026733000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 269871000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9756862000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 10026733000 # number of overall miss cycles
800,802c674,676
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.529915 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.727812 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.332581 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.743590 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.796258 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.426584 # average ReadReq miss latency
807,812c681,686
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 77816.474067 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 77816.474067 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77816.493469 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77816.493469 # average overall miss latency
845c719
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210181444 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210183444 # number of ReadReq MSHR miss cycles
847c721
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600023524 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600025524 # number of ReadReq MSHR miss cycles
852c726
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210181444 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210183444 # number of demand (read+write) MSHR miss cycles
854,855c728,729
< system.cpu.l2cache.demand_mshr_miss_latency::total 8421265207 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210181444 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 8421267207 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210183444 # number of overall MSHR miss cycles
857c731
< system.cpu.l2cache.overall_mshr_miss_latency::total 8421265207 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 8421267207 # number of overall MSHR miss cycles
871c745
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45064.632075 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45065.060892 # average ReadReq mshr miss latency
873c747
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.437163 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.512575 # average ReadReq mshr miss latency
878c752
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency
880,881c754,755
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency
883c757
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency
884a759,884
> system.cpu.dcache.replacements 158306 # number of replacements
> system.cpu.dcache.tagsinuse 4072.986678 # Cycle average of tags in use
> system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4072.986678 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
> system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
> system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670086500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 4670086500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 124709259481 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 124709259481 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 124709259481 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 124709259481 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.307299 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.307299 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 72956.568898 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 72956.568898 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
> system.cpu.dcache.writebacks::total 129052 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060279000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060279000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313871492 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10313871492 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313871492 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10313871492 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.809104 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.809104 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< host_inst_rate 139577 # Simulator instruction rate (inst/s)
< host_op_rate 198063 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 51742306 # Simulator tick rate (ticks/s)
< host_mem_usage 305460 # Number of bytes of host memory used
< host_seconds 508.14 # Real time elapsed on the host
---
> host_inst_rate 43892 # Simulator instruction rate (inst/s)
> host_op_rate 62284 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 16271073 # Simulator tick rate (ticks/s)
> host_mem_usage 263196 # Number of bytes of host memory used
> host_seconds 1615.90 # Real time elapsed on the host
80c80
< system.physmem.totGap 26292446500 # Total gap between requests
---
> system.physmem.totGap 26292447500 # Total gap between requests
174,175c174,175
< system.physmem.totQLat 4868161034 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 6756433034 # Sum of mem lat for all requests
---
> system.physmem.totQLat 4868163034 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 6756435034 # Sum of mem lat for all requests
178c178
< system.physmem.avgQLat 37803.91 # Average queueing delay per request
---
> system.physmem.avgQLat 37803.93 # Average queueing delay per request
181c181
< system.physmem.avgMemAccLat 52467.37 # Average memory access latency
---
> system.physmem.avgMemAccLat 52467.38 # Average memory access latency
249c249
< system.cpu.fetch.icacheStallCycles 12549160 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 12549163 # Number of cycles fetch is stalled on an Icache miss
255,256c255,256
< system.cpu.fetch.BlockedCycles 10606958 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.BlockedCycles 10606959 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
259,262c259,262
< system.cpu.fetch.CacheLines 11672224 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 180779 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 46048900 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.587178 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 11672225 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 180780 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 46048903 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.587177 # Number of instructions fetched each cycle (Total)
265c265
< system.cpu.fetch.rateDist::0 24897026 54.07% 54.07% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 24897029 54.07% 54.07% # Number of instructions fetched each cycle (Total)
277c277
< system.cpu.fetch.rateDist::total 46048900 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 46048903 # Number of instructions fetched each cycle (Total)
281c281
< system.cpu.decode.BlockedCycles 8956467 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 8956470 # Number of cycles decode is blocked
292,293c292,293
< system.cpu.rename.serializeStallCycles 926852 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 19086495 # Number of cycles rename is running
---
> system.cpu.rename.serializeStallCycles 926854 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 19086496 # Number of cycles rename is running
295c295
< system.cpu.rename.RenamedInsts 114852318 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 114852319 # Number of instructions processed by rename
300,302c300,302
< system.cpu.rename.RenamedOperands 115176508 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 529186359 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 529181674 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 115176509 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 529186363 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 529181678 # Number of integer rename lookups
305c305
< system.cpu.rename.UndoneMaps 16015892 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 16015893 # Number of HB maps that are undone due to squashing
320c320
< system.cpu.iq.issued_per_cycle::samples 46048900 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 46048903 # Number of insts issued each cycle
324c324
< system.cpu.iq.issued_per_cycle::0 10795987 23.44% 23.44% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10795990 23.44% 23.44% # Number of insts issued each cycle
336c336
< system.cpu.iq.issued_per_cycle::total 46048900 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 46048903 # Number of insts issued each cycle
409c409
< system.cpu.iq.int_inst_queue_reads 263189734 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 263189737 # Number of integer instruction queue reads
432c432
< system.cpu.iew.iewDispSquashedInsts 290951 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 290952 # Number of squashed instructions skipped by dispatch
462c462
< system.cpu.commit.committed_per_cycle::samples 44431401 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 44431403 # Number of insts commited each cycle
466c466
< system.cpu.commit.committed_per_cycle::0 15343377 34.53% 34.53% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 15343379 34.53% 34.53% # Number of insts commited each cycle
478c478
< system.cpu.commit.committed_per_cycle::total 44431401 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 44431403 # Number of insts commited each cycle
491c491
< system.cpu.rob.rob_reads 149890854 # The number of ROB reads
---
> system.cpu.rob.rob_reads 149890856 # The number of ROB reads
494c494
< system.cpu.idleCycles 6536033 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 6536030 # Total number of cycles that the CPU has spent unscheduled due to idling
509c509
< system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 1820.333458 # Cycle average of tags in use
514c514
< system.cpu.icache.occ_blocks::cpu.inst 1820.333452 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 1820.333458 # Average occupied blocks per requestor
523,540c523,540
< system.cpu.icache.ReadReq_misses::cpu.inst 36657 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 36657 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 36657 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 36657 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 36657 # number of overall misses
< system.cpu.icache.overall_misses::total 36657 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 709011999 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 709011999 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 709011999 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 709011999 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 709011999 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 709011999 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 11672224 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 11672224 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 11672224 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 11672224 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 11672224 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 11672224 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 36658 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 36658 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 36658 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 36658 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 36658 # number of overall misses
> system.cpu.icache.overall_misses::total 36658 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 709083999 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 709083999 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 709083999 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 709083999 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 709083999 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 709083999 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 11672225 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 11672225 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 11672225 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 11672225 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 11672225 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 11672225 # number of overall (read+write) accesses
547,552c547,552
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19341.790081 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19341.790081 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19341.790081 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19341.790081 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19343.226554 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 19343.226554 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 19343.226554 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 19343.226554 # average overall miss latency
561,566c561,566
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits
573,578c573,578
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580604499 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 580604499 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580604499 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 580604499 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580604499 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 580604499 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580605499 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 580605499 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580605499 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 580605499 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580605499 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 580605499 # number of overall MSHR miss cycles
585,590c585,590
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.139734 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.139734 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.170144 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.170144 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency
592,717d591
< system.cpu.dcache.replacements 158306 # number of replacements
< system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use
< system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
< system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
< system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
< system.cpu.dcache.writebacks::total 129052 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
719c593
< system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 30136.955699 # Cycle average of tags in use
725,726c599,600
< system.cpu.l2cache.occ_blocks::cpu.inst 1379.489976 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 1876.569805 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 1379.489982 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 1876.569807 # Average occupied blocks per requestor
759,761c633,635
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269870000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664898500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1934768500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269871000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664900000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1934771000 # number of ReadReq miss cycles
766,771c640,645
< system.cpu.l2cache.demand_miss_latency::cpu.inst 269870000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9756860500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10026730500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 269870000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9756860500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10026730500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 269871000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9756862000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 10026733000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 269871000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9756862000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 10026733000 # number of overall miss cycles
800,802c674,676
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.529915 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.727812 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.332581 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.743590 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.796258 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.426584 # average ReadReq miss latency
807,812c681,686
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 77816.474067 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 77816.474067 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77816.493469 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77816.493469 # average overall miss latency
845c719
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210181444 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210183444 # number of ReadReq MSHR miss cycles
847c721
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600023524 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600025524 # number of ReadReq MSHR miss cycles
852c726
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210181444 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210183444 # number of demand (read+write) MSHR miss cycles
854,855c728,729
< system.cpu.l2cache.demand_mshr_miss_latency::total 8421265207 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210181444 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 8421267207 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210183444 # number of overall MSHR miss cycles
857c731
< system.cpu.l2cache.overall_mshr_miss_latency::total 8421265207 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 8421267207 # number of overall MSHR miss cycles
871c745
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45064.632075 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45065.060892 # average ReadReq mshr miss latency
873c747
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.437163 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.512575 # average ReadReq mshr miss latency
878c752
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency
880,881c754,755
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency
883c757
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency
884a759,884
> system.cpu.dcache.replacements 158306 # number of replacements
> system.cpu.dcache.tagsinuse 4072.986678 # Cycle average of tags in use
> system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4072.986678 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
> system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
> system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670086500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 4670086500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 124709259481 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 124709259481 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 124709259481 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 124709259481 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.307299 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.307299 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 72956.568898 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 72956.568898 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
> system.cpu.dcache.writebacks::total 129052 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060279000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060279000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313871492 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10313871492 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313871492 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10313871492 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.809104 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.809104 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate