7,11c7,11
< host_inst_rate 54926 # Simulator instruction rate (inst/s)
< host_op_rate 77943 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 19021903 # Simulator tick rate (ticks/s)
< host_mem_usage 240316 # Number of bytes of host memory used
< host_seconds 1291.18 # Real time elapsed on the host
---
> host_inst_rate 104807 # Simulator instruction rate (inst/s)
> host_op_rate 148726 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 36296181 # Simulator tick rate (ticks/s)
> host_mem_usage 240672 # Number of bytes of host memory used
> host_seconds 676.68 # Real time elapsed on the host
14,23c14,36
< system.physmem.bytes_read 8687232 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 367552 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 5661632 # Number of bytes written to this memory
< system.physmem.num_reads 135738 # Number of read requests responded to by this memory
< system.physmem.num_writes 88463 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 353703655 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 14965007 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 230515305 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 584218960 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 367552 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8319680 # Number of bytes read from this memory
> system.physmem.bytes_read::total 8687232 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 367552 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 367552 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 5661632 # Number of bytes written to this memory
> system.physmem.bytes_written::total 5661632 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 5743 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 129995 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 135738 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 88463 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 88463 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 14965007 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 338738648 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 353703655 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 14965007 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 14965007 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 230515305 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 230515305 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 230515305 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 14965007 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 338738648 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 584218960 # Total bandwidth to/from this memory (bytes/s)
371a385
> system.cpu.icache.ReadReq_miss_rate::total 0.002824 # miss rate for ReadReq accesses
372a387
> system.cpu.icache.demand_miss_rate::total 0.002824 # miss rate for demand accesses
373a389
> system.cpu.icache.overall_miss_rate::total 0.002824 # miss rate for overall accesses
374a391
> system.cpu.icache.ReadReq_avg_miss_latency::total 11568.616839 # average ReadReq miss latency
375a393
> system.cpu.icache.demand_avg_miss_latency::total 11568.616839 # average overall miss latency
376a395
> system.cpu.icache.overall_avg_miss_latency::total 11568.616839 # average overall miss latency
403a423
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002705 # mshr miss rate for ReadReq accesses
404a425
> system.cpu.icache.demand_mshr_miss_rate::total 0.002705 # mshr miss rate for demand accesses
405a427
> system.cpu.icache.overall_mshr_miss_rate::total 0.002705 # mshr miss rate for overall accesses
406a429
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7991.392638 # average ReadReq mshr miss latency
407a431
> system.cpu.icache.demand_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency
408a433
> system.cpu.icache.overall_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency
463a489
> system.cpu.dcache.ReadReq_miss_rate::total 0.004158 # miss rate for ReadReq accesses
464a491
> system.cpu.dcache.WriteReq_miss_rate::total 0.077587 # miss rate for WriteReq accesses
465a493
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001779 # miss rate for LoadLockedReq accesses
466a495
> system.cpu.dcache.demand_miss_rate::total 0.035602 # miss rate for demand accesses
467a497
> system.cpu.dcache.overall_miss_rate::total 0.035602 # miss rate for overall accesses
468a499
> system.cpu.dcache.ReadReq_avg_miss_latency::total 22097.370069 # average ReadReq miss latency
469a501
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34105.131348 # average WriteReq miss latency
470a503
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12142.857143 # average LoadLockedReq miss latency
471a505
> system.cpu.dcache.demand_avg_miss_latency::total 33303.352734 # average overall miss latency
472a507
> system.cpu.dcache.overall_avg_miss_latency::total 33303.352734 # average overall miss latency
509a545
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses
510a547
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005388 # mshr miss rate for WriteReq accesses
511a549
> system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses
512a551
> system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses
513a553
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18700.810763 # average ReadReq mshr miss latency
514a555
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34284.263770 # average WriteReq mshr miss latency
515a557
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency
516a559
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency
588a632
> system.cpu.l2cache.ReadReq_miss_rate::total 0.370843 # miss rate for ReadReq accesses
589a634
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.851351 # miss rate for UpgradeReq accesses
590a636
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.959483 # miss rate for ReadExReq accesses
592a639
> system.cpu.l2cache.demand_miss_rate::total 0.691038 # miss rate for demand accesses
594a642
> system.cpu.l2cache.overall_miss_rate::total 0.691038 # miss rate for overall accesses
596a645
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34237.831659 # average ReadReq miss latency
597a647
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 547.619048 # average UpgradeReq miss latency
598a649
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34314.620761 # average ReadExReq miss latency
600a652
> system.cpu.l2cache.demand_avg_miss_latency::total 34295.827842 # average overall miss latency
602a655
> system.cpu.l2cache.overall_avg_miss_latency::total 34295.827842 # average overall miss latency
649a703
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.369828 # mshr miss rate for ReadReq accesses
650a705
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.851351 # mshr miss rate for UpgradeReq accesses
651a707
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.959483 # mshr miss rate for ReadExReq accesses
653a710
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.690575 # mshr miss rate for demand accesses
655a713
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.690575 # mshr miss rate for overall accesses
657a716
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.421315 # average ReadReq mshr miss latency
658a718
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.746032 # average UpgradeReq mshr miss latency
659a720
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31144.487118 # average ReadExReq mshr miss latency
661a723
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency
663a726
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency
< host_inst_rate 54926 # Simulator instruction rate (inst/s)
< host_op_rate 77943 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 19021903 # Simulator tick rate (ticks/s)
< host_mem_usage 240316 # Number of bytes of host memory used
< host_seconds 1291.18 # Real time elapsed on the host
---
> host_inst_rate 104807 # Simulator instruction rate (inst/s)
> host_op_rate 148726 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 36296181 # Simulator tick rate (ticks/s)
> host_mem_usage 240672 # Number of bytes of host memory used
> host_seconds 676.68 # Real time elapsed on the host
14,23c14,36
< system.physmem.bytes_read 8687232 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 367552 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 5661632 # Number of bytes written to this memory
< system.physmem.num_reads 135738 # Number of read requests responded to by this memory
< system.physmem.num_writes 88463 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 353703655 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 14965007 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 230515305 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 584218960 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 367552 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8319680 # Number of bytes read from this memory
> system.physmem.bytes_read::total 8687232 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 367552 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 367552 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 5661632 # Number of bytes written to this memory
> system.physmem.bytes_written::total 5661632 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 5743 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 129995 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 135738 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 88463 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 88463 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 14965007 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 338738648 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 353703655 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 14965007 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 14965007 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 230515305 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 230515305 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 230515305 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 14965007 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 338738648 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 584218960 # Total bandwidth to/from this memory (bytes/s)
371a385
> system.cpu.icache.ReadReq_miss_rate::total 0.002824 # miss rate for ReadReq accesses
372a387
> system.cpu.icache.demand_miss_rate::total 0.002824 # miss rate for demand accesses
373a389
> system.cpu.icache.overall_miss_rate::total 0.002824 # miss rate for overall accesses
374a391
> system.cpu.icache.ReadReq_avg_miss_latency::total 11568.616839 # average ReadReq miss latency
375a393
> system.cpu.icache.demand_avg_miss_latency::total 11568.616839 # average overall miss latency
376a395
> system.cpu.icache.overall_avg_miss_latency::total 11568.616839 # average overall miss latency
403a423
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002705 # mshr miss rate for ReadReq accesses
404a425
> system.cpu.icache.demand_mshr_miss_rate::total 0.002705 # mshr miss rate for demand accesses
405a427
> system.cpu.icache.overall_mshr_miss_rate::total 0.002705 # mshr miss rate for overall accesses
406a429
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7991.392638 # average ReadReq mshr miss latency
407a431
> system.cpu.icache.demand_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency
408a433
> system.cpu.icache.overall_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency
463a489
> system.cpu.dcache.ReadReq_miss_rate::total 0.004158 # miss rate for ReadReq accesses
464a491
> system.cpu.dcache.WriteReq_miss_rate::total 0.077587 # miss rate for WriteReq accesses
465a493
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001779 # miss rate for LoadLockedReq accesses
466a495
> system.cpu.dcache.demand_miss_rate::total 0.035602 # miss rate for demand accesses
467a497
> system.cpu.dcache.overall_miss_rate::total 0.035602 # miss rate for overall accesses
468a499
> system.cpu.dcache.ReadReq_avg_miss_latency::total 22097.370069 # average ReadReq miss latency
469a501
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34105.131348 # average WriteReq miss latency
470a503
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12142.857143 # average LoadLockedReq miss latency
471a505
> system.cpu.dcache.demand_avg_miss_latency::total 33303.352734 # average overall miss latency
472a507
> system.cpu.dcache.overall_avg_miss_latency::total 33303.352734 # average overall miss latency
509a545
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses
510a547
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005388 # mshr miss rate for WriteReq accesses
511a549
> system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses
512a551
> system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses
513a553
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18700.810763 # average ReadReq mshr miss latency
514a555
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34284.263770 # average WriteReq mshr miss latency
515a557
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency
516a559
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency
588a632
> system.cpu.l2cache.ReadReq_miss_rate::total 0.370843 # miss rate for ReadReq accesses
589a634
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.851351 # miss rate for UpgradeReq accesses
590a636
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.959483 # miss rate for ReadExReq accesses
592a639
> system.cpu.l2cache.demand_miss_rate::total 0.691038 # miss rate for demand accesses
594a642
> system.cpu.l2cache.overall_miss_rate::total 0.691038 # miss rate for overall accesses
596a645
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34237.831659 # average ReadReq miss latency
597a647
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 547.619048 # average UpgradeReq miss latency
598a649
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34314.620761 # average ReadExReq miss latency
600a652
> system.cpu.l2cache.demand_avg_miss_latency::total 34295.827842 # average overall miss latency
602a655
> system.cpu.l2cache.overall_avg_miss_latency::total 34295.827842 # average overall miss latency
649a703
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.369828 # mshr miss rate for ReadReq accesses
650a705
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.851351 # mshr miss rate for UpgradeReq accesses
651a707
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.959483 # mshr miss rate for ReadExReq accesses
653a710
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.690575 # mshr miss rate for demand accesses
655a713
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.690575 # mshr miss rate for overall accesses
657a716
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.421315 # average ReadReq mshr miss latency
658a718
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.746032 # average UpgradeReq mshr miss latency
659a720
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31144.487118 # average ReadExReq mshr miss latency
661a723
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency
663a726
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency