3,5c3,5
< sim_seconds 0.037982 # Number of seconds simulated
< sim_ticks 37982056000 # Number of ticks simulated
< final_tick 37982056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.038007 # Number of seconds simulated
> sim_ticks 38007342000 # Number of ticks simulated
> final_tick 38007342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 220867 # Simulator instruction rate (inst/s)
< host_op_rate 282464 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 118308818 # Simulator tick rate (ticks/s)
< host_mem_usage 284316 # Number of bytes of host memory used
< host_seconds 321.04 # Real time elapsed on the host
---
> host_inst_rate 224949 # Simulator instruction rate (inst/s)
> host_op_rate 287684 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 120575368 # Simulator tick rate (ticks/s)
> host_mem_usage 283980 # Number of bytes of host memory used
> host_seconds 315.22 # Real time elapsed on the host
16,53c16,53
< system.physmem.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 2372544 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 5696640 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 6178368 # Number of bytes read from this memory
< system.physmem.bytes_read::total 14247552 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 2372544 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 2372544 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6227072 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6227072 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 37071 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 89010 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 96537 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 222618 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 97298 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 97298 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 62464865 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 149982402 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 162665444 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 375112711 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 62464865 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 62464865 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 163947734 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 163947734 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 163947734 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 62464865 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 149982402 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 162665444 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 539060445 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 222619 # Number of read requests accepted
< system.physmem.writeReqs 97298 # Number of write requests accepted
< system.physmem.readBursts 222619 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 97298 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 14237568 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6225984 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 14247616 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 6227072 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 2373952 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 5705216 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 6169536 # Number of bytes read from this memory
> system.physmem.bytes_read::total 14248704 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 2373952 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 2373952 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6224192 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6224192 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 37093 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 89144 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 96399 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 222636 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 97253 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 97253 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 62460353 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 150108261 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 162324848 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 374893461 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 62460353 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 62460353 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 163762886 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 163762886 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 163762886 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 62460353 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 150108261 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 162324848 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 538656347 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 222637 # Number of read requests accepted
> system.physmem.writeReqs 97253 # Number of write requests accepted
> system.physmem.readBursts 222637 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 97253 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 14240000 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6222848 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 14248768 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6224192 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue
56,87c56,87
< system.physmem.perBankRdBursts::0 9655 # Per bank write bursts
< system.physmem.perBankRdBursts::1 9974 # Per bank write bursts
< system.physmem.perBankRdBursts::2 12579 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25363 # Per bank write bursts
< system.physmem.perBankRdBursts::4 17343 # Per bank write bursts
< system.physmem.perBankRdBursts::5 22132 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11760 # Per bank write bursts
< system.physmem.perBankRdBursts::7 14137 # Per bank write bursts
< system.physmem.perBankRdBursts::8 11660 # Per bank write bursts
< system.physmem.perBankRdBursts::9 15453 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11698 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11338 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9437 # Per bank write bursts
< system.physmem.perBankRdBursts::13 9564 # Per bank write bursts
< system.physmem.perBankRdBursts::14 9858 # Per bank write bursts
< system.physmem.perBankRdBursts::15 20511 # Per bank write bursts
< system.physmem.perBankWrBursts::0 5992 # Per bank write bursts
< system.physmem.perBankWrBursts::1 6239 # Per bank write bursts
< system.physmem.perBankWrBursts::2 6121 # Per bank write bursts
< system.physmem.perBankWrBursts::3 6129 # Per bank write bursts
< system.physmem.perBankWrBursts::4 6098 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6229 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6018 # Per bank write bursts
< system.physmem.perBankWrBursts::7 5980 # Per bank write bursts
< system.physmem.perBankWrBursts::8 5938 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6095 # Per bank write bursts
< system.physmem.perBankWrBursts::10 6202 # Per bank write bursts
< system.physmem.perBankWrBursts::11 5916 # Per bank write bursts
< system.physmem.perBankWrBursts::12 6046 # Per bank write bursts
< system.physmem.perBankWrBursts::13 6090 # Per bank write bursts
< system.physmem.perBankWrBursts::14 6173 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6015 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 9656 # Per bank write bursts
> system.physmem.perBankRdBursts::1 9952 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12608 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25349 # Per bank write bursts
> system.physmem.perBankRdBursts::4 17405 # Per bank write bursts
> system.physmem.perBankRdBursts::5 22083 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11752 # Per bank write bursts
> system.physmem.perBankRdBursts::7 14068 # Per bank write bursts
> system.physmem.perBankRdBursts::8 11731 # Per bank write bursts
> system.physmem.perBankRdBursts::9 15466 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11740 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11331 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9464 # Per bank write bursts
> system.physmem.perBankRdBursts::13 9568 # Per bank write bursts
> system.physmem.perBankRdBursts::14 9844 # Per bank write bursts
> system.physmem.perBankRdBursts::15 20483 # Per bank write bursts
> system.physmem.perBankWrBursts::0 5965 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6210 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6157 # Per bank write bursts
> system.physmem.perBankWrBursts::3 6128 # Per bank write bursts
> system.physmem.perBankWrBursts::4 6115 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6243 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6020 # Per bank write bursts
> system.physmem.perBankWrBursts::7 5952 # Per bank write bursts
> system.physmem.perBankWrBursts::8 5952 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6130 # Per bank write bursts
> system.physmem.perBankWrBursts::10 6213 # Per bank write bursts
> system.physmem.perBankWrBursts::11 5918 # Per bank write bursts
> system.physmem.perBankWrBursts::12 6006 # Per bank write bursts
> system.physmem.perBankWrBursts::13 6051 # Per bank write bursts
> system.physmem.perBankWrBursts::14 6145 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6027 # Per bank write bursts
90c90
< system.physmem.totGap 37982044500 # Total gap between requests
---
> system.physmem.totGap 38007330500 # Total gap between requests
97c97
< system.physmem.readPktSize::6 222619 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 222637 # Read request sizes (log2)
104,110c104,110
< system.physmem.writePktSize::6 97298 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 111989 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 59707 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 15764 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 10925 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 6262 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 5252 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 97253 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 112108 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 59931 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 15573 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 10934 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 6190 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 5238 # What read queue length does an incoming req see
112,117c112,117
< system.physmem.rdQLenPdf::7 4266 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 76 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 38 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::7 4261 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3516 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 73 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see
152,176c152,176
< system.physmem.wrQLenPdf::15 1089 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 1856 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 2518 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 3246 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4935 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5530 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6006 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6447 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6796 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 7367 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7813 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8377 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8639 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7998 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6745 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6258 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 95 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 1871 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 2521 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 3276 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4051 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4912 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5531 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5989 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6858 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7322 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7735 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 8436 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8656 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7923 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6697 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6288 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 245 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 111 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 54 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 24 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see
178,181c178,181
< system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
201,214c201,214
< system.physmem.bytesPerActivate::samples 132891 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 153.980270 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 102.520664 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 209.589027 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 82855 62.35% 62.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 32511 24.46% 86.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6209 4.67% 91.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2728 2.05% 93.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 1195 0.90% 94.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 994 0.75% 95.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 885 0.67% 95.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 776 0.58% 96.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 4738 3.57% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 132891 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 132899 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 153.968593 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 102.497917 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 209.528989 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 82983 62.44% 62.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 32243 24.26% 86.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6367 4.79% 91.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2726 2.05% 93.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 1184 0.89% 94.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1005 0.76% 95.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 875 0.66% 95.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 807 0.61% 96.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 4709 3.54% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 132899 # Bytes accessed per row activation
216,219c216,219
< system.physmem.rdPerTurnAround::mean 37.813870 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 211.295819 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 5876 99.88% 99.88% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-1023 6 0.10% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::mean 37.820840 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 210.672420 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 5878 99.92% 99.92% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98% # Reads before turning the bus around for writes
222,248c222,247
< system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.535951 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.496117 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.216118 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 4707 80.01% 80.01% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 47 0.80% 80.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 703 11.95% 92.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 205 3.48% 96.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 109 1.85% 98.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 61 1.04% 99.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 33 0.56% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 11 0.19% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 1 0.02% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 4 0.07% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads
< system.physmem.totQLat 8417974819 # Total ticks spent queuing
< system.physmem.totMemAccLat 12589137319 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1112310000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 37840.06 # Average queueing delay per DRAM burst
< system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
< system.physmem.avgMemAccLat 56590.06 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 374.85 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 163.92 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 375.11 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 163.95 # Average system write bandwidth in MiByte/s
---
> system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.528392 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.490234 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.186972 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 4697 79.85% 79.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 46 0.78% 80.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 744 12.65% 93.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 191 3.25% 96.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 91 1.55% 98.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 73 1.24% 99.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 20 0.34% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 15 0.26% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 2 0.03% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::27 2 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads
> system.physmem.totQLat 8329547257 # Total ticks spent queuing
> system.physmem.totMemAccLat 12501422257 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1112500000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 37436.00 # Average queueing delay per DRAM burst
> system.physmem.avgBusLat 4999.98 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 56185.91 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 374.66 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 163.73 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 374.90 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 163.76 # Average system write bandwidth in MiByte/s
253,259c252,258
< system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing
< system.physmem.readRowHits 157076 # Number of row buffer hits during reads
< system.physmem.writeRowHits 29766 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 70.61 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes
< system.physmem.avgGap 118724.68 # Average gap between requests
---
> system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing
> system.physmem.readRowHits 157173 # Number of row buffer hits during reads
> system.physmem.writeRowHits 29653 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 70.64 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 30.49 # Row buffer hit rate for writes
> system.physmem.avgGap 118813.75 # Average gap between requests
261,304c260,303
< system.physmem_0.actEnergy 508332300 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 270162255 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 877813020 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 254767320 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3007433520.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 2937544590 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 74566560 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 13007568150 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 1007588640 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 71626485 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 22017862440 # Total energy per rank (pJ)
< system.physmem_0.averagePower 579.691165 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 31344656336 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 41004063 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1272480000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 195565250 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 2624595348 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 5323818601 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 28524592738 # Time in different power states
< system.physmem_1.actEnergy 440580840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 234159090 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 710558520 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 253039500 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 2889422640.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 2771748120 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 73304160 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 11932439280 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 1384694400 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 508589940 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 21198847170 # Total energy per rank (pJ)
< system.physmem_1.averagePower 558.127949 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 31712588164 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 50452548 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1222746000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 1938473750 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 3605935527 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 4996269288 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 26168178887 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 17071043 # Number of BP lookups
< system.cpu.branchPred.condPredicted 11458506 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 598065 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9277652 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 7374059 # Number of BTB hits
---
> system.physmem_0.actEnergy 507596880 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 269771370 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 877313220 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 254683800 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3009892080.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2962459860 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 75632160 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 13054365150 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 948417120 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 77983215 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 22038660255 # Total energy per rank (pJ)
> system.physmem_0.averagePower 579.852702 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 31313307761 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 43781047 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1273526000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 214718250 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 2469720434 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 5376727192 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 28628869077 # Time in different power states
> system.physmem_1.actEnergy 441337680 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 234557565 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 711336780 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 252841140 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 2899256880.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2760551040 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 73978560 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 11934955830 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 1428119040 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 493845795 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 21231004530 # Total energy per rank (pJ)
> system.physmem_1.averagePower 558.602674 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 31760586804 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 51273339 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1226918000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 1868150750 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 3718457459 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 4968563857 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 26173978595 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 17074531 # Number of BP lookups
> system.cpu.branchPred.condPredicted 11460402 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 598628 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9274722 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 7374340 # Number of BTB hits
306,312c305,311
< system.cpu.branchPred.BTBHitPct 79.481953 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1854771 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 101571 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 233347 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 194967 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 38380 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 22266 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 79.510092 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1855435 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 101567 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 233050 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 195925 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 37125 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 22231 # Number of mispredicted indirect branches.
314c313
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
344c343
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
374c373
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
404c403
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
435,436c434,435
< system.cpu.pwrStateResidencyTicks::ON 37982056000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 75964113 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 38007342000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 76014685 # number of cpu cycles simulated
439,452c438,451
< system.cpu.fetch.icacheStallCycles 5537723 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 87105546 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 17071043 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 9423797 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 66074321 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1222765 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 12043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 60 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 33616 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 22433583 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 69302 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 72269145 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.523281 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.330897 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 5565404 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 87125388 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 17074531 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 9425700 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 66120510 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1223729 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 11256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 32224 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 22440736 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 69274 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 72341306 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.522198 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.331033 # Number of instructions fetched each cycle (Total)
454,457c453,456
< system.cpu.fetch.rateDist::0 27092588 37.49% 37.49% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 8164913 11.30% 48.79% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 9113637 12.61% 61.40% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 27898007 38.60% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 27150688 37.53% 37.53% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 8169627 11.29% 48.82% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 9114831 12.60% 61.42% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 27906160 38.58% 100.00% # Number of instructions fetched each cycle (Total)
461,488c460,487
< system.cpu.fetch.rateDist::total 72269145 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.224725 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.146667 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 8914938 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 26268747 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 30971085 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 5669704 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 444671 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 3134143 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 168562 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 100303161 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 2799230 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 444671 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 13550474 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 11467047 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 876029 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 31784130 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 14146794 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 98330583 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 860090 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 4210253 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 70388 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 4670257 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 5435231 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 103259286 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 453553071 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 114279094 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 72341306 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.224621 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.146165 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 8942287 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 26299816 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 30976482 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 5677371 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 445350 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 3133946 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 168438 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 100318297 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 2804928 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 445350 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 13582767 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 11480611 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 882043 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 31792045 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 14158490 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 98346425 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 855389 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 4229008 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 68182 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 4663621 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 5443965 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 103273055 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 453619684 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 114297516 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 686 # Number of floating rename lookups
490,507c489,506
< system.cpu.rename.UndoneMaps 9629917 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 18998 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 19022 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 12803731 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 24155645 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 21760500 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1435489 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 2293932 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 97400499 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 34856 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 94484787 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 595355 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 6752748 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 17957034 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1070 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 72269145 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.307401 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.171287 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 9643686 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 18991 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 19021 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 12815345 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 24159121 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 21761593 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1442839 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 2330212 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 97411129 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 34857 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 94489103 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 595557 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 6763379 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 17995254 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 72341306 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.306157 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.170975 # Number of insts issued each cycle
509,514c508,513
< system.cpu.iq.issued_per_cycle::0 24146655 33.41% 33.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 17449315 24.14% 57.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 17027031 23.56% 81.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 11604628 16.06% 97.18% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 2040054 2.82% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 1462 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 24199109 33.45% 33.45% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 17470195 24.15% 57.60% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 17034708 23.55% 81.15% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 11601119 16.04% 97.19% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 2034740 2.81% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 1435 0.00% 100.00% # Number of insts issued each cycle
521c520
< system.cpu.iq.issued_per_cycle::total 72269145 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 72341306 # Number of insts issued each cycle
523,556c522,555
< system.cpu.iq.fu_full::IntAlu 6736684 22.63% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 37 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 11088448 37.25% 59.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 11940306 40.11% 100.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 30 0.00% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 6739464 22.68% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 40 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 11065982 37.24% 59.92% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 11909373 40.08% 100.00% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 33 0.00% 100.00% # attempts to use FU when none available
561,562c560,561
< system.cpu.iq.FU_type_0::IntAlu 49305598 52.18% 52.18% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 86530 0.09% 52.28% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 49308872 52.18% 52.18% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 86547 0.09% 52.28% # Type of FU issued
585c584
< system.cpu.iq.FU_type_0::SimdFloatCmp 11 0.00% 52.28% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatCmp 13 0.00% 52.28% # Type of FU issued
588c587
< system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 52.28% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 52.28% # Type of FU issued
592,593c591,592
< system.cpu.iq.FU_type_0::MemRead 23958815 25.36% 77.63% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 21133689 22.37% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 23960981 25.36% 77.63% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 21132544 22.37% 100.00% # Type of FU issued
598,610c597,609
< system.cpu.iq.FU_type_0::total 94484787 # Type of FU issued
< system.cpu.iq.rate 1.243808 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 29765526 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.315030 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 291599265 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 104199326 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 93203450 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 335 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 124250121 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 192 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 1368397 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 94489103 # Type of FU issued
> system.cpu.iq.rate 1.243037 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 29714913 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.314480 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 291629642 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 104220574 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 93205627 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 544 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 124203819 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 197 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 1369166 # Number of loads that had data forwarded from stores
612,615c611,614
< system.cpu.iew.lsq.thread0.squashedLoads 1289383 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 2091 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1204762 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1292859 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 2033 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 11913 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1205855 # Number of stores squashed
618,619c617,618
< system.cpu.iew.lsq.thread0.rescheduledLoads 147075 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 188044 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 148706 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 187344 # Number of times an access to memory failed due to the cache being blocked
621,624c620,623
< system.cpu.iew.iewSquashCycles 444671 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 622988 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1195662 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 97449431 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 445350 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 625818 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1199933 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 97461708 # Number of instructions dispatched to IQ
626,637c625,636
< system.cpu.iew.iewDispLoadInsts 24155645 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 21760500 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 18936 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 1589 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 1191442 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 249986 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 222081 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 472067 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 93691189 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 23695668 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 793598 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 24159121 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 21761593 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 18937 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 1609 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 1195657 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 11913 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 250763 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 222991 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 473754 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 93695211 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 23697676 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 793892 # Number of squashed instructions skipped in execute
639,650c638,649
< system.cpu.iew.exec_nop 14076 # number of nop insts executed
< system.cpu.iew.exec_refs 44621004 # number of memory reference insts executed
< system.cpu.iew.exec_branches 14207535 # Number of branches executed
< system.cpu.iew.exec_stores 20925336 # Number of stores executed
< system.cpu.iew.exec_rate 1.233361 # Inst execution rate
< system.cpu.iew.wb_sent 93310594 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 93203542 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 44951761 # num instructions producing a value
< system.cpu.iew.wb_consumers 76639550 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.226942 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.586535 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 5895620 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 15722 # number of nop insts executed
> system.cpu.iew.exec_refs 44622526 # number of memory reference insts executed
> system.cpu.iew.exec_branches 14207940 # Number of branches executed
> system.cpu.iew.exec_stores 20924850 # Number of stores executed
> system.cpu.iew.exec_rate 1.232594 # Inst execution rate
> system.cpu.iew.wb_sent 93313259 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 93205726 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 44957522 # num instructions producing a value
> system.cpu.iew.wb_consumers 76634731 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.226154 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.586647 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 5905401 # The number of squashed insts skipped by commit
652,655c651,654
< system.cpu.commit.branchMispredicts 431354 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 71312758 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.271696 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.107515 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 432114 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 71383083 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.270443 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.106463 # Number of insts commited each cycle
657,665c656,664
< system.cpu.commit.committed_per_cycle::0 37859507 53.09% 53.09% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 16683603 23.39% 76.48% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 4297164 6.03% 82.51% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 4156384 5.83% 88.34% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1956005 2.74% 91.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1240140 1.74% 92.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 732437 1.03% 93.85% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 578410 0.81% 94.66% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 3809108 5.34% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 37916370 53.12% 53.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 16693361 23.39% 76.50% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 4299601 6.02% 82.53% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 4172974 5.85% 88.37% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1943479 2.72% 91.09% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1233650 1.73% 92.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 737671 1.03% 93.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 579334 0.81% 94.67% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 3806643 5.33% 100.00% # Number of insts commited each cycle
669c668
< system.cpu.commit.committed_per_cycle::total 71312758 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 71383083 # Number of insts commited each cycle
719,723c718,722
< system.cpu.commit.bw_lim_events 3809108 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 164062130 # The number of ROB reads
< system.cpu.rob.rob_writes 194125448 # The number of ROB writes
< system.cpu.timesIdled 54252 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 3694968 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 3806643 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 164144701 # The number of ROB reads
> system.cpu.rob.rob_writes 194146843 # The number of ROB writes
> system.cpu.timesIdled 54077 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 3673379 # Total number of cycles that the CPU has spent unscheduled due to idling
726,736c725,735
< system.cpu.cpi 1.071311 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.071311 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.933436 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.933436 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 101982930 # number of integer regfile reads
< system.cpu.int_regfile_writes 56612163 # number of integer regfile writes
< system.cpu.fp_regfile_reads 58 # number of floating regfile reads
< system.cpu.fp_regfile_writes 45 # number of floating regfile writes
< system.cpu.cc_regfile_reads 345107562 # number of cc regfile reads
< system.cpu.cc_regfile_writes 38759661 # number of cc regfile writes
< system.cpu.misc_regfile_reads 44102170 # number of misc regfile reads
---
> system.cpu.cpi 1.072024 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.072024 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.932815 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.932815 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 101986551 # number of integer regfile reads
> system.cpu.int_regfile_writes 56614441 # number of integer regfile writes
> system.cpu.fp_regfile_reads 62 # number of floating regfile reads
> system.cpu.fp_regfile_writes 51 # number of floating regfile writes
> system.cpu.cc_regfile_reads 345121100 # number of cc regfile reads
> system.cpu.cc_regfile_writes 38758964 # number of cc regfile writes
> system.cpu.misc_regfile_reads 44102244 # number of misc regfile reads
738,747c737,746
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 484814 # number of replacements
< system.cpu.dcache.tags.tagsinuse 510.868965 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40339815 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 485326 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 83.119007 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 154595500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 510.868965 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 484796 # number of replacements
> system.cpu.dcache.tags.tagsinuse 510.868688 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40338903 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 485308 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 83.120210 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 154723500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 510.868688 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.997790 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy
752,762c751,761
< system.cpu.dcache.tags.tag_accesses 84466838 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 84466838 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 21417711 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 21417711 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18830642 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18830642 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 15309 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 15309 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 84466908 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 84466908 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 21416602 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 21416602 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18830761 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18830761 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 60264 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 60264 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits
765,792c764,791
< system.cpu.dcache.demand_hits::cpu.data 40248353 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 40248353 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 40308541 # number of overall hits
< system.cpu.dcache.overall_hits::total 40308541 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 562442 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 562442 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1019259 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1019259 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 68672 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 68672 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 614 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 614 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1581701 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1581701 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1650373 # number of overall misses
< system.cpu.dcache.overall_misses::total 1650373 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 14412910000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 14412910000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 14258561428 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 14258561428 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5705500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 5705500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 28671471428 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 28671471428 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 28671471428 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 28671471428 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 21980153 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 21980153 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 40247363 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 40247363 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 40307627 # number of overall hits
> system.cpu.dcache.overall_hits::total 40307627 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 563583 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 563583 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1019140 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1019140 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 68608 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 68608 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 617 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 617 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1582723 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1582723 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1651331 # number of overall misses
> system.cpu.dcache.overall_misses::total 1651331 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 14467064000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 14467064000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 14294982430 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 14294982430 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6393500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 6393500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 28762046430 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 28762046430 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 28762046430 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 28762046430 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 21980185 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 21980185 # number of ReadReq accesses(hits+misses)
795,796c794,795
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 128860 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 128860 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 128872 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 128872 # number of SoftPFReq accesses(hits+misses)
801,866c800,865
< system.cpu.dcache.demand_accesses::cpu.data 41830054 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 41830054 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 41958914 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 41958914 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025589 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.025589 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051348 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.051348 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532919 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.532919 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038561 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038561 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.037813 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.037813 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.039333 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.039333 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.593395 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.593395 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13989.144494 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 13989.144494 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9292.345277 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9292.345277 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 18126.985712 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 18126.985712 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 17372.722062 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 17372.722062 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 2956958 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 131265 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.666667 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 22.526629 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 484814 # number of writebacks
< system.cpu.dcache.writebacks::total 484814 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263368 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 263368 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870698 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 870698 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 614 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 1134066 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1134066 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1134066 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1134066 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299074 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 299074 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148561 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 148561 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37704 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 37704 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 447635 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 447635 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 485339 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 485339 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7124794500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7124794500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2343478471 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2343478471 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1981400500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1981400500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9468272971 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9468272971 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11449673471 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11449673471 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013607 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013607 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 41830086 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 41830086 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 41958958 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 41958958 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025641 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.025641 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051342 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.051342 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532373 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.532373 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038749 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038749 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.037837 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.037837 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.039356 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.039356 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25669.801964 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 25669.801964 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14026.514934 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 14026.514934 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10362.236629 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10362.236629 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 18172.508032 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 18172.508032 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 17417.493180 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 17417.493180 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 2976739 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 131356 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.800000 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 22.661614 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 484796 # number of writebacks
> system.cpu.dcache.writebacks::total 484796 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 264511 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 264511 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870576 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 870576 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 617 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 617 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1135087 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1135087 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1135087 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1135087 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299072 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 299072 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148564 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 148564 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37686 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 37686 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 447636 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 447636 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 485322 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 485322 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7113004000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7113004000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2350412971 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2350412971 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2001432500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2001432500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9463416971 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9463416971 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11464849471 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11464849471 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013606 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013606 # mshr miss rate for ReadReq accesses
869,870c868,869
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292597 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292597 # mshr miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292430 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292430 # mshr miss rate for SoftPFReq accesses
875,895c874,894
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23822.848191 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23822.848191 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15774.520036 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15774.520036 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52551.466688 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52551.466688 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21151.770909 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 21151.770909 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23591.084728 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 23591.084728 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 325639 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.373274 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 22095836 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 326151 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 67.747258 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 1176670500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.373274 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.996823 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.996823 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23783.583886 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23783.583886 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.878349 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.878349 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53108.117073 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53108.117073 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21140.875557 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 21140.875557 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23623.181045 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 23623.181045 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 325456 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.336563 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 22103277 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 325967 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 67.808327 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 1174665500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.336563 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.996751 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.996751 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
897,941c896,940
< system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 328 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 45192862 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 45192862 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 22095836 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 22095836 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 22095836 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 22095836 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 22095836 # number of overall hits
< system.cpu.icache.overall_hits::total 22095836 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 337513 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 337513 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 337513 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 337513 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 337513 # number of overall misses
< system.cpu.icache.overall_misses::total 337513 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 5817859355 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 5817859355 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 5817859355 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 5817859355 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 5817859355 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 5817859355 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 22433349 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 22433349 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 22433349 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 22433349 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 22433349 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 22433349 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015045 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.015045 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.015045 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.015045 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.015045 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.015045 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17237.437832 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 17237.437832 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 17237.437832 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 17237.437832 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 562602 # number of cycles access was blocked
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 332 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 45207041 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 45207041 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 22103280 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 22103280 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 22103280 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 22103280 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 22103280 # number of overall hits
> system.cpu.icache.overall_hits::total 22103280 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 337250 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 337250 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 337250 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 337250 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 337250 # number of overall misses
> system.cpu.icache.overall_misses::total 337250 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 5803062852 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 5803062852 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 5803062852 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 5803062852 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 5803062852 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 5803062852 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 22440530 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 22440530 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 22440530 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 22440530 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 22440530 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 22440530 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015029 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.015029 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.015029 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.015029 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.015029 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17207.006233 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 17207.006233 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 17207.006233 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 17207.006233 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 559762 # number of cycles access was blocked
943c942
< system.cpu.icache.blocked::no_mshrs 26054 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 25894 # number of cycles access was blocked
945c944
< system.cpu.icache.avg_blocked_cycles::no_mshrs 21.593690 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 21.617440 # average number of cycles each access was blocked
947,982c946,981
< system.cpu.icache.writebacks::writebacks 325639 # number of writebacks
< system.cpu.icache.writebacks::total 325639 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11348 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 11348 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 11348 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 11348 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 11348 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 11348 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326165 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 326165 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 326165 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 326165 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 326165 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 326165 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5383419413 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 5383419413 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5383419413 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 5383419413 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5383419413 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 5383419413 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16505.202621 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16505.202621 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 823055 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 826389 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 2921 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.writebacks::writebacks 325456 # number of writebacks
> system.cpu.icache.writebacks::total 325456 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11268 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 11268 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 11268 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 11268 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 11268 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 11268 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325982 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 325982 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 325982 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 325982 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 325982 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 325982 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5371171413 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 5371171413 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5371171413 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 5371171413 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5371171413 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 5371171413 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014526 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16476.895697 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16476.895697 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16476.895697 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 16476.895697 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16476.895697 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 16476.895697 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 822258 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 825535 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 2876 # number of redundant prefetches already in prefetch queue
985,991c984,990
< system.cpu.l2cache.prefetcher.pfSpanPage 78691 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 125520 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 15698.936659 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 681800 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 141835 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.806994 # Average number of references to valid blocks.
---
> system.cpu.l2cache.prefetcher.pfSpanPage 78497 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 125579 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 15699.484972 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 681508 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 141902 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.802667 # Average number of references to valid blocks.
993,999c992,998
< system.cpu.l2cache.tags.occ_blocks::writebacks 15629.036475 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 69.900184 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.953921 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004266 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.958187 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 27 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 16288 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 15625.141607 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.343365 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.953683 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004538 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.958221 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 24 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 16299 # Occupied blocks per task id
1002,1003c1001,1002
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 12 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id
1005,1073c1004,1072
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2543 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12218 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 510 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 881 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001648 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 25499859 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 25499859 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 257633 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 257633 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 472926 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 472926 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 137172 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 137172 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 289056 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 289056 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 255940 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 255940 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 289056 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 393112 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 682168 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 289056 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 393112 # number of overall hits
< system.cpu.l2cache.overall_hits::total 682168 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 11425 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 11425 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37095 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 37095 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80789 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 80789 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 37095 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 92214 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 129309 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 37095 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 92214 # number of overall misses
< system.cpu.l2cache.overall_misses::total 129309 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1226064500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1226064500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3155473000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 3155473000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6910815500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 6910815500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 3155473000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8136880000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11292353000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 3155473000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8136880000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11292353000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 257633 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 257633 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 472926 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 472926 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 148597 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 148597 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 326151 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 326151 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336729 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 336729 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 326151 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 485326 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 811477 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 326151 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 485326 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 811477 # number of overall (read+write) accesses
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2587 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12184 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 533 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 859 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001465 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994812 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 25493850 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 25493850 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 260429 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 260429 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 469974 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 469974 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 137044 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 137044 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 288848 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 288848 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 255916 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 255916 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 288848 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 392960 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 681808 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 288848 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 392960 # number of overall hits
> system.cpu.l2cache.overall_hits::total 681808 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 11552 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 11552 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37119 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 37119 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80796 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 80796 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 37119 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 92348 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 129467 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 37119 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 92348 # number of overall misses
> system.cpu.l2cache.overall_misses::total 129467 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1233354500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1233354500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3144915500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 3144915500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6919452000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 6919452000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 3144915500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8152806500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11297722000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 3144915500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8152806500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11297722000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 260429 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 260429 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 469974 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 469974 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 148596 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 148596 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 325967 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 325967 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336712 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 336712 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 325967 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 485308 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 811275 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 325967 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 485308 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 811275 # number of overall (read+write) accesses
1076,1099c1075,1098
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076886 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.076886 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113736 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113736 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239923 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239923 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113736 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.190004 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.159350 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113736 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.190004 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.159350 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107314.179431 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107314.179431 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85064.644831 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85064.644831 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85541.540309 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85541.540309 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85064.644831 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88239.096016 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 87328.438082 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85064.644831 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88239.096016 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 87328.438082 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077741 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.077741 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113873 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113873 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239956 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239956 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113873 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.190287 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.159585 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113873 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.190287 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.159585 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106765.451870 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106765.451870 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.221585 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.221585 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85641.021833 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85641.021833 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.221585 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88283.519946 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 87263.333514 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.221585 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88283.519946 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 87263.333514 # average overall miss latency
1106,1115c1105,1114
< system.cpu.l2cache.unused_prefetches 452 # number of HardPF blocks evicted w/o reference
< system.cpu.l2cache.writebacks::writebacks 97298 # number of writebacks
< system.cpu.l2cache.writebacks::total 97298 # number of writebacks
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3085 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 3085 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 119 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 119 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.unused_prefetches 426 # number of HardPF blocks evicted w/o reference
> system.cpu.l2cache.writebacks::writebacks 97253 # number of writebacks
> system.cpu.l2cache.writebacks::total 97253 # number of writebacks
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3091 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 3091 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 113 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits
1117,1118c1116,1117
< system.cpu.l2cache.demand_mshr_hits::total 3227 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 3229 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits
1120,1154c1119,1153
< system.cpu.l2cache.overall_mshr_hits::total 3227 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 115310 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 115310 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8340 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 8340 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37072 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37072 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80670 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80670 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 37072 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 89010 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 126082 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 37072 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 89010 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115310 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 241392 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10321796922 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10321796922 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 201500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 201500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 722790000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 722790000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2931479000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2931479000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6418843000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6418843000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2931479000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7141633000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10073112000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2931479000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7141633000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10321796922 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20394908922 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_hits::total 3229 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 114995 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 114995 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8461 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 8461 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37094 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37094 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80683 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80683 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 37094 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 89144 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 126238 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 37094 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 89144 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 114995 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 241233 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10227090401 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10227090401 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 218000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 218000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 733523000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 733523000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2920395500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2920395500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6427576500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6427576500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2920395500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7161099500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10081495000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2920395500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7161099500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10227090401 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 20308585401 # number of overall MSHR miss cycles
1159,1169c1158,1168
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056125 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056125 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113665 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239570 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239570 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.155373 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056940 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056940 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113797 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239620 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239620 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.155604 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for overall accesses
1171,1217c1170,1216
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.297472 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89513.458694 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86665.467626 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86665.467626 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79075.285930 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79075.285930 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79569.145903 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79569.145903 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79893.339255 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84488.752411 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 1621957 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 810494 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 18773 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18772 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 662893 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 354931 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 552820 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 28222 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 146565 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 148597 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 148597 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 326165 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 336729 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977954 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455492 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 2433446 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41714496 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62088960 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 103803456 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 272099 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 6227968 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 1083589 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.091107 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.287765 # Request fanout histogram
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.297350 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 88935.087621 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15571.428571 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15571.428571 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86694.598747 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86694.598747 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78729.592387 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78729.592387 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79664.569984 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79664.569984 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79861.016493 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84186.597194 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 1621556 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 810285 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 18616 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18570 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 46 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 662693 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 357682 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 549823 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 28326 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 146207 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 148596 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 148596 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 325982 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 336712 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977404 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455440 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 2432844 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41691008 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62086656 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 103777664 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 271801 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 6225152 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 1083090 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.091523 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.288499 # Request fanout histogram
1219,1221c1218,1220
< system.cpu.toL2Bus.snoop_fanout::0 984867 90.89% 90.89% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 98721 9.11% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 984008 90.85% 90.85% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 99036 9.14% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 46 0.00% 100.00% # Request fanout histogram
1225,1226c1224,1225
< system.cpu.toL2Bus.snoop_fanout::total 1083589 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 1621431500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1083090 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 1621030000 # Layer occupancy (ticks)
1228c1227
< system.cpu.toL2Bus.respLayer0.occupancy 489373744 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 489099244 # Layer occupancy (ticks)
1230c1229
< system.cpu.toL2Bus.respLayer1.occupancy 728066857 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 728047842 # Layer occupancy (ticks)
1232,1233c1231,1232
< system.membus.snoop_filter.tot_requests 348152 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 205320 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.membus.snoop_filter.tot_requests 348230 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 205331 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1238,1249c1237,1248
< system.membus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 214278 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 97298 # Transaction distribution
< system.membus.trans_dist::CleanEvict 28222 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 13 # Transaction distribution
< system.membus.trans_dist::ReadExReq 8340 # Transaction distribution
< system.membus.trans_dist::ReadExResp 8340 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 214279 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570770 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 570770 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20474624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 20474624 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 214175 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 97253 # Transaction distribution
> system.membus.trans_dist::CleanEvict 28326 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 14 # Transaction distribution
> system.membus.trans_dist::ReadExReq 8461 # Transaction distribution
> system.membus.trans_dist::ReadExResp 8461 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570866 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 570866 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20472896 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 20472896 # Cumulative packet size per connected master and slave (bytes)
1252c1251
< system.membus.snoop_fanout::samples 222632 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 222651 # Request fanout histogram
1256c1255
< system.membus.snoop_fanout::0 222632 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 222651 100.00% 100.00% # Request fanout histogram
1261,1262c1260,1261
< system.membus.snoop_fanout::total 222632 # Request fanout histogram
< system.membus.reqLayer0.occupancy 835899979 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 222651 # Request fanout histogram
> system.membus.reqLayer0.occupancy 835869990 # Layer occupancy (ticks)
1264c1263
< system.membus.respLayer1.occupancy 1175524166 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1175713686 # Layer occupancy (ticks)