3,5c3,5
< sim_seconds 0.037283 # Number of seconds simulated
< sim_ticks 37283333000 # Number of ticks simulated
< final_tick 37283333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.037982 # Number of seconds simulated
> sim_ticks 37982056000 # Number of ticks simulated
> final_tick 37982056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 125888 # Simulator instruction rate (inst/s)
< host_op_rate 160996 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 66191855 # Simulator tick rate (ticks/s)
< host_mem_usage 284264 # Number of bytes of host memory used
< host_seconds 563.26 # Real time elapsed on the host
---
> host_inst_rate 105525 # Simulator instruction rate (inst/s)
> host_op_rate 134954 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 56525025 # Simulator tick rate (ticks/s)
> host_mem_usage 282344 # Number of bytes of host memory used
> host_seconds 671.95 # Real time elapsed on the host
16,53c16,53
< system.physmem.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 2379328 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 5690752 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 6174592 # Number of bytes read from this memory
< system.physmem.bytes_read::total 14244672 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 2379328 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 2379328 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6224768 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6224768 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 37177 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 88918 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 96478 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 222573 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 97262 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 97262 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 63817470 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 152635281 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 165612661 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 382065412 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 63817470 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 63817470 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 166958464 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 166958464 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 166958464 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 63817470 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 152635281 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 165612661 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 549023876 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 222574 # Number of read requests accepted
< system.physmem.writeReqs 97262 # Number of write requests accepted
< system.physmem.readBursts 222574 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 97262 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 14235136 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6223360 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 14244736 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 6224768 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 2372544 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 5696640 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 6178368 # Number of bytes read from this memory
> system.physmem.bytes_read::total 14247552 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 2372544 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 2372544 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6227072 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6227072 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 37071 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 89010 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 96537 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 222618 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 97298 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 97298 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 62464865 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 149982402 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 162665444 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 375112711 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 62464865 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 62464865 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 163947734 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 163947734 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 163947734 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 62464865 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 149982402 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 162665444 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 539060445 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 222619 # Number of read requests accepted
> system.physmem.writeReqs 97298 # Number of write requests accepted
> system.physmem.readBursts 222619 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 97298 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 14237568 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6225984 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 14247616 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6227072 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue
56,87c56,87
< system.physmem.perBankRdBursts::0 9684 # Per bank write bursts
< system.physmem.perBankRdBursts::1 9951 # Per bank write bursts
< system.physmem.perBankRdBursts::2 12571 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25345 # Per bank write bursts
< system.physmem.perBankRdBursts::4 17391 # Per bank write bursts
< system.physmem.perBankRdBursts::5 22070 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11722 # Per bank write bursts
< system.physmem.perBankRdBursts::7 14054 # Per bank write bursts
< system.physmem.perBankRdBursts::8 11726 # Per bank write bursts
< system.physmem.perBankRdBursts::9 15447 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11755 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11322 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9441 # Per bank write bursts
< system.physmem.perBankRdBursts::13 9563 # Per bank write bursts
< system.physmem.perBankRdBursts::14 9879 # Per bank write bursts
< system.physmem.perBankRdBursts::15 20503 # Per bank write bursts
< system.physmem.perBankWrBursts::0 5981 # Per bank write bursts
< system.physmem.perBankWrBursts::1 6205 # Per bank write bursts
< system.physmem.perBankWrBursts::2 6090 # Per bank write bursts
< system.physmem.perBankWrBursts::3 6159 # Per bank write bursts
< system.physmem.perBankWrBursts::4 6110 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6252 # Per bank write bursts
< system.physmem.perBankWrBursts::6 5998 # Per bank write bursts
< system.physmem.perBankWrBursts::7 5984 # Per bank write bursts
< system.physmem.perBankWrBursts::8 5961 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6093 # Per bank write bursts
< system.physmem.perBankWrBursts::10 6222 # Per bank write bursts
< system.physmem.perBankWrBursts::11 5895 # Per bank write bursts
< system.physmem.perBankWrBursts::12 6037 # Per bank write bursts
< system.physmem.perBankWrBursts::13 6052 # Per bank write bursts
< system.physmem.perBankWrBursts::14 6175 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6026 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 9655 # Per bank write bursts
> system.physmem.perBankRdBursts::1 9974 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12579 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25363 # Per bank write bursts
> system.physmem.perBankRdBursts::4 17343 # Per bank write bursts
> system.physmem.perBankRdBursts::5 22132 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11760 # Per bank write bursts
> system.physmem.perBankRdBursts::7 14137 # Per bank write bursts
> system.physmem.perBankRdBursts::8 11660 # Per bank write bursts
> system.physmem.perBankRdBursts::9 15453 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11698 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11338 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9437 # Per bank write bursts
> system.physmem.perBankRdBursts::13 9564 # Per bank write bursts
> system.physmem.perBankRdBursts::14 9858 # Per bank write bursts
> system.physmem.perBankRdBursts::15 20511 # Per bank write bursts
> system.physmem.perBankWrBursts::0 5992 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6239 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6121 # Per bank write bursts
> system.physmem.perBankWrBursts::3 6129 # Per bank write bursts
> system.physmem.perBankWrBursts::4 6098 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6229 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6018 # Per bank write bursts
> system.physmem.perBankWrBursts::7 5980 # Per bank write bursts
> system.physmem.perBankWrBursts::8 5938 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6095 # Per bank write bursts
> system.physmem.perBankWrBursts::10 6202 # Per bank write bursts
> system.physmem.perBankWrBursts::11 5916 # Per bank write bursts
> system.physmem.perBankWrBursts::12 6046 # Per bank write bursts
> system.physmem.perBankWrBursts::13 6090 # Per bank write bursts
> system.physmem.perBankWrBursts::14 6173 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6015 # Per bank write bursts
90c90
< system.physmem.totGap 37283321500 # Total gap between requests
---
> system.physmem.totGap 37982044500 # Total gap between requests
97c97
< system.physmem.readPktSize::6 222574 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 222619 # Read request sizes (log2)
104,117c104,117
< system.physmem.writePktSize::6 97262 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 113358 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 61350 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 14014 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 10209 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 5990 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 5097 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 4548 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 4202 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3541 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 97298 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 111989 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 59707 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 15764 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 10925 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 6262 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 5252 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 4622 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 4266 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 76 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 38 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see
152,176c152,176
< system.physmem.wrQLenPdf::15 1119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1183 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 1912 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 2549 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4946 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5524 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6019 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6870 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 7426 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7971 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8650 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8737 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7379 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6528 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6235 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 91 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 53 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1089 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1151 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 1856 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 2518 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 3246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4935 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5530 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6006 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6447 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6796 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7367 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7813 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 8377 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8639 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7998 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6745 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6258 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 95 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see
178,179c178,179
< system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
201,219c201,219
< system.physmem.bytesPerActivate::samples 132565 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 154.319345 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 102.621145 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 210.186270 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 82651 62.35% 62.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 32256 24.33% 86.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6354 4.79% 91.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2721 2.05% 93.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 1163 0.88% 94.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1002 0.76% 95.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 846 0.64% 95.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 812 0.61% 96.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 4760 3.59% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 132565 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 37.864488 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 211.288279 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 5866 99.86% 99.86% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-1023 7 0.12% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 132891 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 153.980270 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 102.520664 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 209.589027 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 82855 62.35% 62.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 32511 24.46% 86.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6209 4.67% 91.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2728 2.05% 93.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 1195 0.90% 94.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 994 0.75% 95.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 885 0.67% 95.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 776 0.58% 96.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 4738 3.57% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 132891 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 37.813870 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 211.295819 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 5876 99.88% 99.88% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-1023 6 0.10% 99.98% # Reads before turning the bus around for writes
221,241c221,242
< system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5874 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.554307 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.512747 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.243213 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 4672 79.54% 79.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 38 0.65% 80.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 729 12.41% 92.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 209 3.56% 96.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 107 1.82% 97.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 58 0.99% 98.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 31 0.53% 99.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 16 0.27% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 11 0.19% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 2 0.03% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5874 # Writes before turning the bus around for reads
< system.physmem.totQLat 7261518854 # Total ticks spent queuing
< system.physmem.totMemAccLat 11431968854 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1112120000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 32647.19 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.535951 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.496117 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.216118 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 4707 80.01% 80.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 47 0.80% 80.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 703 11.95% 92.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 205 3.48% 96.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 109 1.85% 98.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 61 1.04% 99.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 33 0.56% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 11 0.19% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 1 0.02% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 4 0.07% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads
> system.physmem.totQLat 8417974819 # Total ticks spent queuing
> system.physmem.totMemAccLat 12589137319 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1112310000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 37840.06 # Average queueing delay per DRAM burst
243,247c244,248
< system.physmem.avgMemAccLat 51397.19 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 381.81 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 166.92 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 382.07 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 166.96 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 56590.06 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 374.85 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 163.92 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 375.11 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 163.95 # Average system write bandwidth in MiByte/s
249,293c250,304
< system.physmem.busUtil 4.29 # Data bus utilization in percentage
< system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes
< system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing
< system.physmem.readRowHits 157163 # Number of row buffer hits during reads
< system.physmem.writeRowHits 29925 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 70.66 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 30.77 # Row buffer hit rate for writes
< system.physmem.avgGap 116570.12 # Average gap between requests
< system.physmem.pageHitRate 58.52 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 537077520 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 293048250 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 957496800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 315958320 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 23206024395 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 2012333250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 29756923815 # Total energy per rank (pJ)
< system.physmem_0.averagePower 798.183082 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 3201879547 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1244880000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 32834079203 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 464871960 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 253650375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 777051600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 313949520 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 21592790730 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 3427453500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 29264752965 # Total energy per rank (pJ)
< system.physmem_1.averagePower 784.981262 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 5568954615 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1244880000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 30467009135 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 17068882 # Number of BP lookups
< system.cpu.branchPred.condPredicted 11456187 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 597693 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9279962 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 7373647 # Number of BTB hits
---
> system.physmem.busUtil 4.21 # Data bus utilization in percentage
> system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing
> system.physmem.readRowHits 157076 # Number of row buffer hits during reads
> system.physmem.writeRowHits 29766 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 70.61 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes
> system.physmem.avgGap 118724.68 # Average gap between requests
> system.physmem.pageHitRate 58.43 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 508332300 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 270162255 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 877813020 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 254767320 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3007433520.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2937544590 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 74566560 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 13007568150 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 1007588640 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 71626485 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 22017862440 # Total energy per rank (pJ)
> system.physmem_0.averagePower 579.691165 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 31344656336 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 41004063 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1272480000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 195565250 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 2624595348 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 5323818601 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 28524592738 # Time in different power states
> system.physmem_1.actEnergy 440580840 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 234159090 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 710558520 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 253039500 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 2889422640.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2771748120 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 73304160 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 11932439280 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 1384694400 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 508589940 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 21198847170 # Total energy per rank (pJ)
> system.physmem_1.averagePower 558.127949 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 31712588164 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 50452548 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1222746000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 1938473750 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 3605935527 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 4996269288 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 26168178887 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 17071043 # Number of BP lookups
> system.cpu.branchPred.condPredicted 11458506 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 598065 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9277652 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 7374059 # Number of BTB hits
295,301c306,312
< system.cpu.branchPred.BTBHitPct 79.457728 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1854916 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 101589 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 233217 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 195584 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 37633 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 22185 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 79.481953 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1854771 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 101571 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 233347 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 194967 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 38380 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 22266 # Number of mispredicted indirect branches.
303c314
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
333c344
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
363c374
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
393c404
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
424,425c435,436
< system.cpu.pwrStateResidencyTicks::ON 37283333000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 74566667 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 37982056000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 75964113 # number of cpu cycles simulated
428,441c439,452
< system.cpu.fetch.icacheStallCycles 5541341 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 87099155 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 17068882 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 9424147 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 65038748 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1222021 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 11659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 30739 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 22432357 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 69340 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 71233545 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.545306 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.327706 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 5537723 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 87105546 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 17071043 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 9423797 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 66074321 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1222765 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 12043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 60 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 33616 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 22433583 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 69302 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 72269145 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.523281 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.330897 # Number of instructions fetched each cycle (Total)
443,446c454,457
< system.cpu.fetch.rateDist::0 26059108 36.58% 36.58% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 8166381 11.46% 48.05% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 9112889 12.79% 60.84% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 27895167 39.16% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 27092588 37.49% 37.49% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 8164913 11.30% 48.79% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 9113637 12.61% 61.40% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 27898007 38.60% 100.00% # Number of instructions fetched each cycle (Total)
450,477c461,488
< system.cpu.fetch.rateDist::total 71233545 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.228908 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.168071 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 8928507 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 25221623 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 30949867 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 5689167 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 444381 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 3134053 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 168503 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 100299686 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 2798262 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 444381 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 13572247 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 10675080 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 842433 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 31772787 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 13926617 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 98328841 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 859440 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 4124148 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 69439 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 4596367 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 5265270 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 103255092 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 453545884 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 114277398 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 716 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 72269145 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.224725 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.146667 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 8914938 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 26268747 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 30971085 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 5669704 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 444671 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 3134143 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 168562 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 100303161 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 2799230 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 444671 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 13550474 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 11467047 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 876029 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 31784130 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 14146794 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 98330583 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 860090 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 4210253 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 70388 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 4670257 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 5435231 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 103259286 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 453553071 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 114279094 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups
479,496c490,507
< system.cpu.rename.UndoneMaps 9625723 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 18974 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 19002 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 12839389 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 24155878 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 21759886 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1433320 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 2321800 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 97398916 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 34841 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 94478155 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 593843 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 6751150 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 17960313 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1055 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 71233545 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.326316 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.168839 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 9629917 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 18998 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 19022 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 12803731 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 24155645 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 21760500 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1435489 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 2293932 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 97400499 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 34856 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 94484787 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 595355 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 6752748 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 17957034 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1070 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 72269145 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.307401 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.171287 # Number of insts issued each cycle
498,503c509,514
< system.cpu.iq.issued_per_cycle::0 23112455 32.45% 32.45% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 17441476 24.48% 56.93% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 17040128 23.92% 80.85% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 11602976 16.29% 97.14% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 2035055 2.86% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 1455 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 24146655 33.41% 33.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 17449315 24.14% 57.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 17027031 23.56% 81.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 11604628 16.06% 97.18% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 2040054 2.82% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 1462 0.00% 100.00% # Number of insts issued each cycle
510c521
< system.cpu.iq.issued_per_cycle::total 71233545 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 72269145 # Number of insts issued each cycle
512,513c523,524
< system.cpu.iq.fu_full::IntAlu 6731709 22.63% 22.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 38 0.00% 22.63% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 6736684 22.63% 22.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 37 0.00% 22.63% # attempts to use FU when none available
541,542c552,553
< system.cpu.iq.fu_full::MemRead 11081856 37.26% 59.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 11930481 40.11% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 11088474 37.25% 59.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 11940322 40.11% 100.00% # attempts to use FU when none available
546,547c557,558
< system.cpu.iq.FU_type_0::IntAlu 49303920 52.19% 52.19% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 86563 0.09% 52.28% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 49305598 52.18% 52.18% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 86530 0.09% 52.28% # Type of FU issued
568c579
< system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.28% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatCmp 11 0.00% 52.28% # Type of FU issued
571c582
< system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.28% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 52.28% # Type of FU issued
575,576c586,587
< system.cpu.iq.FU_type_0::MemRead 23954982 25.36% 77.63% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 21132627 22.37% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 23958877 25.36% 77.63% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 21133721 22.37% 100.00% # Type of FU issued
579,591c590,602
< system.cpu.iq.FU_type_0::total 94478155 # Type of FU issued
< system.cpu.iq.rate 1.267029 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 29744084 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.314825 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 290527434 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 104196109 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 93201296 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 348 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 616 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 124222040 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 1368179 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 94484787 # Type of FU issued
> system.cpu.iq.rate 1.243808 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 29765517 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.315030 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 291599265 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 104199326 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 93203450 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 124250121 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 183 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 1368397 # Number of loads that had data forwarded from stores
593,594c604,605
< system.cpu.iew.lsq.thread0.squashedLoads 1289616 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 2048 # Number of memory responses ignored because the instruction is squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1289383 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 2091 # Number of memory responses ignored because the instruction is squashed
596c607
< system.cpu.iew.lsq.thread0.squashedStores 1204148 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 1204762 # Number of stores squashed
599,600c610,611
< system.cpu.iew.lsq.thread0.rescheduledLoads 144864 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 185613 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 147075 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 188044 # Number of times an access to memory failed due to the cache being blocked
602,605c613,616
< system.cpu.iew.iewSquashCycles 444381 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 624509 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1115710 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 97447803 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 444671 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 622988 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1195662 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 97449431 # Number of instructions dispatched to IQ
607,611c618,622
< system.cpu.iew.iewDispLoadInsts 24155878 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 21759886 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 18921 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 1617 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 1111435 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewDispLoadInsts 24155645 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 21760500 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 18936 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 1589 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 1191442 # Number of times the LSQ has become full, causing a stall
613,618c624,629
< system.cpu.iew.predictedTakenIncorrect 249911 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 221890 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 471801 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 93685311 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 23691817 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 792844 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedTakenIncorrect 249986 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 222081 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 472067 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 93691189 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 23695668 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 793598 # Number of squashed instructions skipped in execute
620,631c631,642
< system.cpu.iew.exec_nop 14046 # number of nop insts executed
< system.cpu.iew.exec_refs 44616394 # number of memory reference insts executed
< system.cpu.iew.exec_branches 14207133 # Number of branches executed
< system.cpu.iew.exec_stores 20924577 # Number of stores executed
< system.cpu.iew.exec_rate 1.256397 # Inst execution rate
< system.cpu.iew.wb_sent 93308677 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 93201392 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 44951021 # num instructions producing a value
< system.cpu.iew.wb_consumers 76633881 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.249907 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.586569 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 5894305 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 14076 # number of nop insts executed
> system.cpu.iew.exec_refs 44621004 # number of memory reference insts executed
> system.cpu.iew.exec_branches 14207535 # Number of branches executed
> system.cpu.iew.exec_stores 20925336 # Number of stores executed
> system.cpu.iew.exec_rate 1.233361 # Inst execution rate
> system.cpu.iew.wb_sent 93310594 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 93203542 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 44951761 # num instructions producing a value
> system.cpu.iew.wb_consumers 76639550 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.226942 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.586535 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 5895620 # The number of squashed insts skipped by commit
633,636c644,647
< system.cpu.commit.branchMispredicts 431064 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 70277782 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.290424 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.118209 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 431354 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 71312758 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.271696 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.107515 # Number of insts commited each cycle
638,646c649,657
< system.cpu.commit.committed_per_cycle::0 36842990 52.42% 52.42% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 16674938 23.73% 76.15% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 4291723 6.11% 82.26% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 4149088 5.90% 88.16% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1947878 2.77% 90.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1240751 1.77% 92.70% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 737656 1.05% 93.75% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 580756 0.83% 94.58% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 3812002 5.42% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 37859507 53.09% 53.09% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 16683603 23.39% 76.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 4297164 6.03% 82.51% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 4156384 5.83% 88.34% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1956005 2.74% 91.08% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1240140 1.74% 92.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 732437 1.03% 93.85% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 578410 0.81% 94.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 3809108 5.34% 100.00% # Number of insts commited each cycle
650c661
< system.cpu.commit.committed_per_cycle::total 70277782 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 71312758 # Number of insts commited each cycle
696,700c707,711
< system.cpu.commit.bw_lim_events 3812002 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 163022945 # The number of ROB reads
< system.cpu.rob.rob_writes 194122181 # The number of ROB writes
< system.cpu.timesIdled 54257 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 3333122 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 3809108 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 164062130 # The number of ROB reads
> system.cpu.rob.rob_writes 194125448 # The number of ROB writes
> system.cpu.timesIdled 54252 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 3694968 # Total number of cycles that the CPU has spent unscheduled due to idling
703,713c714,724
< system.cpu.cpi 1.051603 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.051603 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.950930 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.950930 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 101976703 # number of integer regfile reads
< system.cpu.int_regfile_writes 56611271 # number of integer regfile writes
< system.cpu.fp_regfile_reads 60 # number of floating regfile reads
< system.cpu.fp_regfile_writes 48 # number of floating regfile writes
< system.cpu.cc_regfile_reads 345090037 # number of cc regfile reads
< system.cpu.cc_regfile_writes 38758670 # number of cc regfile writes
< system.cpu.misc_regfile_reads 44101489 # number of misc regfile reads
---
> system.cpu.cpi 1.071311 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.071311 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.933436 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.933436 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 101982930 # number of integer regfile reads
> system.cpu.int_regfile_writes 56612163 # number of integer regfile writes
> system.cpu.fp_regfile_reads 58 # number of floating regfile reads
> system.cpu.fp_regfile_writes 45 # number of floating regfile writes
> system.cpu.cc_regfile_reads 345107562 # number of cc regfile reads
> system.cpu.cc_regfile_writes 38759661 # number of cc regfile writes
> system.cpu.misc_regfile_reads 44102170 # number of misc regfile reads
715,724c726,735
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 484862 # number of replacements
< system.cpu.dcache.tags.tagsinuse 510.874566 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40338135 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 485374 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 83.107325 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 151605500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 510.874566 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.997802 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 484814 # number of replacements
> system.cpu.dcache.tags.tagsinuse 510.868965 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40339815 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 485326 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 83.119007 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 154595500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 510.868965 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy
729,739c740,750
< system.cpu.dcache.tags.tag_accesses 84467396 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 84467396 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 21414103 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 21414103 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18832546 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18832546 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 60212 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 60212 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 15310 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 15310 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 84466838 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 84466838 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 21417711 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 21417711 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18830642 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18830642 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 15309 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 15309 # number of LoadLockedReq hits
742,769c753,780
< system.cpu.dcache.demand_hits::cpu.data 40246649 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 40246649 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 40306861 # number of overall hits
< system.cpu.dcache.overall_hits::total 40306861 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 566310 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 566310 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1017355 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1017355 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 68643 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 68643 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 613 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 613 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1583665 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1583665 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1652308 # number of overall misses
< system.cpu.dcache.overall_misses::total 1652308 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 13581553500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 13581553500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 13903205430 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 13903205430 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5738500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 5738500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 27484758930 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 27484758930 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 27484758930 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 27484758930 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 21980413 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 21980413 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 40248353 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 40248353 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 40308541 # number of overall hits
> system.cpu.dcache.overall_hits::total 40308541 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 562442 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 562442 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1019259 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1019259 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 68672 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 68672 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 614 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 614 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1581701 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1581701 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1650373 # number of overall misses
> system.cpu.dcache.overall_misses::total 1650373 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 14412910000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 14412910000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 14258561428 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 14258561428 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5705500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 5705500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 28671471428 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 28671471428 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 28671471428 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 28671471428 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 21980153 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 21980153 # number of ReadReq accesses(hits+misses)
772,773c783,784
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 128860 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 128860 # number of SoftPFReq accesses(hits+misses)
778,843c789,854
< system.cpu.dcache.demand_accesses::cpu.data 41830314 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 41830314 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 41959169 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 41959169 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025764 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.025764 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051252 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.051252 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532715 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.532715 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038498 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038498 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.037859 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.037859 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.039379 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.039379 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23982.542247 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 23982.542247 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13666.031454 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 13666.031454 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9361.337684 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9361.337684 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 17355.159664 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 17355.159664 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 16634.161990 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 16634.161990 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 2820837 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 130956 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 21.540342 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 484862 # number of writebacks
< system.cpu.dcache.writebacks::total 484862 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267183 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 267183 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868792 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 868792 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 613 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 613 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 1135975 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1135975 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1135975 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1135975 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299127 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 299127 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148563 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 148563 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37696 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 37696 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 447690 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 447690 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 485386 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 485386 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6671017500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6671017500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2276896471 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2276896471 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1910092000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1910092000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947913971 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8947913971 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10858005971 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10858005971 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013609 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013609 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 41830054 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 41830054 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 41958914 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 41958914 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025589 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.025589 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051348 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.051348 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532919 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.532919 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038561 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038561 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.037813 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.037813 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.039333 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.039333 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.593395 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.593395 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13989.144494 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 13989.144494 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9292.345277 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9292.345277 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 18126.985712 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 18126.985712 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 17372.722062 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 17372.722062 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 2956958 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 131265 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.666667 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 22.526629 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 484814 # number of writebacks
> system.cpu.dcache.writebacks::total 484814 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263368 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 263368 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870698 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 870698 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 614 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1134066 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1134066 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1134066 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1134066 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299074 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 299074 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148561 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 148561 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37704 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 37704 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 447635 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 447635 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 485339 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 485339 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7124794500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7124794500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2343478471 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2343478471 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1981400500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1981400500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9468272971 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9468272971 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11449673471 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11449673471 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013607 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013607 # mshr miss rate for ReadReq accesses
846,871c857,882
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292546 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292546 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010703 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.010703 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011568 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.011568 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22301.622722 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22301.622722 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15326.134172 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15326.134172 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50670.946520 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50670.946520 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19986.852445 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 19986.852445 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22369.837554 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22369.837554 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 325915 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.404253 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 22094458 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 326427 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 67.685755 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 1157973500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.404253 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.996883 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.996883 # Average percentage of cache occupancy
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292597 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292597 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010701 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.010701 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011567 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.011567 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23822.848191 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23822.848191 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15774.520036 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15774.520036 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52551.466688 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52551.466688 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21151.770909 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 21151.770909 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23591.084728 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 23591.084728 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 325639 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.373274 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 22095836 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 326151 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 67.747258 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 1176670500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.373274 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.996823 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.996823 # Average percentage of cache occupancy
873,877c884,888
< system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 328 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id
879,920c890,931
< system.cpu.icache.tags.tag_accesses 45190725 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 45190725 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 22094458 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 22094458 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 22094458 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 22094458 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 22094458 # number of overall hits
< system.cpu.icache.overall_hits::total 22094458 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 337685 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 337685 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 337685 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 337685 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 337685 # number of overall misses
< system.cpu.icache.overall_misses::total 337685 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 5566889382 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 5566889382 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 5566889382 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 5566889382 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 5566889382 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 5566889382 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 22432143 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 22432143 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 22432143 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 22432143 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 22432143 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 22432143 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015054 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.015054 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.015054 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.015054 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.015054 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.015054 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16485.450589 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 16485.450589 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 16485.450589 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 16485.450589 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 546680 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 53 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 25668 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 45192862 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 45192862 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 22095836 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 22095836 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 22095836 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 22095836 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 22095836 # number of overall hits
> system.cpu.icache.overall_hits::total 22095836 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 337513 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 337513 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 337513 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 337513 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 337513 # number of overall misses
> system.cpu.icache.overall_misses::total 337513 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 5817859355 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 5817859355 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 5817859355 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 5817859355 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 5817859355 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 5817859355 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 22433349 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 22433349 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 22433349 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 22433349 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 22433349 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 22433349 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015045 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.015045 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.015045 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.015045 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.015045 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.015045 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17237.437832 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 17237.437832 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 17237.437832 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 17237.437832 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 562602 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 26054 # number of cycles access was blocked
922,959c933,970
< system.cpu.icache.avg_blocked_cycles::no_mshrs 21.298114 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 26.500000 # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 325915 # number of writebacks
< system.cpu.icache.writebacks::total 325915 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11245 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 11245 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 11245 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 11245 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 11245 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 11245 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326440 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 326440 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 326440 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 326440 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 326440 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 326440 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5156036946 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 5156036946 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5156036946 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 5156036946 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5156036946 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 5156036946 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014552 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.014552 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.014552 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15794.746189 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15794.746189 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 822007 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 825699 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 3235 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 21.593690 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked
> system.cpu.icache.writebacks::writebacks 325639 # number of writebacks
> system.cpu.icache.writebacks::total 325639 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11348 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 11348 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 11348 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 11348 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 11348 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 11348 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326165 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 326165 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 326165 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 326165 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 326165 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 326165 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5383419413 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 5383419413 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5383419413 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 5383419413 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5383419413 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 5383419413 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16505.202621 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16505.202621 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 823055 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 826389 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 2921 # number of redundant prefetches already in prefetch queue
962,968c973,979
< system.cpu.l2cache.prefetcher.pfSpanPage 78661 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 125486 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 15697.579441 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 682126 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 141813 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.810039 # Average number of references to valid blocks.
---
> system.cpu.l2cache.prefetcher.pfSpanPage 78691 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 125520 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 15698.936659 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 681800 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 141835 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.806994 # Average number of references to valid blocks.
970,976c981,987
< system.cpu.l2cache.tags.occ_blocks::writebacks 15632.148504 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 65.430937 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.954111 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003994 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.958104 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 23 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 16304 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 15629.036475 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 69.900184 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.953921 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004266 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.958187 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 27 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 16288 # Occupied blocks per task id
978,1050c989,1061
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 12 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2745 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12082 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 548 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 792 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001404 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 25510486 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 25510486 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 254711 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 254711 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 476176 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 476176 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 137223 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 137223 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 289219 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 289219 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 256138 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 256138 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 289219 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 393361 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 682580 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 289219 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 393361 # number of overall hits
< system.cpu.l2cache.overall_hits::total 682580 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 11378 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 11378 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37206 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 37206 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80635 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 80635 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 37206 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 92013 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 129219 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 37206 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 92013 # number of overall misses
< system.cpu.l2cache.overall_misses::total 129219 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1158421000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1158421000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2926655500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2926655500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6384062000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 6384062000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2926655500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7542483000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10469138500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2926655500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7542483000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10469138500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 254711 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 254711 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 476176 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 476176 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 12 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 12 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 148601 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 148601 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 326425 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 326425 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336773 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 336773 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 326425 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 485374 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 811799 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 326425 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 485374 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 811799 # number of overall (read+write) accesses
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2543 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12218 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 510 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 881 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001648 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 25499859 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 25499859 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 257633 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 257633 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 472926 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 472926 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 137172 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 137172 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 289056 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 289056 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 255940 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 255940 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 289056 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 393112 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 682168 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 289056 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 393112 # number of overall hits
> system.cpu.l2cache.overall_hits::total 682168 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 11425 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 11425 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37095 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 37095 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80789 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 80789 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 37095 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 92214 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 129309 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 37095 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 92214 # number of overall misses
> system.cpu.l2cache.overall_misses::total 129309 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1226064500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1226064500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3155473000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 3155473000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6910815500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 6910815500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 3155473000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8136880000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11292353000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 3155473000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8136880000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11292353000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 257633 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 257633 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 472926 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 472926 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 148597 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 148597 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 326151 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 326151 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336729 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 336729 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 326151 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 485326 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 811477 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 326151 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 485326 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 811477 # number of overall (read+write) accesses
1053,1076c1064,1087
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076567 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.076567 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113980 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113980 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239434 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239434 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113980 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.189571 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.159176 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113980 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.189571 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.159176 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101812.357181 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101812.357181 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78660.847713 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78660.847713 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79172.344515 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79172.344515 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78660.847713 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81971.927880 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 81018.569251 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78660.847713 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81971.927880 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 81018.569251 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076886 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.076886 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113736 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113736 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239923 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239923 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113736 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.190004 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.159350 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113736 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.190004 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.159350 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107314.179431 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107314.179431 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85064.644831 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85064.644831 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85541.540309 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85541.540309 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85064.644831 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88239.096016 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 87328.438082 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85064.644831 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88239.096016 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 87328.438082 # average overall miss latency
1083,1131c1094,1142
< system.cpu.l2cache.unused_prefetches 412 # number of HardPF blocks evicted w/o reference
< system.cpu.l2cache.writebacks::writebacks 97262 # number of writebacks
< system.cpu.l2cache.writebacks::total 97262 # number of writebacks
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2980 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 2980 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 28 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 28 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 115 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 115 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 3095 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 3123 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 3095 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 3123 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 115252 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 115252 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 12 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8398 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 8398 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37178 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37178 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80520 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80520 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 37178 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 88918 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 126096 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 37178 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 88918 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115252 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 241348 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 9954483724 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 9954483724 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 680267500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 680267500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2701591500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2701591500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5893524000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5893524000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2701591500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6573791500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9275383000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2701591500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6573791500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 9954483724 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 19229866724 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.unused_prefetches 452 # number of HardPF blocks evicted w/o reference
> system.cpu.l2cache.writebacks::writebacks 97298 # number of writebacks
> system.cpu.l2cache.writebacks::total 97298 # number of writebacks
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3085 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 3085 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 119 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 119 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 3204 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 3227 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 3204 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 3227 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 115310 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 115310 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8340 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 8340 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37072 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37072 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80670 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80670 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 37072 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 89010 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 126082 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 37072 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 89010 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115310 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 241392 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10321796922 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10321796922 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 201500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 201500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 722790000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 722790000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2931479000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2931479000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6418843000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6418843000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2931479000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7141633000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10073112000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2931479000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7141633000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10321796922 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 20394908922 # number of overall MSHR miss cycles
1136,1146c1147,1157
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056514 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056514 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113894 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239093 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239093 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.155329 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056125 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056125 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113665 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239570 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239570 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.155373 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for overall accesses
1148,1170c1159,1181
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.297300 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 86371.461875 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15458.333333 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15458.333333 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81003.512741 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81003.512741 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72666.402173 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72666.402173 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73193.293592 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73193.293592 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73558.106522 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79676.925949 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 1622603 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 810817 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79904 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 18775 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18774 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.297472 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89513.458694 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86665.467626 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86665.467626 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79075.285930 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79075.285930 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79569.145903 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79569.145903 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79893.339255 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84488.752411 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 1621957 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 810494 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 18773 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18772 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1172,1194c1183,1205
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 663212 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 351973 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 556066 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 28224 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 144126 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 148601 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 148601 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 326440 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 336773 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 978779 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455634 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 2434413 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41749696 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62095104 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 103844800 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 269627 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 6225728 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 1081438 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.091286 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.288019 # Request fanout histogram
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 662893 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 354931 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 552820 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 28222 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 146565 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 148597 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 148597 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 326165 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 336729 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977954 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455492 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 2433446 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41714496 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62088960 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 103803456 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 272099 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 6227968 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 1083589 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.091107 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.287765 # Request fanout histogram
1196,1197c1207,1208
< system.cpu.toL2Bus.snoop_fanout::0 982719 90.87% 90.87% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 98718 9.13% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 984867 90.89% 90.89% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 98721 9.11% 100.00% # Request fanout histogram
1202,1205c1213,1216
< system.cpu.toL2Bus.snoop_fanout::total 1081438 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 1622078500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 489794228 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1083589 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 1621431500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 489373744 # Layer occupancy (ticks)
1207,1210c1218,1221
< system.cpu.toL2Bus.respLayer1.occupancy 728148836 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
< system.membus.snoop_filter.tot_requests 348072 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 205263 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.respLayer1.occupancy 728066857 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%)
> system.membus.snoop_filter.tot_requests 348152 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 205320 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1215,1226c1226,1237
< system.membus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 214175 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 97262 # Transaction distribution
< system.membus.trans_dist::CleanEvict 28224 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 12 # Transaction distribution
< system.membus.trans_dist::ReadExReq 8398 # Transaction distribution
< system.membus.trans_dist::ReadExResp 8398 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570645 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 570645 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20469440 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 20469440 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 214278 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 97298 # Transaction distribution
> system.membus.trans_dist::CleanEvict 28222 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 13 # Transaction distribution
> system.membus.trans_dist::ReadExReq 8340 # Transaction distribution
> system.membus.trans_dist::ReadExResp 8340 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 214279 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570770 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 570770 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20474624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 20474624 # Cumulative packet size per connected master and slave (bytes)
1229c1240
< system.membus.snoop_fanout::samples 222586 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 222632 # Request fanout histogram
1233c1244
< system.membus.snoop_fanout::0 222586 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 222632 100.00% 100.00% # Request fanout histogram
1238,1239c1249,1250
< system.membus.snoop_fanout::total 222586 # Request fanout histogram
< system.membus.reqLayer0.occupancy 837454269 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 222632 # Request fanout histogram
> system.membus.reqLayer0.occupancy 835899979 # Layer occupancy (ticks)
1241,1242c1252,1253
< system.membus.respLayer1.occupancy 1175863136 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 3.2 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 1175524166 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 3.1 # Layer utilization (%)