1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.024561 # Number of seconds simulated
4sim_ticks 24560764000 # Number of ticks simulated
5final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.024561 # Number of seconds simulated
4sim_ticks 24560764000 # Number of ticks simulated
5final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 54926 # Simulator instruction rate (inst/s)
8host_op_rate 77943 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 19021903 # Simulator tick rate (ticks/s)
10host_mem_usage 240316 # Number of bytes of host memory used
11host_seconds 1291.18 # Real time elapsed on the host
| 7host_inst_rate 104807 # Simulator instruction rate (inst/s)
8host_op_rate 148726 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 36296181 # Simulator tick rate (ticks/s)
10host_mem_usage 240672 # Number of bytes of host memory used
11host_seconds 676.68 # Real time elapsed on the host
|
12sim_insts 70920072 # Number of instructions simulated
13sim_ops 100639320 # Number of ops (including micro ops) simulated
| 12sim_insts 70920072 # Number of instructions simulated
13sim_ops 100639320 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read 8687232 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 367552 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 5661632 # Number of bytes written to this memory
17system.physmem.num_reads 135738 # Number of read requests responded to by this memory
18system.physmem.num_writes 88463 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 353703655 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 14965007 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 230515305 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 584218960 # Total bandwidth to/from this memory (bytes/s)
| 14system.physmem.bytes_read::cpu.inst 367552 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 8319680 # Number of bytes read from this memory
16system.physmem.bytes_read::total 8687232 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 367552 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 367552 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 5661632 # Number of bytes written to this memory
20system.physmem.bytes_written::total 5661632 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 5743 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 129995 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 135738 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 88463 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 88463 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 14965007 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 338738648 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 353703655 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 14965007 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 14965007 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 230515305 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 230515305 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 230515305 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 14965007 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 338738648 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 584218960 # Total bandwidth to/from this memory (bytes/s)
|
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
32system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
33system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
34system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
35system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
36system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
37system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
38system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
39system.cpu.dtb.read_accesses 0 # DTB read accesses
40system.cpu.dtb.write_accesses 0 # DTB write accesses
41system.cpu.dtb.inst_accesses 0 # ITB inst accesses
42system.cpu.dtb.hits 0 # DTB hits
43system.cpu.dtb.misses 0 # DTB misses
44system.cpu.dtb.accesses 0 # DTB accesses
45system.cpu.itb.inst_hits 0 # ITB inst hits
46system.cpu.itb.inst_misses 0 # ITB inst misses
47system.cpu.itb.read_hits 0 # DTB read hits
48system.cpu.itb.read_misses 0 # DTB read misses
49system.cpu.itb.write_hits 0 # DTB write hits
50system.cpu.itb.write_misses 0 # DTB write misses
51system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
52system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
53system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
54system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
55system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
56system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
57system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
58system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
60system.cpu.itb.read_accesses 0 # DTB read accesses
61system.cpu.itb.write_accesses 0 # DTB write accesses
62system.cpu.itb.inst_accesses 0 # ITB inst accesses
63system.cpu.itb.hits 0 # DTB hits
64system.cpu.itb.misses 0 # DTB misses
65system.cpu.itb.accesses 0 # DTB accesses
66system.cpu.workload.num_syscalls 1946 # Number of system calls
67system.cpu.numCycles 49121529 # number of cpu cycles simulated
68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
70system.cpu.BPredUnit.lookups 17484643 # Number of BP lookups
71system.cpu.BPredUnit.condPredicted 13346532 # Number of conditional branches predicted
72system.cpu.BPredUnit.condIncorrect 763895 # Number of conditional branches incorrect
73system.cpu.BPredUnit.BTBLookups 12042742 # Number of BTB lookups
74system.cpu.BPredUnit.BTBHits 8272877 # Number of BTB hits
75system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
76system.cpu.BPredUnit.usedRAS 1873235 # Number of times the RAS was used to get a target.
77system.cpu.BPredUnit.RASInCorrect 186435 # Number of incorrect RAS predictions.
78system.cpu.fetch.icacheStallCycles 13233353 # Number of cycles fetch is stalled on an Icache miss
79system.cpu.fetch.Insts 89314081 # Number of instructions fetch has processed
80system.cpu.fetch.Branches 17484643 # Number of branches that fetch encountered
81system.cpu.fetch.predictedBranches 10146112 # Number of branches that fetch has predicted taken
82system.cpu.fetch.Cycles 22235900 # Number of cycles fetch has run and was not squashing or blocked
83system.cpu.fetch.SquashCycles 3054378 # Number of cycles fetch has spent squashing
84system.cpu.fetch.BlockedCycles 9993886 # Number of cycles fetch has spent blocked
85system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
86system.cpu.fetch.PendingTrapStallCycles 494 # Number of stall cycles due to pending traps
87system.cpu.fetch.CacheLines 12432222 # Number of cache lines fetched
88system.cpu.fetch.IcacheSquashes 242141 # Number of outstanding Icache misses that were squashed
89system.cpu.fetch.rateDist::samples 47666513 # Number of instructions fetched each cycle (Total)
90system.cpu.fetch.rateDist::mean 2.625620 # Number of instructions fetched each cycle (Total)
91system.cpu.fetch.rateDist::stdev 3.342151 # Number of instructions fetched each cycle (Total)
92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
93system.cpu.fetch.rateDist::0 25452916 53.40% 53.40% # Number of instructions fetched each cycle (Total)
94system.cpu.fetch.rateDist::1 2276272 4.78% 58.17% # Number of instructions fetched each cycle (Total)
95system.cpu.fetch.rateDist::2 2010669 4.22% 62.39% # Number of instructions fetched each cycle (Total)
96system.cpu.fetch.rateDist::3 2082167 4.37% 66.76% # Number of instructions fetched each cycle (Total)
97system.cpu.fetch.rateDist::4 1606372 3.37% 70.13% # Number of instructions fetched each cycle (Total)
98system.cpu.fetch.rateDist::5 1473384 3.09% 73.22% # Number of instructions fetched each cycle (Total)
99system.cpu.fetch.rateDist::6 1003270 2.10% 75.33% # Number of instructions fetched each cycle (Total)
100system.cpu.fetch.rateDist::7 1293693 2.71% 78.04% # Number of instructions fetched each cycle (Total)
101system.cpu.fetch.rateDist::8 10467770 21.96% 100.00% # Number of instructions fetched each cycle (Total)
102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
105system.cpu.fetch.rateDist::total 47666513 # Number of instructions fetched each cycle (Total)
106system.cpu.fetch.branchRate 0.355947 # Number of branch fetches per cycle
107system.cpu.fetch.rate 1.818227 # Number of inst fetches per cycle
108system.cpu.decode.IdleCycles 15402794 # Number of cycles decode is idle
109system.cpu.decode.BlockedCycles 8395926 # Number of cycles decode is blocked
110system.cpu.decode.RunCycles 20419082 # Number of cycles decode is running
111system.cpu.decode.UnblockCycles 1357324 # Number of cycles decode is unblocking
112system.cpu.decode.SquashCycles 2091387 # Number of cycles decode is squashing
113system.cpu.decode.BranchResolved 3552582 # Number of times decode resolved a branch
114system.cpu.decode.BranchMispred 114889 # Number of times decode detected a branch misprediction
115system.cpu.decode.DecodedInsts 122010152 # Number of instructions handled by decode
116system.cpu.decode.SquashedInsts 381349 # Number of squashed instructions handled by decode
117system.cpu.rename.SquashCycles 2091387 # Number of cycles rename is squashing
118system.cpu.rename.IdleCycles 17235553 # Number of cycles rename is idle
119system.cpu.rename.BlockCycles 2381046 # Number of cycles rename is blocking
120system.cpu.rename.serializeStallCycles 774700 # count of cycles rename stalled for serializing inst
121system.cpu.rename.RunCycles 19895179 # Number of cycles rename is running
122system.cpu.rename.UnblockCycles 5288648 # Number of cycles rename is unblocking
123system.cpu.rename.RenamedInsts 118965286 # Number of instructions processed by rename
124system.cpu.rename.ROBFullEvents 65 # Number of times rename has blocked due to ROB full
125system.cpu.rename.IQFullEvents 10051 # Number of times rename has blocked due to IQ full
126system.cpu.rename.LSQFullEvents 4471697 # Number of times rename has blocked due to LSQ full
127system.cpu.rename.FullRegisterEvents 173 # Number of times there has been no free registers
128system.cpu.rename.RenamedOperands 119289544 # Number of destination operands rename has renamed
129system.cpu.rename.RenameLookups 547314245 # Number of register rename lookups that rename has made
130system.cpu.rename.int_rename_lookups 547305502 # Number of integer rename lookups
131system.cpu.rename.fp_rename_lookups 8743 # Number of floating rename lookups
132system.cpu.rename.CommittedMaps 99152581 # Number of HB maps that are committed
133system.cpu.rename.UndoneMaps 20136963 # Number of HB maps that are undone due to squashing
134system.cpu.rename.serializingInsts 50089 # count of serializing insts renamed
135system.cpu.rename.tempSerializingInsts 50062 # count of temporary serializing insts renamed
136system.cpu.rename.skidInsts 12897670 # count of insts added to the skid buffer
137system.cpu.memDep0.insertedLoads 30342934 # Number of loads inserted to the mem dependence unit.
138system.cpu.memDep0.insertedStores 22764283 # Number of stores inserted to the mem dependence unit.
139system.cpu.memDep0.conflictingLoads 3373932 # Number of conflicting loads.
140system.cpu.memDep0.conflictingStores 4070444 # Number of conflicting stores.
141system.cpu.iq.iqInstsAdded 114201865 # Number of instructions added to the IQ (excludes non-spec)
142system.cpu.iq.iqNonSpecInstsAdded 59946 # Number of non-speculative instructions added to the IQ
143system.cpu.iq.iqInstsIssued 108885427 # Number of instructions issued
144system.cpu.iq.iqSquashedInstsIssued 355885 # Number of squashed instructions issued
145system.cpu.iq.iqSquashedInstsExamined 13447173 # Number of squashed instructions iterated over during squash; mainly for profiling
146system.cpu.iq.iqSquashedOperandsExamined 32642565 # Number of squashed operands that are examined and possibly removed from graph
147system.cpu.iq.iqSquashedNonSpecRemoved 23673 # Number of squashed non-spec instructions that were removed
148system.cpu.iq.issued_per_cycle::samples 47666513 # Number of insts issued each cycle
149system.cpu.iq.issued_per_cycle::mean 2.284317 # Number of insts issued each cycle
150system.cpu.iq.issued_per_cycle::stdev 2.003120 # Number of insts issued each cycle
151system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
152system.cpu.iq.issued_per_cycle::0 11902735 24.97% 24.97% # Number of insts issued each cycle
153system.cpu.iq.issued_per_cycle::1 8314690 17.44% 42.41% # Number of insts issued each cycle
154system.cpu.iq.issued_per_cycle::2 7496951 15.73% 58.14% # Number of insts issued each cycle
155system.cpu.iq.issued_per_cycle::3 7072171 14.84% 72.98% # Number of insts issued each cycle
156system.cpu.iq.issued_per_cycle::4 5553695 11.65% 84.63% # Number of insts issued each cycle
157system.cpu.iq.issued_per_cycle::5 3902484 8.19% 92.82% # Number of insts issued each cycle
158system.cpu.iq.issued_per_cycle::6 1926147 4.04% 96.86% # Number of insts issued each cycle
159system.cpu.iq.issued_per_cycle::7 904880 1.90% 98.76% # Number of insts issued each cycle
160system.cpu.iq.issued_per_cycle::8 592760 1.24% 100.00% # Number of insts issued each cycle
161system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
162system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
163system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
164system.cpu.iq.issued_per_cycle::total 47666513 # Number of insts issued each cycle
165system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
166system.cpu.iq.fu_full::IntAlu 112261 4.35% 4.35% # attempts to use FU when none available
167system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available
168system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available
169system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.35% # attempts to use FU when none available
170system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available
171system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available
172system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available
173system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available
174system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
175system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available
176system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available
177system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available
178system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available
179system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available
180system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available
181system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available
182system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available
183system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available
184system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available
185system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available
186system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available
187system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available
188system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available
189system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available
190system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available
191system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available
192system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available
193system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available
194system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
195system.cpu.iq.fu_full::MemRead 1423319 55.12% 59.47% # attempts to use FU when none available
196system.cpu.iq.fu_full::MemWrite 1046695 40.53% 100.00% # attempts to use FU when none available
197system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
198system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
199system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
200system.cpu.iq.FU_type_0::IntAlu 57627292 52.92% 52.92% # Type of FU issued
201system.cpu.iq.FU_type_0::IntMult 88925 0.08% 53.01% # Type of FU issued
202system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.01% # Type of FU issued
203system.cpu.iq.FU_type_0::FloatAdd 277 0.00% 53.01% # Type of FU issued
204system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.01% # Type of FU issued
205system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.01% # Type of FU issued
206system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.01% # Type of FU issued
207system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.01% # Type of FU issued
208system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.01% # Type of FU issued
209system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.01% # Type of FU issued
210system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.01% # Type of FU issued
211system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.01% # Type of FU issued
212system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.01% # Type of FU issued
213system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.01% # Type of FU issued
214system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.01% # Type of FU issued
215system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.01% # Type of FU issued
216system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.01% # Type of FU issued
217system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.01% # Type of FU issued
218system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.01% # Type of FU issued
219system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.01% # Type of FU issued
220system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.01% # Type of FU issued
221system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.01% # Type of FU issued
222system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.01% # Type of FU issued
223system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.01% # Type of FU issued
224system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.01% # Type of FU issued
225system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.01% # Type of FU issued
226system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.01% # Type of FU issued
227system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.01% # Type of FU issued
228system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.01% # Type of FU issued
229system.cpu.iq.FU_type_0::MemRead 29380371 26.98% 79.99% # Type of FU issued
230system.cpu.iq.FU_type_0::MemWrite 21788555 20.01% 100.00% # Type of FU issued
231system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
232system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
233system.cpu.iq.FU_type_0::total 108885427 # Type of FU issued
234system.cpu.iq.rate 2.216654 # Inst issue rate
235system.cpu.iq.fu_busy_cnt 2582277 # FU busy when requested
236system.cpu.iq.fu_busy_rate 0.023716 # FU busy rate (busy events/executed inst)
237system.cpu.iq.int_inst_queue_reads 268374678 # Number of integer instruction queue reads
238system.cpu.iq.int_inst_queue_writes 127734912 # Number of integer instruction queue writes
239system.cpu.iq.int_inst_queue_wakeup_accesses 106613834 # Number of integer instruction queue wakeup accesses
240system.cpu.iq.fp_inst_queue_reads 851 # Number of floating instruction queue reads
241system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes
242system.cpu.iq.fp_inst_queue_wakeup_accesses 211 # Number of floating instruction queue wakeup accesses
243system.cpu.iq.int_alu_accesses 111467277 # Number of integer alu accesses
244system.cpu.iq.fp_alu_accesses 427 # Number of floating point alu accesses
245system.cpu.iew.lsq.thread0.forwLoads 2219770 # Number of loads that had data forwarded from stores
246system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
247system.cpu.iew.lsq.thread0.squashedLoads 3033338 # Number of loads squashed
248system.cpu.iew.lsq.thread0.ignoredResponses 8348 # Number of memory responses ignored because the instruction is squashed
249system.cpu.iew.lsq.thread0.memOrderViolation 28761 # Number of memory ordering violations
250system.cpu.iew.lsq.thread0.squashedStores 2206058 # Number of stores squashed
251system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
252system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
253system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled
254system.cpu.iew.lsq.thread0.cacheBlocked 51 # Number of times an access to memory failed due to the cache being blocked
255system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
256system.cpu.iew.iewSquashCycles 2091387 # Number of cycles IEW is squashing
257system.cpu.iew.iewBlockCycles 991755 # Number of cycles IEW is blocking
258system.cpu.iew.iewUnblockCycles 31052 # Number of cycles IEW is unblocking
259system.cpu.iew.iewDispatchedInsts 114342127 # Number of instructions dispatched to IQ
260system.cpu.iew.iewDispSquashedInsts 442332 # Number of squashed instructions skipped by dispatch
261system.cpu.iew.iewDispLoadInsts 30342934 # Number of dispatched load instructions
262system.cpu.iew.iewDispStoreInsts 22764283 # Number of dispatched store instructions
263system.cpu.iew.iewDispNonSpecInsts 43712 # Number of dispatched non-speculative instructions
264system.cpu.iew.iewIQFullEvents 1891 # Number of times the IQ has become full, causing a stall
265system.cpu.iew.iewLSQFullEvents 1967 # Number of times the LSQ has become full, causing a stall
266system.cpu.iew.memOrderViolationEvents 28761 # Number of memory order violations
267system.cpu.iew.predictedTakenIncorrect 532244 # Number of branches that were predicted taken incorrectly
268system.cpu.iew.predictedNotTakenIncorrect 266639 # Number of branches that were predicted not taken incorrectly
269system.cpu.iew.branchMispredicts 798883 # Number of branch mispredicts detected at execute
270system.cpu.iew.iewExecutedInsts 107583415 # Number of executed instructions
271system.cpu.iew.iewExecLoadInsts 28980389 # Number of load instructions executed
272system.cpu.iew.iewExecSquashedInsts 1302012 # Number of squashed instructions skipped in execute
273system.cpu.iew.exec_swp 0 # number of swp insts executed
274system.cpu.iew.exec_nop 80316 # number of nop insts executed
275system.cpu.iew.exec_refs 50461236 # number of memory reference insts executed
276system.cpu.iew.exec_branches 14752818 # Number of branches executed
277system.cpu.iew.exec_stores 21480847 # Number of stores executed
278system.cpu.iew.exec_rate 2.190148 # Inst execution rate
279system.cpu.iew.wb_sent 106971474 # cumulative count of insts sent to commit
280system.cpu.iew.wb_count 106614045 # cumulative count of insts written-back
281system.cpu.iew.wb_producers 53628736 # num instructions producing a value
282system.cpu.iew.wb_consumers 104822222 # num instructions consuming a value
283system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
284system.cpu.iew.wb_rate 2.170414 # insts written-back per cycle
285system.cpu.iew.wb_fanout 0.511616 # average fanout of values written-back
286system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
287system.cpu.commit.commitCommittedInsts 70925624 # The number of committed instructions
288system.cpu.commit.commitCommittedOps 100644872 # The number of committed instructions
289system.cpu.commit.commitSquashedInsts 13697900 # The number of squashed insts skipped by commit
290system.cpu.commit.commitNonSpecStalls 36273 # The number of times commit has been forced to stall to communicate backwards
291system.cpu.commit.branchMispredicts 715054 # The number of times a branch was mispredicted
292system.cpu.commit.committed_per_cycle::samples 45575127 # Number of insts commited each cycle
293system.cpu.commit.committed_per_cycle::mean 2.208329 # Number of insts commited each cycle
294system.cpu.commit.committed_per_cycle::stdev 2.734720 # Number of insts commited each cycle
295system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
296system.cpu.commit.committed_per_cycle::0 16228357 35.61% 35.61% # Number of insts commited each cycle
297system.cpu.commit.committed_per_cycle::1 11797211 25.89% 61.49% # Number of insts commited each cycle
298system.cpu.commit.committed_per_cycle::2 3508330 7.70% 69.19% # Number of insts commited each cycle
299system.cpu.commit.committed_per_cycle::3 2972714 6.52% 75.71% # Number of insts commited each cycle
300system.cpu.commit.committed_per_cycle::4 1972056 4.33% 80.04% # Number of insts commited each cycle
301system.cpu.commit.committed_per_cycle::5 1932722 4.24% 84.28% # Number of insts commited each cycle
302system.cpu.commit.committed_per_cycle::6 698627 1.53% 85.81% # Number of insts commited each cycle
303system.cpu.commit.committed_per_cycle::7 551617 1.21% 87.02% # Number of insts commited each cycle
304system.cpu.commit.committed_per_cycle::8 5913493 12.98% 100.00% # Number of insts commited each cycle
305system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
306system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
307system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
308system.cpu.commit.committed_per_cycle::total 45575127 # Number of insts commited each cycle
309system.cpu.commit.committedInsts 70925624 # Number of instructions committed
310system.cpu.commit.committedOps 100644872 # Number of ops (including micro ops) committed
311system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
312system.cpu.commit.refs 47867821 # Number of memory references committed
313system.cpu.commit.loads 27309596 # Number of loads committed
314system.cpu.commit.membars 15920 # Number of memory barriers committed
315system.cpu.commit.branches 13671115 # Number of branches committed
316system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
317system.cpu.commit.int_insts 91482735 # Number of committed integer instructions.
318system.cpu.commit.function_calls 1679850 # Number of function calls committed.
319system.cpu.commit.bw_lim_events 5913493 # number cycles where commit BW limit reached
320system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
321system.cpu.rob.rob_reads 153979107 # The number of ROB reads
322system.cpu.rob.rob_writes 230788170 # The number of ROB writes
323system.cpu.timesIdled 64143 # Number of times that the entire CPU went into an idle state and unscheduled itself
324system.cpu.idleCycles 1455016 # Total number of cycles that the CPU has spent unscheduled due to idling
325system.cpu.committedInsts 70920072 # Number of Instructions Simulated
326system.cpu.committedOps 100639320 # Number of Ops (including micro ops) Simulated
327system.cpu.committedInsts_total 70920072 # Number of Instructions Simulated
328system.cpu.cpi 0.692632 # CPI: Cycles Per Instruction
329system.cpu.cpi_total 0.692632 # CPI: Total CPI of All Threads
330system.cpu.ipc 1.443768 # IPC: Instructions Per Cycle
331system.cpu.ipc_total 1.443768 # IPC: Total IPC of All Threads
332system.cpu.int_regfile_reads 517371049 # number of integer regfile reads
333system.cpu.int_regfile_writes 104514948 # number of integer regfile writes
334system.cpu.fp_regfile_reads 1051 # number of floating regfile reads
335system.cpu.fp_regfile_writes 886 # number of floating regfile writes
336system.cpu.misc_regfile_reads 147913903 # number of misc regfile reads
337system.cpu.misc_regfile_writes 36814 # number of misc regfile writes
338system.cpu.icache.replacements 31518 # number of replacements
339system.cpu.icache.tagsinuse 1822.469235 # Cycle average of tags in use
340system.cpu.icache.total_refs 12397113 # Total number of references to valid blocks.
341system.cpu.icache.sampled_refs 33561 # Sample count of references to valid blocks.
342system.cpu.icache.avg_refs 369.390453 # Average number of references to valid blocks.
343system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
344system.cpu.icache.occ_blocks::cpu.inst 1822.469235 # Average occupied blocks per requestor
345system.cpu.icache.occ_percent::cpu.inst 0.889878 # Average percentage of cache occupancy
346system.cpu.icache.occ_percent::total 0.889878 # Average percentage of cache occupancy
347system.cpu.icache.ReadReq_hits::cpu.inst 12397114 # number of ReadReq hits
348system.cpu.icache.ReadReq_hits::total 12397114 # number of ReadReq hits
349system.cpu.icache.demand_hits::cpu.inst 12397114 # number of demand (read+write) hits
350system.cpu.icache.demand_hits::total 12397114 # number of demand (read+write) hits
351system.cpu.icache.overall_hits::cpu.inst 12397114 # number of overall hits
352system.cpu.icache.overall_hits::total 12397114 # number of overall hits
353system.cpu.icache.ReadReq_misses::cpu.inst 35108 # number of ReadReq misses
354system.cpu.icache.ReadReq_misses::total 35108 # number of ReadReq misses
355system.cpu.icache.demand_misses::cpu.inst 35108 # number of demand (read+write) misses
356system.cpu.icache.demand_misses::total 35108 # number of demand (read+write) misses
357system.cpu.icache.overall_misses::cpu.inst 35108 # number of overall misses
358system.cpu.icache.overall_misses::total 35108 # number of overall misses
359system.cpu.icache.ReadReq_miss_latency::cpu.inst 406151000 # number of ReadReq miss cycles
360system.cpu.icache.ReadReq_miss_latency::total 406151000 # number of ReadReq miss cycles
361system.cpu.icache.demand_miss_latency::cpu.inst 406151000 # number of demand (read+write) miss cycles
362system.cpu.icache.demand_miss_latency::total 406151000 # number of demand (read+write) miss cycles
363system.cpu.icache.overall_miss_latency::cpu.inst 406151000 # number of overall miss cycles
364system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles
365system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses)
367system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses
368system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses
369system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses
370system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses
371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses
| 37system.cpu.dtb.inst_hits 0 # ITB inst hits
38system.cpu.dtb.inst_misses 0 # ITB inst misses
39system.cpu.dtb.read_hits 0 # DTB read hits
40system.cpu.dtb.read_misses 0 # DTB read misses
41system.cpu.dtb.write_hits 0 # DTB write hits
42system.cpu.dtb.write_misses 0 # DTB write misses
43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
45system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
46system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
47system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
48system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
49system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
50system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
51system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
52system.cpu.dtb.read_accesses 0 # DTB read accesses
53system.cpu.dtb.write_accesses 0 # DTB write accesses
54system.cpu.dtb.inst_accesses 0 # ITB inst accesses
55system.cpu.dtb.hits 0 # DTB hits
56system.cpu.dtb.misses 0 # DTB misses
57system.cpu.dtb.accesses 0 # DTB accesses
58system.cpu.itb.inst_hits 0 # ITB inst hits
59system.cpu.itb.inst_misses 0 # ITB inst misses
60system.cpu.itb.read_hits 0 # DTB read hits
61system.cpu.itb.read_misses 0 # DTB read misses
62system.cpu.itb.write_hits 0 # DTB write hits
63system.cpu.itb.write_misses 0 # DTB write misses
64system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
65system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
66system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
67system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
68system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
69system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
70system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
71system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
73system.cpu.itb.read_accesses 0 # DTB read accesses
74system.cpu.itb.write_accesses 0 # DTB write accesses
75system.cpu.itb.inst_accesses 0 # ITB inst accesses
76system.cpu.itb.hits 0 # DTB hits
77system.cpu.itb.misses 0 # DTB misses
78system.cpu.itb.accesses 0 # DTB accesses
79system.cpu.workload.num_syscalls 1946 # Number of system calls
80system.cpu.numCycles 49121529 # number of cpu cycles simulated
81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
83system.cpu.BPredUnit.lookups 17484643 # Number of BP lookups
84system.cpu.BPredUnit.condPredicted 13346532 # Number of conditional branches predicted
85system.cpu.BPredUnit.condIncorrect 763895 # Number of conditional branches incorrect
86system.cpu.BPredUnit.BTBLookups 12042742 # Number of BTB lookups
87system.cpu.BPredUnit.BTBHits 8272877 # Number of BTB hits
88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
89system.cpu.BPredUnit.usedRAS 1873235 # Number of times the RAS was used to get a target.
90system.cpu.BPredUnit.RASInCorrect 186435 # Number of incorrect RAS predictions.
91system.cpu.fetch.icacheStallCycles 13233353 # Number of cycles fetch is stalled on an Icache miss
92system.cpu.fetch.Insts 89314081 # Number of instructions fetch has processed
93system.cpu.fetch.Branches 17484643 # Number of branches that fetch encountered
94system.cpu.fetch.predictedBranches 10146112 # Number of branches that fetch has predicted taken
95system.cpu.fetch.Cycles 22235900 # Number of cycles fetch has run and was not squashing or blocked
96system.cpu.fetch.SquashCycles 3054378 # Number of cycles fetch has spent squashing
97system.cpu.fetch.BlockedCycles 9993886 # Number of cycles fetch has spent blocked
98system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
99system.cpu.fetch.PendingTrapStallCycles 494 # Number of stall cycles due to pending traps
100system.cpu.fetch.CacheLines 12432222 # Number of cache lines fetched
101system.cpu.fetch.IcacheSquashes 242141 # Number of outstanding Icache misses that were squashed
102system.cpu.fetch.rateDist::samples 47666513 # Number of instructions fetched each cycle (Total)
103system.cpu.fetch.rateDist::mean 2.625620 # Number of instructions fetched each cycle (Total)
104system.cpu.fetch.rateDist::stdev 3.342151 # Number of instructions fetched each cycle (Total)
105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
106system.cpu.fetch.rateDist::0 25452916 53.40% 53.40% # Number of instructions fetched each cycle (Total)
107system.cpu.fetch.rateDist::1 2276272 4.78% 58.17% # Number of instructions fetched each cycle (Total)
108system.cpu.fetch.rateDist::2 2010669 4.22% 62.39% # Number of instructions fetched each cycle (Total)
109system.cpu.fetch.rateDist::3 2082167 4.37% 66.76% # Number of instructions fetched each cycle (Total)
110system.cpu.fetch.rateDist::4 1606372 3.37% 70.13% # Number of instructions fetched each cycle (Total)
111system.cpu.fetch.rateDist::5 1473384 3.09% 73.22% # Number of instructions fetched each cycle (Total)
112system.cpu.fetch.rateDist::6 1003270 2.10% 75.33% # Number of instructions fetched each cycle (Total)
113system.cpu.fetch.rateDist::7 1293693 2.71% 78.04% # Number of instructions fetched each cycle (Total)
114system.cpu.fetch.rateDist::8 10467770 21.96% 100.00% # Number of instructions fetched each cycle (Total)
115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
118system.cpu.fetch.rateDist::total 47666513 # Number of instructions fetched each cycle (Total)
119system.cpu.fetch.branchRate 0.355947 # Number of branch fetches per cycle
120system.cpu.fetch.rate 1.818227 # Number of inst fetches per cycle
121system.cpu.decode.IdleCycles 15402794 # Number of cycles decode is idle
122system.cpu.decode.BlockedCycles 8395926 # Number of cycles decode is blocked
123system.cpu.decode.RunCycles 20419082 # Number of cycles decode is running
124system.cpu.decode.UnblockCycles 1357324 # Number of cycles decode is unblocking
125system.cpu.decode.SquashCycles 2091387 # Number of cycles decode is squashing
126system.cpu.decode.BranchResolved 3552582 # Number of times decode resolved a branch
127system.cpu.decode.BranchMispred 114889 # Number of times decode detected a branch misprediction
128system.cpu.decode.DecodedInsts 122010152 # Number of instructions handled by decode
129system.cpu.decode.SquashedInsts 381349 # Number of squashed instructions handled by decode
130system.cpu.rename.SquashCycles 2091387 # Number of cycles rename is squashing
131system.cpu.rename.IdleCycles 17235553 # Number of cycles rename is idle
132system.cpu.rename.BlockCycles 2381046 # Number of cycles rename is blocking
133system.cpu.rename.serializeStallCycles 774700 # count of cycles rename stalled for serializing inst
134system.cpu.rename.RunCycles 19895179 # Number of cycles rename is running
135system.cpu.rename.UnblockCycles 5288648 # Number of cycles rename is unblocking
136system.cpu.rename.RenamedInsts 118965286 # Number of instructions processed by rename
137system.cpu.rename.ROBFullEvents 65 # Number of times rename has blocked due to ROB full
138system.cpu.rename.IQFullEvents 10051 # Number of times rename has blocked due to IQ full
139system.cpu.rename.LSQFullEvents 4471697 # Number of times rename has blocked due to LSQ full
140system.cpu.rename.FullRegisterEvents 173 # Number of times there has been no free registers
141system.cpu.rename.RenamedOperands 119289544 # Number of destination operands rename has renamed
142system.cpu.rename.RenameLookups 547314245 # Number of register rename lookups that rename has made
143system.cpu.rename.int_rename_lookups 547305502 # Number of integer rename lookups
144system.cpu.rename.fp_rename_lookups 8743 # Number of floating rename lookups
145system.cpu.rename.CommittedMaps 99152581 # Number of HB maps that are committed
146system.cpu.rename.UndoneMaps 20136963 # Number of HB maps that are undone due to squashing
147system.cpu.rename.serializingInsts 50089 # count of serializing insts renamed
148system.cpu.rename.tempSerializingInsts 50062 # count of temporary serializing insts renamed
149system.cpu.rename.skidInsts 12897670 # count of insts added to the skid buffer
150system.cpu.memDep0.insertedLoads 30342934 # Number of loads inserted to the mem dependence unit.
151system.cpu.memDep0.insertedStores 22764283 # Number of stores inserted to the mem dependence unit.
152system.cpu.memDep0.conflictingLoads 3373932 # Number of conflicting loads.
153system.cpu.memDep0.conflictingStores 4070444 # Number of conflicting stores.
154system.cpu.iq.iqInstsAdded 114201865 # Number of instructions added to the IQ (excludes non-spec)
155system.cpu.iq.iqNonSpecInstsAdded 59946 # Number of non-speculative instructions added to the IQ
156system.cpu.iq.iqInstsIssued 108885427 # Number of instructions issued
157system.cpu.iq.iqSquashedInstsIssued 355885 # Number of squashed instructions issued
158system.cpu.iq.iqSquashedInstsExamined 13447173 # Number of squashed instructions iterated over during squash; mainly for profiling
159system.cpu.iq.iqSquashedOperandsExamined 32642565 # Number of squashed operands that are examined and possibly removed from graph
160system.cpu.iq.iqSquashedNonSpecRemoved 23673 # Number of squashed non-spec instructions that were removed
161system.cpu.iq.issued_per_cycle::samples 47666513 # Number of insts issued each cycle
162system.cpu.iq.issued_per_cycle::mean 2.284317 # Number of insts issued each cycle
163system.cpu.iq.issued_per_cycle::stdev 2.003120 # Number of insts issued each cycle
164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
165system.cpu.iq.issued_per_cycle::0 11902735 24.97% 24.97% # Number of insts issued each cycle
166system.cpu.iq.issued_per_cycle::1 8314690 17.44% 42.41% # Number of insts issued each cycle
167system.cpu.iq.issued_per_cycle::2 7496951 15.73% 58.14% # Number of insts issued each cycle
168system.cpu.iq.issued_per_cycle::3 7072171 14.84% 72.98% # Number of insts issued each cycle
169system.cpu.iq.issued_per_cycle::4 5553695 11.65% 84.63% # Number of insts issued each cycle
170system.cpu.iq.issued_per_cycle::5 3902484 8.19% 92.82% # Number of insts issued each cycle
171system.cpu.iq.issued_per_cycle::6 1926147 4.04% 96.86% # Number of insts issued each cycle
172system.cpu.iq.issued_per_cycle::7 904880 1.90% 98.76% # Number of insts issued each cycle
173system.cpu.iq.issued_per_cycle::8 592760 1.24% 100.00% # Number of insts issued each cycle
174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
177system.cpu.iq.issued_per_cycle::total 47666513 # Number of insts issued each cycle
178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
179system.cpu.iq.fu_full::IntAlu 112261 4.35% 4.35% # attempts to use FU when none available
180system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available
181system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available
182system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.35% # attempts to use FU when none available
183system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available
184system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available
185system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available
186system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available
187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
188system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available
189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available
190system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available
191system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available
192system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available
193system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available
194system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available
195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available
196system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available
197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available
198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available
199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available
200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available
201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available
202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available
203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available
204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available
205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available
206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available
207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
208system.cpu.iq.fu_full::MemRead 1423319 55.12% 59.47% # attempts to use FU when none available
209system.cpu.iq.fu_full::MemWrite 1046695 40.53% 100.00% # attempts to use FU when none available
210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
213system.cpu.iq.FU_type_0::IntAlu 57627292 52.92% 52.92% # Type of FU issued
214system.cpu.iq.FU_type_0::IntMult 88925 0.08% 53.01% # Type of FU issued
215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.01% # Type of FU issued
216system.cpu.iq.FU_type_0::FloatAdd 277 0.00% 53.01% # Type of FU issued
217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.01% # Type of FU issued
218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.01% # Type of FU issued
219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.01% # Type of FU issued
220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.01% # Type of FU issued
221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.01% # Type of FU issued
222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.01% # Type of FU issued
223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.01% # Type of FU issued
224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.01% # Type of FU issued
225system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.01% # Type of FU issued
226system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.01% # Type of FU issued
227system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.01% # Type of FU issued
228system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.01% # Type of FU issued
229system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.01% # Type of FU issued
230system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.01% # Type of FU issued
231system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.01% # Type of FU issued
232system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.01% # Type of FU issued
233system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.01% # Type of FU issued
234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.01% # Type of FU issued
235system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.01% # Type of FU issued
236system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.01% # Type of FU issued
237system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.01% # Type of FU issued
238system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.01% # Type of FU issued
239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.01% # Type of FU issued
240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.01% # Type of FU issued
241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.01% # Type of FU issued
242system.cpu.iq.FU_type_0::MemRead 29380371 26.98% 79.99% # Type of FU issued
243system.cpu.iq.FU_type_0::MemWrite 21788555 20.01% 100.00% # Type of FU issued
244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
246system.cpu.iq.FU_type_0::total 108885427 # Type of FU issued
247system.cpu.iq.rate 2.216654 # Inst issue rate
248system.cpu.iq.fu_busy_cnt 2582277 # FU busy when requested
249system.cpu.iq.fu_busy_rate 0.023716 # FU busy rate (busy events/executed inst)
250system.cpu.iq.int_inst_queue_reads 268374678 # Number of integer instruction queue reads
251system.cpu.iq.int_inst_queue_writes 127734912 # Number of integer instruction queue writes
252system.cpu.iq.int_inst_queue_wakeup_accesses 106613834 # Number of integer instruction queue wakeup accesses
253system.cpu.iq.fp_inst_queue_reads 851 # Number of floating instruction queue reads
254system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes
255system.cpu.iq.fp_inst_queue_wakeup_accesses 211 # Number of floating instruction queue wakeup accesses
256system.cpu.iq.int_alu_accesses 111467277 # Number of integer alu accesses
257system.cpu.iq.fp_alu_accesses 427 # Number of floating point alu accesses
258system.cpu.iew.lsq.thread0.forwLoads 2219770 # Number of loads that had data forwarded from stores
259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
260system.cpu.iew.lsq.thread0.squashedLoads 3033338 # Number of loads squashed
261system.cpu.iew.lsq.thread0.ignoredResponses 8348 # Number of memory responses ignored because the instruction is squashed
262system.cpu.iew.lsq.thread0.memOrderViolation 28761 # Number of memory ordering violations
263system.cpu.iew.lsq.thread0.squashedStores 2206058 # Number of stores squashed
264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
266system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled
267system.cpu.iew.lsq.thread0.cacheBlocked 51 # Number of times an access to memory failed due to the cache being blocked
268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
269system.cpu.iew.iewSquashCycles 2091387 # Number of cycles IEW is squashing
270system.cpu.iew.iewBlockCycles 991755 # Number of cycles IEW is blocking
271system.cpu.iew.iewUnblockCycles 31052 # Number of cycles IEW is unblocking
272system.cpu.iew.iewDispatchedInsts 114342127 # Number of instructions dispatched to IQ
273system.cpu.iew.iewDispSquashedInsts 442332 # Number of squashed instructions skipped by dispatch
274system.cpu.iew.iewDispLoadInsts 30342934 # Number of dispatched load instructions
275system.cpu.iew.iewDispStoreInsts 22764283 # Number of dispatched store instructions
276system.cpu.iew.iewDispNonSpecInsts 43712 # Number of dispatched non-speculative instructions
277system.cpu.iew.iewIQFullEvents 1891 # Number of times the IQ has become full, causing a stall
278system.cpu.iew.iewLSQFullEvents 1967 # Number of times the LSQ has become full, causing a stall
279system.cpu.iew.memOrderViolationEvents 28761 # Number of memory order violations
280system.cpu.iew.predictedTakenIncorrect 532244 # Number of branches that were predicted taken incorrectly
281system.cpu.iew.predictedNotTakenIncorrect 266639 # Number of branches that were predicted not taken incorrectly
282system.cpu.iew.branchMispredicts 798883 # Number of branch mispredicts detected at execute
283system.cpu.iew.iewExecutedInsts 107583415 # Number of executed instructions
284system.cpu.iew.iewExecLoadInsts 28980389 # Number of load instructions executed
285system.cpu.iew.iewExecSquashedInsts 1302012 # Number of squashed instructions skipped in execute
286system.cpu.iew.exec_swp 0 # number of swp insts executed
287system.cpu.iew.exec_nop 80316 # number of nop insts executed
288system.cpu.iew.exec_refs 50461236 # number of memory reference insts executed
289system.cpu.iew.exec_branches 14752818 # Number of branches executed
290system.cpu.iew.exec_stores 21480847 # Number of stores executed
291system.cpu.iew.exec_rate 2.190148 # Inst execution rate
292system.cpu.iew.wb_sent 106971474 # cumulative count of insts sent to commit
293system.cpu.iew.wb_count 106614045 # cumulative count of insts written-back
294system.cpu.iew.wb_producers 53628736 # num instructions producing a value
295system.cpu.iew.wb_consumers 104822222 # num instructions consuming a value
296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
297system.cpu.iew.wb_rate 2.170414 # insts written-back per cycle
298system.cpu.iew.wb_fanout 0.511616 # average fanout of values written-back
299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
300system.cpu.commit.commitCommittedInsts 70925624 # The number of committed instructions
301system.cpu.commit.commitCommittedOps 100644872 # The number of committed instructions
302system.cpu.commit.commitSquashedInsts 13697900 # The number of squashed insts skipped by commit
303system.cpu.commit.commitNonSpecStalls 36273 # The number of times commit has been forced to stall to communicate backwards
304system.cpu.commit.branchMispredicts 715054 # The number of times a branch was mispredicted
305system.cpu.commit.committed_per_cycle::samples 45575127 # Number of insts commited each cycle
306system.cpu.commit.committed_per_cycle::mean 2.208329 # Number of insts commited each cycle
307system.cpu.commit.committed_per_cycle::stdev 2.734720 # Number of insts commited each cycle
308system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
309system.cpu.commit.committed_per_cycle::0 16228357 35.61% 35.61% # Number of insts commited each cycle
310system.cpu.commit.committed_per_cycle::1 11797211 25.89% 61.49% # Number of insts commited each cycle
311system.cpu.commit.committed_per_cycle::2 3508330 7.70% 69.19% # Number of insts commited each cycle
312system.cpu.commit.committed_per_cycle::3 2972714 6.52% 75.71% # Number of insts commited each cycle
313system.cpu.commit.committed_per_cycle::4 1972056 4.33% 80.04% # Number of insts commited each cycle
314system.cpu.commit.committed_per_cycle::5 1932722 4.24% 84.28% # Number of insts commited each cycle
315system.cpu.commit.committed_per_cycle::6 698627 1.53% 85.81% # Number of insts commited each cycle
316system.cpu.commit.committed_per_cycle::7 551617 1.21% 87.02% # Number of insts commited each cycle
317system.cpu.commit.committed_per_cycle::8 5913493 12.98% 100.00% # Number of insts commited each cycle
318system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
319system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
320system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
321system.cpu.commit.committed_per_cycle::total 45575127 # Number of insts commited each cycle
322system.cpu.commit.committedInsts 70925624 # Number of instructions committed
323system.cpu.commit.committedOps 100644872 # Number of ops (including micro ops) committed
324system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
325system.cpu.commit.refs 47867821 # Number of memory references committed
326system.cpu.commit.loads 27309596 # Number of loads committed
327system.cpu.commit.membars 15920 # Number of memory barriers committed
328system.cpu.commit.branches 13671115 # Number of branches committed
329system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
330system.cpu.commit.int_insts 91482735 # Number of committed integer instructions.
331system.cpu.commit.function_calls 1679850 # Number of function calls committed.
332system.cpu.commit.bw_lim_events 5913493 # number cycles where commit BW limit reached
333system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
334system.cpu.rob.rob_reads 153979107 # The number of ROB reads
335system.cpu.rob.rob_writes 230788170 # The number of ROB writes
336system.cpu.timesIdled 64143 # Number of times that the entire CPU went into an idle state and unscheduled itself
337system.cpu.idleCycles 1455016 # Total number of cycles that the CPU has spent unscheduled due to idling
338system.cpu.committedInsts 70920072 # Number of Instructions Simulated
339system.cpu.committedOps 100639320 # Number of Ops (including micro ops) Simulated
340system.cpu.committedInsts_total 70920072 # Number of Instructions Simulated
341system.cpu.cpi 0.692632 # CPI: Cycles Per Instruction
342system.cpu.cpi_total 0.692632 # CPI: Total CPI of All Threads
343system.cpu.ipc 1.443768 # IPC: Instructions Per Cycle
344system.cpu.ipc_total 1.443768 # IPC: Total IPC of All Threads
345system.cpu.int_regfile_reads 517371049 # number of integer regfile reads
346system.cpu.int_regfile_writes 104514948 # number of integer regfile writes
347system.cpu.fp_regfile_reads 1051 # number of floating regfile reads
348system.cpu.fp_regfile_writes 886 # number of floating regfile writes
349system.cpu.misc_regfile_reads 147913903 # number of misc regfile reads
350system.cpu.misc_regfile_writes 36814 # number of misc regfile writes
351system.cpu.icache.replacements 31518 # number of replacements
352system.cpu.icache.tagsinuse 1822.469235 # Cycle average of tags in use
353system.cpu.icache.total_refs 12397113 # Total number of references to valid blocks.
354system.cpu.icache.sampled_refs 33561 # Sample count of references to valid blocks.
355system.cpu.icache.avg_refs 369.390453 # Average number of references to valid blocks.
356system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
357system.cpu.icache.occ_blocks::cpu.inst 1822.469235 # Average occupied blocks per requestor
358system.cpu.icache.occ_percent::cpu.inst 0.889878 # Average percentage of cache occupancy
359system.cpu.icache.occ_percent::total 0.889878 # Average percentage of cache occupancy
360system.cpu.icache.ReadReq_hits::cpu.inst 12397114 # number of ReadReq hits
361system.cpu.icache.ReadReq_hits::total 12397114 # number of ReadReq hits
362system.cpu.icache.demand_hits::cpu.inst 12397114 # number of demand (read+write) hits
363system.cpu.icache.demand_hits::total 12397114 # number of demand (read+write) hits
364system.cpu.icache.overall_hits::cpu.inst 12397114 # number of overall hits
365system.cpu.icache.overall_hits::total 12397114 # number of overall hits
366system.cpu.icache.ReadReq_misses::cpu.inst 35108 # number of ReadReq misses
367system.cpu.icache.ReadReq_misses::total 35108 # number of ReadReq misses
368system.cpu.icache.demand_misses::cpu.inst 35108 # number of demand (read+write) misses
369system.cpu.icache.demand_misses::total 35108 # number of demand (read+write) misses
370system.cpu.icache.overall_misses::cpu.inst 35108 # number of overall misses
371system.cpu.icache.overall_misses::total 35108 # number of overall misses
372system.cpu.icache.ReadReq_miss_latency::cpu.inst 406151000 # number of ReadReq miss cycles
373system.cpu.icache.ReadReq_miss_latency::total 406151000 # number of ReadReq miss cycles
374system.cpu.icache.demand_miss_latency::cpu.inst 406151000 # number of demand (read+write) miss cycles
375system.cpu.icache.demand_miss_latency::total 406151000 # number of demand (read+write) miss cycles
376system.cpu.icache.overall_miss_latency::cpu.inst 406151000 # number of overall miss cycles
377system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles
378system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses)
379system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses)
380system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses
381system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses
382system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses
383system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses
384system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses
|
| 385system.cpu.icache.ReadReq_miss_rate::total 0.002824 # miss rate for ReadReq accesses
|
372system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses
| 386system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses
|
| 387system.cpu.icache.demand_miss_rate::total 0.002824 # miss rate for demand accesses
|
373system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses
| 388system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses
|
| 389system.cpu.icache.overall_miss_rate::total 0.002824 # miss rate for overall accesses
|
374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency
| 390system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency
|
| 391system.cpu.icache.ReadReq_avg_miss_latency::total 11568.616839 # average ReadReq miss latency
|
375system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
| 392system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
|
| 393system.cpu.icache.demand_avg_miss_latency::total 11568.616839 # average overall miss latency
|
376system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
| 394system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
|
| 395system.cpu.icache.overall_avg_miss_latency::total 11568.616839 # average overall miss latency
|
377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
381system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
382system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
383system.cpu.icache.fast_writes 0 # number of fast writes performed
384system.cpu.icache.cache_copies 0 # number of cache copies performed
385system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1474 # number of ReadReq MSHR hits
386system.cpu.icache.ReadReq_mshr_hits::total 1474 # number of ReadReq MSHR hits
387system.cpu.icache.demand_mshr_hits::cpu.inst 1474 # number of demand (read+write) MSHR hits
388system.cpu.icache.demand_mshr_hits::total 1474 # number of demand (read+write) MSHR hits
389system.cpu.icache.overall_mshr_hits::cpu.inst 1474 # number of overall MSHR hits
390system.cpu.icache.overall_mshr_hits::total 1474 # number of overall MSHR hits
391system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33634 # number of ReadReq MSHR misses
392system.cpu.icache.ReadReq_mshr_misses::total 33634 # number of ReadReq MSHR misses
393system.cpu.icache.demand_mshr_misses::cpu.inst 33634 # number of demand (read+write) MSHR misses
394system.cpu.icache.demand_mshr_misses::total 33634 # number of demand (read+write) MSHR misses
395system.cpu.icache.overall_mshr_misses::cpu.inst 33634 # number of overall MSHR misses
396system.cpu.icache.overall_mshr_misses::total 33634 # number of overall MSHR misses
397system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268782500 # number of ReadReq MSHR miss cycles
398system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles
399system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles
400system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles
401system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles
402system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles
403system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses
| 396system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
397system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
398system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
399system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
400system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
401system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
402system.cpu.icache.fast_writes 0 # number of fast writes performed
403system.cpu.icache.cache_copies 0 # number of cache copies performed
404system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1474 # number of ReadReq MSHR hits
405system.cpu.icache.ReadReq_mshr_hits::total 1474 # number of ReadReq MSHR hits
406system.cpu.icache.demand_mshr_hits::cpu.inst 1474 # number of demand (read+write) MSHR hits
407system.cpu.icache.demand_mshr_hits::total 1474 # number of demand (read+write) MSHR hits
408system.cpu.icache.overall_mshr_hits::cpu.inst 1474 # number of overall MSHR hits
409system.cpu.icache.overall_mshr_hits::total 1474 # number of overall MSHR hits
410system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33634 # number of ReadReq MSHR misses
411system.cpu.icache.ReadReq_mshr_misses::total 33634 # number of ReadReq MSHR misses
412system.cpu.icache.demand_mshr_misses::cpu.inst 33634 # number of demand (read+write) MSHR misses
413system.cpu.icache.demand_mshr_misses::total 33634 # number of demand (read+write) MSHR misses
414system.cpu.icache.overall_mshr_misses::cpu.inst 33634 # number of overall MSHR misses
415system.cpu.icache.overall_mshr_misses::total 33634 # number of overall MSHR misses
416system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268782500 # number of ReadReq MSHR miss cycles
417system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles
418system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles
419system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles
420system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles
421system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles
422system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses
|
| 423system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002705 # mshr miss rate for ReadReq accesses
|
404system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses
| 424system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses
|
| 425system.cpu.icache.demand_mshr_miss_rate::total 0.002705 # mshr miss rate for demand accesses
|
405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses
| 426system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses
|
| 427system.cpu.icache.overall_mshr_miss_rate::total 0.002705 # mshr miss rate for overall accesses
|
406system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency
| 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency
|
| 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7991.392638 # average ReadReq mshr miss latency
|
407system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
| 430system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
|
| 431system.cpu.icache.demand_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency
|
408system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
| 432system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
|
| 433system.cpu.icache.overall_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency
|
409system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
410system.cpu.dcache.replacements 158907 # number of replacements
411system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use
412system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks.
413system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks.
414system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks.
415system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit.
416system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor
417system.cpu.dcache.occ_percent::cpu.data 0.993836 # Average percentage of cache occupancy
418system.cpu.dcache.occ_percent::total 0.993836 # Average percentage of cache occupancy
419system.cpu.dcache.ReadReq_hits::cpu.data 26393302 # number of ReadReq hits
420system.cpu.dcache.ReadReq_hits::total 26393302 # number of ReadReq hits
421system.cpu.dcache.WriteReq_hits::cpu.data 18309799 # number of WriteReq hits
422system.cpu.dcache.WriteReq_hits::total 18309799 # number of WriteReq hits
423system.cpu.dcache.LoadLockedReq_hits::cpu.data 19644 # number of LoadLockedReq hits
424system.cpu.dcache.LoadLockedReq_hits::total 19644 # number of LoadLockedReq hits
425system.cpu.dcache.StoreCondReq_hits::cpu.data 18406 # number of StoreCondReq hits
426system.cpu.dcache.StoreCondReq_hits::total 18406 # number of StoreCondReq hits
427system.cpu.dcache.demand_hits::cpu.data 44703101 # number of demand (read+write) hits
428system.cpu.dcache.demand_hits::total 44703101 # number of demand (read+write) hits
429system.cpu.dcache.overall_hits::cpu.data 44703101 # number of overall hits
430system.cpu.dcache.overall_hits::total 44703101 # number of overall hits
431system.cpu.dcache.ReadReq_misses::cpu.data 110193 # number of ReadReq misses
432system.cpu.dcache.ReadReq_misses::total 110193 # number of ReadReq misses
433system.cpu.dcache.WriteReq_misses::cpu.data 1540102 # number of WriteReq misses
434system.cpu.dcache.WriteReq_misses::total 1540102 # number of WriteReq misses
435system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses
436system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses
437system.cpu.dcache.demand_misses::cpu.data 1650295 # number of demand (read+write) misses
438system.cpu.dcache.demand_misses::total 1650295 # number of demand (read+write) misses
439system.cpu.dcache.overall_misses::cpu.data 1650295 # number of overall misses
440system.cpu.dcache.overall_misses::total 1650295 # number of overall misses
441system.cpu.dcache.ReadReq_miss_latency::cpu.data 2434975500 # number of ReadReq miss cycles
442system.cpu.dcache.ReadReq_miss_latency::total 2434975500 # number of ReadReq miss cycles
443system.cpu.dcache.WriteReq_miss_latency::cpu.data 52525381000 # number of WriteReq miss cycles
444system.cpu.dcache.WriteReq_miss_latency::total 52525381000 # number of WriteReq miss cycles
445system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 425000 # number of LoadLockedReq miss cycles
446system.cpu.dcache.LoadLockedReq_miss_latency::total 425000 # number of LoadLockedReq miss cycles
447system.cpu.dcache.demand_miss_latency::cpu.data 54960356500 # number of demand (read+write) miss cycles
448system.cpu.dcache.demand_miss_latency::total 54960356500 # number of demand (read+write) miss cycles
449system.cpu.dcache.overall_miss_latency::cpu.data 54960356500 # number of overall miss cycles
450system.cpu.dcache.overall_miss_latency::total 54960356500 # number of overall miss cycles
451system.cpu.dcache.ReadReq_accesses::cpu.data 26503495 # number of ReadReq accesses(hits+misses)
452system.cpu.dcache.ReadReq_accesses::total 26503495 # number of ReadReq accesses(hits+misses)
453system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
454system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
455system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19679 # number of LoadLockedReq accesses(hits+misses)
456system.cpu.dcache.LoadLockedReq_accesses::total 19679 # number of LoadLockedReq accesses(hits+misses)
457system.cpu.dcache.StoreCondReq_accesses::cpu.data 18406 # number of StoreCondReq accesses(hits+misses)
458system.cpu.dcache.StoreCondReq_accesses::total 18406 # number of StoreCondReq accesses(hits+misses)
459system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses
460system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses
461system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses
462system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses
463system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses
| 434system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
435system.cpu.dcache.replacements 158907 # number of replacements
436system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use
437system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks.
438system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks.
439system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks.
440system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit.
441system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor
442system.cpu.dcache.occ_percent::cpu.data 0.993836 # Average percentage of cache occupancy
443system.cpu.dcache.occ_percent::total 0.993836 # Average percentage of cache occupancy
444system.cpu.dcache.ReadReq_hits::cpu.data 26393302 # number of ReadReq hits
445system.cpu.dcache.ReadReq_hits::total 26393302 # number of ReadReq hits
446system.cpu.dcache.WriteReq_hits::cpu.data 18309799 # number of WriteReq hits
447system.cpu.dcache.WriteReq_hits::total 18309799 # number of WriteReq hits
448system.cpu.dcache.LoadLockedReq_hits::cpu.data 19644 # number of LoadLockedReq hits
449system.cpu.dcache.LoadLockedReq_hits::total 19644 # number of LoadLockedReq hits
450system.cpu.dcache.StoreCondReq_hits::cpu.data 18406 # number of StoreCondReq hits
451system.cpu.dcache.StoreCondReq_hits::total 18406 # number of StoreCondReq hits
452system.cpu.dcache.demand_hits::cpu.data 44703101 # number of demand (read+write) hits
453system.cpu.dcache.demand_hits::total 44703101 # number of demand (read+write) hits
454system.cpu.dcache.overall_hits::cpu.data 44703101 # number of overall hits
455system.cpu.dcache.overall_hits::total 44703101 # number of overall hits
456system.cpu.dcache.ReadReq_misses::cpu.data 110193 # number of ReadReq misses
457system.cpu.dcache.ReadReq_misses::total 110193 # number of ReadReq misses
458system.cpu.dcache.WriteReq_misses::cpu.data 1540102 # number of WriteReq misses
459system.cpu.dcache.WriteReq_misses::total 1540102 # number of WriteReq misses
460system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses
461system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses
462system.cpu.dcache.demand_misses::cpu.data 1650295 # number of demand (read+write) misses
463system.cpu.dcache.demand_misses::total 1650295 # number of demand (read+write) misses
464system.cpu.dcache.overall_misses::cpu.data 1650295 # number of overall misses
465system.cpu.dcache.overall_misses::total 1650295 # number of overall misses
466system.cpu.dcache.ReadReq_miss_latency::cpu.data 2434975500 # number of ReadReq miss cycles
467system.cpu.dcache.ReadReq_miss_latency::total 2434975500 # number of ReadReq miss cycles
468system.cpu.dcache.WriteReq_miss_latency::cpu.data 52525381000 # number of WriteReq miss cycles
469system.cpu.dcache.WriteReq_miss_latency::total 52525381000 # number of WriteReq miss cycles
470system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 425000 # number of LoadLockedReq miss cycles
471system.cpu.dcache.LoadLockedReq_miss_latency::total 425000 # number of LoadLockedReq miss cycles
472system.cpu.dcache.demand_miss_latency::cpu.data 54960356500 # number of demand (read+write) miss cycles
473system.cpu.dcache.demand_miss_latency::total 54960356500 # number of demand (read+write) miss cycles
474system.cpu.dcache.overall_miss_latency::cpu.data 54960356500 # number of overall miss cycles
475system.cpu.dcache.overall_miss_latency::total 54960356500 # number of overall miss cycles
476system.cpu.dcache.ReadReq_accesses::cpu.data 26503495 # number of ReadReq accesses(hits+misses)
477system.cpu.dcache.ReadReq_accesses::total 26503495 # number of ReadReq accesses(hits+misses)
478system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
479system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
480system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19679 # number of LoadLockedReq accesses(hits+misses)
481system.cpu.dcache.LoadLockedReq_accesses::total 19679 # number of LoadLockedReq accesses(hits+misses)
482system.cpu.dcache.StoreCondReq_accesses::cpu.data 18406 # number of StoreCondReq accesses(hits+misses)
483system.cpu.dcache.StoreCondReq_accesses::total 18406 # number of StoreCondReq accesses(hits+misses)
484system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses
485system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses
486system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses
487system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses
488system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses
|
| 489system.cpu.dcache.ReadReq_miss_rate::total 0.004158 # miss rate for ReadReq accesses
|
464system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses
| 490system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses
|
| 491system.cpu.dcache.WriteReq_miss_rate::total 0.077587 # miss rate for WriteReq accesses
|
465system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses
| 492system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses
|
| 493system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001779 # miss rate for LoadLockedReq accesses
|
466system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses
| 494system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses
|
| 495system.cpu.dcache.demand_miss_rate::total 0.035602 # miss rate for demand accesses
|
467system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses
| 496system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses
|
| 497system.cpu.dcache.overall_miss_rate::total 0.035602 # miss rate for overall accesses
|
468system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency
| 498system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency
|
| 499system.cpu.dcache.ReadReq_avg_miss_latency::total 22097.370069 # average ReadReq miss latency
|
469system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency
| 500system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency
|
| 501system.cpu.dcache.WriteReq_avg_miss_latency::total 34105.131348 # average WriteReq miss latency
|
470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency
| 502system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency
|
| 503system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12142.857143 # average LoadLockedReq miss latency
|
471system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
| 504system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
|
| 505system.cpu.dcache.demand_avg_miss_latency::total 33303.352734 # average overall miss latency
|
472system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
| 506system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
|
| 507system.cpu.dcache.overall_avg_miss_latency::total 33303.352734 # average overall miss latency
|
473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
474system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
476system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
478system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked
479system.cpu.dcache.fast_writes 0 # number of fast writes performed
480system.cpu.dcache.cache_copies 0 # number of cache copies performed
481system.cpu.dcache.writebacks::writebacks 123795 # number of writebacks
482system.cpu.dcache.writebacks::total 123795 # number of writebacks
483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54073 # number of ReadReq MSHR hits
484system.cpu.dcache.ReadReq_mshr_hits::total 54073 # number of ReadReq MSHR hits
485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1433145 # number of WriteReq MSHR hits
486system.cpu.dcache.WriteReq_mshr_hits::total 1433145 # number of WriteReq MSHR hits
487system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits
488system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits
489system.cpu.dcache.demand_mshr_hits::cpu.data 1487218 # number of demand (read+write) MSHR hits
490system.cpu.dcache.demand_mshr_hits::total 1487218 # number of demand (read+write) MSHR hits
491system.cpu.dcache.overall_mshr_hits::cpu.data 1487218 # number of overall MSHR hits
492system.cpu.dcache.overall_mshr_hits::total 1487218 # number of overall MSHR hits
493system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56120 # number of ReadReq MSHR misses
494system.cpu.dcache.ReadReq_mshr_misses::total 56120 # number of ReadReq MSHR misses
495system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106957 # number of WriteReq MSHR misses
496system.cpu.dcache.WriteReq_mshr_misses::total 106957 # number of WriteReq MSHR misses
497system.cpu.dcache.demand_mshr_misses::cpu.data 163077 # number of demand (read+write) MSHR misses
498system.cpu.dcache.demand_mshr_misses::total 163077 # number of demand (read+write) MSHR misses
499system.cpu.dcache.overall_mshr_misses::cpu.data 163077 # number of overall MSHR misses
500system.cpu.dcache.overall_mshr_misses::total 163077 # number of overall MSHR misses
501system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1049489500 # number of ReadReq MSHR miss cycles
502system.cpu.dcache.ReadReq_mshr_miss_latency::total 1049489500 # number of ReadReq MSHR miss cycles
503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3666942000 # number of WriteReq MSHR miss cycles
504system.cpu.dcache.WriteReq_mshr_miss_latency::total 3666942000 # number of WriteReq MSHR miss cycles
505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4716431500 # number of demand (read+write) MSHR miss cycles
506system.cpu.dcache.demand_mshr_miss_latency::total 4716431500 # number of demand (read+write) MSHR miss cycles
507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4716431500 # number of overall MSHR miss cycles
508system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles
509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses
| 508system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
509system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked
510system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
511system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
512system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
513system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked
514system.cpu.dcache.fast_writes 0 # number of fast writes performed
515system.cpu.dcache.cache_copies 0 # number of cache copies performed
516system.cpu.dcache.writebacks::writebacks 123795 # number of writebacks
517system.cpu.dcache.writebacks::total 123795 # number of writebacks
518system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54073 # number of ReadReq MSHR hits
519system.cpu.dcache.ReadReq_mshr_hits::total 54073 # number of ReadReq MSHR hits
520system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1433145 # number of WriteReq MSHR hits
521system.cpu.dcache.WriteReq_mshr_hits::total 1433145 # number of WriteReq MSHR hits
522system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits
523system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits
524system.cpu.dcache.demand_mshr_hits::cpu.data 1487218 # number of demand (read+write) MSHR hits
525system.cpu.dcache.demand_mshr_hits::total 1487218 # number of demand (read+write) MSHR hits
526system.cpu.dcache.overall_mshr_hits::cpu.data 1487218 # number of overall MSHR hits
527system.cpu.dcache.overall_mshr_hits::total 1487218 # number of overall MSHR hits
528system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56120 # number of ReadReq MSHR misses
529system.cpu.dcache.ReadReq_mshr_misses::total 56120 # number of ReadReq MSHR misses
530system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106957 # number of WriteReq MSHR misses
531system.cpu.dcache.WriteReq_mshr_misses::total 106957 # number of WriteReq MSHR misses
532system.cpu.dcache.demand_mshr_misses::cpu.data 163077 # number of demand (read+write) MSHR misses
533system.cpu.dcache.demand_mshr_misses::total 163077 # number of demand (read+write) MSHR misses
534system.cpu.dcache.overall_mshr_misses::cpu.data 163077 # number of overall MSHR misses
535system.cpu.dcache.overall_mshr_misses::total 163077 # number of overall MSHR misses
536system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1049489500 # number of ReadReq MSHR miss cycles
537system.cpu.dcache.ReadReq_mshr_miss_latency::total 1049489500 # number of ReadReq MSHR miss cycles
538system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3666942000 # number of WriteReq MSHR miss cycles
539system.cpu.dcache.WriteReq_mshr_miss_latency::total 3666942000 # number of WriteReq MSHR miss cycles
540system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4716431500 # number of demand (read+write) MSHR miss cycles
541system.cpu.dcache.demand_mshr_miss_latency::total 4716431500 # number of demand (read+write) MSHR miss cycles
542system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4716431500 # number of overall MSHR miss cycles
543system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles
544system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses
|
| 545system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses
|
510system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses
| 546system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses
|
| 547system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005388 # mshr miss rate for WriteReq accesses
|
511system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses
| 548system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses
|
| 549system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses
|
512system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses
| 550system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses
|
| 551system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses
|
513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency
| 552system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency
|
| 553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18700.810763 # average ReadReq mshr miss latency
|
514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency
| 554system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency
|
| 555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34284.263770 # average WriteReq mshr miss latency
|
515system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
| 556system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
|
| 557system.cpu.dcache.demand_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency
|
516system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
| 558system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
|
| 559system.cpu.dcache.overall_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency
|
517system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
518system.cpu.l2cache.replacements 115487 # number of replacements
519system.cpu.l2cache.tagsinuse 18346.494934 # Cycle average of tags in use
520system.cpu.l2cache.total_refs 78611 # Total number of references to valid blocks.
521system.cpu.l2cache.sampled_refs 134352 # Sample count of references to valid blocks.
522system.cpu.l2cache.avg_refs 0.585112 # Average number of references to valid blocks.
523system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
524system.cpu.l2cache.occ_blocks::writebacks 15851.533035 # Average occupied blocks per requestor
525system.cpu.l2cache.occ_blocks::cpu.inst 880.199051 # Average occupied blocks per requestor
526system.cpu.l2cache.occ_blocks::cpu.data 1614.762848 # Average occupied blocks per requestor
527system.cpu.l2cache.occ_percent::writebacks 0.483750 # Average percentage of cache occupancy
528system.cpu.l2cache.occ_percent::cpu.inst 0.026862 # Average percentage of cache occupancy
529system.cpu.l2cache.occ_percent::cpu.data 0.049279 # Average percentage of cache occupancy
530system.cpu.l2cache.occ_percent::total 0.559891 # Average percentage of cache occupancy
531system.cpu.l2cache.ReadReq_hits::cpu.inst 27786 # number of ReadReq hits
532system.cpu.l2cache.ReadReq_hits::cpu.data 28611 # number of ReadReq hits
533system.cpu.l2cache.ReadReq_hits::total 56397 # number of ReadReq hits
534system.cpu.l2cache.Writeback_hits::writebacks 123795 # number of Writeback hits
535system.cpu.l2cache.Writeback_hits::total 123795 # number of Writeback hits
536system.cpu.l2cache.UpgradeReq_hits::cpu.data 11 # number of UpgradeReq hits
537system.cpu.l2cache.UpgradeReq_hits::total 11 # number of UpgradeReq hits
538system.cpu.l2cache.ReadExReq_hits::cpu.data 4332 # number of ReadExReq hits
539system.cpu.l2cache.ReadExReq_hits::total 4332 # number of ReadExReq hits
540system.cpu.l2cache.demand_hits::cpu.inst 27786 # number of demand (read+write) hits
541system.cpu.l2cache.demand_hits::cpu.data 32943 # number of demand (read+write) hits
542system.cpu.l2cache.demand_hits::total 60729 # number of demand (read+write) hits
543system.cpu.l2cache.overall_hits::cpu.inst 27786 # number of overall hits
544system.cpu.l2cache.overall_hits::cpu.data 32943 # number of overall hits
545system.cpu.l2cache.overall_hits::total 60729 # number of overall hits
546system.cpu.l2cache.ReadReq_misses::cpu.inst 5769 # number of ReadReq misses
547system.cpu.l2cache.ReadReq_misses::cpu.data 27473 # number of ReadReq misses
548system.cpu.l2cache.ReadReq_misses::total 33242 # number of ReadReq misses
549system.cpu.l2cache.UpgradeReq_misses::cpu.data 63 # number of UpgradeReq misses
550system.cpu.l2cache.UpgradeReq_misses::total 63 # number of UpgradeReq misses
551system.cpu.l2cache.ReadExReq_misses::cpu.data 102587 # number of ReadExReq misses
552system.cpu.l2cache.ReadExReq_misses::total 102587 # number of ReadExReq misses
553system.cpu.l2cache.demand_misses::cpu.inst 5769 # number of demand (read+write) misses
554system.cpu.l2cache.demand_misses::cpu.data 130060 # number of demand (read+write) misses
555system.cpu.l2cache.demand_misses::total 135829 # number of demand (read+write) misses
556system.cpu.l2cache.overall_misses::cpu.inst 5769 # number of overall misses
557system.cpu.l2cache.overall_misses::cpu.data 130060 # number of overall misses
558system.cpu.l2cache.overall_misses::total 135829 # number of overall misses
559system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 197487500 # number of ReadReq miss cycles
560system.cpu.l2cache.ReadReq_miss_latency::cpu.data 940646500 # number of ReadReq miss cycles
561system.cpu.l2cache.ReadReq_miss_latency::total 1138134000 # number of ReadReq miss cycles
562system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 34500 # number of UpgradeReq miss cycles
563system.cpu.l2cache.UpgradeReq_miss_latency::total 34500 # number of UpgradeReq miss cycles
564system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3520234000 # number of ReadExReq miss cycles
565system.cpu.l2cache.ReadExReq_miss_latency::total 3520234000 # number of ReadExReq miss cycles
566system.cpu.l2cache.demand_miss_latency::cpu.inst 197487500 # number of demand (read+write) miss cycles
567system.cpu.l2cache.demand_miss_latency::cpu.data 4460880500 # number of demand (read+write) miss cycles
568system.cpu.l2cache.demand_miss_latency::total 4658368000 # number of demand (read+write) miss cycles
569system.cpu.l2cache.overall_miss_latency::cpu.inst 197487500 # number of overall miss cycles
570system.cpu.l2cache.overall_miss_latency::cpu.data 4460880500 # number of overall miss cycles
571system.cpu.l2cache.overall_miss_latency::total 4658368000 # number of overall miss cycles
572system.cpu.l2cache.ReadReq_accesses::cpu.inst 33555 # number of ReadReq accesses(hits+misses)
573system.cpu.l2cache.ReadReq_accesses::cpu.data 56084 # number of ReadReq accesses(hits+misses)
574system.cpu.l2cache.ReadReq_accesses::total 89639 # number of ReadReq accesses(hits+misses)
575system.cpu.l2cache.Writeback_accesses::writebacks 123795 # number of Writeback accesses(hits+misses)
576system.cpu.l2cache.Writeback_accesses::total 123795 # number of Writeback accesses(hits+misses)
577system.cpu.l2cache.UpgradeReq_accesses::cpu.data 74 # number of UpgradeReq accesses(hits+misses)
578system.cpu.l2cache.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses)
579system.cpu.l2cache.ReadExReq_accesses::cpu.data 106919 # number of ReadExReq accesses(hits+misses)
580system.cpu.l2cache.ReadExReq_accesses::total 106919 # number of ReadExReq accesses(hits+misses)
581system.cpu.l2cache.demand_accesses::cpu.inst 33555 # number of demand (read+write) accesses
582system.cpu.l2cache.demand_accesses::cpu.data 163003 # number of demand (read+write) accesses
583system.cpu.l2cache.demand_accesses::total 196558 # number of demand (read+write) accesses
584system.cpu.l2cache.overall_accesses::cpu.inst 33555 # number of overall (read+write) accesses
585system.cpu.l2cache.overall_accesses::cpu.data 163003 # number of overall (read+write) accesses
586system.cpu.l2cache.overall_accesses::total 196558 # number of overall (read+write) accesses
587system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171927 # miss rate for ReadReq accesses
588system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.489855 # miss rate for ReadReq accesses
| 560system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
561system.cpu.l2cache.replacements 115487 # number of replacements
562system.cpu.l2cache.tagsinuse 18346.494934 # Cycle average of tags in use
563system.cpu.l2cache.total_refs 78611 # Total number of references to valid blocks.
564system.cpu.l2cache.sampled_refs 134352 # Sample count of references to valid blocks.
565system.cpu.l2cache.avg_refs 0.585112 # Average number of references to valid blocks.
566system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
567system.cpu.l2cache.occ_blocks::writebacks 15851.533035 # Average occupied blocks per requestor
568system.cpu.l2cache.occ_blocks::cpu.inst 880.199051 # Average occupied blocks per requestor
569system.cpu.l2cache.occ_blocks::cpu.data 1614.762848 # Average occupied blocks per requestor
570system.cpu.l2cache.occ_percent::writebacks 0.483750 # Average percentage of cache occupancy
571system.cpu.l2cache.occ_percent::cpu.inst 0.026862 # Average percentage of cache occupancy
572system.cpu.l2cache.occ_percent::cpu.data 0.049279 # Average percentage of cache occupancy
573system.cpu.l2cache.occ_percent::total 0.559891 # Average percentage of cache occupancy
574system.cpu.l2cache.ReadReq_hits::cpu.inst 27786 # number of ReadReq hits
575system.cpu.l2cache.ReadReq_hits::cpu.data 28611 # number of ReadReq hits
576system.cpu.l2cache.ReadReq_hits::total 56397 # number of ReadReq hits
577system.cpu.l2cache.Writeback_hits::writebacks 123795 # number of Writeback hits
578system.cpu.l2cache.Writeback_hits::total 123795 # number of Writeback hits
579system.cpu.l2cache.UpgradeReq_hits::cpu.data 11 # number of UpgradeReq hits
580system.cpu.l2cache.UpgradeReq_hits::total 11 # number of UpgradeReq hits
581system.cpu.l2cache.ReadExReq_hits::cpu.data 4332 # number of ReadExReq hits
582system.cpu.l2cache.ReadExReq_hits::total 4332 # number of ReadExReq hits
583system.cpu.l2cache.demand_hits::cpu.inst 27786 # number of demand (read+write) hits
584system.cpu.l2cache.demand_hits::cpu.data 32943 # number of demand (read+write) hits
585system.cpu.l2cache.demand_hits::total 60729 # number of demand (read+write) hits
586system.cpu.l2cache.overall_hits::cpu.inst 27786 # number of overall hits
587system.cpu.l2cache.overall_hits::cpu.data 32943 # number of overall hits
588system.cpu.l2cache.overall_hits::total 60729 # number of overall hits
589system.cpu.l2cache.ReadReq_misses::cpu.inst 5769 # number of ReadReq misses
590system.cpu.l2cache.ReadReq_misses::cpu.data 27473 # number of ReadReq misses
591system.cpu.l2cache.ReadReq_misses::total 33242 # number of ReadReq misses
592system.cpu.l2cache.UpgradeReq_misses::cpu.data 63 # number of UpgradeReq misses
593system.cpu.l2cache.UpgradeReq_misses::total 63 # number of UpgradeReq misses
594system.cpu.l2cache.ReadExReq_misses::cpu.data 102587 # number of ReadExReq misses
595system.cpu.l2cache.ReadExReq_misses::total 102587 # number of ReadExReq misses
596system.cpu.l2cache.demand_misses::cpu.inst 5769 # number of demand (read+write) misses
597system.cpu.l2cache.demand_misses::cpu.data 130060 # number of demand (read+write) misses
598system.cpu.l2cache.demand_misses::total 135829 # number of demand (read+write) misses
599system.cpu.l2cache.overall_misses::cpu.inst 5769 # number of overall misses
600system.cpu.l2cache.overall_misses::cpu.data 130060 # number of overall misses
601system.cpu.l2cache.overall_misses::total 135829 # number of overall misses
602system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 197487500 # number of ReadReq miss cycles
603system.cpu.l2cache.ReadReq_miss_latency::cpu.data 940646500 # number of ReadReq miss cycles
604system.cpu.l2cache.ReadReq_miss_latency::total 1138134000 # number of ReadReq miss cycles
605system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 34500 # number of UpgradeReq miss cycles
606system.cpu.l2cache.UpgradeReq_miss_latency::total 34500 # number of UpgradeReq miss cycles
607system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3520234000 # number of ReadExReq miss cycles
608system.cpu.l2cache.ReadExReq_miss_latency::total 3520234000 # number of ReadExReq miss cycles
609system.cpu.l2cache.demand_miss_latency::cpu.inst 197487500 # number of demand (read+write) miss cycles
610system.cpu.l2cache.demand_miss_latency::cpu.data 4460880500 # number of demand (read+write) miss cycles
611system.cpu.l2cache.demand_miss_latency::total 4658368000 # number of demand (read+write) miss cycles
612system.cpu.l2cache.overall_miss_latency::cpu.inst 197487500 # number of overall miss cycles
613system.cpu.l2cache.overall_miss_latency::cpu.data 4460880500 # number of overall miss cycles
614system.cpu.l2cache.overall_miss_latency::total 4658368000 # number of overall miss cycles
615system.cpu.l2cache.ReadReq_accesses::cpu.inst 33555 # number of ReadReq accesses(hits+misses)
616system.cpu.l2cache.ReadReq_accesses::cpu.data 56084 # number of ReadReq accesses(hits+misses)
617system.cpu.l2cache.ReadReq_accesses::total 89639 # number of ReadReq accesses(hits+misses)
618system.cpu.l2cache.Writeback_accesses::writebacks 123795 # number of Writeback accesses(hits+misses)
619system.cpu.l2cache.Writeback_accesses::total 123795 # number of Writeback accesses(hits+misses)
620system.cpu.l2cache.UpgradeReq_accesses::cpu.data 74 # number of UpgradeReq accesses(hits+misses)
621system.cpu.l2cache.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses)
622system.cpu.l2cache.ReadExReq_accesses::cpu.data 106919 # number of ReadExReq accesses(hits+misses)
623system.cpu.l2cache.ReadExReq_accesses::total 106919 # number of ReadExReq accesses(hits+misses)
624system.cpu.l2cache.demand_accesses::cpu.inst 33555 # number of demand (read+write) accesses
625system.cpu.l2cache.demand_accesses::cpu.data 163003 # number of demand (read+write) accesses
626system.cpu.l2cache.demand_accesses::total 196558 # number of demand (read+write) accesses
627system.cpu.l2cache.overall_accesses::cpu.inst 33555 # number of overall (read+write) accesses
628system.cpu.l2cache.overall_accesses::cpu.data 163003 # number of overall (read+write) accesses
629system.cpu.l2cache.overall_accesses::total 196558 # number of overall (read+write) accesses
630system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171927 # miss rate for ReadReq accesses
631system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.489855 # miss rate for ReadReq accesses
|
| 632system.cpu.l2cache.ReadReq_miss_rate::total 0.370843 # miss rate for ReadReq accesses
|
589system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.851351 # miss rate for UpgradeReq accesses
| 633system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.851351 # miss rate for UpgradeReq accesses
|
| 634system.cpu.l2cache.UpgradeReq_miss_rate::total 0.851351 # miss rate for UpgradeReq accesses
|
590system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959483 # miss rate for ReadExReq accesses
| 635system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959483 # miss rate for ReadExReq accesses
|
| 636system.cpu.l2cache.ReadExReq_miss_rate::total 0.959483 # miss rate for ReadExReq accesses
|
591system.cpu.l2cache.demand_miss_rate::cpu.inst 0.171927 # miss rate for demand accesses
592system.cpu.l2cache.demand_miss_rate::cpu.data 0.797899 # miss rate for demand accesses
| 637system.cpu.l2cache.demand_miss_rate::cpu.inst 0.171927 # miss rate for demand accesses
638system.cpu.l2cache.demand_miss_rate::cpu.data 0.797899 # miss rate for demand accesses
|
| 639system.cpu.l2cache.demand_miss_rate::total 0.691038 # miss rate for demand accesses
|
593system.cpu.l2cache.overall_miss_rate::cpu.inst 0.171927 # miss rate for overall accesses
594system.cpu.l2cache.overall_miss_rate::cpu.data 0.797899 # miss rate for overall accesses
| 640system.cpu.l2cache.overall_miss_rate::cpu.inst 0.171927 # miss rate for overall accesses
641system.cpu.l2cache.overall_miss_rate::cpu.data 0.797899 # miss rate for overall accesses
|
| 642system.cpu.l2cache.overall_miss_rate::total 0.691038 # miss rate for overall accesses
|
595system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34232.535968 # average ReadReq miss latency
596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34238.943690 # average ReadReq miss latency
| 643system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34232.535968 # average ReadReq miss latency
644system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34238.943690 # average ReadReq miss latency
|
| 645system.cpu.l2cache.ReadReq_avg_miss_latency::total 34237.831659 # average ReadReq miss latency
|
597system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 547.619048 # average UpgradeReq miss latency
| 646system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 547.619048 # average UpgradeReq miss latency
|
| 647system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 547.619048 # average UpgradeReq miss latency
|
598system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.620761 # average ReadExReq miss latency
| 648system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.620761 # average ReadExReq miss latency
|
| 649system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34314.620761 # average ReadExReq miss latency
|
599system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
600system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
| 650system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
651system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
|
| 652system.cpu.l2cache.demand_avg_miss_latency::total 34295.827842 # average overall miss latency
|
601system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
602system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
| 653system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
654system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
|
| 655system.cpu.l2cache.overall_avg_miss_latency::total 34295.827842 # average overall miss latency
|
603system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
604system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
605system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
606system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
607system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
608system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
609system.cpu.l2cache.fast_writes 0 # number of fast writes performed
610system.cpu.l2cache.cache_copies 0 # number of cache copies performed
611system.cpu.l2cache.writebacks::writebacks 88463 # number of writebacks
612system.cpu.l2cache.writebacks::total 88463 # number of writebacks
613system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 26 # number of ReadReq MSHR hits
614system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
615system.cpu.l2cache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
616system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits
617system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits
618system.cpu.l2cache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
619system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
620system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits
621system.cpu.l2cache.overall_mshr_hits::total 91 # number of overall MSHR hits
622system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5743 # number of ReadReq MSHR misses
623system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27408 # number of ReadReq MSHR misses
624system.cpu.l2cache.ReadReq_mshr_misses::total 33151 # number of ReadReq MSHR misses
625system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 63 # number of UpgradeReq MSHR misses
626system.cpu.l2cache.UpgradeReq_mshr_misses::total 63 # number of UpgradeReq MSHR misses
627system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102587 # number of ReadExReq MSHR misses
628system.cpu.l2cache.ReadExReq_mshr_misses::total 102587 # number of ReadExReq MSHR misses
629system.cpu.l2cache.demand_mshr_misses::cpu.inst 5743 # number of demand (read+write) MSHR misses
630system.cpu.l2cache.demand_mshr_misses::cpu.data 129995 # number of demand (read+write) MSHR misses
631system.cpu.l2cache.demand_mshr_misses::total 135738 # number of demand (read+write) MSHR misses
632system.cpu.l2cache.overall_mshr_misses::cpu.inst 5743 # number of overall MSHR misses
633system.cpu.l2cache.overall_mshr_misses::cpu.data 129995 # number of overall MSHR misses
634system.cpu.l2cache.overall_mshr_misses::total 135738 # number of overall MSHR misses
635system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 178439000 # number of ReadReq MSHR miss cycles
636system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 852007500 # number of ReadReq MSHR miss cycles
637system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1030446500 # number of ReadReq MSHR miss cycles
638system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1955000 # number of UpgradeReq MSHR miss cycles
639system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1955000 # number of UpgradeReq MSHR miss cycles
640system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3195019500 # number of ReadExReq MSHR miss cycles
641system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3195019500 # number of ReadExReq MSHR miss cycles
642system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178439000 # number of demand (read+write) MSHR miss cycles
643system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4047027000 # number of demand (read+write) MSHR miss cycles
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645system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178439000 # number of overall MSHR miss cycles
646system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4047027000 # number of overall MSHR miss cycles
647system.cpu.l2cache.overall_mshr_miss_latency::total 4225466000 # number of overall MSHR miss cycles
648system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for ReadReq accesses
649system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488696 # mshr miss rate for ReadReq accesses
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657system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
658system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
659system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
660system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
661system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
662system.cpu.l2cache.fast_writes 0 # number of fast writes performed
663system.cpu.l2cache.cache_copies 0 # number of cache copies performed
664system.cpu.l2cache.writebacks::writebacks 88463 # number of writebacks
665system.cpu.l2cache.writebacks::total 88463 # number of writebacks
666system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 26 # number of ReadReq MSHR hits
667system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
668system.cpu.l2cache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
669system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits
670system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits
671system.cpu.l2cache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
672system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
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676system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27408 # number of ReadReq MSHR misses
677system.cpu.l2cache.ReadReq_mshr_misses::total 33151 # number of ReadReq MSHR misses
678system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 63 # number of UpgradeReq MSHR misses
679system.cpu.l2cache.UpgradeReq_mshr_misses::total 63 # number of UpgradeReq MSHR misses
680system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102587 # number of ReadExReq MSHR misses
681system.cpu.l2cache.ReadExReq_mshr_misses::total 102587 # number of ReadExReq MSHR misses
682system.cpu.l2cache.demand_mshr_misses::cpu.inst 5743 # number of demand (read+write) MSHR misses
683system.cpu.l2cache.demand_mshr_misses::cpu.data 129995 # number of demand (read+write) MSHR misses
684system.cpu.l2cache.demand_mshr_misses::total 135738 # number of demand (read+write) MSHR misses
685system.cpu.l2cache.overall_mshr_misses::cpu.inst 5743 # number of overall MSHR misses
686system.cpu.l2cache.overall_mshr_misses::cpu.data 129995 # number of overall MSHR misses
687system.cpu.l2cache.overall_mshr_misses::total 135738 # number of overall MSHR misses
688system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 178439000 # number of ReadReq MSHR miss cycles
689system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 852007500 # number of ReadReq MSHR miss cycles
690system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1030446500 # number of ReadReq MSHR miss cycles
691system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1955000 # number of UpgradeReq MSHR miss cycles
692system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1955000 # number of UpgradeReq MSHR miss cycles
693system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3195019500 # number of ReadExReq MSHR miss cycles
694system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3195019500 # number of ReadExReq MSHR miss cycles
695system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178439000 # number of demand (read+write) MSHR miss cycles
696system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4047027000 # number of demand (read+write) MSHR miss cycles
697system.cpu.l2cache.demand_mshr_miss_latency::total 4225466000 # number of demand (read+write) MSHR miss cycles
698system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178439000 # number of overall MSHR miss cycles
699system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4047027000 # number of overall MSHR miss cycles
700system.cpu.l2cache.overall_mshr_miss_latency::total 4225466000 # number of overall MSHR miss cycles
701system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for ReadReq accesses
702system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488696 # mshr miss rate for ReadReq accesses
|
| 703system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.369828 # mshr miss rate for ReadReq accesses
|
650system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.851351 # mshr miss rate for UpgradeReq accesses
| 704system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.851351 # mshr miss rate for UpgradeReq accesses
|
| 705system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.851351 # mshr miss rate for UpgradeReq accesses
|
651system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959483 # mshr miss rate for ReadExReq accesses
| 706system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959483 # mshr miss rate for ReadExReq accesses
|
| 707system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.959483 # mshr miss rate for ReadExReq accesses
|
652system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for demand accesses
653system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for demand accesses
| 708system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for demand accesses
709system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for demand accesses
|
| 710system.cpu.l2cache.demand_mshr_miss_rate::total 0.690575 # mshr miss rate for demand accesses
|
654system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for overall accesses
655system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for overall accesses
| 711system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for overall accesses
712system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for overall accesses
|
| 713system.cpu.l2cache.overall_mshr_miss_rate::total 0.690575 # mshr miss rate for overall accesses
|
656system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759 # average ReadReq mshr miss latency
657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004 # average ReadReq mshr miss latency
| 714system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759 # average ReadReq mshr miss latency
715system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004 # average ReadReq mshr miss latency
|
| 716system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.421315 # average ReadReq mshr miss latency
|
658system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032 # average UpgradeReq mshr miss latency
| 717system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032 # average UpgradeReq mshr miss latency
|
| 718system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.746032 # average UpgradeReq mshr miss latency
|
659system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency
| 719system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency
|
| 720system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31144.487118 # average ReadExReq mshr miss latency
|
660system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
| 721system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
722system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
|
| 723system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency
|
662system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
663system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
| 724system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
725system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
|
| 726system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency
|
664system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
665
666---------- End Simulation Statistics ----------
| 727system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
728
729---------- End Simulation Statistics ----------
|