Cross Reference: /gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

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stats.txt (10220:9eab5efc02e8)	stats.txt (10229:aae7735450a9)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026655 # Number of seconds simulated 4sim_ticks 26655046000 # Number of ticks simulated 5final_tick 26655046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 108502 # Simulator instruction rate (inst/s) 8host_op_rate 153979 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40787374 # Simulator tick rate (ticks/s) 10host_mem_usage 322284 # Number of bytes of host memory used 11host_seconds 653.51 # Real time elapsed on the host 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 100626876 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 298176 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8241600 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 298176 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 298176 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5372544 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5372544 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4659 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128775 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 83946 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 83946 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 11186475 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 298008265 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 309194739 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 11186475 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 11186475 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 201558234 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 201558234 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 201558234 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 11186475 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 298008265 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 510752973 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 128776 # Number of read requests accepted 40system.physmem.writeReqs 83946 # Number of write requests accepted 41system.physmem.readBursts 128776 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 83946 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 8241344 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue 45system.physmem.bytesWritten 5371328 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 8241664 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 5372544 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 320 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8145 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8395 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8248 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8167 # Per bank write bursts 55system.physmem.perBankRdBursts::4 8288 # Per bank write bursts 56system.physmem.perBankRdBursts::5 8447 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8087 # Per bank write bursts 58system.physmem.perBankRdBursts::7 7963 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8065 # Per bank write bursts 60system.physmem.perBankRdBursts::9 7608 # Per bank write bursts 61system.physmem.perBankRdBursts::10 7787 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7815 # Per bank write bursts 63system.physmem.perBankRdBursts::12 7882 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7885 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7978 # Per bank write bursts 66system.physmem.perBankRdBursts::15 8011 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5180 # Per bank write bursts 68system.physmem.perBankWrBursts::1 5377 # Per bank write bursts 69system.physmem.perBankWrBursts::2 5291 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5157 # Per bank write bursts 71system.physmem.perBankWrBursts::4 5265 # Per bank write bursts 72system.physmem.perBankWrBursts::5 5517 # Per bank write bursts 73system.physmem.perBankWrBursts::6 5199 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5049 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5030 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5091 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5246 # Per bank write bursts 78system.physmem.perBankWrBursts::11 5144 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5342 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5451 # Per bank write bursts 82system.physmem.perBankWrBursts::15 5225 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 26655030500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 128776 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 83946 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 74138 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 53140 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 1433 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 52 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 643 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 655 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 2224 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4090 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4895 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5167 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5187 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5223 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5237 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5353 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5362 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5604 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5798 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 6233 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 6000 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5239 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 37804 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 360.014390 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 216.175335 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 343.156707 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 12089 31.98% 31.98% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 7874 20.83% 52.81% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 3781 10.00% 62.81% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2728 7.22% 70.02% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2397 6.34% 76.36% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1617 4.28% 80.64% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1220 3.23% 83.87% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1066 2.82% 86.69% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 5032 13.31% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 37804 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5144 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 25.030132 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 392.032521 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5142 99.96% 99.96% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5144 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5144 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 16.315513 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 16.292869 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.917660 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 4492 87.33% 87.33% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 6 0.12% 87.44% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 431 8.38% 95.82% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 161 3.13% 98.95% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20 33 0.64% 99.59% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::21 11 0.21% 99.81% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::22 6 0.12% 99.92% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::23 1 0.02% 99.94% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::28 1 0.02% 99.96% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::30 1 0.02% 99.98% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::total 5144 # Writes before turning the bus around for reads 233system.physmem.totQLat 2471536000 # Total ticks spent queuing 234system.physmem.totMemAccLat 4885992250 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 643855000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 19193.27 # Average queueing delay per DRAM burst 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 238system.physmem.avgMemAccLat 37943.27 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 309.19 # Average DRAM read bandwidth in MiByte/s 240system.physmem.avgWrBW 201.51 # Average achieved write bandwidth in MiByte/s 241system.physmem.avgRdBWSys 309.20 # Average system read bandwidth in MiByte/s 242system.physmem.avgWrBWSys 201.56 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 244system.physmem.busUtil 3.99 # Data bus utilization in percentage 245system.physmem.busUtilRead 2.42 # Data bus utilization in percentage for reads 246system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes 247system.physmem.avgRdQLen 1.35 # Average read queue length when enqueuing 248system.physmem.avgWrQLen 23.52 # Average write queue length when enqueuing 249system.physmem.readRowHits 112800 # Number of row buffer hits during reads 250system.physmem.writeRowHits 62083 # Number of row buffer hits during writes 251system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads 252system.physmem.writeRowHitRate 73.96 # Row buffer hit rate for writes 253system.physmem.avgGap 125304.53 # Average gap between requests 254system.physmem.pageHitRate 82.21 # Row buffer hit rate, read and write combined 255system.physmem.memoryStateTime::IDLE 11333884750 # Time in different power states 256system.physmem.memoryStateTime::REF 889980000 # Time in different power states 257system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 258system.physmem.memoryStateTime::ACT 14428773750 # Time in different power states 259system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 260system.membus.throughput 510752973 # Throughput (bytes/s) 261system.membus.trans_dist::ReadReq 26520 # Transaction distribution 262system.membus.trans_dist::ReadResp 26519 # Transaction distribution 263system.membus.trans_dist::Writeback 83946 # Transaction distribution 264system.membus.trans_dist::UpgradeReq 320 # Transaction distribution 265system.membus.trans_dist::UpgradeResp 320 # Transaction distribution 266system.membus.trans_dist::ReadExReq 102256 # Transaction distribution 267system.membus.trans_dist::ReadExResp 102256 # Transaction distribution 268system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342137 # Packet count per connected master and slave (bytes) 269system.membus.pkt_count::total 342137 # Packet count per connected master and slave (bytes) 270system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614144 # Cumulative packet size per connected master and slave (bytes) 271system.membus.tot_pkt_size::total 13614144 # Cumulative packet size per connected master and slave (bytes) 272system.membus.data_through_bus 13614144 # Total data (bytes) 273system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 274system.membus.reqLayer0.occupancy 932451500 # Layer occupancy (ticks) 275system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) 276system.membus.respLayer1.occupancy 1211794930 # Layer occupancy (ticks) 277system.membus.respLayer1.utilization 4.5 # Layer utilization (%) 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.branchPred.lookups 16636502 # Number of BP lookups 280system.cpu.branchPred.condPredicted 12767541 # Number of conditional branches predicted 281system.cpu.branchPred.condIncorrect 605249 # Number of conditional branches incorrect 282system.cpu.branchPred.BTBLookups 10577266 # Number of BTB lookups 283system.cpu.branchPred.BTBHits 7776939 # Number of BTB hits 284system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 285system.cpu.branchPred.BTBHitPct 73.525039 # BTB Hit Percentage 286system.cpu.branchPred.usedRAS 1824082 # Number of times the RAS was used to get a target. 287system.cpu.branchPred.RASInCorrect 113194 # Number of incorrect RAS predictions. 288system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 289system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 290system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 291system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 292system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 293system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 294system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 295system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 296system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 297system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 298system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 299system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 300system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 301system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 304system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 305system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 306system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 307system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 308system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 309system.cpu.dtb.inst_hits 0 # ITB inst hits 310system.cpu.dtb.inst_misses 0 # ITB inst misses 311system.cpu.dtb.read_hits 0 # DTB read hits 312system.cpu.dtb.read_misses 0 # DTB read misses 313system.cpu.dtb.write_hits 0 # DTB write hits 314system.cpu.dtb.write_misses 0 # DTB write misses 315system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 316system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 317system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 318system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 319system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 320system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 321system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 322system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 323system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 324system.cpu.dtb.read_accesses 0 # DTB read accesses 325system.cpu.dtb.write_accesses 0 # DTB write accesses 326system.cpu.dtb.inst_accesses 0 # ITB inst accesses 327system.cpu.dtb.hits 0 # DTB hits 328system.cpu.dtb.misses 0 # DTB misses 329system.cpu.dtb.accesses 0 # DTB accesses 330system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 331system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 332system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 333system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 334system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 335system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 336system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 337system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 338system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 340system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 341system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 342system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 343system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 344system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 345system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 346system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 347system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 348system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 349system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 350system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 351system.cpu.itb.inst_hits 0 # ITB inst hits 352system.cpu.itb.inst_misses 0 # ITB inst misses 353system.cpu.itb.read_hits 0 # DTB read hits 354system.cpu.itb.read_misses 0 # DTB read misses 355system.cpu.itb.write_hits 0 # DTB write hits 356system.cpu.itb.write_misses 0 # DTB write misses 357system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 358system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 359system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 360system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 361system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 362system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 363system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 364system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 365system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 366system.cpu.itb.read_accesses 0 # DTB read accesses 367system.cpu.itb.write_accesses 0 # DTB write accesses 368system.cpu.itb.inst_accesses 0 # ITB inst accesses 369system.cpu.itb.hits 0 # DTB hits 370system.cpu.itb.misses 0 # DTB misses 371system.cpu.itb.accesses 0 # DTB accesses 372system.cpu.workload.num_syscalls 1946 # Number of system calls 373system.cpu.numCycles 53310093 # number of cpu cycles simulated 374system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 375system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 376system.cpu.fetch.icacheStallCycles 12544266 # Number of cycles fetch is stalled on an Icache miss 377system.cpu.fetch.Insts 85245132 # Number of instructions fetch has processed 378system.cpu.fetch.Branches 16636502 # Number of branches that fetch encountered 379system.cpu.fetch.predictedBranches 9601021 # Number of branches that fetch has predicted taken 380system.cpu.fetch.Cycles 21203621 # Number of cycles fetch has run and was not squashing or blocked 381system.cpu.fetch.SquashCycles 2373453 # Number of cycles fetch has spent squashing 382system.cpu.fetch.BlockedCycles 10826846 # Number of cycles fetch has spent blocked 383system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 384system.cpu.fetch.PendingTrapStallCycles 346 # Number of stall cycles due to pending traps 385system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR 386system.cpu.fetch.CacheLines 11685368 # Number of cache lines fetched 387system.cpu.fetch.IcacheSquashes 181941 # Number of outstanding Icache misses that were squashed 388system.cpu.fetch.rateDist::samples 46316681 # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::mean 2.577051 # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::stdev 3.331362 # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::0 25133357 54.26% 54.26% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::1 2139356 4.62% 58.88% # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::2 1964088 4.24% 63.12% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::3 2042720 4.41% 67.53% # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::4 1470632 3.18% 70.71% # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::5 1380684 2.98% 73.69% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::6 958438 2.07% 75.76% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::7 1191046 2.57% 78.33% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::8 10036360 21.67% 100.00% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::total 46316681 # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.branchRate 0.312070 # Number of branch fetches per cycle 406system.cpu.fetch.rate 1.599043 # Number of inst fetches per cycle 407system.cpu.decode.IdleCycles 14641724 # Number of cycles decode is idle 408system.cpu.decode.BlockedCycles 9163742 # Number of cycles decode is blocked 409system.cpu.decode.RunCycles 19491129 # Number of cycles decode is running 410system.cpu.decode.UnblockCycles 1382035 # Number of cycles decode is unblocking 411system.cpu.decode.SquashCycles 1638051 # Number of cycles decode is squashing 412system.cpu.decode.BranchResolved 3333190 # Number of times decode resolved a branch 413system.cpu.decode.BranchMispred 105248 # Number of times decode detected a branch misprediction 414system.cpu.decode.DecodedInsts 116897409 # Number of instructions handled by decode 415system.cpu.decode.SquashedInsts 363517 # Number of squashed instructions handled by decode 416system.cpu.rename.SquashCycles 1638051 # Number of cycles rename is squashing 417system.cpu.rename.IdleCycles 16359930 # Number of cycles rename is idle 418system.cpu.rename.BlockCycles 2678860 # Number of cycles rename is blocking 419system.cpu.rename.serializeStallCycles 1013546 # count of cycles rename stalled for serializing inst 420system.cpu.rename.RunCycles 19105164 # Number of cycles rename is running 421system.cpu.rename.UnblockCycles 5521130 # Number of cycles rename is unblocking 422system.cpu.rename.RenamedInsts 115000815 # Number of instructions processed by rename 423system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full 424system.cpu.rename.IQFullEvents 16720 # Number of times rename has blocked due to IQ full 425system.cpu.rename.LSQFullEvents 4660350 # Number of times rename has blocked due to LSQ full 426system.cpu.rename.FullRegisterEvents 282 # Number of times there has been no free registers 427system.cpu.rename.RenamedOperands 115331621 # Number of destination operands rename has renamed 428system.cpu.rename.RenameLookups 529914525 # Number of register rename lookups that rename has made 429system.cpu.rename.int_rename_lookups 476510410 # Number of integer rename lookups 430system.cpu.rename.fp_rename_lookups 2776 # Number of floating rename lookups 431system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed 432system.cpu.rename.UndoneMaps 16198949 # Number of HB maps that are undone due to squashing 433system.cpu.rename.serializingInsts 20436 # count of serializing insts renamed 434system.cpu.rename.tempSerializingInsts 20434 # count of temporary serializing insts renamed 435system.cpu.rename.skidInsts 13095384 # count of insts added to the skid buffer 436system.cpu.memDep0.insertedLoads 29625138 # Number of loads inserted to the mem dependence unit. 437system.cpu.memDep0.insertedStores 22434042 # Number of stores inserted to the mem dependence unit. 438system.cpu.memDep0.conflictingLoads 3869725 # Number of conflicting loads. 439system.cpu.memDep0.conflictingStores 4362550 # Number of conflicting stores. 440system.cpu.iq.iqInstsAdded 111565619 # Number of instructions added to the IQ (excludes non-spec) 441system.cpu.iq.iqNonSpecInstsAdded 36058 # Number of non-speculative instructions added to the IQ 442system.cpu.iq.iqInstsIssued 107262004 # Number of instructions issued 443system.cpu.iq.iqSquashedInstsIssued 275498 # Number of squashed instructions issued 444system.cpu.iq.iqSquashedInstsExamined 10829281 # Number of squashed instructions iterated over during squash; mainly for profiling 445system.cpu.iq.iqSquashedOperandsExamined 25946611 # Number of squashed operands that are examined and possibly removed from graph 446system.cpu.iq.iqSquashedNonSpecRemoved 2272 # Number of squashed non-spec instructions that were removed 447system.cpu.iq.issued_per_cycle::samples 46316681 # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::mean 2.315840 # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::stdev 1.990470 # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::0 11030019 23.81% 23.81% # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::1 8138803 17.57% 41.39% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::2 7430883 16.04% 57.43% # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::3 7110857 15.35% 72.78% # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::4 5417654 11.70% 84.48% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::5 3891349 8.40% 92.88% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::6 1848302 3.99% 96.87% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::7 878821 1.90% 98.77% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::8 569993 1.23% 100.00% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::total 46316681 # Number of insts issued each cycle 464system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 465system.cpu.iq.fu_full::IntAlu 113827 4.59% 4.59% # attempts to use FU when none available 466system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available 467system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available 468system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.59% # attempts to use FU when none available 469system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available 470system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available 471system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available 472system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available 494system.cpu.iq.fu_full::MemRead 1360293 54.84% 59.43% # attempts to use FU when none available 495system.cpu.iq.fu_full::MemWrite 1006288 40.57% 100.00% # attempts to use FU when none available 496system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 497system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 498system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 499system.cpu.iq.FU_type_0::IntAlu 56646184 52.81% 52.81% # Type of FU issued 500system.cpu.iq.FU_type_0::IntMult 91539 0.09% 52.90% # Type of FU issued 501system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued 502system.cpu.iq.FU_type_0::FloatAdd 222 0.00% 52.90% # Type of FU issued 503system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued 504system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued 505system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued 506system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued 507system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued 528system.cpu.iq.FU_type_0::MemRead 28903042 26.95% 79.84% # Type of FU issued 529system.cpu.iq.FU_type_0::MemWrite 21621010 20.16% 100.00% # Type of FU issued 530system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 531system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 532system.cpu.iq.FU_type_0::total 107262004 # Type of FU issued 533system.cpu.iq.rate 2.012039 # Inst issue rate 534system.cpu.iq.fu_busy_cnt 2480410 # FU busy when requested 535system.cpu.iq.fu_busy_rate 0.023125 # FU busy rate (busy events/executed inst) 536system.cpu.iq.int_inst_queue_reads 263595997 # Number of integer instruction queue reads 537system.cpu.iq.int_inst_queue_writes 122458930 # Number of integer instruction queue writes 538system.cpu.iq.int_inst_queue_wakeup_accesses 105571537 # Number of integer instruction queue wakeup accesses 539system.cpu.iq.fp_inst_queue_reads 600 # Number of floating instruction queue reads 540system.cpu.iq.fp_inst_queue_writes 932 # Number of floating instruction queue writes 541system.cpu.iq.fp_inst_queue_wakeup_accesses 176 # Number of floating instruction queue wakeup accesses 542system.cpu.iq.int_alu_accesses 109742111 # Number of integer alu accesses 543system.cpu.iq.fp_alu_accesses 303 # Number of floating point alu accesses 544system.cpu.iew.lsq.thread0.forwLoads 2179776 # Number of loads that had data forwarded from stores 545system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 546system.cpu.iew.lsq.thread0.squashedLoads 2318030 # Number of loads squashed 547system.cpu.iew.lsq.thread0.ignoredResponses 6495 # Number of memory responses ignored because the instruction is squashed 548system.cpu.iew.lsq.thread0.memOrderViolation 30041 # Number of memory ordering violations 549system.cpu.iew.lsq.thread0.squashedStores 1878304 # Number of stores squashed 550system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 551system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 552system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled 553system.cpu.iew.lsq.thread0.cacheBlocked 708 # Number of times an access to memory failed due to the cache being blocked 554system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 555system.cpu.iew.iewSquashCycles 1638051 # Number of cycles IEW is squashing 556system.cpu.iew.iewBlockCycles 1126663 # Number of cycles IEW is blocking 557system.cpu.iew.iewUnblockCycles 45667 # Number of cycles IEW is unblocking 558system.cpu.iew.iewDispatchedInsts 111611483 # Number of instructions dispatched to IQ 559system.cpu.iew.iewDispSquashedInsts 295320 # Number of squashed instructions skipped by dispatch 560system.cpu.iew.iewDispLoadInsts 29625138 # Number of dispatched load instructions 561system.cpu.iew.iewDispStoreInsts 22434042 # Number of dispatched store instructions 562system.cpu.iew.iewDispNonSpecInsts 20138 # Number of dispatched non-speculative instructions 563system.cpu.iew.iewIQFullEvents 6203 # Number of times the IQ has become full, causing a stall 564system.cpu.iew.iewLSQFullEvents 5120 # Number of times the LSQ has become full, causing a stall 565system.cpu.iew.memOrderViolationEvents 30041 # Number of memory order violations 566system.cpu.iew.predictedTakenIncorrect 394287 # Number of branches that were predicted taken incorrectly 567system.cpu.iew.predictedNotTakenIncorrect 181285 # Number of branches that were predicted not taken incorrectly 568system.cpu.iew.branchMispredicts 575572 # Number of branch mispredicts detected at execute 569system.cpu.iew.iewExecutedInsts 106232062 # Number of executed instructions 570system.cpu.iew.iewExecLoadInsts 28604336 # Number of load instructions executed 571system.cpu.iew.iewExecSquashedInsts 1029942 # Number of squashed instructions skipped in execute 572system.cpu.iew.exec_swp 0 # number of swp insts executed 573system.cpu.iew.exec_nop 9806 # number of nop insts executed 574system.cpu.iew.exec_refs 49939736 # number of memory reference insts executed 575system.cpu.iew.exec_branches 14601830 # Number of branches executed 576system.cpu.iew.exec_stores 21335400 # Number of stores executed 577system.cpu.iew.exec_rate 1.992720 # Inst execution rate 578system.cpu.iew.wb_sent 105794271 # cumulative count of insts sent to commit 579system.cpu.iew.wb_count 105571713 # cumulative count of insts written-back 580system.cpu.iew.wb_producers 53289529 # num instructions producing a value 581system.cpu.iew.wb_consumers 103696689 # num instructions consuming a value 582system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 583system.cpu.iew.wb_rate 1.980333 # insts written-back per cycle 584system.cpu.iew.wb_fanout 0.513898 # average fanout of values written-back 585system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 586system.cpu.commit.commitSquashedInsts 10980049 # The number of squashed insts skipped by commit 587system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 588system.cpu.commit.branchMispredicts 501819 # The number of times a branch was mispredicted 589system.cpu.commit.committed_per_cycle::samples 44678630 # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::mean 2.252362 # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::stdev 2.761359 # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::0 15558775 34.82% 34.82% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::1 11701818 26.19% 61.01% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::2 3471869 7.77% 68.79% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::3 2879306 6.44% 75.23% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::4 1869514 4.18% 79.41% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::5 1922443 4.30% 83.72% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::6 688922 1.54% 85.26% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::7 562713 1.26% 86.52% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::8 6023270 13.48% 100.00% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::total 44678630 # Number of insts commited each cycle 606system.cpu.commit.committedInsts 70913181 # Number of instructions committed 607system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed 608system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 609system.cpu.commit.refs 47862846 # Number of memory references committed 610system.cpu.commit.loads 27307108 # Number of loads committed 611system.cpu.commit.membars 15920 # Number of memory barriers committed 612system.cpu.commit.branches 13741485 # Number of branches committed 613system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 614system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. 615system.cpu.commit.function_calls 1679850 # Number of function calls committed. 616system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 617system.cpu.commit.op_class_0::IntAlu 52689456 52.36% 52.36% # Class of committed instruction 618system.cpu.commit.op_class_0::IntMult 80119 0.08% 52.44% # Class of committed instruction 619system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.44% # Class of committed instruction 620system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.44% # Class of committed instruction 621system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.44% # Class of committed instruction 622system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.44% # Class of committed instruction 623system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.44% # Class of committed instruction 624system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.44% # Class of committed instruction 625system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.44% # Class of committed instruction 626system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.44% # Class of committed instruction 627system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.44% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.44% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.44% # Class of committed instruction 630system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.44% # Class of committed instruction 631system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.44% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.44% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.44% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.44% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.44% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.44% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.44% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.44% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.44% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.44% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.44% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.44% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.44% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.44% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.44% # Class of committed instruction 646system.cpu.commit.op_class_0::MemRead 27307108 27.14% 79.57% # Class of committed instruction 647system.cpu.commit.op_class_0::MemWrite 20555738 20.43% 100.00% # Class of committed instruction 648system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 649system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 650system.cpu.commit.op_class_0::total 100632428 # Class of committed instruction 651system.cpu.commit.bw_lim_events 6023270 # number cycles where commit BW limit reached 652system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 653system.cpu.rob.rob_reads 150242538 # The number of ROB reads 654system.cpu.rob.rob_writes 224871982 # The number of ROB writes 655system.cpu.timesIdled 79510 # Number of times that the entire CPU went into an idle state and unscheduled itself 656system.cpu.idleCycles 6993412 # Total number of cycles that the CPU has spent unscheduled due to idling 657system.cpu.committedInsts 70907629 # Number of Instructions Simulated 658system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026655 # Number of seconds simulated 4sim_ticks 26655046000 # Number of ticks simulated 5final_tick 26655046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 108502 # Simulator instruction rate (inst/s) 8host_op_rate 153979 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40787374 # Simulator tick rate (ticks/s) 10host_mem_usage 322284 # Number of bytes of host memory used 11host_seconds 653.51 # Real time elapsed on the host 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 100626876 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 298176 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8241600 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 298176 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 298176 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5372544 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5372544 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4659 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128775 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 83946 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 83946 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 11186475 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 298008265 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 309194739 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 11186475 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 11186475 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 201558234 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 201558234 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 201558234 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 11186475 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 298008265 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 510752973 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 128776 # Number of read requests accepted 40system.physmem.writeReqs 83946 # Number of write requests accepted 41system.physmem.readBursts 128776 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 83946 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 8241344 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue 45system.physmem.bytesWritten 5371328 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 8241664 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 5372544 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 320 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8145 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8395 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8248 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8167 # Per bank write bursts 55system.physmem.perBankRdBursts::4 8288 # Per bank write bursts 56system.physmem.perBankRdBursts::5 8447 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8087 # Per bank write bursts 58system.physmem.perBankRdBursts::7 7963 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8065 # Per bank write bursts 60system.physmem.perBankRdBursts::9 7608 # Per bank write bursts 61system.physmem.perBankRdBursts::10 7787 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7815 # Per bank write bursts 63system.physmem.perBankRdBursts::12 7882 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7885 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7978 # Per bank write bursts 66system.physmem.perBankRdBursts::15 8011 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5180 # Per bank write bursts 68system.physmem.perBankWrBursts::1 5377 # Per bank write bursts 69system.physmem.perBankWrBursts::2 5291 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5157 # Per bank write bursts 71system.physmem.perBankWrBursts::4 5265 # Per bank write bursts 72system.physmem.perBankWrBursts::5 5517 # Per bank write bursts 73system.physmem.perBankWrBursts::6 5199 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5049 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5030 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5091 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5246 # Per bank write bursts 78system.physmem.perBankWrBursts::11 5144 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5342 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5451 # Per bank write bursts 82system.physmem.perBankWrBursts::15 5225 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 26655030500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 128776 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 83946 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 74138 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 53140 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 1433 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 52 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 643 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 655 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 2224 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4090 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4895 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5167 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5187 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5223 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5237 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5353 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5362 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5604 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5798 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 6233 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 6000 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5239 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 37804 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 360.014390 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 216.175335 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 343.156707 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 12089 31.98% 31.98% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 7874 20.83% 52.81% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 3781 10.00% 62.81% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2728 7.22% 70.02% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2397 6.34% 76.36% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1617 4.28% 80.64% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1220 3.23% 83.87% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1066 2.82% 86.69% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 5032 13.31% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 37804 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5144 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 25.030132 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 392.032521 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5142 99.96% 99.96% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5144 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5144 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 16.315513 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 16.292869 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.917660 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 4492 87.33% 87.33% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 6 0.12% 87.44% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 431 8.38% 95.82% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 161 3.13% 98.95% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20 33 0.64% 99.59% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::21 11 0.21% 99.81% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::22 6 0.12% 99.92% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::23 1 0.02% 99.94% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::28 1 0.02% 99.96% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::30 1 0.02% 99.98% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::total 5144 # Writes before turning the bus around for reads 233system.physmem.totQLat 2471536000 # Total ticks spent queuing 234system.physmem.totMemAccLat 4885992250 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 643855000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 19193.27 # Average queueing delay per DRAM burst 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 238system.physmem.avgMemAccLat 37943.27 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 309.19 # Average DRAM read bandwidth in MiByte/s 240system.physmem.avgWrBW 201.51 # Average achieved write bandwidth in MiByte/s 241system.physmem.avgRdBWSys 309.20 # Average system read bandwidth in MiByte/s 242system.physmem.avgWrBWSys 201.56 # Average system write bandwidth in MiByte/s 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 244system.physmem.busUtil 3.99 # Data bus utilization in percentage 245system.physmem.busUtilRead 2.42 # Data bus utilization in percentage for reads 246system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes 247system.physmem.avgRdQLen 1.35 # Average read queue length when enqueuing 248system.physmem.avgWrQLen 23.52 # Average write queue length when enqueuing 249system.physmem.readRowHits 112800 # Number of row buffer hits during reads 250system.physmem.writeRowHits 62083 # Number of row buffer hits during writes 251system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads 252system.physmem.writeRowHitRate 73.96 # Row buffer hit rate for writes 253system.physmem.avgGap 125304.53 # Average gap between requests 254system.physmem.pageHitRate 82.21 # Row buffer hit rate, read and write combined 255system.physmem.memoryStateTime::IDLE 11333884750 # Time in different power states 256system.physmem.memoryStateTime::REF 889980000 # Time in different power states 257system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 258system.physmem.memoryStateTime::ACT 14428773750 # Time in different power states 259system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 260system.membus.throughput 510752973 # Throughput (bytes/s) 261system.membus.trans_dist::ReadReq 26520 # Transaction distribution 262system.membus.trans_dist::ReadResp 26519 # Transaction distribution 263system.membus.trans_dist::Writeback 83946 # Transaction distribution 264system.membus.trans_dist::UpgradeReq 320 # Transaction distribution 265system.membus.trans_dist::UpgradeResp 320 # Transaction distribution 266system.membus.trans_dist::ReadExReq 102256 # Transaction distribution 267system.membus.trans_dist::ReadExResp 102256 # Transaction distribution 268system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342137 # Packet count per connected master and slave (bytes) 269system.membus.pkt_count::total 342137 # Packet count per connected master and slave (bytes) 270system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614144 # Cumulative packet size per connected master and slave (bytes) 271system.membus.tot_pkt_size::total 13614144 # Cumulative packet size per connected master and slave (bytes) 272system.membus.data_through_bus 13614144 # Total data (bytes) 273system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 274system.membus.reqLayer0.occupancy 932451500 # Layer occupancy (ticks) 275system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) 276system.membus.respLayer1.occupancy 1211794930 # Layer occupancy (ticks) 277system.membus.respLayer1.utilization 4.5 # Layer utilization (%) 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.branchPred.lookups 16636502 # Number of BP lookups 280system.cpu.branchPred.condPredicted 12767541 # Number of conditional branches predicted 281system.cpu.branchPred.condIncorrect 605249 # Number of conditional branches incorrect 282system.cpu.branchPred.BTBLookups 10577266 # Number of BTB lookups 283system.cpu.branchPred.BTBHits 7776939 # Number of BTB hits 284system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 285system.cpu.branchPred.BTBHitPct 73.525039 # BTB Hit Percentage 286system.cpu.branchPred.usedRAS 1824082 # Number of times the RAS was used to get a target. 287system.cpu.branchPred.RASInCorrect 113194 # Number of incorrect RAS predictions. 288system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 289system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 290system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 291system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 292system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 293system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 294system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 295system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 296system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 297system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 298system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 299system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 300system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 301system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 304system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 305system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 306system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 307system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 308system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 309system.cpu.dtb.inst_hits 0 # ITB inst hits 310system.cpu.dtb.inst_misses 0 # ITB inst misses 311system.cpu.dtb.read_hits 0 # DTB read hits 312system.cpu.dtb.read_misses 0 # DTB read misses 313system.cpu.dtb.write_hits 0 # DTB write hits 314system.cpu.dtb.write_misses 0 # DTB write misses 315system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 316system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 317system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 318system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 319system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 320system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 321system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 322system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 323system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 324system.cpu.dtb.read_accesses 0 # DTB read accesses 325system.cpu.dtb.write_accesses 0 # DTB write accesses 326system.cpu.dtb.inst_accesses 0 # ITB inst accesses 327system.cpu.dtb.hits 0 # DTB hits 328system.cpu.dtb.misses 0 # DTB misses 329system.cpu.dtb.accesses 0 # DTB accesses 330system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 331system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 332system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 333system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 334system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 335system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 336system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 337system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 338system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 340system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 341system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 342system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 343system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 344system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 345system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 346system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 347system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 348system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 349system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 350system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 351system.cpu.itb.inst_hits 0 # ITB inst hits 352system.cpu.itb.inst_misses 0 # ITB inst misses 353system.cpu.itb.read_hits 0 # DTB read hits 354system.cpu.itb.read_misses 0 # DTB read misses 355system.cpu.itb.write_hits 0 # DTB write hits 356system.cpu.itb.write_misses 0 # DTB write misses 357system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 358system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 359system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 360system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 361system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 362system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 363system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 364system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 365system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 366system.cpu.itb.read_accesses 0 # DTB read accesses 367system.cpu.itb.write_accesses 0 # DTB write accesses 368system.cpu.itb.inst_accesses 0 # ITB inst accesses 369system.cpu.itb.hits 0 # DTB hits 370system.cpu.itb.misses 0 # DTB misses 371system.cpu.itb.accesses 0 # DTB accesses 372system.cpu.workload.num_syscalls 1946 # Number of system calls 373system.cpu.numCycles 53310093 # number of cpu cycles simulated 374system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 375system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 376system.cpu.fetch.icacheStallCycles 12544266 # Number of cycles fetch is stalled on an Icache miss 377system.cpu.fetch.Insts 85245132 # Number of instructions fetch has processed 378system.cpu.fetch.Branches 16636502 # Number of branches that fetch encountered 379system.cpu.fetch.predictedBranches 9601021 # Number of branches that fetch has predicted taken 380system.cpu.fetch.Cycles 21203621 # Number of cycles fetch has run and was not squashing or blocked 381system.cpu.fetch.SquashCycles 2373453 # Number of cycles fetch has spent squashing 382system.cpu.fetch.BlockedCycles 10826846 # Number of cycles fetch has spent blocked 383system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 384system.cpu.fetch.PendingTrapStallCycles 346 # Number of stall cycles due to pending traps 385system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR 386system.cpu.fetch.CacheLines 11685368 # Number of cache lines fetched 387system.cpu.fetch.IcacheSquashes 181941 # Number of outstanding Icache misses that were squashed 388system.cpu.fetch.rateDist::samples 46316681 # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::mean 2.577051 # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::stdev 3.331362 # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::0 25133357 54.26% 54.26% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::1 2139356 4.62% 58.88% # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::2 1964088 4.24% 63.12% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::3 2042720 4.41% 67.53% # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::4 1470632 3.18% 70.71% # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::5 1380684 2.98% 73.69% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::6 958438 2.07% 75.76% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::7 1191046 2.57% 78.33% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::8 10036360 21.67% 100.00% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::total 46316681 # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.branchRate 0.312070 # Number of branch fetches per cycle 406system.cpu.fetch.rate 1.599043 # Number of inst fetches per cycle 407system.cpu.decode.IdleCycles 14641724 # Number of cycles decode is idle 408system.cpu.decode.BlockedCycles 9163742 # Number of cycles decode is blocked 409system.cpu.decode.RunCycles 19491129 # Number of cycles decode is running 410system.cpu.decode.UnblockCycles 1382035 # Number of cycles decode is unblocking 411system.cpu.decode.SquashCycles 1638051 # Number of cycles decode is squashing 412system.cpu.decode.BranchResolved 3333190 # Number of times decode resolved a branch 413system.cpu.decode.BranchMispred 105248 # Number of times decode detected a branch misprediction 414system.cpu.decode.DecodedInsts 116897409 # Number of instructions handled by decode 415system.cpu.decode.SquashedInsts 363517 # Number of squashed instructions handled by decode 416system.cpu.rename.SquashCycles 1638051 # Number of cycles rename is squashing 417system.cpu.rename.IdleCycles 16359930 # Number of cycles rename is idle 418system.cpu.rename.BlockCycles 2678860 # Number of cycles rename is blocking 419system.cpu.rename.serializeStallCycles 1013546 # count of cycles rename stalled for serializing inst 420system.cpu.rename.RunCycles 19105164 # Number of cycles rename is running 421system.cpu.rename.UnblockCycles 5521130 # Number of cycles rename is unblocking 422system.cpu.rename.RenamedInsts 115000815 # Number of instructions processed by rename 423system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full 424system.cpu.rename.IQFullEvents 16720 # Number of times rename has blocked due to IQ full 425system.cpu.rename.LSQFullEvents 4660350 # Number of times rename has blocked due to LSQ full 426system.cpu.rename.FullRegisterEvents 282 # Number of times there has been no free registers 427system.cpu.rename.RenamedOperands 115331621 # Number of destination operands rename has renamed 428system.cpu.rename.RenameLookups 529914525 # Number of register rename lookups that rename has made 429system.cpu.rename.int_rename_lookups 476510410 # Number of integer rename lookups 430system.cpu.rename.fp_rename_lookups 2776 # Number of floating rename lookups 431system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed 432system.cpu.rename.UndoneMaps 16198949 # Number of HB maps that are undone due to squashing 433system.cpu.rename.serializingInsts 20436 # count of serializing insts renamed 434system.cpu.rename.tempSerializingInsts 20434 # count of temporary serializing insts renamed 435system.cpu.rename.skidInsts 13095384 # count of insts added to the skid buffer 436system.cpu.memDep0.insertedLoads 29625138 # Number of loads inserted to the mem dependence unit. 437system.cpu.memDep0.insertedStores 22434042 # Number of stores inserted to the mem dependence unit. 438system.cpu.memDep0.conflictingLoads 3869725 # Number of conflicting loads. 439system.cpu.memDep0.conflictingStores 4362550 # Number of conflicting stores. 440system.cpu.iq.iqInstsAdded 111565619 # Number of instructions added to the IQ (excludes non-spec) 441system.cpu.iq.iqNonSpecInstsAdded 36058 # Number of non-speculative instructions added to the IQ 442system.cpu.iq.iqInstsIssued 107262004 # Number of instructions issued 443system.cpu.iq.iqSquashedInstsIssued 275498 # Number of squashed instructions issued 444system.cpu.iq.iqSquashedInstsExamined 10829281 # Number of squashed instructions iterated over during squash; mainly for profiling 445system.cpu.iq.iqSquashedOperandsExamined 25946611 # Number of squashed operands that are examined and possibly removed from graph 446system.cpu.iq.iqSquashedNonSpecRemoved 2272 # Number of squashed non-spec instructions that were removed 447system.cpu.iq.issued_per_cycle::samples 46316681 # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::mean 2.315840 # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::stdev 1.990470 # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::0 11030019 23.81% 23.81% # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::1 8138803 17.57% 41.39% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::2 7430883 16.04% 57.43% # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::3 7110857 15.35% 72.78% # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::4 5417654 11.70% 84.48% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::5 3891349 8.40% 92.88% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::6 1848302 3.99% 96.87% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::7 878821 1.90% 98.77% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::8 569993 1.23% 100.00% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::total 46316681 # Number of insts issued each cycle 464system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 465system.cpu.iq.fu_full::IntAlu 113827 4.59% 4.59% # attempts to use FU when none available 466system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available 467system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available 468system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.59% # attempts to use FU when none available 469system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available 470system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available 471system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available 472system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available 494system.cpu.iq.fu_full::MemRead 1360293 54.84% 59.43% # attempts to use FU when none available 495system.cpu.iq.fu_full::MemWrite 1006288 40.57% 100.00% # attempts to use FU when none available 496system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 497system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 498system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 499system.cpu.iq.FU_type_0::IntAlu 56646184 52.81% 52.81% # Type of FU issued 500system.cpu.iq.FU_type_0::IntMult 91539 0.09% 52.90% # Type of FU issued 501system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued 502system.cpu.iq.FU_type_0::FloatAdd 222 0.00% 52.90% # Type of FU issued 503system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued 504system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued 505system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued 506system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued 507system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued 528system.cpu.iq.FU_type_0::MemRead 28903042 26.95% 79.84% # Type of FU issued 529system.cpu.iq.FU_type_0::MemWrite 21621010 20.16% 100.00% # Type of FU issued 530system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 531system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 532system.cpu.iq.FU_type_0::total 107262004 # Type of FU issued 533system.cpu.iq.rate 2.012039 # Inst issue rate 534system.cpu.iq.fu_busy_cnt 2480410 # FU busy when requested 535system.cpu.iq.fu_busy_rate 0.023125 # FU busy rate (busy events/executed inst) 536system.cpu.iq.int_inst_queue_reads 263595997 # Number of integer instruction queue reads 537system.cpu.iq.int_inst_queue_writes 122458930 # Number of integer instruction queue writes 538system.cpu.iq.int_inst_queue_wakeup_accesses 105571537 # Number of integer instruction queue wakeup accesses 539system.cpu.iq.fp_inst_queue_reads 600 # Number of floating instruction queue reads 540system.cpu.iq.fp_inst_queue_writes 932 # Number of floating instruction queue writes 541system.cpu.iq.fp_inst_queue_wakeup_accesses 176 # Number of floating instruction queue wakeup accesses 542system.cpu.iq.int_alu_accesses 109742111 # Number of integer alu accesses 543system.cpu.iq.fp_alu_accesses 303 # Number of floating point alu accesses 544system.cpu.iew.lsq.thread0.forwLoads 2179776 # Number of loads that had data forwarded from stores 545system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 546system.cpu.iew.lsq.thread0.squashedLoads 2318030 # Number of loads squashed 547system.cpu.iew.lsq.thread0.ignoredResponses 6495 # Number of memory responses ignored because the instruction is squashed 548system.cpu.iew.lsq.thread0.memOrderViolation 30041 # Number of memory ordering violations 549system.cpu.iew.lsq.thread0.squashedStores 1878304 # Number of stores squashed 550system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 551system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 552system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled 553system.cpu.iew.lsq.thread0.cacheBlocked 708 # Number of times an access to memory failed due to the cache being blocked 554system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 555system.cpu.iew.iewSquashCycles 1638051 # Number of cycles IEW is squashing 556system.cpu.iew.iewBlockCycles 1126663 # Number of cycles IEW is blocking 557system.cpu.iew.iewUnblockCycles 45667 # Number of cycles IEW is unblocking 558system.cpu.iew.iewDispatchedInsts 111611483 # Number of instructions dispatched to IQ 559system.cpu.iew.iewDispSquashedInsts 295320 # Number of squashed instructions skipped by dispatch 560system.cpu.iew.iewDispLoadInsts 29625138 # Number of dispatched load instructions 561system.cpu.iew.iewDispStoreInsts 22434042 # Number of dispatched store instructions 562system.cpu.iew.iewDispNonSpecInsts 20138 # Number of dispatched non-speculative instructions 563system.cpu.iew.iewIQFullEvents 6203 # Number of times the IQ has become full, causing a stall 564system.cpu.iew.iewLSQFullEvents 5120 # Number of times the LSQ has become full, causing a stall 565system.cpu.iew.memOrderViolationEvents 30041 # Number of memory order violations 566system.cpu.iew.predictedTakenIncorrect 394287 # Number of branches that were predicted taken incorrectly 567system.cpu.iew.predictedNotTakenIncorrect 181285 # Number of branches that were predicted not taken incorrectly 568system.cpu.iew.branchMispredicts 575572 # Number of branch mispredicts detected at execute 569system.cpu.iew.iewExecutedInsts 106232062 # Number of executed instructions 570system.cpu.iew.iewExecLoadInsts 28604336 # Number of load instructions executed 571system.cpu.iew.iewExecSquashedInsts 1029942 # Number of squashed instructions skipped in execute 572system.cpu.iew.exec_swp 0 # number of swp insts executed 573system.cpu.iew.exec_nop 9806 # number of nop insts executed 574system.cpu.iew.exec_refs 49939736 # number of memory reference insts executed 575system.cpu.iew.exec_branches 14601830 # Number of branches executed 576system.cpu.iew.exec_stores 21335400 # Number of stores executed 577system.cpu.iew.exec_rate 1.992720 # Inst execution rate 578system.cpu.iew.wb_sent 105794271 # cumulative count of insts sent to commit 579system.cpu.iew.wb_count 105571713 # cumulative count of insts written-back 580system.cpu.iew.wb_producers 53289529 # num instructions producing a value 581system.cpu.iew.wb_consumers 103696689 # num instructions consuming a value 582system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 583system.cpu.iew.wb_rate 1.980333 # insts written-back per cycle 584system.cpu.iew.wb_fanout 0.513898 # average fanout of values written-back 585system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 586system.cpu.commit.commitSquashedInsts 10980049 # The number of squashed insts skipped by commit 587system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 588system.cpu.commit.branchMispredicts 501819 # The number of times a branch was mispredicted 589system.cpu.commit.committed_per_cycle::samples 44678630 # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::mean 2.252362 # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::stdev 2.761359 # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::0 15558775 34.82% 34.82% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::1 11701818 26.19% 61.01% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::2 3471869 7.77% 68.79% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::3 2879306 6.44% 75.23% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::4 1869514 4.18% 79.41% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::5 1922443 4.30% 83.72% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::6 688922 1.54% 85.26% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::7 562713 1.26% 86.52% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::8 6023270 13.48% 100.00% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::total 44678630 # Number of insts commited each cycle 606system.cpu.commit.committedInsts 70913181 # Number of instructions committed 607system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed 608system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 609system.cpu.commit.refs 47862846 # Number of memory references committed 610system.cpu.commit.loads 27307108 # Number of loads committed 611system.cpu.commit.membars 15920 # Number of memory barriers committed 612system.cpu.commit.branches 13741485 # Number of branches committed 613system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 614system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. 615system.cpu.commit.function_calls 1679850 # Number of function calls committed. 616system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 617system.cpu.commit.op_class_0::IntAlu 52689456 52.36% 52.36% # Class of committed instruction 618system.cpu.commit.op_class_0::IntMult 80119 0.08% 52.44% # Class of committed instruction 619system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.44% # Class of committed instruction 620system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.44% # Class of committed instruction 621system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.44% # Class of committed instruction 622system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.44% # Class of committed instruction 623system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.44% # Class of committed instruction 624system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.44% # Class of committed instruction 625system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.44% # Class of committed instruction 626system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.44% # Class of committed instruction 627system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.44% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.44% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.44% # Class of committed instruction 630system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.44% # Class of committed instruction 631system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.44% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.44% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.44% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.44% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.44% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.44% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.44% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.44% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.44% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.44% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.44% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.44% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.44% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.44% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.44% # Class of committed instruction 646system.cpu.commit.op_class_0::MemRead 27307108 27.14% 79.57% # Class of committed instruction 647system.cpu.commit.op_class_0::MemWrite 20555738 20.43% 100.00% # Class of committed instruction 648system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 649system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 650system.cpu.commit.op_class_0::total 100632428 # Class of committed instruction 651system.cpu.commit.bw_lim_events 6023270 # number cycles where commit BW limit reached 652system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 653system.cpu.rob.rob_reads 150242538 # The number of ROB reads 654system.cpu.rob.rob_writes 224871982 # The number of ROB writes 655system.cpu.timesIdled 79510 # Number of times that the entire CPU went into an idle state and unscheduled itself 656system.cpu.idleCycles 6993412 # Total number of cycles that the CPU has spent unscheduled due to idling 657system.cpu.committedInsts 70907629 # Number of Instructions Simulated 658system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
659system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
660system.cpu.cpi 0.751825 # CPI: Cycles Per Instruction 661system.cpu.cpi_total 0.751825 # CPI: Total CPI of All Threads 662system.cpu.ipc 1.330098 # IPC: Instructions Per Cycle 663system.cpu.ipc_total 1.330098 # IPC: Total IPC of All Threads 664system.cpu.int_regfile_reads 511631717 # number of integer regfile reads 665system.cpu.int_regfile_writes 103353872 # number of integer regfile writes 666system.cpu.fp_regfile_reads 846 # number of floating regfile reads 667system.cpu.fp_regfile_writes 710 # number of floating regfile writes 668system.cpu.misc_regfile_reads 49341635 # number of misc regfile reads 669system.cpu.misc_regfile_writes 31840 # number of misc regfile writes 670system.cpu.toL2Bus.throughput 775139386 # Throughput (bytes/s) 671system.cpu.toL2Bus.trans_dist::ReadReq 86625 # Transaction distribution 672system.cpu.toL2Bus.trans_dist::ReadResp 86624 # Transaction distribution 673system.cpu.toL2Bus.trans_dist::Writeback 129165 # Transaction distribution 674system.cpu.toL2Bus.trans_dist::UpgradeReq 335 # Transaction distribution 675system.cpu.toL2Bus.trans_dist::UpgradeResp 335 # Transaction distribution 676system.cpu.toL2Bus.trans_dist::ReadExReq 107045 # Transaction distribution 677system.cpu.toL2Bus.trans_dist::ReadExResp 107045 # Transaction distribution 678system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62039 # Packet count per connected master and slave (bytes) 679system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454624 # Packet count per connected master and slave (bytes) 680system.cpu.toL2Bus.pkt_count::total 516663 # Packet count per connected master and slave (bytes) 681system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1968896 # Cumulative packet size per connected master and slave (bytes) 682system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18659776 # Cumulative packet size per connected master and slave (bytes) 683system.cpu.toL2Bus.tot_pkt_size::total 20628672 # Cumulative packet size per connected master and slave (bytes) 684system.cpu.toL2Bus.data_through_bus 20628672 # Total data (bytes) 685system.cpu.toL2Bus.snoop_data_through_bus 32704 # Total snoop data (bytes) 686system.cpu.toL2Bus.reqLayer0.occupancy 290752497 # Layer occupancy (ticks) 687system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 688system.cpu.toL2Bus.respLayer0.occupancy 47657477 # Layer occupancy (ticks) 689system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 690system.cpu.toL2Bus.respLayer1.occupancy 267144007 # Layer occupancy (ticks) 691system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 692system.cpu.icache.tags.replacements 28917 # number of replacements 693system.cpu.icache.tags.tagsinuse 1807.865134 # Cycle average of tags in use 694system.cpu.icache.tags.total_refs 11650266 # Total number of references to valid blocks. 695system.cpu.icache.tags.sampled_refs 30950 # Sample count of references to valid blocks. 696system.cpu.icache.tags.avg_refs 376.422165 # Average number of references to valid blocks. 697system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 698system.cpu.icache.tags.occ_blocks::cpu.inst 1807.865134 # Average occupied blocks per requestor 699system.cpu.icache.tags.occ_percent::cpu.inst 0.882747 # Average percentage of cache occupancy 700system.cpu.icache.tags.occ_percent::total 0.882747 # Average percentage of cache occupancy 701system.cpu.icache.tags.occ_task_id_blocks::1024 2033 # Occupied blocks per task id 702system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 703system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 704system.cpu.icache.tags.age_task_id_blocks_1024::3 1259 # Occupied blocks per task id 705system.cpu.icache.tags.age_task_id_blocks_1024::4 672 # Occupied blocks per task id 706system.cpu.icache.tags.occ_task_id_percent::1024 0.992676 # Percentage of cache occupancy per task id 707system.cpu.icache.tags.tag_accesses 23402009 # Number of tag accesses 708system.cpu.icache.tags.data_accesses 23402009 # Number of data accesses 709system.cpu.icache.ReadReq_hits::cpu.inst 11650274 # number of ReadReq hits 710system.cpu.icache.ReadReq_hits::total 11650274 # number of ReadReq hits 711system.cpu.icache.demand_hits::cpu.inst 11650274 # number of demand (read+write) hits 712system.cpu.icache.demand_hits::total 11650274 # number of demand (read+write) hits 713system.cpu.icache.overall_hits::cpu.inst 11650274 # number of overall hits 714system.cpu.icache.overall_hits::total 11650274 # number of overall hits 715system.cpu.icache.ReadReq_misses::cpu.inst 35093 # number of ReadReq misses 716system.cpu.icache.ReadReq_misses::total 35093 # number of ReadReq misses 717system.cpu.icache.demand_misses::cpu.inst 35093 # number of demand (read+write) misses 718system.cpu.icache.demand_misses::total 35093 # number of demand (read+write) misses 719system.cpu.icache.overall_misses::cpu.inst 35093 # number of overall misses 720system.cpu.icache.overall_misses::total 35093 # number of overall misses 721system.cpu.icache.ReadReq_miss_latency::cpu.inst 796173972 # number of ReadReq miss cycles 722system.cpu.icache.ReadReq_miss_latency::total 796173972 # number of ReadReq miss cycles 723system.cpu.icache.demand_miss_latency::cpu.inst 796173972 # number of demand (read+write) miss cycles 724system.cpu.icache.demand_miss_latency::total 796173972 # number of demand (read+write) miss cycles 725system.cpu.icache.overall_miss_latency::cpu.inst 796173972 # number of overall miss cycles 726system.cpu.icache.overall_miss_latency::total 796173972 # number of overall miss cycles 727system.cpu.icache.ReadReq_accesses::cpu.inst 11685367 # number of ReadReq accesses(hits+misses) 728system.cpu.icache.ReadReq_accesses::total 11685367 # number of ReadReq accesses(hits+misses) 729system.cpu.icache.demand_accesses::cpu.inst 11685367 # number of demand (read+write) accesses 730system.cpu.icache.demand_accesses::total 11685367 # number of demand (read+write) accesses 731system.cpu.icache.overall_accesses::cpu.inst 11685367 # number of overall (read+write) accesses 732system.cpu.icache.overall_accesses::total 11685367 # number of overall (read+write) accesses 733system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003003 # miss rate for ReadReq accesses 734system.cpu.icache.ReadReq_miss_rate::total 0.003003 # miss rate for ReadReq accesses 735system.cpu.icache.demand_miss_rate::cpu.inst 0.003003 # miss rate for demand accesses 736system.cpu.icache.demand_miss_rate::total 0.003003 # miss rate for demand accesses 737system.cpu.icache.overall_miss_rate::cpu.inst 0.003003 # miss rate for overall accesses 738system.cpu.icache.overall_miss_rate::total 0.003003 # miss rate for overall accesses 739system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22687.543727 # average ReadReq miss latency 740system.cpu.icache.ReadReq_avg_miss_latency::total 22687.543727 # average ReadReq miss latency 741system.cpu.icache.demand_avg_miss_latency::cpu.inst 22687.543727 # average overall miss latency 742system.cpu.icache.demand_avg_miss_latency::total 22687.543727 # average overall miss latency 743system.cpu.icache.overall_avg_miss_latency::cpu.inst 22687.543727 # average overall miss latency 744system.cpu.icache.overall_avg_miss_latency::total 22687.543727 # average overall miss latency 745system.cpu.icache.blocked_cycles::no_mshrs 1584 # number of cycles access was blocked 746system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 747system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked 748system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 749system.cpu.icache.avg_blocked_cycles::no_mshrs 60.923077 # average number of cycles each access was blocked 750system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 751system.cpu.icache.fast_writes 0 # number of fast writes performed 752system.cpu.icache.cache_copies 0 # number of cache copies performed 753system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3818 # number of ReadReq MSHR hits 754system.cpu.icache.ReadReq_mshr_hits::total 3818 # number of ReadReq MSHR hits 755system.cpu.icache.demand_mshr_hits::cpu.inst 3818 # number of demand (read+write) MSHR hits 756system.cpu.icache.demand_mshr_hits::total 3818 # number of demand (read+write) MSHR hits 757system.cpu.icache.overall_mshr_hits::cpu.inst 3818 # number of overall MSHR hits 758system.cpu.icache.overall_mshr_hits::total 3818 # number of overall MSHR hits 759system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31275 # number of ReadReq MSHR misses 760system.cpu.icache.ReadReq_mshr_misses::total 31275 # number of ReadReq MSHR misses 761system.cpu.icache.demand_mshr_misses::cpu.inst 31275 # number of demand (read+write) MSHR misses 762system.cpu.icache.demand_mshr_misses::total 31275 # number of demand (read+write) MSHR misses 763system.cpu.icache.overall_mshr_misses::cpu.inst 31275 # number of overall MSHR misses 764system.cpu.icache.overall_mshr_misses::total 31275 # number of overall MSHR misses 765system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 647196022 # number of ReadReq MSHR miss cycles 766system.cpu.icache.ReadReq_mshr_miss_latency::total 647196022 # number of ReadReq MSHR miss cycles 767system.cpu.icache.demand_mshr_miss_latency::cpu.inst 647196022 # number of demand (read+write) MSHR miss cycles 768system.cpu.icache.demand_mshr_miss_latency::total 647196022 # number of demand (read+write) MSHR miss cycles 769system.cpu.icache.overall_mshr_miss_latency::cpu.inst 647196022 # number of overall MSHR miss cycles 770system.cpu.icache.overall_mshr_miss_latency::total 647196022 # number of overall MSHR miss cycles 771system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses 772system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses 773system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses 774system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses 775system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses 776system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses 777system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.717730 # average ReadReq mshr miss latency 778system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.717730 # average ReadReq mshr miss latency 779system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.717730 # average overall mshr miss latency 780system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.717730 # average overall mshr miss latency 781system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.717730 # average overall mshr miss latency 782system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.717730 # average overall mshr miss latency 783system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 784system.cpu.l2cache.tags.replacements 95645 # number of replacements 785system.cpu.l2cache.tags.tagsinuse 29867.639929 # Cycle average of tags in use 786system.cpu.l2cache.tags.total_refs 88414 # Total number of references to valid blocks. 787system.cpu.l2cache.tags.sampled_refs 126758 # Sample count of references to valid blocks. 788system.cpu.l2cache.tags.avg_refs 0.697502 # Average number of references to valid blocks. 789system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 790system.cpu.l2cache.tags.occ_blocks::writebacks 26665.630532 # Average occupied blocks per requestor 791system.cpu.l2cache.tags.occ_blocks::cpu.inst 1369.813019 # Average occupied blocks per requestor 792system.cpu.l2cache.tags.occ_blocks::cpu.data 1832.196377 # Average occupied blocks per requestor 793system.cpu.l2cache.tags.occ_percent::writebacks 0.813770 # Average percentage of cache occupancy 794system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041803 # Average percentage of cache occupancy 795system.cpu.l2cache.tags.occ_percent::cpu.data 0.055914 # Average percentage of cache occupancy 796system.cpu.l2cache.tags.occ_percent::total 0.911488 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_task_id_blocks::1024 31113 # Occupied blocks per task id 798system.cpu.l2cache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id 799system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1847 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20513 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8219 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id 803system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949493 # Percentage of cache occupancy per task id 804system.cpu.l2cache.tags.tag_accesses 2815092 # Number of tag accesses 805system.cpu.l2cache.tags.data_accesses 2815092 # Number of data accesses 806system.cpu.l2cache.ReadReq_hits::cpu.inst 26089 # number of ReadReq hits 807system.cpu.l2cache.ReadReq_hits::cpu.data 33429 # number of ReadReq hits 808system.cpu.l2cache.ReadReq_hits::total 59518 # number of ReadReq hits 809system.cpu.l2cache.Writeback_hits::writebacks 129165 # number of Writeback hits 810system.cpu.l2cache.Writeback_hits::total 129165 # number of Writeback hits 811system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits 812system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits 813system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # number of ReadExReq hits 814system.cpu.l2cache.ReadExReq_hits::total 4788 # number of ReadExReq hits 815system.cpu.l2cache.demand_hits::cpu.inst 26089 # number of demand (read+write) hits 816system.cpu.l2cache.demand_hits::cpu.data 38217 # number of demand (read+write) hits 817system.cpu.l2cache.demand_hits::total 64306 # number of demand (read+write) hits 818system.cpu.l2cache.overall_hits::cpu.inst 26089 # number of overall hits 819system.cpu.l2cache.overall_hits::cpu.data 38217 # number of overall hits 820system.cpu.l2cache.overall_hits::total 64306 # number of overall hits 821system.cpu.l2cache.ReadReq_misses::cpu.inst 4675 # number of ReadReq misses 822system.cpu.l2cache.ReadReq_misses::cpu.data 21921 # number of ReadReq misses 823system.cpu.l2cache.ReadReq_misses::total 26596 # number of ReadReq misses 824system.cpu.l2cache.UpgradeReq_misses::cpu.data 319 # number of UpgradeReq misses 825system.cpu.l2cache.UpgradeReq_misses::total 319 # number of UpgradeReq misses 826system.cpu.l2cache.ReadExReq_misses::cpu.data 102257 # number of ReadExReq misses 827system.cpu.l2cache.ReadExReq_misses::total 102257 # number of ReadExReq misses 828system.cpu.l2cache.demand_misses::cpu.inst 4675 # number of demand (read+write) misses 829system.cpu.l2cache.demand_misses::cpu.data 124178 # number of demand (read+write) misses 830system.cpu.l2cache.demand_misses::total 128853 # number of demand (read+write) misses 831system.cpu.l2cache.overall_misses::cpu.inst 4675 # number of overall misses 832system.cpu.l2cache.overall_misses::cpu.data 124178 # number of overall misses 833system.cpu.l2cache.overall_misses::total 128853 # number of overall misses 834system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 354274500 # number of ReadReq miss cycles 835system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1813961250 # number of ReadReq miss cycles 836system.cpu.l2cache.ReadReq_miss_latency::total 2168235750 # number of ReadReq miss cycles 837system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles 838system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles 839system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8348408999 # number of ReadExReq miss cycles 840system.cpu.l2cache.ReadExReq_miss_latency::total 8348408999 # number of ReadExReq miss cycles 841system.cpu.l2cache.demand_miss_latency::cpu.inst 354274500 # number of demand (read+write) miss cycles 842system.cpu.l2cache.demand_miss_latency::cpu.data 10162370249 # number of demand (read+write) miss cycles 843system.cpu.l2cache.demand_miss_latency::total 10516644749 # number of demand (read+write) miss cycles 844system.cpu.l2cache.overall_miss_latency::cpu.inst 354274500 # number of overall miss cycles 845system.cpu.l2cache.overall_miss_latency::cpu.data 10162370249 # number of overall miss cycles 846system.cpu.l2cache.overall_miss_latency::total 10516644749 # number of overall miss cycles 847system.cpu.l2cache.ReadReq_accesses::cpu.inst 30764 # number of ReadReq accesses(hits+misses) 848system.cpu.l2cache.ReadReq_accesses::cpu.data 55350 # number of ReadReq accesses(hits+misses) 849system.cpu.l2cache.ReadReq_accesses::total 86114 # number of ReadReq accesses(hits+misses) 850system.cpu.l2cache.Writeback_accesses::writebacks 129165 # number of Writeback accesses(hits+misses) 851system.cpu.l2cache.Writeback_accesses::total 129165 # number of Writeback accesses(hits+misses) 852system.cpu.l2cache.UpgradeReq_accesses::cpu.data 335 # number of UpgradeReq accesses(hits+misses) 853system.cpu.l2cache.UpgradeReq_accesses::total 335 # number of UpgradeReq accesses(hits+misses) 854system.cpu.l2cache.ReadExReq_accesses::cpu.data 107045 # number of ReadExReq accesses(hits+misses) 855system.cpu.l2cache.ReadExReq_accesses::total 107045 # number of ReadExReq accesses(hits+misses) 856system.cpu.l2cache.demand_accesses::cpu.inst 30764 # number of demand (read+write) accesses 857system.cpu.l2cache.demand_accesses::cpu.data 162395 # number of demand (read+write) accesses 858system.cpu.l2cache.demand_accesses::total 193159 # number of demand (read+write) accesses 859system.cpu.l2cache.overall_accesses::cpu.inst 30764 # number of overall (read+write) accesses 860system.cpu.l2cache.overall_accesses::cpu.data 162395 # number of overall (read+write) accesses 861system.cpu.l2cache.overall_accesses::total 193159 # number of overall (read+write) accesses 862system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.151963 # miss rate for ReadReq accesses 863system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.396043 # miss rate for ReadReq accesses 864system.cpu.l2cache.ReadReq_miss_rate::total 0.308846 # miss rate for ReadReq accesses 865system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.952239 # miss rate for UpgradeReq accesses 866system.cpu.l2cache.UpgradeReq_miss_rate::total 0.952239 # miss rate for UpgradeReq accesses 867system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955271 # miss rate for ReadExReq accesses 868system.cpu.l2cache.ReadExReq_miss_rate::total 0.955271 # miss rate for ReadExReq accesses 869system.cpu.l2cache.demand_miss_rate::cpu.inst 0.151963 # miss rate for demand accesses 870system.cpu.l2cache.demand_miss_rate::cpu.data 0.764666 # miss rate for demand accesses 871system.cpu.l2cache.demand_miss_rate::total 0.667083 # miss rate for demand accesses 872system.cpu.l2cache.overall_miss_rate::cpu.inst 0.151963 # miss rate for overall accesses 873system.cpu.l2cache.overall_miss_rate::cpu.data 0.764666 # miss rate for overall accesses 874system.cpu.l2cache.overall_miss_rate::total 0.667083 # miss rate for overall accesses 875system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75780.641711 # average ReadReq miss latency 876system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82749.931572 # average ReadReq miss latency 877system.cpu.l2cache.ReadReq_avg_miss_latency::total 81524.881561 # average ReadReq miss latency 878system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 72.097179 # average UpgradeReq miss latency 879system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 72.097179 # average UpgradeReq miss latency 880system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81641.442630 # average ReadExReq miss latency 881system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81641.442630 # average ReadExReq miss latency 882system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75780.641711 # average overall miss latency 883system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81837.122912 # average overall miss latency 884system.cpu.l2cache.demand_avg_miss_latency::total 81617.383755 # average overall miss latency 885system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75780.641711 # average overall miss latency 886system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81837.122912 # average overall miss latency 887system.cpu.l2cache.overall_avg_miss_latency::total 81617.383755 # average overall miss latency 888system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 889system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 890system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 891system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 892system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 893system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 894system.cpu.l2cache.fast_writes 0 # number of fast writes performed 895system.cpu.l2cache.cache_copies 0 # number of cache copies performed 896system.cpu.l2cache.writebacks::writebacks 83946 # number of writebacks 897system.cpu.l2cache.writebacks::total 83946 # number of writebacks 898system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits 899system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits 900system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits 901system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits 902system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits 903system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits 904system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits 905system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits 906system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits 907system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4659 # number of ReadReq MSHR misses 908system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21861 # number of ReadReq MSHR misses 909system.cpu.l2cache.ReadReq_mshr_misses::total 26520 # number of ReadReq MSHR misses 910system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 319 # number of UpgradeReq MSHR misses 911system.cpu.l2cache.UpgradeReq_mshr_misses::total 319 # number of UpgradeReq MSHR misses 912system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses 913system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses 914system.cpu.l2cache.demand_mshr_misses::cpu.inst 4659 # number of demand (read+write) MSHR misses 915system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses 916system.cpu.l2cache.demand_mshr_misses::total 128777 # number of demand (read+write) MSHR misses 917system.cpu.l2cache.overall_mshr_misses::cpu.inst 4659 # number of overall MSHR misses 918system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses 919system.cpu.l2cache.overall_mshr_misses::total 128777 # number of overall MSHR misses 920system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 294952000 # number of ReadReq MSHR miss cycles 921system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1536285750 # number of ReadReq MSHR miss cycles 922system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1831237750 # number of ReadReq MSHR miss cycles 923system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3196819 # number of UpgradeReq MSHR miss cycles 924system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3196819 # number of UpgradeReq MSHR miss cycles 925system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7058409501 # number of ReadExReq MSHR miss cycles 926system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7058409501 # number of ReadExReq MSHR miss cycles 927system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 294952000 # number of demand (read+write) MSHR miss cycles 928system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8594695251 # number of demand (read+write) MSHR miss cycles 929system.cpu.l2cache.demand_mshr_miss_latency::total 8889647251 # number of demand (read+write) MSHR miss cycles 930system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294952000 # number of overall MSHR miss cycles 931system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8594695251 # number of overall MSHR miss cycles 932system.cpu.l2cache.overall_mshr_miss_latency::total 8889647251 # number of overall MSHR miss cycles 933system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151443 # mshr miss rate for ReadReq accesses 934system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394959 # mshr miss rate for ReadReq accesses 935system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307964 # mshr miss rate for ReadReq accesses 936system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.952239 # mshr miss rate for UpgradeReq accesses 937system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.952239 # mshr miss rate for UpgradeReq accesses 938system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955271 # mshr miss rate for ReadExReq accesses 939system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955271 # mshr miss rate for ReadExReq accesses 940system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151443 # mshr miss rate for demand accesses 941system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764297 # mshr miss rate for demand accesses 942system.cpu.l2cache.demand_mshr_miss_rate::total 0.666689 # mshr miss rate for demand accesses 943system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151443 # mshr miss rate for overall accesses 944system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764297 # mshr miss rate for overall accesses 945system.cpu.l2cache.overall_mshr_miss_rate::total 0.666689 # mshr miss rate for overall accesses 946system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63308.006010 # average ReadReq mshr miss latency 947system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70275.181831 # average ReadReq mshr miss latency 948system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69051.197210 # average ReadReq mshr miss latency 949system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10021.376176 # average UpgradeReq mshr miss latency 950system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10021.376176 # average UpgradeReq mshr miss latency 951system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69026.174257 # average ReadExReq mshr miss latency 952system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69026.174257 # average ReadExReq mshr miss latency 953system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63308.006010 # average overall mshr miss latency 954system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69246.162934 # average overall mshr miss latency 955system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69031.327419 # average overall mshr miss latency 956system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63308.006010 # average overall mshr miss latency 957system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69246.162934 # average overall mshr miss latency 958system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69031.327419 # average overall mshr miss latency 959system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 960system.cpu.dcache.tags.replacements 158298 # number of replacements 961system.cpu.dcache.tags.tagsinuse 4068.579596 # Cycle average of tags in use 962system.cpu.dcache.tags.total_refs 44367951 # Total number of references to valid blocks. 963system.cpu.dcache.tags.sampled_refs 162394 # Sample count of references to valid blocks. 964system.cpu.dcache.tags.avg_refs 273.211763 # Average number of references to valid blocks. 965system.cpu.dcache.tags.warmup_cycle 366659250 # Cycle when the warmup percentage was hit. 966system.cpu.dcache.tags.occ_blocks::cpu.data 4068.579596 # Average occupied blocks per requestor 967system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy 968system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy 969system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 970system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id 971system.cpu.dcache.tags.age_task_id_blocks_1024::1 1762 # Occupied blocks per task id 972system.cpu.dcache.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id 973system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 974system.cpu.dcache.tags.tag_accesses 92310952 # Number of tag accesses 975system.cpu.dcache.tags.data_accesses 92310952 # Number of data accesses 976system.cpu.dcache.ReadReq_hits::cpu.data 26067775 # number of ReadReq hits 977system.cpu.dcache.ReadReq_hits::total 26067775 # number of ReadReq hits 978system.cpu.dcache.WriteReq_hits::cpu.data 18267649 # number of WriteReq hits 979system.cpu.dcache.WriteReq_hits::total 18267649 # number of WriteReq hits 980system.cpu.dcache.LoadLockedReq_hits::cpu.data 15993 # number of LoadLockedReq hits 981system.cpu.dcache.LoadLockedReq_hits::total 15993 # number of LoadLockedReq hits 982system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 983system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 984system.cpu.dcache.demand_hits::cpu.data 44335424 # number of demand (read+write) hits 985system.cpu.dcache.demand_hits::total 44335424 # number of demand (read+write) hits 986system.cpu.dcache.overall_hits::cpu.data 44335424 # number of overall hits 987system.cpu.dcache.overall_hits::total 44335424 # number of overall hits 988system.cpu.dcache.ReadReq_misses::cpu.data 124650 # number of ReadReq misses 989system.cpu.dcache.ReadReq_misses::total 124650 # number of ReadReq misses 990system.cpu.dcache.WriteReq_misses::cpu.data 1582252 # number of WriteReq misses 991system.cpu.dcache.WriteReq_misses::total 1582252 # number of WriteReq misses 992system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses 993system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses 994system.cpu.dcache.demand_misses::cpu.data 1706902 # number of demand (read+write) misses 995system.cpu.dcache.demand_misses::total 1706902 # number of demand (read+write) misses 996system.cpu.dcache.overall_misses::cpu.data 1706902 # number of overall misses 997system.cpu.dcache.overall_misses::total 1706902 # number of overall misses 998system.cpu.dcache.ReadReq_miss_latency::cpu.data 5082447470 # number of ReadReq miss cycles 999system.cpu.dcache.ReadReq_miss_latency::total 5082447470 # number of ReadReq miss cycles 1000system.cpu.dcache.WriteReq_miss_latency::cpu.data 124553146004 # number of WriteReq miss cycles 1001system.cpu.dcache.WriteReq_miss_latency::total 124553146004 # number of WriteReq miss cycles 1002system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 917250 # number of LoadLockedReq miss cycles 1003system.cpu.dcache.LoadLockedReq_miss_latency::total 917250 # number of LoadLockedReq miss cycles 1004system.cpu.dcache.demand_miss_latency::cpu.data 129635593474 # number of demand (read+write) miss cycles 1005system.cpu.dcache.demand_miss_latency::total 129635593474 # number of demand (read+write) miss cycles 1006system.cpu.dcache.overall_miss_latency::cpu.data 129635593474 # number of overall miss cycles 1007system.cpu.dcache.overall_miss_latency::total 129635593474 # number of overall miss cycles 1008system.cpu.dcache.ReadReq_accesses::cpu.data 26192425 # number of ReadReq accesses(hits+misses) 1009system.cpu.dcache.ReadReq_accesses::total 26192425 # number of ReadReq accesses(hits+misses) 1010system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 1011system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 1012system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16034 # number of LoadLockedReq accesses(hits+misses) 1013system.cpu.dcache.LoadLockedReq_accesses::total 16034 # number of LoadLockedReq accesses(hits+misses) 1014system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 1015system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 1016system.cpu.dcache.demand_accesses::cpu.data 46042326 # number of demand (read+write) accesses 1017system.cpu.dcache.demand_accesses::total 46042326 # number of demand (read+write) accesses 1018system.cpu.dcache.overall_accesses::cpu.data 46042326 # number of overall (read+write) accesses 1019system.cpu.dcache.overall_accesses::total 46042326 # number of overall (read+write) accesses 1020system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004759 # miss rate for ReadReq accesses 1021system.cpu.dcache.ReadReq_miss_rate::total 0.004759 # miss rate for ReadReq accesses 1022system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079711 # miss rate for WriteReq accesses 1023system.cpu.dcache.WriteReq_miss_rate::total 0.079711 # miss rate for WriteReq accesses 1024system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002557 # miss rate for LoadLockedReq accesses 1025system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002557 # miss rate for LoadLockedReq accesses 1026system.cpu.dcache.demand_miss_rate::cpu.data 0.037072 # miss rate for demand accesses 1027system.cpu.dcache.demand_miss_rate::total 0.037072 # miss rate for demand accesses 1028system.cpu.dcache.overall_miss_rate::cpu.data 0.037072 # miss rate for overall accesses 1029system.cpu.dcache.overall_miss_rate::total 0.037072 # miss rate for overall accesses 1030system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40773.746249 # average ReadReq miss latency 1031system.cpu.dcache.ReadReq_avg_miss_latency::total 40773.746249 # average ReadReq miss latency 1032system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78718.905714 # average WriteReq miss latency 1033system.cpu.dcache.WriteReq_avg_miss_latency::total 78718.905714 # average WriteReq miss latency 1034system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22371.951220 # average LoadLockedReq miss latency 1035system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22371.951220 # average LoadLockedReq miss latency 1036system.cpu.dcache.demand_avg_miss_latency::cpu.data 75947.883050 # average overall miss latency 1037system.cpu.dcache.demand_avg_miss_latency::total 75947.883050 # average overall miss latency 1038system.cpu.dcache.overall_avg_miss_latency::cpu.data 75947.883050 # average overall miss latency 1039system.cpu.dcache.overall_avg_miss_latency::total 75947.883050 # average overall miss latency 1040system.cpu.dcache.blocked_cycles::no_mshrs 3831 # number of cycles access was blocked 1041system.cpu.dcache.blocked_cycles::no_targets 1303 # number of cycles access was blocked 1042system.cpu.dcache.blocked::no_mshrs 134 # number of cycles access was blocked 1043system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked 1044system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.589552 # average number of cycles each access was blocked 1045system.cpu.dcache.avg_blocked_cycles::no_targets 81.437500 # average number of cycles each access was blocked 1046system.cpu.dcache.fast_writes 0 # number of fast writes performed 1047system.cpu.dcache.cache_copies 0 # number of cache copies performed 1048system.cpu.dcache.writebacks::writebacks 129165 # number of writebacks 1049system.cpu.dcache.writebacks::total 129165 # number of writebacks 1050system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69269 # number of ReadReq MSHR hits 1051system.cpu.dcache.ReadReq_mshr_hits::total 69269 # number of ReadReq MSHR hits 1052system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1474904 # number of WriteReq MSHR hits 1053system.cpu.dcache.WriteReq_mshr_hits::total 1474904 # number of WriteReq MSHR hits 1054system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits 1055system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits 1056system.cpu.dcache.demand_mshr_hits::cpu.data 1544173 # number of demand (read+write) MSHR hits 1057system.cpu.dcache.demand_mshr_hits::total 1544173 # number of demand (read+write) MSHR hits 1058system.cpu.dcache.overall_mshr_hits::cpu.data 1544173 # number of overall MSHR hits 1059system.cpu.dcache.overall_mshr_hits::total 1544173 # number of overall MSHR hits 1060system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55381 # number of ReadReq MSHR misses 1061system.cpu.dcache.ReadReq_mshr_misses::total 55381 # number of ReadReq MSHR misses 1062system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107348 # number of WriteReq MSHR misses 1063system.cpu.dcache.WriteReq_mshr_misses::total 107348 # number of WriteReq MSHR misses 1064system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses 1065system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses 1066system.cpu.dcache.demand_mshr_misses::cpu.data 162729 # number of demand (read+write) MSHR misses 1067system.cpu.dcache.demand_mshr_misses::total 162729 # number of demand (read+write) MSHR misses 1068system.cpu.dcache.overall_mshr_misses::cpu.data 162729 # number of overall MSHR misses 1069system.cpu.dcache.overall_mshr_misses::total 162729 # number of overall MSHR misses 1070system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2206437312 # number of ReadReq MSHR miss cycles 1071system.cpu.dcache.ReadReq_mshr_miss_latency::total 2206437312 # number of ReadReq MSHR miss cycles 1072system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8512084920 # number of WriteReq MSHR miss cycles 1073system.cpu.dcache.WriteReq_mshr_miss_latency::total 8512084920 # number of WriteReq MSHR miss cycles 1074system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 11500 # number of LoadLockedReq MSHR miss cycles 1075system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 11500 # number of LoadLockedReq MSHR miss cycles 1076system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10718522232 # number of demand (read+write) MSHR miss cycles 1077system.cpu.dcache.demand_mshr_miss_latency::total 10718522232 # number of demand (read+write) MSHR miss cycles 1078system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10718522232 # number of overall MSHR miss cycles 1079system.cpu.dcache.overall_mshr_miss_latency::total 10718522232 # number of overall MSHR miss cycles 1080system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002114 # mshr miss rate for ReadReq accesses 1081system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002114 # mshr miss rate for ReadReq accesses 1082system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses 1083system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses 1084system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.000062 # mshr miss rate for LoadLockedReq accesses 1085system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.000062 # mshr miss rate for LoadLockedReq accesses 1086system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003534 # mshr miss rate for demand accesses 1087system.cpu.dcache.demand_mshr_miss_rate::total 0.003534 # mshr miss rate for demand accesses 1088system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003534 # mshr miss rate for overall accesses 1089system.cpu.dcache.overall_mshr_miss_rate::total 0.003534 # mshr miss rate for overall accesses 1090system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39841.052202 # average ReadReq mshr miss latency 1091system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39841.052202 # average ReadReq mshr miss latency 1092system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79294.303760 # average WriteReq mshr miss latency 1093system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79294.303760 # average WriteReq mshr miss latency 1094system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11500 # average LoadLockedReq mshr miss latency 1095system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11500 # average LoadLockedReq mshr miss latency 1096system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65867.314566 # average overall mshr miss latency 1097system.cpu.dcache.demand_avg_mshr_miss_latency::total 65867.314566 # average overall mshr miss latency 1098system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65867.314566 # average overall mshr miss latency 1099system.cpu.dcache.overall_avg_mshr_miss_latency::total 65867.314566 # average overall mshr miss latency 1100system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1101 1102---------- End Simulation Statistics ----------	659system.cpu.cpi 0.751825 # CPI: Cycles Per Instruction 660system.cpu.cpi_total 0.751825 # CPI: Total CPI of All Threads 661system.cpu.ipc 1.330098 # IPC: Instructions Per Cycle 662system.cpu.ipc_total 1.330098 # IPC: Total IPC of All Threads 663system.cpu.int_regfile_reads 511631717 # number of integer regfile reads 664system.cpu.int_regfile_writes 103353872 # number of integer regfile writes 665system.cpu.fp_regfile_reads 846 # number of floating regfile reads 666system.cpu.fp_regfile_writes 710 # number of floating regfile writes 667system.cpu.misc_regfile_reads 49341635 # number of misc regfile reads 668system.cpu.misc_regfile_writes 31840 # number of misc regfile writes 669system.cpu.toL2Bus.throughput 775139386 # Throughput (bytes/s) 670system.cpu.toL2Bus.trans_dist::ReadReq 86625 # Transaction distribution 671system.cpu.toL2Bus.trans_dist::ReadResp 86624 # Transaction distribution 672system.cpu.toL2Bus.trans_dist::Writeback 129165 # Transaction distribution 673system.cpu.toL2Bus.trans_dist::UpgradeReq 335 # Transaction distribution 674system.cpu.toL2Bus.trans_dist::UpgradeResp 335 # Transaction distribution 675system.cpu.toL2Bus.trans_dist::ReadExReq 107045 # Transaction distribution 676system.cpu.toL2Bus.trans_dist::ReadExResp 107045 # Transaction distribution 677system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62039 # Packet count per connected master and slave (bytes) 678system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454624 # Packet count per connected master and slave (bytes) 679system.cpu.toL2Bus.pkt_count::total 516663 # Packet count per connected master and slave (bytes) 680system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1968896 # Cumulative packet size per connected master and slave (bytes) 681system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18659776 # Cumulative packet size per connected master and slave (bytes) 682system.cpu.toL2Bus.tot_pkt_size::total 20628672 # Cumulative packet size per connected master and slave (bytes) 683system.cpu.toL2Bus.data_through_bus 20628672 # Total data (bytes) 684system.cpu.toL2Bus.snoop_data_through_bus 32704 # Total snoop data (bytes) 685system.cpu.toL2Bus.reqLayer0.occupancy 290752497 # Layer occupancy (ticks) 686system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 687system.cpu.toL2Bus.respLayer0.occupancy 47657477 # Layer occupancy (ticks) 688system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 689system.cpu.toL2Bus.respLayer1.occupancy 267144007 # Layer occupancy (ticks) 690system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 691system.cpu.icache.tags.replacements 28917 # number of replacements 692system.cpu.icache.tags.tagsinuse 1807.865134 # Cycle average of tags in use 693system.cpu.icache.tags.total_refs 11650266 # Total number of references to valid blocks. 694system.cpu.icache.tags.sampled_refs 30950 # Sample count of references to valid blocks. 695system.cpu.icache.tags.avg_refs 376.422165 # Average number of references to valid blocks. 696system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 697system.cpu.icache.tags.occ_blocks::cpu.inst 1807.865134 # Average occupied blocks per requestor 698system.cpu.icache.tags.occ_percent::cpu.inst 0.882747 # Average percentage of cache occupancy 699system.cpu.icache.tags.occ_percent::total 0.882747 # Average percentage of cache occupancy 700system.cpu.icache.tags.occ_task_id_blocks::1024 2033 # Occupied blocks per task id 701system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 702system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 703system.cpu.icache.tags.age_task_id_blocks_1024::3 1259 # Occupied blocks per task id 704system.cpu.icache.tags.age_task_id_blocks_1024::4 672 # Occupied blocks per task id 705system.cpu.icache.tags.occ_task_id_percent::1024 0.992676 # Percentage of cache occupancy per task id 706system.cpu.icache.tags.tag_accesses 23402009 # Number of tag accesses 707system.cpu.icache.tags.data_accesses 23402009 # Number of data accesses 708system.cpu.icache.ReadReq_hits::cpu.inst 11650274 # number of ReadReq hits 709system.cpu.icache.ReadReq_hits::total 11650274 # number of ReadReq hits 710system.cpu.icache.demand_hits::cpu.inst 11650274 # number of demand (read+write) hits 711system.cpu.icache.demand_hits::total 11650274 # number of demand (read+write) hits 712system.cpu.icache.overall_hits::cpu.inst 11650274 # number of overall hits 713system.cpu.icache.overall_hits::total 11650274 # number of overall hits 714system.cpu.icache.ReadReq_misses::cpu.inst 35093 # number of ReadReq misses 715system.cpu.icache.ReadReq_misses::total 35093 # number of ReadReq misses 716system.cpu.icache.demand_misses::cpu.inst 35093 # number of demand (read+write) misses 717system.cpu.icache.demand_misses::total 35093 # number of demand (read+write) misses 718system.cpu.icache.overall_misses::cpu.inst 35093 # number of overall misses 719system.cpu.icache.overall_misses::total 35093 # number of overall misses 720system.cpu.icache.ReadReq_miss_latency::cpu.inst 796173972 # number of ReadReq miss cycles 721system.cpu.icache.ReadReq_miss_latency::total 796173972 # number of ReadReq miss cycles 722system.cpu.icache.demand_miss_latency::cpu.inst 796173972 # number of demand (read+write) miss cycles 723system.cpu.icache.demand_miss_latency::total 796173972 # number of demand (read+write) miss cycles 724system.cpu.icache.overall_miss_latency::cpu.inst 796173972 # number of overall miss cycles 725system.cpu.icache.overall_miss_latency::total 796173972 # number of overall miss cycles 726system.cpu.icache.ReadReq_accesses::cpu.inst 11685367 # number of ReadReq accesses(hits+misses) 727system.cpu.icache.ReadReq_accesses::total 11685367 # number of ReadReq accesses(hits+misses) 728system.cpu.icache.demand_accesses::cpu.inst 11685367 # number of demand (read+write) accesses 729system.cpu.icache.demand_accesses::total 11685367 # number of demand (read+write) accesses 730system.cpu.icache.overall_accesses::cpu.inst 11685367 # number of overall (read+write) accesses 731system.cpu.icache.overall_accesses::total 11685367 # number of overall (read+write) accesses 732system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003003 # miss rate for ReadReq accesses 733system.cpu.icache.ReadReq_miss_rate::total 0.003003 # miss rate for ReadReq accesses 734system.cpu.icache.demand_miss_rate::cpu.inst 0.003003 # miss rate for demand accesses 735system.cpu.icache.demand_miss_rate::total 0.003003 # miss rate for demand accesses 736system.cpu.icache.overall_miss_rate::cpu.inst 0.003003 # miss rate for overall accesses 737system.cpu.icache.overall_miss_rate::total 0.003003 # miss rate for overall accesses 738system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22687.543727 # average ReadReq miss latency 739system.cpu.icache.ReadReq_avg_miss_latency::total 22687.543727 # average ReadReq miss latency 740system.cpu.icache.demand_avg_miss_latency::cpu.inst 22687.543727 # average overall miss latency 741system.cpu.icache.demand_avg_miss_latency::total 22687.543727 # average overall miss latency 742system.cpu.icache.overall_avg_miss_latency::cpu.inst 22687.543727 # average overall miss latency 743system.cpu.icache.overall_avg_miss_latency::total 22687.543727 # average overall miss latency 744system.cpu.icache.blocked_cycles::no_mshrs 1584 # number of cycles access was blocked 745system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 746system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked 747system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 748system.cpu.icache.avg_blocked_cycles::no_mshrs 60.923077 # average number of cycles each access was blocked 749system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 750system.cpu.icache.fast_writes 0 # number of fast writes performed 751system.cpu.icache.cache_copies 0 # number of cache copies performed 752system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3818 # number of ReadReq MSHR hits 753system.cpu.icache.ReadReq_mshr_hits::total 3818 # number of ReadReq MSHR hits 754system.cpu.icache.demand_mshr_hits::cpu.inst 3818 # number of demand (read+write) MSHR hits 755system.cpu.icache.demand_mshr_hits::total 3818 # number of demand (read+write) MSHR hits 756system.cpu.icache.overall_mshr_hits::cpu.inst 3818 # number of overall MSHR hits 757system.cpu.icache.overall_mshr_hits::total 3818 # number of overall MSHR hits 758system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31275 # number of ReadReq MSHR misses 759system.cpu.icache.ReadReq_mshr_misses::total 31275 # number of ReadReq MSHR misses 760system.cpu.icache.demand_mshr_misses::cpu.inst 31275 # number of demand (read+write) MSHR misses 761system.cpu.icache.demand_mshr_misses::total 31275 # number of demand (read+write) MSHR misses 762system.cpu.icache.overall_mshr_misses::cpu.inst 31275 # number of overall MSHR misses 763system.cpu.icache.overall_mshr_misses::total 31275 # number of overall MSHR misses 764system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 647196022 # number of ReadReq MSHR miss cycles 765system.cpu.icache.ReadReq_mshr_miss_latency::total 647196022 # number of ReadReq MSHR miss cycles 766system.cpu.icache.demand_mshr_miss_latency::cpu.inst 647196022 # number of demand (read+write) MSHR miss cycles 767system.cpu.icache.demand_mshr_miss_latency::total 647196022 # number of demand (read+write) MSHR miss cycles 768system.cpu.icache.overall_mshr_miss_latency::cpu.inst 647196022 # number of overall MSHR miss cycles 769system.cpu.icache.overall_mshr_miss_latency::total 647196022 # number of overall MSHR miss cycles 770system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses 771system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses 772system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses 773system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses 774system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses 775system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses 776system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.717730 # average ReadReq mshr miss latency 777system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.717730 # average ReadReq mshr miss latency 778system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.717730 # average overall mshr miss latency 779system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.717730 # average overall mshr miss latency 780system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.717730 # average overall mshr miss latency 781system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.717730 # average overall mshr miss latency 782system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 783system.cpu.l2cache.tags.replacements 95645 # number of replacements 784system.cpu.l2cache.tags.tagsinuse 29867.639929 # Cycle average of tags in use 785system.cpu.l2cache.tags.total_refs 88414 # Total number of references to valid blocks. 786system.cpu.l2cache.tags.sampled_refs 126758 # Sample count of references to valid blocks. 787system.cpu.l2cache.tags.avg_refs 0.697502 # Average number of references to valid blocks. 788system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 789system.cpu.l2cache.tags.occ_blocks::writebacks 26665.630532 # Average occupied blocks per requestor 790system.cpu.l2cache.tags.occ_blocks::cpu.inst 1369.813019 # Average occupied blocks per requestor 791system.cpu.l2cache.tags.occ_blocks::cpu.data 1832.196377 # Average occupied blocks per requestor 792system.cpu.l2cache.tags.occ_percent::writebacks 0.813770 # Average percentage of cache occupancy 793system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041803 # Average percentage of cache occupancy 794system.cpu.l2cache.tags.occ_percent::cpu.data 0.055914 # Average percentage of cache occupancy 795system.cpu.l2cache.tags.occ_percent::total 0.911488 # Average percentage of cache occupancy 796system.cpu.l2cache.tags.occ_task_id_blocks::1024 31113 # Occupied blocks per task id 797system.cpu.l2cache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id 798system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1847 # Occupied blocks per task id 799system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20513 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8219 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id 802system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949493 # Percentage of cache occupancy per task id 803system.cpu.l2cache.tags.tag_accesses 2815092 # Number of tag accesses 804system.cpu.l2cache.tags.data_accesses 2815092 # Number of data accesses 805system.cpu.l2cache.ReadReq_hits::cpu.inst 26089 # number of ReadReq hits 806system.cpu.l2cache.ReadReq_hits::cpu.data 33429 # number of ReadReq hits 807system.cpu.l2cache.ReadReq_hits::total 59518 # number of ReadReq hits 808system.cpu.l2cache.Writeback_hits::writebacks 129165 # number of Writeback hits 809system.cpu.l2cache.Writeback_hits::total 129165 # number of Writeback hits 810system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits 811system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits 812system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # number of ReadExReq hits 813system.cpu.l2cache.ReadExReq_hits::total 4788 # number of ReadExReq hits 814system.cpu.l2cache.demand_hits::cpu.inst 26089 # number of demand (read+write) hits 815system.cpu.l2cache.demand_hits::cpu.data 38217 # number of demand (read+write) hits 816system.cpu.l2cache.demand_hits::total 64306 # number of demand (read+write) hits 817system.cpu.l2cache.overall_hits::cpu.inst 26089 # number of overall hits 818system.cpu.l2cache.overall_hits::cpu.data 38217 # number of overall hits 819system.cpu.l2cache.overall_hits::total 64306 # number of overall hits 820system.cpu.l2cache.ReadReq_misses::cpu.inst 4675 # number of ReadReq misses 821system.cpu.l2cache.ReadReq_misses::cpu.data 21921 # number of ReadReq misses 822system.cpu.l2cache.ReadReq_misses::total 26596 # number of ReadReq misses 823system.cpu.l2cache.UpgradeReq_misses::cpu.data 319 # number of UpgradeReq misses 824system.cpu.l2cache.UpgradeReq_misses::total 319 # number of UpgradeReq misses 825system.cpu.l2cache.ReadExReq_misses::cpu.data 102257 # number of ReadExReq misses 826system.cpu.l2cache.ReadExReq_misses::total 102257 # number of ReadExReq misses 827system.cpu.l2cache.demand_misses::cpu.inst 4675 # number of demand (read+write) misses 828system.cpu.l2cache.demand_misses::cpu.data 124178 # number of demand (read+write) misses 829system.cpu.l2cache.demand_misses::total 128853 # number of demand (read+write) misses 830system.cpu.l2cache.overall_misses::cpu.inst 4675 # number of overall misses 831system.cpu.l2cache.overall_misses::cpu.data 124178 # number of overall misses 832system.cpu.l2cache.overall_misses::total 128853 # number of overall misses 833system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 354274500 # number of ReadReq miss cycles 834system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1813961250 # number of ReadReq miss cycles 835system.cpu.l2cache.ReadReq_miss_latency::total 2168235750 # number of ReadReq miss cycles 836system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles 837system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles 838system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8348408999 # number of ReadExReq miss cycles 839system.cpu.l2cache.ReadExReq_miss_latency::total 8348408999 # number of ReadExReq miss cycles 840system.cpu.l2cache.demand_miss_latency::cpu.inst 354274500 # number of demand (read+write) miss cycles 841system.cpu.l2cache.demand_miss_latency::cpu.data 10162370249 # number of demand (read+write) miss cycles 842system.cpu.l2cache.demand_miss_latency::total 10516644749 # number of demand (read+write) miss cycles 843system.cpu.l2cache.overall_miss_latency::cpu.inst 354274500 # number of overall miss cycles 844system.cpu.l2cache.overall_miss_latency::cpu.data 10162370249 # number of overall miss cycles 845system.cpu.l2cache.overall_miss_latency::total 10516644749 # number of overall miss cycles 846system.cpu.l2cache.ReadReq_accesses::cpu.inst 30764 # number of ReadReq accesses(hits+misses) 847system.cpu.l2cache.ReadReq_accesses::cpu.data 55350 # number of ReadReq accesses(hits+misses) 848system.cpu.l2cache.ReadReq_accesses::total 86114 # number of ReadReq accesses(hits+misses) 849system.cpu.l2cache.Writeback_accesses::writebacks 129165 # number of Writeback accesses(hits+misses) 850system.cpu.l2cache.Writeback_accesses::total 129165 # number of Writeback accesses(hits+misses) 851system.cpu.l2cache.UpgradeReq_accesses::cpu.data 335 # number of UpgradeReq accesses(hits+misses) 852system.cpu.l2cache.UpgradeReq_accesses::total 335 # number of UpgradeReq accesses(hits+misses) 853system.cpu.l2cache.ReadExReq_accesses::cpu.data 107045 # number of ReadExReq accesses(hits+misses) 854system.cpu.l2cache.ReadExReq_accesses::total 107045 # number of ReadExReq accesses(hits+misses) 855system.cpu.l2cache.demand_accesses::cpu.inst 30764 # number of demand (read+write) accesses 856system.cpu.l2cache.demand_accesses::cpu.data 162395 # number of demand (read+write) accesses 857system.cpu.l2cache.demand_accesses::total 193159 # number of demand (read+write) accesses 858system.cpu.l2cache.overall_accesses::cpu.inst 30764 # number of overall (read+write) accesses 859system.cpu.l2cache.overall_accesses::cpu.data 162395 # number of overall (read+write) accesses 860system.cpu.l2cache.overall_accesses::total 193159 # number of overall (read+write) accesses 861system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.151963 # miss rate for ReadReq accesses 862system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.396043 # miss rate for ReadReq accesses 863system.cpu.l2cache.ReadReq_miss_rate::total 0.308846 # miss rate for ReadReq accesses 864system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.952239 # miss rate for UpgradeReq accesses 865system.cpu.l2cache.UpgradeReq_miss_rate::total 0.952239 # miss rate for UpgradeReq accesses 866system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955271 # miss rate for ReadExReq accesses 867system.cpu.l2cache.ReadExReq_miss_rate::total 0.955271 # miss rate for ReadExReq accesses 868system.cpu.l2cache.demand_miss_rate::cpu.inst 0.151963 # miss rate for demand accesses 869system.cpu.l2cache.demand_miss_rate::cpu.data 0.764666 # miss rate for demand accesses 870system.cpu.l2cache.demand_miss_rate::total 0.667083 # miss rate for demand accesses 871system.cpu.l2cache.overall_miss_rate::cpu.inst 0.151963 # miss rate for overall accesses 872system.cpu.l2cache.overall_miss_rate::cpu.data 0.764666 # miss rate for overall accesses 873system.cpu.l2cache.overall_miss_rate::total 0.667083 # miss rate for overall accesses 874system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75780.641711 # average ReadReq miss latency 875system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82749.931572 # average ReadReq miss latency 876system.cpu.l2cache.ReadReq_avg_miss_latency::total 81524.881561 # average ReadReq miss latency 877system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 72.097179 # average UpgradeReq miss latency 878system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 72.097179 # average UpgradeReq miss latency 879system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81641.442630 # average ReadExReq miss latency 880system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81641.442630 # average ReadExReq miss latency 881system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75780.641711 # average overall miss latency 882system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81837.122912 # average overall miss latency 883system.cpu.l2cache.demand_avg_miss_latency::total 81617.383755 # average overall miss latency 884system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75780.641711 # average overall miss latency 885system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81837.122912 # average overall miss latency 886system.cpu.l2cache.overall_avg_miss_latency::total 81617.383755 # average overall miss latency 887system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 888system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 889system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 890system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 891system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 892system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 893system.cpu.l2cache.fast_writes 0 # number of fast writes performed 894system.cpu.l2cache.cache_copies 0 # number of cache copies performed 895system.cpu.l2cache.writebacks::writebacks 83946 # number of writebacks 896system.cpu.l2cache.writebacks::total 83946 # number of writebacks 897system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits 898system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits 899system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits 900system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits 901system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits 902system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits 903system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits 904system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits 905system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits 906system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4659 # number of ReadReq MSHR misses 907system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21861 # number of ReadReq MSHR misses 908system.cpu.l2cache.ReadReq_mshr_misses::total 26520 # number of ReadReq MSHR misses 909system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 319 # number of UpgradeReq MSHR misses 910system.cpu.l2cache.UpgradeReq_mshr_misses::total 319 # number of UpgradeReq MSHR misses 911system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses 912system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses 913system.cpu.l2cache.demand_mshr_misses::cpu.inst 4659 # number of demand (read+write) MSHR misses 914system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses 915system.cpu.l2cache.demand_mshr_misses::total 128777 # number of demand (read+write) MSHR misses 916system.cpu.l2cache.overall_mshr_misses::cpu.inst 4659 # number of overall MSHR misses 917system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses 918system.cpu.l2cache.overall_mshr_misses::total 128777 # number of overall MSHR misses 919system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 294952000 # number of ReadReq MSHR miss cycles 920system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1536285750 # number of ReadReq MSHR miss cycles 921system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1831237750 # number of ReadReq MSHR miss cycles 922system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3196819 # number of UpgradeReq MSHR miss cycles 923system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3196819 # number of UpgradeReq MSHR miss cycles 924system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7058409501 # number of ReadExReq MSHR miss cycles 925system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7058409501 # number of ReadExReq MSHR miss cycles 926system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 294952000 # number of demand (read+write) MSHR miss cycles 927system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8594695251 # number of demand (read+write) MSHR miss cycles 928system.cpu.l2cache.demand_mshr_miss_latency::total 8889647251 # number of demand (read+write) MSHR miss cycles 929system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294952000 # number of overall MSHR miss cycles 930system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8594695251 # number of overall MSHR miss cycles 931system.cpu.l2cache.overall_mshr_miss_latency::total 8889647251 # number of overall MSHR miss cycles 932system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151443 # mshr miss rate for ReadReq accesses 933system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394959 # mshr miss rate for ReadReq accesses 934system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307964 # mshr miss rate for ReadReq accesses 935system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.952239 # mshr miss rate for UpgradeReq accesses 936system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.952239 # mshr miss rate for UpgradeReq accesses 937system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955271 # mshr miss rate for ReadExReq accesses 938system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955271 # mshr miss rate for ReadExReq accesses 939system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151443 # mshr miss rate for demand accesses 940system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764297 # mshr miss rate for demand accesses 941system.cpu.l2cache.demand_mshr_miss_rate::total 0.666689 # mshr miss rate for demand accesses 942system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151443 # mshr miss rate for overall accesses 943system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764297 # mshr miss rate for overall accesses 944system.cpu.l2cache.overall_mshr_miss_rate::total 0.666689 # mshr miss rate for overall accesses 945system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63308.006010 # average ReadReq mshr miss latency 946system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70275.181831 # average ReadReq mshr miss latency 947system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69051.197210 # average ReadReq mshr miss latency 948system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10021.376176 # average UpgradeReq mshr miss latency 949system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10021.376176 # average UpgradeReq mshr miss latency 950system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69026.174257 # average ReadExReq mshr miss latency 951system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69026.174257 # average ReadExReq mshr miss latency 952system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63308.006010 # average overall mshr miss latency 953system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69246.162934 # average overall mshr miss latency 954system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69031.327419 # average overall mshr miss latency 955system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63308.006010 # average overall mshr miss latency 956system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69246.162934 # average overall mshr miss latency 957system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69031.327419 # average overall mshr miss latency 958system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 959system.cpu.dcache.tags.replacements 158298 # number of replacements 960system.cpu.dcache.tags.tagsinuse 4068.579596 # Cycle average of tags in use 961system.cpu.dcache.tags.total_refs 44367951 # Total number of references to valid blocks. 962system.cpu.dcache.tags.sampled_refs 162394 # Sample count of references to valid blocks. 963system.cpu.dcache.tags.avg_refs 273.211763 # Average number of references to valid blocks. 964system.cpu.dcache.tags.warmup_cycle 366659250 # Cycle when the warmup percentage was hit. 965system.cpu.dcache.tags.occ_blocks::cpu.data 4068.579596 # Average occupied blocks per requestor 966system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy 967system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy 968system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 969system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id 970system.cpu.dcache.tags.age_task_id_blocks_1024::1 1762 # Occupied blocks per task id 971system.cpu.dcache.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id 972system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 973system.cpu.dcache.tags.tag_accesses 92310952 # Number of tag accesses 974system.cpu.dcache.tags.data_accesses 92310952 # Number of data accesses 975system.cpu.dcache.ReadReq_hits::cpu.data 26067775 # number of ReadReq hits 976system.cpu.dcache.ReadReq_hits::total 26067775 # number of ReadReq hits 977system.cpu.dcache.WriteReq_hits::cpu.data 18267649 # number of WriteReq hits 978system.cpu.dcache.WriteReq_hits::total 18267649 # number of WriteReq hits 979system.cpu.dcache.LoadLockedReq_hits::cpu.data 15993 # number of LoadLockedReq hits 980system.cpu.dcache.LoadLockedReq_hits::total 15993 # number of LoadLockedReq hits 981system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 982system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 983system.cpu.dcache.demand_hits::cpu.data 44335424 # number of demand (read+write) hits 984system.cpu.dcache.demand_hits::total 44335424 # number of demand (read+write) hits 985system.cpu.dcache.overall_hits::cpu.data 44335424 # number of overall hits 986system.cpu.dcache.overall_hits::total 44335424 # number of overall hits 987system.cpu.dcache.ReadReq_misses::cpu.data 124650 # number of ReadReq misses 988system.cpu.dcache.ReadReq_misses::total 124650 # number of ReadReq misses 989system.cpu.dcache.WriteReq_misses::cpu.data 1582252 # number of WriteReq misses 990system.cpu.dcache.WriteReq_misses::total 1582252 # number of WriteReq misses 991system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses 992system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses 993system.cpu.dcache.demand_misses::cpu.data 1706902 # number of demand (read+write) misses 994system.cpu.dcache.demand_misses::total 1706902 # number of demand (read+write) misses 995system.cpu.dcache.overall_misses::cpu.data 1706902 # number of overall misses 996system.cpu.dcache.overall_misses::total 1706902 # number of overall misses 997system.cpu.dcache.ReadReq_miss_latency::cpu.data 5082447470 # number of ReadReq miss cycles 998system.cpu.dcache.ReadReq_miss_latency::total 5082447470 # number of ReadReq miss cycles 999system.cpu.dcache.WriteReq_miss_latency::cpu.data 124553146004 # number of WriteReq miss cycles 1000system.cpu.dcache.WriteReq_miss_latency::total 124553146004 # number of WriteReq miss cycles 1001system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 917250 # number of LoadLockedReq miss cycles 1002system.cpu.dcache.LoadLockedReq_miss_latency::total 917250 # number of LoadLockedReq miss cycles 1003system.cpu.dcache.demand_miss_latency::cpu.data 129635593474 # number of demand (read+write) miss cycles 1004system.cpu.dcache.demand_miss_latency::total 129635593474 # number of demand (read+write) miss cycles 1005system.cpu.dcache.overall_miss_latency::cpu.data 129635593474 # number of overall miss cycles 1006system.cpu.dcache.overall_miss_latency::total 129635593474 # number of overall miss cycles 1007system.cpu.dcache.ReadReq_accesses::cpu.data 26192425 # number of ReadReq accesses(hits+misses) 1008system.cpu.dcache.ReadReq_accesses::total 26192425 # number of ReadReq accesses(hits+misses) 1009system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 1010system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 1011system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16034 # number of LoadLockedReq accesses(hits+misses) 1012system.cpu.dcache.LoadLockedReq_accesses::total 16034 # number of LoadLockedReq accesses(hits+misses) 1013system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 1014system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 1015system.cpu.dcache.demand_accesses::cpu.data 46042326 # number of demand (read+write) accesses 1016system.cpu.dcache.demand_accesses::total 46042326 # number of demand (read+write) accesses 1017system.cpu.dcache.overall_accesses::cpu.data 46042326 # number of overall (read+write) accesses 1018system.cpu.dcache.overall_accesses::total 46042326 # number of overall (read+write) accesses 1019system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004759 # miss rate for ReadReq accesses 1020system.cpu.dcache.ReadReq_miss_rate::total 0.004759 # miss rate for ReadReq accesses 1021system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079711 # miss rate for WriteReq accesses 1022system.cpu.dcache.WriteReq_miss_rate::total 0.079711 # miss rate for WriteReq accesses 1023system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002557 # miss rate for LoadLockedReq accesses 1024system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002557 # miss rate for LoadLockedReq accesses 1025system.cpu.dcache.demand_miss_rate::cpu.data 0.037072 # miss rate for demand accesses 1026system.cpu.dcache.demand_miss_rate::total 0.037072 # miss rate for demand accesses 1027system.cpu.dcache.overall_miss_rate::cpu.data 0.037072 # miss rate for overall accesses 1028system.cpu.dcache.overall_miss_rate::total 0.037072 # miss rate for overall accesses 1029system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40773.746249 # average ReadReq miss latency 1030system.cpu.dcache.ReadReq_avg_miss_latency::total 40773.746249 # average ReadReq miss latency 1031system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78718.905714 # average WriteReq miss latency 1032system.cpu.dcache.WriteReq_avg_miss_latency::total 78718.905714 # average WriteReq miss latency 1033system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22371.951220 # average LoadLockedReq miss latency 1034system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22371.951220 # average LoadLockedReq miss latency 1035system.cpu.dcache.demand_avg_miss_latency::cpu.data 75947.883050 # average overall miss latency 1036system.cpu.dcache.demand_avg_miss_latency::total 75947.883050 # average overall miss latency 1037system.cpu.dcache.overall_avg_miss_latency::cpu.data 75947.883050 # average overall miss latency 1038system.cpu.dcache.overall_avg_miss_latency::total 75947.883050 # average overall miss latency 1039system.cpu.dcache.blocked_cycles::no_mshrs 3831 # number of cycles access was blocked 1040system.cpu.dcache.blocked_cycles::no_targets 1303 # number of cycles access was blocked 1041system.cpu.dcache.blocked::no_mshrs 134 # number of cycles access was blocked 1042system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked 1043system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.589552 # average number of cycles each access was blocked 1044system.cpu.dcache.avg_blocked_cycles::no_targets 81.437500 # average number of cycles each access was blocked 1045system.cpu.dcache.fast_writes 0 # number of fast writes performed 1046system.cpu.dcache.cache_copies 0 # number of cache copies performed 1047system.cpu.dcache.writebacks::writebacks 129165 # number of writebacks 1048system.cpu.dcache.writebacks::total 129165 # number of writebacks 1049system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69269 # number of ReadReq MSHR hits 1050system.cpu.dcache.ReadReq_mshr_hits::total 69269 # number of ReadReq MSHR hits 1051system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1474904 # number of WriteReq MSHR hits 1052system.cpu.dcache.WriteReq_mshr_hits::total 1474904 # number of WriteReq MSHR hits 1053system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits 1054system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits 1055system.cpu.dcache.demand_mshr_hits::cpu.data 1544173 # number of demand (read+write) MSHR hits 1056system.cpu.dcache.demand_mshr_hits::total 1544173 # number of demand (read+write) MSHR hits 1057system.cpu.dcache.overall_mshr_hits::cpu.data 1544173 # number of overall MSHR hits 1058system.cpu.dcache.overall_mshr_hits::total 1544173 # number of overall MSHR hits 1059system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55381 # number of ReadReq MSHR misses 1060system.cpu.dcache.ReadReq_mshr_misses::total 55381 # number of ReadReq MSHR misses 1061system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107348 # number of WriteReq MSHR misses 1062system.cpu.dcache.WriteReq_mshr_misses::total 107348 # number of WriteReq MSHR misses 1063system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses 1064system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses 1065system.cpu.dcache.demand_mshr_misses::cpu.data 162729 # number of demand (read+write) MSHR misses 1066system.cpu.dcache.demand_mshr_misses::total 162729 # number of demand (read+write) MSHR misses 1067system.cpu.dcache.overall_mshr_misses::cpu.data 162729 # number of overall MSHR misses 1068system.cpu.dcache.overall_mshr_misses::total 162729 # number of overall MSHR misses 1069system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2206437312 # number of ReadReq MSHR miss cycles 1070system.cpu.dcache.ReadReq_mshr_miss_latency::total 2206437312 # number of ReadReq MSHR miss cycles 1071system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8512084920 # number of WriteReq MSHR miss cycles 1072system.cpu.dcache.WriteReq_mshr_miss_latency::total 8512084920 # number of WriteReq MSHR miss cycles 1073system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 11500 # number of LoadLockedReq MSHR miss cycles 1074system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 11500 # number of LoadLockedReq MSHR miss cycles 1075system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10718522232 # number of demand (read+write) MSHR miss cycles 1076system.cpu.dcache.demand_mshr_miss_latency::total 10718522232 # number of demand (read+write) MSHR miss cycles 1077system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10718522232 # number of overall MSHR miss cycles 1078system.cpu.dcache.overall_mshr_miss_latency::total 10718522232 # number of overall MSHR miss cycles 1079system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002114 # mshr miss rate for ReadReq accesses 1080system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002114 # mshr miss rate for ReadReq accesses 1081system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses 1082system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses 1083system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.000062 # mshr miss rate for LoadLockedReq accesses 1084system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.000062 # mshr miss rate for LoadLockedReq accesses 1085system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003534 # mshr miss rate for demand accesses 1086system.cpu.dcache.demand_mshr_miss_rate::total 0.003534 # mshr miss rate for demand accesses 1087system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003534 # mshr miss rate for overall accesses 1088system.cpu.dcache.overall_mshr_miss_rate::total 0.003534 # mshr miss rate for overall accesses 1089system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39841.052202 # average ReadReq mshr miss latency 1090system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39841.052202 # average ReadReq mshr miss latency 1091system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79294.303760 # average WriteReq mshr miss latency 1092system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79294.303760 # average WriteReq mshr miss latency 1093system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11500 # average LoadLockedReq mshr miss latency 1094system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11500 # average LoadLockedReq mshr miss latency 1095system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65867.314566 # average overall mshr miss latency 1096system.cpu.dcache.demand_avg_mshr_miss_latency::total 65867.314566 # average overall mshr miss latency 1097system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65867.314566 # average overall mshr miss latency 1098system.cpu.dcache.overall_avg_mshr_miss_latency::total 65867.314566 # average overall mshr miss latency 1099system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1100 1101---------- End Simulation Statistics ----------