1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.024561 # Number of seconds simulated
4sim_ticks 24560764000 # Number of ticks simulated
5final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 54926 # Simulator instruction rate (inst/s)
8host_op_rate 77943 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 19021903 # Simulator tick rate (ticks/s)
10host_mem_usage 240316 # Number of bytes of host memory used
11host_seconds 1291.18 # Real time elapsed on the host
12sim_insts 70920072 # Number of instructions simulated
13sim_ops 100639320 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 8687232 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 367552 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 5661632 # Number of bytes written to this memory
17system.physmem.num_reads 135738 # Number of read requests responded to by this memory
18system.physmem.num_writes 88463 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 353703655 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 14965007 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 230515305 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 584218960 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 332 unchanged lines hidden (view full) ---
364system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles
365system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses)
367system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses
368system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses
369system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses
370system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses
371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses
372system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses
373system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses
374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency
375system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
376system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
381system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
382system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
383system.cpu.icache.fast_writes 0 # number of fast writes performed
384system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
396system.cpu.icache.overall_mshr_misses::total 33634 # number of overall MSHR misses
397system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268782500 # number of ReadReq MSHR miss cycles
398system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles
399system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles
400system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles
401system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles
402system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles
403system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses
404system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses
405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses
406system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency
407system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
408system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
409system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
410system.cpu.dcache.replacements 158907 # number of replacements
411system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use
412system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks.
413system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks.
414system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks.
415system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit.
416system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor
--- 39 unchanged lines hidden (view full) ---
456system.cpu.dcache.LoadLockedReq_accesses::total 19679 # number of LoadLockedReq accesses(hits+misses)
457system.cpu.dcache.StoreCondReq_accesses::cpu.data 18406 # number of StoreCondReq accesses(hits+misses)
458system.cpu.dcache.StoreCondReq_accesses::total 18406 # number of StoreCondReq accesses(hits+misses)
459system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses
460system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses
461system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses
462system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses
463system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses
464system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses
465system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses
466system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses
467system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses
468system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency
469system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency
470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency
471system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
472system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
474system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
476system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
478system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked
479system.cpu.dcache.fast_writes 0 # number of fast writes performed
480system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 21 unchanged lines hidden (view full) ---
502system.cpu.dcache.ReadReq_mshr_miss_latency::total 1049489500 # number of ReadReq MSHR miss cycles
503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3666942000 # number of WriteReq MSHR miss cycles
504system.cpu.dcache.WriteReq_mshr_miss_latency::total 3666942000 # number of WriteReq MSHR miss cycles
505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4716431500 # number of demand (read+write) MSHR miss cycles
506system.cpu.dcache.demand_mshr_miss_latency::total 4716431500 # number of demand (read+write) MSHR miss cycles
507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4716431500 # number of overall MSHR miss cycles
508system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles
509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses
510system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses
511system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses
512system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses
513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency
514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency
515system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
516system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
517system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
518system.cpu.l2cache.replacements 115487 # number of replacements
519system.cpu.l2cache.tagsinuse 18346.494934 # Cycle average of tags in use
520system.cpu.l2cache.total_refs 78611 # Total number of references to valid blocks.
521system.cpu.l2cache.sampled_refs 134352 # Sample count of references to valid blocks.
522system.cpu.l2cache.avg_refs 0.585112 # Average number of references to valid blocks.
523system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
524system.cpu.l2cache.occ_blocks::writebacks 15851.533035 # Average occupied blocks per requestor
--- 56 unchanged lines hidden (view full) ---
581system.cpu.l2cache.demand_accesses::cpu.inst 33555 # number of demand (read+write) accesses
582system.cpu.l2cache.demand_accesses::cpu.data 163003 # number of demand (read+write) accesses
583system.cpu.l2cache.demand_accesses::total 196558 # number of demand (read+write) accesses
584system.cpu.l2cache.overall_accesses::cpu.inst 33555 # number of overall (read+write) accesses
585system.cpu.l2cache.overall_accesses::cpu.data 163003 # number of overall (read+write) accesses
586system.cpu.l2cache.overall_accesses::total 196558 # number of overall (read+write) accesses
587system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171927 # miss rate for ReadReq accesses
588system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.489855 # miss rate for ReadReq accesses
589system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.851351 # miss rate for UpgradeReq accesses
590system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959483 # miss rate for ReadExReq accesses
591system.cpu.l2cache.demand_miss_rate::cpu.inst 0.171927 # miss rate for demand accesses
592system.cpu.l2cache.demand_miss_rate::cpu.data 0.797899 # miss rate for demand accesses
593system.cpu.l2cache.overall_miss_rate::cpu.inst 0.171927 # miss rate for overall accesses
594system.cpu.l2cache.overall_miss_rate::cpu.data 0.797899 # miss rate for overall accesses
595system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34232.535968 # average ReadReq miss latency
596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34238.943690 # average ReadReq miss latency
597system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 547.619048 # average UpgradeReq miss latency
598system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.620761 # average ReadExReq miss latency
599system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
600system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
601system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
602system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
603system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
604system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
605system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
606system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
607system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
608system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
609system.cpu.l2cache.fast_writes 0 # number of fast writes performed
610system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 31 unchanged lines hidden (view full) ---
642system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178439000 # number of demand (read+write) MSHR miss cycles
643system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4047027000 # number of demand (read+write) MSHR miss cycles
644system.cpu.l2cache.demand_mshr_miss_latency::total 4225466000 # number of demand (read+write) MSHR miss cycles
645system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178439000 # number of overall MSHR miss cycles
646system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4047027000 # number of overall MSHR miss cycles
647system.cpu.l2cache.overall_mshr_miss_latency::total 4225466000 # number of overall MSHR miss cycles
648system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for ReadReq accesses
649system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488696 # mshr miss rate for ReadReq accesses
650system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.851351 # mshr miss rate for UpgradeReq accesses
651system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959483 # mshr miss rate for ReadExReq accesses
652system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for demand accesses
653system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for demand accesses
654system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for overall accesses
655system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for overall accesses
656system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759 # average ReadReq mshr miss latency
657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004 # average ReadReq mshr miss latency
658system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032 # average UpgradeReq mshr miss latency
659system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency
660system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
662system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
663system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
664system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
665
666---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.024561 # Number of seconds simulated
4sim_ticks 24560764000 # Number of ticks simulated
5final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 54926 # Simulator instruction rate (inst/s)
8host_op_rate 77943 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 19021903 # Simulator tick rate (ticks/s)
10host_mem_usage 240316 # Number of bytes of host memory used
11host_seconds 1291.18 # Real time elapsed on the host
12sim_insts 70920072 # Number of instructions simulated
13sim_ops 100639320 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 8687232 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 367552 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 5661632 # Number of bytes written to this memory
17system.physmem.num_reads 135738 # Number of read requests responded to by this memory
18system.physmem.num_writes 88463 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 353703655 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 14965007 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 230515305 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 584218960 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 332 unchanged lines hidden (view full) ---
364system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles
365system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses)
367system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses
368system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses
369system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses
370system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses
371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses
372system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses
373system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses
374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency
375system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
376system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
381system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
382system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
383system.cpu.icache.fast_writes 0 # number of fast writes performed
384system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
396system.cpu.icache.overall_mshr_misses::total 33634 # number of overall MSHR misses
397system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268782500 # number of ReadReq MSHR miss cycles
398system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles
399system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles
400system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles
401system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles
402system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles
403system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses
404system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses
405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses
406system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency
407system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
408system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
409system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
410system.cpu.dcache.replacements 158907 # number of replacements
411system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use
412system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks.
413system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks.
414system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks.
415system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit.
416system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor
--- 39 unchanged lines hidden (view full) ---
456system.cpu.dcache.LoadLockedReq_accesses::total 19679 # number of LoadLockedReq accesses(hits+misses)
457system.cpu.dcache.StoreCondReq_accesses::cpu.data 18406 # number of StoreCondReq accesses(hits+misses)
458system.cpu.dcache.StoreCondReq_accesses::total 18406 # number of StoreCondReq accesses(hits+misses)
459system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses
460system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses
461system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses
462system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses
463system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses
464system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses
465system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses
466system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses
467system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses
468system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency
469system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency
470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency
471system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
472system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
474system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
476system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
478system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked
479system.cpu.dcache.fast_writes 0 # number of fast writes performed
480system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 21 unchanged lines hidden (view full) ---
502system.cpu.dcache.ReadReq_mshr_miss_latency::total 1049489500 # number of ReadReq MSHR miss cycles
503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3666942000 # number of WriteReq MSHR miss cycles
504system.cpu.dcache.WriteReq_mshr_miss_latency::total 3666942000 # number of WriteReq MSHR miss cycles
505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4716431500 # number of demand (read+write) MSHR miss cycles
506system.cpu.dcache.demand_mshr_miss_latency::total 4716431500 # number of demand (read+write) MSHR miss cycles
507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4716431500 # number of overall MSHR miss cycles
508system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles
509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses
510system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses
511system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses
512system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses
513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency
514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency
515system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
516system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
517system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
518system.cpu.l2cache.replacements 115487 # number of replacements
519system.cpu.l2cache.tagsinuse 18346.494934 # Cycle average of tags in use
520system.cpu.l2cache.total_refs 78611 # Total number of references to valid blocks.
521system.cpu.l2cache.sampled_refs 134352 # Sample count of references to valid blocks.
522system.cpu.l2cache.avg_refs 0.585112 # Average number of references to valid blocks.
523system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
524system.cpu.l2cache.occ_blocks::writebacks 15851.533035 # Average occupied blocks per requestor
--- 56 unchanged lines hidden (view full) ---
581system.cpu.l2cache.demand_accesses::cpu.inst 33555 # number of demand (read+write) accesses
582system.cpu.l2cache.demand_accesses::cpu.data 163003 # number of demand (read+write) accesses
583system.cpu.l2cache.demand_accesses::total 196558 # number of demand (read+write) accesses
584system.cpu.l2cache.overall_accesses::cpu.inst 33555 # number of overall (read+write) accesses
585system.cpu.l2cache.overall_accesses::cpu.data 163003 # number of overall (read+write) accesses
586system.cpu.l2cache.overall_accesses::total 196558 # number of overall (read+write) accesses
587system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171927 # miss rate for ReadReq accesses
588system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.489855 # miss rate for ReadReq accesses
589system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.851351 # miss rate for UpgradeReq accesses
590system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959483 # miss rate for ReadExReq accesses
591system.cpu.l2cache.demand_miss_rate::cpu.inst 0.171927 # miss rate for demand accesses
592system.cpu.l2cache.demand_miss_rate::cpu.data 0.797899 # miss rate for demand accesses
593system.cpu.l2cache.overall_miss_rate::cpu.inst 0.171927 # miss rate for overall accesses
594system.cpu.l2cache.overall_miss_rate::cpu.data 0.797899 # miss rate for overall accesses
595system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34232.535968 # average ReadReq miss latency
596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34238.943690 # average ReadReq miss latency
597system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 547.619048 # average UpgradeReq miss latency
598system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.620761 # average ReadExReq miss latency
599system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
600system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
601system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
602system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
603system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
604system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
605system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
606system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
607system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
608system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
609system.cpu.l2cache.fast_writes 0 # number of fast writes performed
610system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 31 unchanged lines hidden (view full) ---
642system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178439000 # number of demand (read+write) MSHR miss cycles
643system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4047027000 # number of demand (read+write) MSHR miss cycles
644system.cpu.l2cache.demand_mshr_miss_latency::total 4225466000 # number of demand (read+write) MSHR miss cycles
645system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178439000 # number of overall MSHR miss cycles
646system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4047027000 # number of overall MSHR miss cycles
647system.cpu.l2cache.overall_mshr_miss_latency::total 4225466000 # number of overall MSHR miss cycles
648system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for ReadReq accesses
649system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488696 # mshr miss rate for ReadReq accesses
650system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.851351 # mshr miss rate for UpgradeReq accesses
651system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959483 # mshr miss rate for ReadExReq accesses
652system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for demand accesses
653system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for demand accesses
654system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for overall accesses
655system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for overall accesses
656system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759 # average ReadReq mshr miss latency
657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004 # average ReadReq mshr miss latency
658system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032 # average UpgradeReq mshr miss latency
659system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency
660system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
662system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
663system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
664system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
665
666---------- End Simulation Statistics ----------