1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.031189 # Number of seconds simulated
4sim_ticks 31189496500 # Number of ticks simulated
5final_tick 31189496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 144507 # Simulator instruction rate (inst/s)
8host_op_rate 205068 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 63556485 # Simulator tick rate (ticks/s)
10host_mem_usage 231932 # Number of bytes of host memory used
11host_seconds 490.74 # Real time elapsed on the host
12sim_insts 70914922 # Number of instructions simulated
13sim_ops 100634170 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 8651712 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 350080 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 5661248 # Number of bytes written to this memory
17system.physmem.num_reads 135183 # Number of read requests responded to by this memory
18system.physmem.num_writes 88457 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 277391846 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 11224291 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 181511362 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 458903208 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 27 unchanged lines hidden (view full) ---
59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
60system.cpu.itb.read_accesses 0 # DTB read accesses
61system.cpu.itb.write_accesses 0 # DTB write accesses
62system.cpu.itb.inst_accesses 0 # ITB inst accesses
63system.cpu.itb.hits 0 # DTB hits
64system.cpu.itb.misses 0 # DTB misses
65system.cpu.itb.accesses 0 # DTB accesses
66system.cpu.workload.num_syscalls 1946 # Number of system calls
67system.cpu.numCycles 62378994 # number of cpu cycles simulated
68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
70system.cpu.BPredUnit.lookups 17633191 # Number of BP lookups
71system.cpu.BPredUnit.condPredicted 11526968 # Number of conditional branches predicted
72system.cpu.BPredUnit.condIncorrect 822695 # Number of conditional branches incorrect
73system.cpu.BPredUnit.BTBLookups 15043788 # Number of BTB lookups
74system.cpu.BPredUnit.BTBHits 9743985 # Number of BTB hits
75system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
76system.cpu.BPredUnit.usedRAS 1887457 # Number of times the RAS was used to get a target.
77system.cpu.BPredUnit.RASInCorrect 176874 # Number of incorrect RAS predictions.
78system.cpu.fetch.icacheStallCycles 12969342 # Number of cycles fetch is stalled on an Icache miss
79system.cpu.fetch.Insts 88531281 # Number of instructions fetch has processed
80system.cpu.fetch.Branches 17633191 # Number of branches that fetch encountered
81system.cpu.fetch.predictedBranches 11631442 # Number of branches that fetch has predicted taken
82system.cpu.fetch.Cycles 22985471 # Number of cycles fetch has run and was not squashing or blocked
83system.cpu.fetch.SquashCycles 2899094 # Number of cycles fetch has spent squashing
84system.cpu.fetch.BlockedCycles 23117489 # Number of cycles fetch has spent blocked
85system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
86system.cpu.fetch.PendingTrapStallCycles 528 # Number of stall cycles due to pending traps
87system.cpu.fetch.CacheLines 12209631 # Number of cache lines fetched
88system.cpu.fetch.IcacheSquashes 231060 # Number of outstanding Icache misses that were squashed
89system.cpu.fetch.rateDist::samples 61072156 # Number of instructions fetched each cycle (Total)
90system.cpu.fetch.rateDist::mean 2.021104 # Number of instructions fetched each cycle (Total)
91system.cpu.fetch.rateDist::stdev 3.077628 # Number of instructions fetched each cycle (Total)
92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
93system.cpu.fetch.rateDist::0 38102442 62.39% 62.39% # Number of instructions fetched each cycle (Total)
94system.cpu.fetch.rateDist::1 2437370 3.99% 66.38% # Number of instructions fetched each cycle (Total)
95system.cpu.fetch.rateDist::2 2604913 4.27% 70.65% # Number of instructions fetched each cycle (Total)
96system.cpu.fetch.rateDist::3 2468790 4.04% 74.69% # Number of instructions fetched each cycle (Total)
97system.cpu.fetch.rateDist::4 1717886 2.81% 77.50% # Number of instructions fetched each cycle (Total)
98system.cpu.fetch.rateDist::5 1703957 2.79% 80.29% # Number of instructions fetched each cycle (Total)
99system.cpu.fetch.rateDist::6 1004465 1.64% 81.94% # Number of instructions fetched each cycle (Total)
100system.cpu.fetch.rateDist::7 1297144 2.12% 84.06% # Number of instructions fetched each cycle (Total)
101system.cpu.fetch.rateDist::8 9735189 15.94% 100.00% # Number of instructions fetched each cycle (Total)
102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
105system.cpu.fetch.rateDist::total 61072156 # Number of instructions fetched each cycle (Total)
106system.cpu.fetch.branchRate 0.282678 # Number of branch fetches per cycle
107system.cpu.fetch.rate 1.419248 # Number of inst fetches per cycle
108system.cpu.decode.IdleCycles 14874533 # Number of cycles decode is idle
109system.cpu.decode.BlockedCycles 21847562 # Number of cycles decode is blocked
110system.cpu.decode.RunCycles 21380234 # Number of cycles decode is running
111system.cpu.decode.UnblockCycles 1066852 # Number of cycles decode is unblocking
112system.cpu.decode.SquashCycles 1902975 # Number of cycles decode is squashing
113system.cpu.decode.BranchResolved 3467400 # Number of times decode resolved a branch
114system.cpu.decode.BranchMispred 97940 # Number of times decode detected a branch misprediction
115system.cpu.decode.DecodedInsts 120324997 # Number of instructions handled by decode
116system.cpu.decode.SquashedInsts 332105 # Number of squashed instructions handled by decode
117system.cpu.rename.SquashCycles 1902975 # Number of cycles rename is squashing
118system.cpu.rename.IdleCycles 16806585 # Number of cycles rename is idle
119system.cpu.rename.BlockCycles 2006065 # Number of cycles rename is blocking
120system.cpu.rename.serializeStallCycles 15518837 # count of cycles rename stalled for serializing inst
121system.cpu.rename.RunCycles 20487124 # Number of cycles rename is running
122system.cpu.rename.UnblockCycles 4350570 # Number of cycles rename is unblocking
123system.cpu.rename.RenamedInsts 117025506 # Number of instructions processed by rename
124system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full
125system.cpu.rename.IQFullEvents 3620 # Number of times rename has blocked due to IQ full
126system.cpu.rename.LSQFullEvents 3001536 # Number of times rename has blocked due to LSQ full
127system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers
128system.cpu.rename.RenamedOperands 118973415 # Number of destination operands rename has renamed
129system.cpu.rename.RenameLookups 538271633 # Number of register rename lookups that rename has made
130system.cpu.rename.int_rename_lookups 538269997 # Number of integer rename lookups
131system.cpu.rename.fp_rename_lookups 1636 # Number of floating rename lookups
132system.cpu.rename.CommittedMaps 99144341 # Number of HB maps that are committed
133system.cpu.rename.UndoneMaps 19829074 # Number of HB maps that are undone due to squashing
134system.cpu.rename.serializingInsts 778296 # count of serializing insts renamed
135system.cpu.rename.tempSerializingInsts 778691 # count of temporary serializing insts renamed
136system.cpu.rename.skidInsts 12144889 # count of insts added to the skid buffer
137system.cpu.memDep0.insertedLoads 29749506 # Number of loads inserted to the mem dependence unit.
138system.cpu.memDep0.insertedStores 22307130 # Number of stores inserted to the mem dependence unit.
139system.cpu.memDep0.conflictingLoads 2475389 # Number of conflicting loads.
140system.cpu.memDep0.conflictingStores 3455641 # Number of conflicting stores.
141system.cpu.iq.iqInstsAdded 111742619 # Number of instructions added to the IQ (excludes non-spec)
142system.cpu.iq.iqNonSpecInstsAdded 774376 # Number of non-speculative instructions added to the IQ
143system.cpu.iq.iqInstsIssued 107620542 # Number of instructions issued
144system.cpu.iq.iqSquashedInstsIssued 306039 # Number of squashed instructions issued
145system.cpu.iq.iqSquashedInstsExamined 11663320 # Number of squashed instructions iterated over during squash; mainly for profiling
146system.cpu.iq.iqSquashedOperandsExamined 29339036 # Number of squashed operands that are examined and possibly removed from graph
147system.cpu.iq.iqSquashedNonSpecRemoved 71343 # Number of squashed non-spec instructions that were removed
148system.cpu.iq.issued_per_cycle::samples 61072156 # Number of insts issued each cycle
149system.cpu.iq.issued_per_cycle::mean 1.762187 # Number of insts issued each cycle
150system.cpu.iq.issued_per_cycle::stdev 1.902803 # Number of insts issued each cycle
151system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
152system.cpu.iq.issued_per_cycle::0 22164835 36.29% 36.29% # Number of insts issued each cycle
153system.cpu.iq.issued_per_cycle::1 11626045 19.04% 55.33% # Number of insts issued each cycle
154system.cpu.iq.issued_per_cycle::2 8572984 14.04% 69.37% # Number of insts issued each cycle
155system.cpu.iq.issued_per_cycle::3 7394656 12.11% 81.47% # Number of insts issued each cycle
156system.cpu.iq.issued_per_cycle::4 4788181 7.84% 89.32% # Number of insts issued each cycle
157system.cpu.iq.issued_per_cycle::5 3517678 5.76% 95.08% # Number of insts issued each cycle
158system.cpu.iq.issued_per_cycle::6 1664983 2.73% 97.80% # Number of insts issued each cycle
159system.cpu.iq.issued_per_cycle::7 808803 1.32% 99.13% # Number of insts issued each cycle
160system.cpu.iq.issued_per_cycle::8 533991 0.87% 100.00% # Number of insts issued each cycle
161system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
162system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
163system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
164system.cpu.iq.issued_per_cycle::total 61072156 # Number of insts issued each cycle
165system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
166system.cpu.iq.fu_full::IntAlu 87531 3.32% 3.32% # attempts to use FU when none available
167system.cpu.iq.fu_full::IntMult 0 0.00% 3.32% # attempts to use FU when none available
168system.cpu.iq.fu_full::IntDiv 0 0.00% 3.32% # attempts to use FU when none available
169system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.32% # attempts to use FU when none available
170system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.32% # attempts to use FU when none available
171system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.32% # attempts to use FU when none available
172system.cpu.iq.fu_full::FloatMult 0 0.00% 3.32% # attempts to use FU when none available
173system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.32% # attempts to use FU when none available
174system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.32% # attempts to use FU when none available
175system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.32% # attempts to use FU when none available
176system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.32% # attempts to use FU when none available
177system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.32% # attempts to use FU when none available
178system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.32% # attempts to use FU when none available
179system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.32% # attempts to use FU when none available
180system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.32% # attempts to use FU when none available
181system.cpu.iq.fu_full::SimdMult 0 0.00% 3.32% # attempts to use FU when none available
182system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.32% # attempts to use FU when none available
183system.cpu.iq.fu_full::SimdShift 0 0.00% 3.32% # attempts to use FU when none available
184system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.32% # attempts to use FU when none available
185system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.32% # attempts to use FU when none available
186system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.32% # attempts to use FU when none available
187system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.32% # attempts to use FU when none available
188system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.32% # attempts to use FU when none available
189system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.32% # attempts to use FU when none available
190system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.32% # attempts to use FU when none available
191system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.32% # attempts to use FU when none available
192system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.32% # attempts to use FU when none available
193system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.32% # attempts to use FU when none available
194system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.32% # attempts to use FU when none available
195system.cpu.iq.fu_full::MemRead 1485029 56.34% 59.66% # attempts to use FU when none available
196system.cpu.iq.fu_full::MemWrite 1063128 40.34% 100.00% # attempts to use FU when none available
197system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
198system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
199system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
200system.cpu.iq.FU_type_0::IntAlu 57005331 52.97% 52.97% # Type of FU issued
201system.cpu.iq.FU_type_0::IntMult 87377 0.08% 53.05% # Type of FU issued
202system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued
203system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 53.05% # Type of FU issued
204system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued
205system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued
206system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued
207system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.05% # Type of FU issued
208system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.05% # Type of FU issued
209system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.05% # Type of FU issued
210system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.05% # Type of FU issued
211system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.05% # Type of FU issued
212system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.05% # Type of FU issued
213system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.05% # Type of FU issued
214system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.05% # Type of FU issued
215system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.05% # Type of FU issued
216system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.05% # Type of FU issued
217system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.05% # Type of FU issued
218system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.05% # Type of FU issued
219system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.05% # Type of FU issued
220system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.05% # Type of FU issued
221system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.05% # Type of FU issued
222system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.05% # Type of FU issued
223system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.05% # Type of FU issued
224system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.05% # Type of FU issued
225system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.05% # Type of FU issued
226system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued
227system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued
228system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued
229system.cpu.iq.FU_type_0::MemRead 28993103 26.94% 79.99% # Type of FU issued
230system.cpu.iq.FU_type_0::MemWrite 21534684 20.01% 100.00% # Type of FU issued
231system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
232system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
233system.cpu.iq.FU_type_0::total 107620542 # Type of FU issued
234system.cpu.iq.rate 1.725269 # Inst issue rate
235system.cpu.iq.fu_busy_cnt 2635688 # FU busy when requested
236system.cpu.iq.fu_busy_rate 0.024491 # FU busy rate (busy events/executed inst)
237system.cpu.iq.int_inst_queue_reads 279254757 # Number of integer instruction queue reads
238system.cpu.iq.int_inst_queue_writes 124195436 # Number of integer instruction queue writes
239system.cpu.iq.int_inst_queue_wakeup_accesses 105415832 # Number of integer instruction queue wakeup accesses
240system.cpu.iq.fp_inst_queue_reads 210 # Number of floating instruction queue reads
241system.cpu.iq.fp_inst_queue_writes 218 # Number of floating instruction queue writes
242system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses
243system.cpu.iq.int_alu_accesses 110256122 # Number of integer alu accesses
244system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses
245system.cpu.iew.lsq.thread0.forwLoads 1866930 # Number of loads that had data forwarded from stores
246system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
247system.cpu.iew.lsq.thread0.squashedLoads 2440940 # Number of loads squashed
248system.cpu.iew.lsq.thread0.ignoredResponses 3458 # Number of memory responses ignored because the instruction is squashed
249system.cpu.iew.lsq.thread0.memOrderViolation 15970 # Number of memory ordering violations
250system.cpu.iew.lsq.thread0.squashedStores 1749935 # Number of stores squashed
251system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
252system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
253system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled
254system.cpu.iew.lsq.thread0.cacheBlocked 52 # Number of times an access to memory failed due to the cache being blocked
255system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
256system.cpu.iew.iewSquashCycles 1902975 # Number of cycles IEW is squashing
257system.cpu.iew.iewBlockCycles 953135 # Number of cycles IEW is blocking
258system.cpu.iew.iewUnblockCycles 28579 # Number of cycles IEW is unblocking
259system.cpu.iew.iewDispatchedInsts 112593446 # Number of instructions dispatched to IQ
260system.cpu.iew.iewDispSquashedInsts 617881 # Number of squashed instructions skipped by dispatch
261system.cpu.iew.iewDispLoadInsts 29749506 # Number of dispatched load instructions
262system.cpu.iew.iewDispStoreInsts 22307130 # Number of dispatched store instructions
263system.cpu.iew.iewDispNonSpecInsts 757118 # Number of dispatched non-speculative instructions
264system.cpu.iew.iewIQFullEvents 1133 # Number of times the IQ has become full, causing a stall
265system.cpu.iew.iewLSQFullEvents 1194 # Number of times the LSQ has become full, causing a stall
266system.cpu.iew.memOrderViolationEvents 15970 # Number of memory order violations
267system.cpu.iew.predictedTakenIncorrect 682654 # Number of branches that were predicted taken incorrectly
268system.cpu.iew.predictedNotTakenIncorrect 198883 # Number of branches that were predicted not taken incorrectly
269system.cpu.iew.branchMispredicts 881537 # Number of branch mispredicts detected at execute
270system.cpu.iew.iewExecutedInsts 106278016 # Number of executed instructions
271system.cpu.iew.iewExecLoadInsts 28622846 # Number of load instructions executed
272system.cpu.iew.iewExecSquashedInsts 1342526 # Number of squashed instructions skipped in execute
273system.cpu.iew.exec_swp 0 # number of swp insts executed
274system.cpu.iew.exec_nop 76451 # number of nop insts executed
275system.cpu.iew.exec_refs 49854993 # number of memory reference insts executed
276system.cpu.iew.exec_branches 14601868 # Number of branches executed
277system.cpu.iew.exec_stores 21232147 # Number of stores executed
278system.cpu.iew.exec_rate 1.703747 # Inst execution rate
279system.cpu.iew.wb_sent 105729046 # cumulative count of insts sent to commit
280system.cpu.iew.wb_count 105415908 # cumulative count of insts written-back
281system.cpu.iew.wb_producers 52516965 # num instructions producing a value
282system.cpu.iew.wb_consumers 101175097 # num instructions consuming a value
283system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
284system.cpu.iew.wb_rate 1.689926 # insts written-back per cycle
285system.cpu.iew.wb_fanout 0.519070 # average fanout of values written-back
286system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
287system.cpu.commit.commitCommittedInsts 70920474 # The number of committed instructions
288system.cpu.commit.commitCommittedOps 100639722 # The number of committed instructions
289system.cpu.commit.commitSquashedInsts 11954174 # The number of squashed insts skipped by commit
290system.cpu.commit.commitNonSpecStalls 703033 # The number of times commit has been forced to stall to communicate backwards
291system.cpu.commit.branchMispredicts 788567 # The number of times a branch was mispredicted
292system.cpu.commit.committed_per_cycle::samples 59169182 # Number of insts commited each cycle
293system.cpu.commit.committed_per_cycle::mean 1.700881 # Number of insts commited each cycle
294system.cpu.commit.committed_per_cycle::stdev 2.430495 # Number of insts commited each cycle
295system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
296system.cpu.commit.committed_per_cycle::0 26246833 44.36% 44.36% # Number of insts commited each cycle
297system.cpu.commit.committed_per_cycle::1 14645427 24.75% 69.11% # Number of insts commited each cycle
298system.cpu.commit.committed_per_cycle::2 4228470 7.15% 76.26% # Number of insts commited each cycle
299system.cpu.commit.committed_per_cycle::3 3643076 6.16% 82.41% # Number of insts commited each cycle
300system.cpu.commit.committed_per_cycle::4 2266929 3.83% 86.25% # Number of insts commited each cycle
301system.cpu.commit.committed_per_cycle::5 1888235 3.19% 89.44% # Number of insts commited each cycle
302system.cpu.commit.committed_per_cycle::6 703093 1.19% 90.62% # Number of insts commited each cycle
303system.cpu.commit.committed_per_cycle::7 496274 0.84% 91.46% # Number of insts commited each cycle
304system.cpu.commit.committed_per_cycle::8 5050845 8.54% 100.00% # Number of insts commited each cycle
305system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
306system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
307system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
308system.cpu.commit.committed_per_cycle::total 59169182 # Number of insts commited each cycle
309system.cpu.commit.committedInsts 70920474 # Number of instructions committed
310system.cpu.commit.committedOps 100639722 # Number of ops (including micro ops) committed
311system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
312system.cpu.commit.refs 47865761 # Number of memory references committed
313system.cpu.commit.loads 27308566 # Number of loads committed
314system.cpu.commit.membars 15920 # Number of memory barriers committed
315system.cpu.commit.branches 13670085 # Number of branches committed
316system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
317system.cpu.commit.int_insts 91478615 # Number of committed integer instructions.
318system.cpu.commit.function_calls 1679850 # Number of function calls committed.
319system.cpu.commit.bw_lim_events 5050845 # number cycles where commit BW limit reached
320system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
321system.cpu.rob.rob_reads 166686934 # The number of ROB reads
322system.cpu.rob.rob_writes 227096473 # The number of ROB writes
323system.cpu.timesIdled 61617 # Number of times that the entire CPU went into an idle state and unscheduled itself
324system.cpu.idleCycles 1306838 # Total number of cycles that the CPU has spent unscheduled due to idling
325system.cpu.committedInsts 70914922 # Number of Instructions Simulated
326system.cpu.committedOps 100634170 # Number of Ops (including micro ops) Simulated
327system.cpu.committedInsts_total 70914922 # Number of Instructions Simulated
328system.cpu.cpi 0.879631 # CPI: Cycles Per Instruction
329system.cpu.cpi_total 0.879631 # CPI: Total CPI of All Threads
330system.cpu.ipc 1.136840 # IPC: Instructions Per Cycle
331system.cpu.ipc_total 1.136840 # IPC: Total IPC of All Threads
332system.cpu.int_regfile_reads 511674990 # number of integer regfile reads
333system.cpu.int_regfile_writes 103897673 # number of integer regfile writes
334system.cpu.fp_regfile_reads 166 # number of floating regfile reads
335system.cpu.fp_regfile_writes 126 # number of floating regfile writes
336system.cpu.misc_regfile_reads 146219619 # number of misc regfile reads
337system.cpu.misc_regfile_writes 34754 # number of misc regfile writes
338system.cpu.icache.replacements 26131 # number of replacements
339system.cpu.icache.tagsinuse 1805.600642 # Cycle average of tags in use
340system.cpu.icache.total_refs 12180358 # Total number of references to valid blocks.
341system.cpu.icache.sampled_refs 28166 # Sample count of references to valid blocks.
342system.cpu.icache.avg_refs 432.448981 # Average number of references to valid blocks.
343system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
344system.cpu.icache.occ_blocks::cpu.inst 1805.600642 # Average occupied blocks per requestor
345system.cpu.icache.occ_percent::cpu.inst 0.881641 # Average percentage of cache occupancy
346system.cpu.icache.occ_percent::total 0.881641 # Average percentage of cache occupancy
347system.cpu.icache.ReadReq_hits::cpu.inst 12180359 # number of ReadReq hits
348system.cpu.icache.ReadReq_hits::total 12180359 # number of ReadReq hits
349system.cpu.icache.demand_hits::cpu.inst 12180359 # number of demand (read+write) hits
350system.cpu.icache.demand_hits::total 12180359 # number of demand (read+write) hits
351system.cpu.icache.overall_hits::cpu.inst 12180359 # number of overall hits
352system.cpu.icache.overall_hits::total 12180359 # number of overall hits
353system.cpu.icache.ReadReq_misses::cpu.inst 29272 # number of ReadReq misses
354system.cpu.icache.ReadReq_misses::total 29272 # number of ReadReq misses
355system.cpu.icache.demand_misses::cpu.inst 29272 # number of demand (read+write) misses
356system.cpu.icache.demand_misses::total 29272 # number of demand (read+write) misses
357system.cpu.icache.overall_misses::cpu.inst 29272 # number of overall misses
358system.cpu.icache.overall_misses::total 29272 # number of overall misses
359system.cpu.icache.ReadReq_miss_latency::cpu.inst 357988500 # number of ReadReq miss cycles
360system.cpu.icache.ReadReq_miss_latency::total 357988500 # number of ReadReq miss cycles
361system.cpu.icache.demand_miss_latency::cpu.inst 357988500 # number of demand (read+write) miss cycles
362system.cpu.icache.demand_miss_latency::total 357988500 # number of demand (read+write) miss cycles
363system.cpu.icache.overall_miss_latency::cpu.inst 357988500 # number of overall miss cycles
364system.cpu.icache.overall_miss_latency::total 357988500 # number of overall miss cycles
365system.cpu.icache.ReadReq_accesses::cpu.inst 12209631 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.ReadReq_accesses::total 12209631 # number of ReadReq accesses(hits+misses)
367system.cpu.icache.demand_accesses::cpu.inst 12209631 # number of demand (read+write) accesses
368system.cpu.icache.demand_accesses::total 12209631 # number of demand (read+write) accesses
369system.cpu.icache.overall_accesses::cpu.inst 12209631 # number of overall (read+write) accesses
370system.cpu.icache.overall_accesses::total 12209631 # number of overall (read+write) accesses
371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002397 # miss rate for ReadReq accesses
372system.cpu.icache.demand_miss_rate::cpu.inst 0.002397 # miss rate for demand accesses
373system.cpu.icache.overall_miss_rate::cpu.inst 0.002397 # miss rate for overall accesses
374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12229.724652 # average ReadReq miss latency
375system.cpu.icache.demand_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency
376system.cpu.icache.overall_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency
377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
381system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
382system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
383system.cpu.icache.fast_writes 0 # number of fast writes performed
384system.cpu.icache.cache_copies 0 # number of cache copies performed
385system.cpu.icache.writebacks::writebacks 1 # number of writebacks
386system.cpu.icache.writebacks::total 1 # number of writebacks
387system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1063 # number of ReadReq MSHR hits
388system.cpu.icache.ReadReq_mshr_hits::total 1063 # number of ReadReq MSHR hits
389system.cpu.icache.demand_mshr_hits::cpu.inst 1063 # number of demand (read+write) MSHR hits
390system.cpu.icache.demand_mshr_hits::total 1063 # number of demand (read+write) MSHR hits
391system.cpu.icache.overall_mshr_hits::cpu.inst 1063 # number of overall MSHR hits
392system.cpu.icache.overall_mshr_hits::total 1063 # number of overall MSHR hits
393system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28209 # number of ReadReq MSHR misses
394system.cpu.icache.ReadReq_mshr_misses::total 28209 # number of ReadReq MSHR misses
395system.cpu.icache.demand_mshr_misses::cpu.inst 28209 # number of demand (read+write) MSHR misses
396system.cpu.icache.demand_mshr_misses::total 28209 # number of demand (read+write) MSHR misses
397system.cpu.icache.overall_mshr_misses::cpu.inst 28209 # number of overall MSHR misses
398system.cpu.icache.overall_mshr_misses::total 28209 # number of overall MSHR misses
399system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 247071500 # number of ReadReq MSHR miss cycles
400system.cpu.icache.ReadReq_mshr_miss_latency::total 247071500 # number of ReadReq MSHR miss cycles
401system.cpu.icache.demand_mshr_miss_latency::cpu.inst 247071500 # number of demand (read+write) MSHR miss cycles
402system.cpu.icache.demand_mshr_miss_latency::total 247071500 # number of demand (read+write) MSHR miss cycles
403system.cpu.icache.overall_mshr_miss_latency::cpu.inst 247071500 # number of overall MSHR miss cycles
404system.cpu.icache.overall_mshr_miss_latency::total 247071500 # number of overall MSHR miss cycles
405system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for ReadReq accesses
406system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for demand accesses
407system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for overall accesses
408system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8758.605410 # average ReadReq mshr miss latency
409system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency
410system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency
411system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
412system.cpu.dcache.replacements 157892 # number of replacements
413system.cpu.dcache.tagsinuse 4072.334227 # Cycle average of tags in use
414system.cpu.dcache.total_refs 44746410 # Total number of references to valid blocks.
415system.cpu.dcache.sampled_refs 161988 # Sample count of references to valid blocks.
416system.cpu.dcache.avg_refs 276.232869 # Average number of references to valid blocks.
417system.cpu.dcache.warmup_cycle 306594000 # Cycle when the warmup percentage was hit.
418system.cpu.dcache.occ_blocks::cpu.data 4072.334227 # Average occupied blocks per requestor
419system.cpu.dcache.occ_percent::cpu.data 0.994222 # Average percentage of cache occupancy
420system.cpu.dcache.occ_percent::total 0.994222 # Average percentage of cache occupancy
421system.cpu.dcache.ReadReq_hits::cpu.data 26399659 # number of ReadReq hits
422system.cpu.dcache.ReadReq_hits::total 26399659 # number of ReadReq hits
423system.cpu.dcache.WriteReq_hits::cpu.data 18310286 # number of WriteReq hits
424system.cpu.dcache.WriteReq_hits::total 18310286 # number of WriteReq hits
425system.cpu.dcache.LoadLockedReq_hits::cpu.data 18924 # number of LoadLockedReq hits
426system.cpu.dcache.LoadLockedReq_hits::total 18924 # number of LoadLockedReq hits
427system.cpu.dcache.StoreCondReq_hits::cpu.data 17376 # number of StoreCondReq hits
428system.cpu.dcache.StoreCondReq_hits::total 17376 # number of StoreCondReq hits
429system.cpu.dcache.demand_hits::cpu.data 44709945 # number of demand (read+write) hits
430system.cpu.dcache.demand_hits::total 44709945 # number of demand (read+write) hits
431system.cpu.dcache.overall_hits::cpu.data 44709945 # number of overall hits
432system.cpu.dcache.overall_hits::total 44709945 # number of overall hits
433system.cpu.dcache.ReadReq_misses::cpu.data 108879 # number of ReadReq misses
434system.cpu.dcache.ReadReq_misses::total 108879 # number of ReadReq misses
435system.cpu.dcache.WriteReq_misses::cpu.data 1539615 # number of WriteReq misses
436system.cpu.dcache.WriteReq_misses::total 1539615 # number of WriteReq misses
437system.cpu.dcache.LoadLockedReq_misses::cpu.data 26 # number of LoadLockedReq misses
438system.cpu.dcache.LoadLockedReq_misses::total 26 # number of LoadLockedReq misses
439system.cpu.dcache.demand_misses::cpu.data 1648494 # number of demand (read+write) misses
440system.cpu.dcache.demand_misses::total 1648494 # number of demand (read+write) misses
441system.cpu.dcache.overall_misses::cpu.data 1648494 # number of overall misses
442system.cpu.dcache.overall_misses::total 1648494 # number of overall misses
443system.cpu.dcache.ReadReq_miss_latency::cpu.data 2418798500 # number of ReadReq miss cycles
444system.cpu.dcache.ReadReq_miss_latency::total 2418798500 # number of ReadReq miss cycles
445system.cpu.dcache.WriteReq_miss_latency::cpu.data 52283607500 # number of WriteReq miss cycles
446system.cpu.dcache.WriteReq_miss_latency::total 52283607500 # number of WriteReq miss cycles
447system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 349000 # number of LoadLockedReq miss cycles
448system.cpu.dcache.LoadLockedReq_miss_latency::total 349000 # number of LoadLockedReq miss cycles
449system.cpu.dcache.demand_miss_latency::cpu.data 54702406000 # number of demand (read+write) miss cycles
450system.cpu.dcache.demand_miss_latency::total 54702406000 # number of demand (read+write) miss cycles
451system.cpu.dcache.overall_miss_latency::cpu.data 54702406000 # number of overall miss cycles
452system.cpu.dcache.overall_miss_latency::total 54702406000 # number of overall miss cycles
453system.cpu.dcache.ReadReq_accesses::cpu.data 26508538 # number of ReadReq accesses(hits+misses)
454system.cpu.dcache.ReadReq_accesses::total 26508538 # number of ReadReq accesses(hits+misses)
455system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
456system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
457system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18950 # number of LoadLockedReq accesses(hits+misses)
458system.cpu.dcache.LoadLockedReq_accesses::total 18950 # number of LoadLockedReq accesses(hits+misses)
459system.cpu.dcache.StoreCondReq_accesses::cpu.data 17376 # number of StoreCondReq accesses(hits+misses)
460system.cpu.dcache.StoreCondReq_accesses::total 17376 # number of StoreCondReq accesses(hits+misses)
461system.cpu.dcache.demand_accesses::cpu.data 46358439 # number of demand (read+write) accesses
462system.cpu.dcache.demand_accesses::total 46358439 # number of demand (read+write) accesses
463system.cpu.dcache.overall_accesses::cpu.data 46358439 # number of overall (read+write) accesses
464system.cpu.dcache.overall_accesses::total 46358439 # number of overall (read+write) accesses
465system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004107 # miss rate for ReadReq accesses
466system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077563 # miss rate for WriteReq accesses
467system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001372 # miss rate for LoadLockedReq accesses
468system.cpu.dcache.demand_miss_rate::cpu.data 0.035560 # miss rate for demand accesses
469system.cpu.dcache.overall_miss_rate::cpu.data 0.035560 # miss rate for overall accesses
470system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22215.473140 # average ReadReq miss latency
471system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33958.884202 # average WriteReq miss latency
472system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.076923 # average LoadLockedReq miss latency
473system.cpu.dcache.demand_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency
474system.cpu.dcache.overall_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency
475system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
476system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked
477system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
478system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
479system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
480system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked
481system.cpu.dcache.fast_writes 0 # number of fast writes performed
482system.cpu.dcache.cache_copies 0 # number of cache copies performed
483system.cpu.dcache.writebacks::writebacks 123473 # number of writebacks
484system.cpu.dcache.writebacks::total 123473 # number of writebacks
485system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53766 # number of ReadReq MSHR hits
486system.cpu.dcache.ReadReq_mshr_hits::total 53766 # number of ReadReq MSHR hits
487system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432695 # number of WriteReq MSHR hits
488system.cpu.dcache.WriteReq_mshr_hits::total 1432695 # number of WriteReq MSHR hits
489system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 26 # number of LoadLockedReq MSHR hits
490system.cpu.dcache.LoadLockedReq_mshr_hits::total 26 # number of LoadLockedReq MSHR hits
491system.cpu.dcache.demand_mshr_hits::cpu.data 1486461 # number of demand (read+write) MSHR hits
492system.cpu.dcache.demand_mshr_hits::total 1486461 # number of demand (read+write) MSHR hits
493system.cpu.dcache.overall_mshr_hits::cpu.data 1486461 # number of overall MSHR hits
494system.cpu.dcache.overall_mshr_hits::total 1486461 # number of overall MSHR hits
495system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55113 # number of ReadReq MSHR misses
496system.cpu.dcache.ReadReq_mshr_misses::total 55113 # number of ReadReq MSHR misses
497system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106920 # number of WriteReq MSHR misses
498system.cpu.dcache.WriteReq_mshr_misses::total 106920 # number of WriteReq MSHR misses
499system.cpu.dcache.demand_mshr_misses::cpu.data 162033 # number of demand (read+write) MSHR misses
500system.cpu.dcache.demand_mshr_misses::total 162033 # number of demand (read+write) MSHR misses
501system.cpu.dcache.overall_mshr_misses::cpu.data 162033 # number of overall MSHR misses
502system.cpu.dcache.overall_mshr_misses::total 162033 # number of overall MSHR misses
503system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1035745500 # number of ReadReq MSHR miss cycles
504system.cpu.dcache.ReadReq_mshr_miss_latency::total 1035745500 # number of ReadReq MSHR miss cycles
505system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3662420000 # number of WriteReq MSHR miss cycles
506system.cpu.dcache.WriteReq_mshr_miss_latency::total 3662420000 # number of WriteReq MSHR miss cycles
507system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4698165500 # number of demand (read+write) MSHR miss cycles
508system.cpu.dcache.demand_mshr_miss_latency::total 4698165500 # number of demand (read+write) MSHR miss cycles
509system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4698165500 # number of overall MSHR miss cycles
510system.cpu.dcache.overall_mshr_miss_latency::total 4698165500 # number of overall MSHR miss cycles
511system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002079 # mshr miss rate for ReadReq accesses
512system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005386 # mshr miss rate for WriteReq accesses
513system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003495 # mshr miss rate for demand accesses
514system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003495 # mshr miss rate for overall accesses
515system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18793.125034 # average ReadReq mshr miss latency
516system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34253.834643 # average WriteReq mshr miss latency
517system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28995.115193 # average overall mshr miss latency
518system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28995.115193 # average overall mshr miss latency
519system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
520system.cpu.l2cache.replacements 114916 # number of replacements
521system.cpu.l2cache.tagsinuse 18304.706842 # Cycle average of tags in use
522system.cpu.l2cache.total_refs 72481 # Total number of references to valid blocks.
523system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks.
524system.cpu.l2cache.avg_refs 0.541817 # Average number of references to valid blocks.
525system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
526system.cpu.l2cache.occ_blocks::writebacks 15934.147051 # Average occupied blocks per requestor
527system.cpu.l2cache.occ_blocks::cpu.inst 839.668596 # Average occupied blocks per requestor
528system.cpu.l2cache.occ_blocks::cpu.data 1530.891195 # Average occupied blocks per requestor
529system.cpu.l2cache.occ_percent::writebacks 0.486272 # Average percentage of cache occupancy
530system.cpu.l2cache.occ_percent::cpu.inst 0.025625 # Average percentage of cache occupancy
531system.cpu.l2cache.occ_percent::cpu.data 0.046719 # Average percentage of cache occupancy
532system.cpu.l2cache.occ_percent::total 0.558615 # Average percentage of cache occupancy
533system.cpu.l2cache.ReadReq_hits::cpu.inst 22667 # number of ReadReq hits
534system.cpu.l2cache.ReadReq_hits::cpu.data 27904 # number of ReadReq hits
535system.cpu.l2cache.ReadReq_hits::total 50571 # number of ReadReq hits
536system.cpu.l2cache.Writeback_hits::writebacks 123474 # number of Writeback hits
537system.cpu.l2cache.Writeback_hits::total 123474 # number of Writeback hits
538system.cpu.l2cache.UpgradeReq_hits::cpu.data 14 # number of UpgradeReq hits
539system.cpu.l2cache.UpgradeReq_hits::total 14 # number of UpgradeReq hits
540system.cpu.l2cache.ReadExReq_hits::cpu.data 4310 # number of ReadExReq hits
541system.cpu.l2cache.ReadExReq_hits::total 4310 # number of ReadExReq hits
542system.cpu.l2cache.demand_hits::cpu.inst 22667 # number of demand (read+write) hits
543system.cpu.l2cache.demand_hits::cpu.data 32214 # number of demand (read+write) hits
544system.cpu.l2cache.demand_hits::total 54881 # number of demand (read+write) hits
545system.cpu.l2cache.overall_hits::cpu.inst 22667 # number of overall hits
546system.cpu.l2cache.overall_hits::cpu.data 32214 # number of overall hits
547system.cpu.l2cache.overall_hits::total 54881 # number of overall hits
548system.cpu.l2cache.ReadReq_misses::cpu.inst 5494 # number of ReadReq misses
549system.cpu.l2cache.ReadReq_misses::cpu.data 27173 # number of ReadReq misses
550system.cpu.l2cache.ReadReq_misses::total 32667 # number of ReadReq misses
551system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses
552system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses
553system.cpu.l2cache.ReadExReq_misses::cpu.data 102597 # number of ReadExReq misses
554system.cpu.l2cache.ReadExReq_misses::total 102597 # number of ReadExReq misses
555system.cpu.l2cache.demand_misses::cpu.inst 5494 # number of demand (read+write) misses
556system.cpu.l2cache.demand_misses::cpu.data 129770 # number of demand (read+write) misses
557system.cpu.l2cache.demand_misses::total 135264 # number of demand (read+write) misses
558system.cpu.l2cache.overall_misses::cpu.inst 5494 # number of overall misses
559system.cpu.l2cache.overall_misses::cpu.data 129770 # number of overall misses
560system.cpu.l2cache.overall_misses::total 135264 # number of overall misses
561system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188188000 # number of ReadReq miss cycles
562system.cpu.l2cache.ReadReq_miss_latency::cpu.data 930191000 # number of ReadReq miss cycles
563system.cpu.l2cache.ReadReq_miss_latency::total 1118379000 # number of ReadReq miss cycles
564system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3526118000 # number of ReadExReq miss cycles
565system.cpu.l2cache.ReadExReq_miss_latency::total 3526118000 # number of ReadExReq miss cycles
566system.cpu.l2cache.demand_miss_latency::cpu.inst 188188000 # number of demand (read+write) miss cycles
567system.cpu.l2cache.demand_miss_latency::cpu.data 4456309000 # number of demand (read+write) miss cycles
568system.cpu.l2cache.demand_miss_latency::total 4644497000 # number of demand (read+write) miss cycles
569system.cpu.l2cache.overall_miss_latency::cpu.inst 188188000 # number of overall miss cycles
570system.cpu.l2cache.overall_miss_latency::cpu.data 4456309000 # number of overall miss cycles
571system.cpu.l2cache.overall_miss_latency::total 4644497000 # number of overall miss cycles
572system.cpu.l2cache.ReadReq_accesses::cpu.inst 28161 # number of ReadReq accesses(hits+misses)
573system.cpu.l2cache.ReadReq_accesses::cpu.data 55077 # number of ReadReq accesses(hits+misses)
574system.cpu.l2cache.ReadReq_accesses::total 83238 # number of ReadReq accesses(hits+misses)
575system.cpu.l2cache.Writeback_accesses::writebacks 123474 # number of Writeback accesses(hits+misses)
576system.cpu.l2cache.Writeback_accesses::total 123474 # number of Writeback accesses(hits+misses)
577system.cpu.l2cache.UpgradeReq_accesses::cpu.data 44 # number of UpgradeReq accesses(hits+misses)
578system.cpu.l2cache.UpgradeReq_accesses::total 44 # number of UpgradeReq accesses(hits+misses)
579system.cpu.l2cache.ReadExReq_accesses::cpu.data 106907 # number of ReadExReq accesses(hits+misses)
580system.cpu.l2cache.ReadExReq_accesses::total 106907 # number of ReadExReq accesses(hits+misses)
581system.cpu.l2cache.demand_accesses::cpu.inst 28161 # number of demand (read+write) accesses
582system.cpu.l2cache.demand_accesses::cpu.data 161984 # number of demand (read+write) accesses
583system.cpu.l2cache.demand_accesses::total 190145 # number of demand (read+write) accesses
584system.cpu.l2cache.overall_accesses::cpu.inst 28161 # number of overall (read+write) accesses
585system.cpu.l2cache.overall_accesses::cpu.data 161984 # number of overall (read+write) accesses
586system.cpu.l2cache.overall_accesses::total 190145 # number of overall (read+write) accesses
587system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.195093 # miss rate for ReadReq accesses
588system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.493364 # miss rate for ReadReq accesses
589system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.681818 # miss rate for UpgradeReq accesses
590system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959685 # miss rate for ReadExReq accesses
591system.cpu.l2cache.demand_miss_rate::cpu.inst 0.195093 # miss rate for demand accesses
592system.cpu.l2cache.demand_miss_rate::cpu.data 0.801129 # miss rate for demand accesses
593system.cpu.l2cache.overall_miss_rate::cpu.inst 0.195093 # miss rate for overall accesses
594system.cpu.l2cache.overall_miss_rate::cpu.data 0.801129 # miss rate for overall accesses
595system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.367310 # average ReadReq miss latency
596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34232.179001 # average ReadReq miss latency
597system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.626763 # average ReadExReq miss latency
598system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency
599system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency
600system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency
601system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency
602system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
603system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
604system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
605system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
606system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
607system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
608system.cpu.l2cache.fast_writes 0 # number of fast writes performed
609system.cpu.l2cache.cache_copies 0 # number of cache copies performed
610system.cpu.l2cache.writebacks::writebacks 88457 # number of writebacks
611system.cpu.l2cache.writebacks::total 88457 # number of writebacks
612system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits
613system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits
614system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
615system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits
616system.cpu.l2cache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits
617system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
618system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits
619system.cpu.l2cache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits
620system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits
621system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5470 # number of ReadReq MSHR misses
622system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27116 # number of ReadReq MSHR misses
623system.cpu.l2cache.ReadReq_mshr_misses::total 32586 # number of ReadReq MSHR misses
624system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses
625system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses
626system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102597 # number of ReadExReq MSHR misses
627system.cpu.l2cache.ReadExReq_mshr_misses::total 102597 # number of ReadExReq MSHR misses
628system.cpu.l2cache.demand_mshr_misses::cpu.inst 5470 # number of demand (read+write) MSHR misses
629system.cpu.l2cache.demand_mshr_misses::cpu.data 129713 # number of demand (read+write) MSHR misses
630system.cpu.l2cache.demand_mshr_misses::total 135183 # number of demand (read+write) MSHR misses
631system.cpu.l2cache.overall_mshr_misses::cpu.inst 5470 # number of overall MSHR misses
632system.cpu.l2cache.overall_mshr_misses::cpu.data 129713 # number of overall MSHR misses
633system.cpu.l2cache.overall_mshr_misses::total 135183 # number of overall MSHR misses
634system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169929500 # number of ReadReq MSHR miss cycles
635system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 842885000 # number of ReadReq MSHR miss cycles
636system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1012814500 # number of ReadReq MSHR miss cycles
637system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 931000 # number of UpgradeReq MSHR miss cycles
638system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 931000 # number of UpgradeReq MSHR miss cycles
639system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3197894500 # number of ReadExReq MSHR miss cycles
640system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3197894500 # number of ReadExReq MSHR miss cycles
641system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169929500 # number of demand (read+write) MSHR miss cycles
642system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4040779500 # number of demand (read+write) MSHR miss cycles
643system.cpu.l2cache.demand_mshr_miss_latency::total 4210709000 # number of demand (read+write) MSHR miss cycles
644system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169929500 # number of overall MSHR miss cycles
645system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4040779500 # number of overall MSHR miss cycles
646system.cpu.l2cache.overall_mshr_miss_latency::total 4210709000 # number of overall MSHR miss cycles
647system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for ReadReq accesses
648system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.492329 # mshr miss rate for ReadReq accesses
649system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.681818 # mshr miss rate for UpgradeReq accesses
650system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959685 # mshr miss rate for ReadExReq accesses
651system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for demand accesses
652system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for demand accesses
653system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for overall accesses
654system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for overall accesses
655system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.722121 # average ReadReq mshr miss latency
656system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31084.415105 # average ReadReq mshr miss latency
657system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31033.333333 # average UpgradeReq mshr miss latency
658system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31169.473766 # average ReadExReq mshr miss latency
659system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency
660system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency
661system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency
662system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency
663system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
664
665---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.031189 # Number of seconds simulated
4sim_ticks 31189496500 # Number of ticks simulated
5final_tick 31189496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 144507 # Simulator instruction rate (inst/s)
8host_op_rate 205068 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 63556485 # Simulator tick rate (ticks/s)
10host_mem_usage 231932 # Number of bytes of host memory used
11host_seconds 490.74 # Real time elapsed on the host
12sim_insts 70914922 # Number of instructions simulated
13sim_ops 100634170 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 8651712 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 350080 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 5661248 # Number of bytes written to this memory
17system.physmem.num_reads 135183 # Number of read requests responded to by this memory
18system.physmem.num_writes 88457 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 277391846 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 11224291 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 181511362 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 458903208 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 27 unchanged lines hidden (view full) ---
59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
60system.cpu.itb.read_accesses 0 # DTB read accesses
61system.cpu.itb.write_accesses 0 # DTB write accesses
62system.cpu.itb.inst_accesses 0 # ITB inst accesses
63system.cpu.itb.hits 0 # DTB hits
64system.cpu.itb.misses 0 # DTB misses
65system.cpu.itb.accesses 0 # DTB accesses
66system.cpu.workload.num_syscalls 1946 # Number of system calls
67system.cpu.numCycles 62378994 # number of cpu cycles simulated
68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
70system.cpu.BPredUnit.lookups 17633191 # Number of BP lookups
71system.cpu.BPredUnit.condPredicted 11526968 # Number of conditional branches predicted
72system.cpu.BPredUnit.condIncorrect 822695 # Number of conditional branches incorrect
73system.cpu.BPredUnit.BTBLookups 15043788 # Number of BTB lookups
74system.cpu.BPredUnit.BTBHits 9743985 # Number of BTB hits
75system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
76system.cpu.BPredUnit.usedRAS 1887457 # Number of times the RAS was used to get a target.
77system.cpu.BPredUnit.RASInCorrect 176874 # Number of incorrect RAS predictions.
78system.cpu.fetch.icacheStallCycles 12969342 # Number of cycles fetch is stalled on an Icache miss
79system.cpu.fetch.Insts 88531281 # Number of instructions fetch has processed
80system.cpu.fetch.Branches 17633191 # Number of branches that fetch encountered
81system.cpu.fetch.predictedBranches 11631442 # Number of branches that fetch has predicted taken
82system.cpu.fetch.Cycles 22985471 # Number of cycles fetch has run and was not squashing or blocked
83system.cpu.fetch.SquashCycles 2899094 # Number of cycles fetch has spent squashing
84system.cpu.fetch.BlockedCycles 23117489 # Number of cycles fetch has spent blocked
85system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
86system.cpu.fetch.PendingTrapStallCycles 528 # Number of stall cycles due to pending traps
87system.cpu.fetch.CacheLines 12209631 # Number of cache lines fetched
88system.cpu.fetch.IcacheSquashes 231060 # Number of outstanding Icache misses that were squashed
89system.cpu.fetch.rateDist::samples 61072156 # Number of instructions fetched each cycle (Total)
90system.cpu.fetch.rateDist::mean 2.021104 # Number of instructions fetched each cycle (Total)
91system.cpu.fetch.rateDist::stdev 3.077628 # Number of instructions fetched each cycle (Total)
92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
93system.cpu.fetch.rateDist::0 38102442 62.39% 62.39% # Number of instructions fetched each cycle (Total)
94system.cpu.fetch.rateDist::1 2437370 3.99% 66.38% # Number of instructions fetched each cycle (Total)
95system.cpu.fetch.rateDist::2 2604913 4.27% 70.65% # Number of instructions fetched each cycle (Total)
96system.cpu.fetch.rateDist::3 2468790 4.04% 74.69% # Number of instructions fetched each cycle (Total)
97system.cpu.fetch.rateDist::4 1717886 2.81% 77.50% # Number of instructions fetched each cycle (Total)
98system.cpu.fetch.rateDist::5 1703957 2.79% 80.29% # Number of instructions fetched each cycle (Total)
99system.cpu.fetch.rateDist::6 1004465 1.64% 81.94% # Number of instructions fetched each cycle (Total)
100system.cpu.fetch.rateDist::7 1297144 2.12% 84.06% # Number of instructions fetched each cycle (Total)
101system.cpu.fetch.rateDist::8 9735189 15.94% 100.00% # Number of instructions fetched each cycle (Total)
102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
105system.cpu.fetch.rateDist::total 61072156 # Number of instructions fetched each cycle (Total)
106system.cpu.fetch.branchRate 0.282678 # Number of branch fetches per cycle
107system.cpu.fetch.rate 1.419248 # Number of inst fetches per cycle
108system.cpu.decode.IdleCycles 14874533 # Number of cycles decode is idle
109system.cpu.decode.BlockedCycles 21847562 # Number of cycles decode is blocked
110system.cpu.decode.RunCycles 21380234 # Number of cycles decode is running
111system.cpu.decode.UnblockCycles 1066852 # Number of cycles decode is unblocking
112system.cpu.decode.SquashCycles 1902975 # Number of cycles decode is squashing
113system.cpu.decode.BranchResolved 3467400 # Number of times decode resolved a branch
114system.cpu.decode.BranchMispred 97940 # Number of times decode detected a branch misprediction
115system.cpu.decode.DecodedInsts 120324997 # Number of instructions handled by decode
116system.cpu.decode.SquashedInsts 332105 # Number of squashed instructions handled by decode
117system.cpu.rename.SquashCycles 1902975 # Number of cycles rename is squashing
118system.cpu.rename.IdleCycles 16806585 # Number of cycles rename is idle
119system.cpu.rename.BlockCycles 2006065 # Number of cycles rename is blocking
120system.cpu.rename.serializeStallCycles 15518837 # count of cycles rename stalled for serializing inst
121system.cpu.rename.RunCycles 20487124 # Number of cycles rename is running
122system.cpu.rename.UnblockCycles 4350570 # Number of cycles rename is unblocking
123system.cpu.rename.RenamedInsts 117025506 # Number of instructions processed by rename
124system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full
125system.cpu.rename.IQFullEvents 3620 # Number of times rename has blocked due to IQ full
126system.cpu.rename.LSQFullEvents 3001536 # Number of times rename has blocked due to LSQ full
127system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers
128system.cpu.rename.RenamedOperands 118973415 # Number of destination operands rename has renamed
129system.cpu.rename.RenameLookups 538271633 # Number of register rename lookups that rename has made
130system.cpu.rename.int_rename_lookups 538269997 # Number of integer rename lookups
131system.cpu.rename.fp_rename_lookups 1636 # Number of floating rename lookups
132system.cpu.rename.CommittedMaps 99144341 # Number of HB maps that are committed
133system.cpu.rename.UndoneMaps 19829074 # Number of HB maps that are undone due to squashing
134system.cpu.rename.serializingInsts 778296 # count of serializing insts renamed
135system.cpu.rename.tempSerializingInsts 778691 # count of temporary serializing insts renamed
136system.cpu.rename.skidInsts 12144889 # count of insts added to the skid buffer
137system.cpu.memDep0.insertedLoads 29749506 # Number of loads inserted to the mem dependence unit.
138system.cpu.memDep0.insertedStores 22307130 # Number of stores inserted to the mem dependence unit.
139system.cpu.memDep0.conflictingLoads 2475389 # Number of conflicting loads.
140system.cpu.memDep0.conflictingStores 3455641 # Number of conflicting stores.
141system.cpu.iq.iqInstsAdded 111742619 # Number of instructions added to the IQ (excludes non-spec)
142system.cpu.iq.iqNonSpecInstsAdded 774376 # Number of non-speculative instructions added to the IQ
143system.cpu.iq.iqInstsIssued 107620542 # Number of instructions issued
144system.cpu.iq.iqSquashedInstsIssued 306039 # Number of squashed instructions issued
145system.cpu.iq.iqSquashedInstsExamined 11663320 # Number of squashed instructions iterated over during squash; mainly for profiling
146system.cpu.iq.iqSquashedOperandsExamined 29339036 # Number of squashed operands that are examined and possibly removed from graph
147system.cpu.iq.iqSquashedNonSpecRemoved 71343 # Number of squashed non-spec instructions that were removed
148system.cpu.iq.issued_per_cycle::samples 61072156 # Number of insts issued each cycle
149system.cpu.iq.issued_per_cycle::mean 1.762187 # Number of insts issued each cycle
150system.cpu.iq.issued_per_cycle::stdev 1.902803 # Number of insts issued each cycle
151system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
152system.cpu.iq.issued_per_cycle::0 22164835 36.29% 36.29% # Number of insts issued each cycle
153system.cpu.iq.issued_per_cycle::1 11626045 19.04% 55.33% # Number of insts issued each cycle
154system.cpu.iq.issued_per_cycle::2 8572984 14.04% 69.37% # Number of insts issued each cycle
155system.cpu.iq.issued_per_cycle::3 7394656 12.11% 81.47% # Number of insts issued each cycle
156system.cpu.iq.issued_per_cycle::4 4788181 7.84% 89.32% # Number of insts issued each cycle
157system.cpu.iq.issued_per_cycle::5 3517678 5.76% 95.08% # Number of insts issued each cycle
158system.cpu.iq.issued_per_cycle::6 1664983 2.73% 97.80% # Number of insts issued each cycle
159system.cpu.iq.issued_per_cycle::7 808803 1.32% 99.13% # Number of insts issued each cycle
160system.cpu.iq.issued_per_cycle::8 533991 0.87% 100.00% # Number of insts issued each cycle
161system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
162system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
163system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
164system.cpu.iq.issued_per_cycle::total 61072156 # Number of insts issued each cycle
165system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
166system.cpu.iq.fu_full::IntAlu 87531 3.32% 3.32% # attempts to use FU when none available
167system.cpu.iq.fu_full::IntMult 0 0.00% 3.32% # attempts to use FU when none available
168system.cpu.iq.fu_full::IntDiv 0 0.00% 3.32% # attempts to use FU when none available
169system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.32% # attempts to use FU when none available
170system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.32% # attempts to use FU when none available
171system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.32% # attempts to use FU when none available
172system.cpu.iq.fu_full::FloatMult 0 0.00% 3.32% # attempts to use FU when none available
173system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.32% # attempts to use FU when none available
174system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.32% # attempts to use FU when none available
175system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.32% # attempts to use FU when none available
176system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.32% # attempts to use FU when none available
177system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.32% # attempts to use FU when none available
178system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.32% # attempts to use FU when none available
179system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.32% # attempts to use FU when none available
180system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.32% # attempts to use FU when none available
181system.cpu.iq.fu_full::SimdMult 0 0.00% 3.32% # attempts to use FU when none available
182system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.32% # attempts to use FU when none available
183system.cpu.iq.fu_full::SimdShift 0 0.00% 3.32% # attempts to use FU when none available
184system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.32% # attempts to use FU when none available
185system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.32% # attempts to use FU when none available
186system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.32% # attempts to use FU when none available
187system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.32% # attempts to use FU when none available
188system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.32% # attempts to use FU when none available
189system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.32% # attempts to use FU when none available
190system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.32% # attempts to use FU when none available
191system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.32% # attempts to use FU when none available
192system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.32% # attempts to use FU when none available
193system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.32% # attempts to use FU when none available
194system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.32% # attempts to use FU when none available
195system.cpu.iq.fu_full::MemRead 1485029 56.34% 59.66% # attempts to use FU when none available
196system.cpu.iq.fu_full::MemWrite 1063128 40.34% 100.00% # attempts to use FU when none available
197system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
198system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
199system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
200system.cpu.iq.FU_type_0::IntAlu 57005331 52.97% 52.97% # Type of FU issued
201system.cpu.iq.FU_type_0::IntMult 87377 0.08% 53.05% # Type of FU issued
202system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued
203system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 53.05% # Type of FU issued
204system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued
205system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued
206system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued
207system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.05% # Type of FU issued
208system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.05% # Type of FU issued
209system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.05% # Type of FU issued
210system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.05% # Type of FU issued
211system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.05% # Type of FU issued
212system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.05% # Type of FU issued
213system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.05% # Type of FU issued
214system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.05% # Type of FU issued
215system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.05% # Type of FU issued
216system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.05% # Type of FU issued
217system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.05% # Type of FU issued
218system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.05% # Type of FU issued
219system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.05% # Type of FU issued
220system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.05% # Type of FU issued
221system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.05% # Type of FU issued
222system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.05% # Type of FU issued
223system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.05% # Type of FU issued
224system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.05% # Type of FU issued
225system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.05% # Type of FU issued
226system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued
227system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued
228system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued
229system.cpu.iq.FU_type_0::MemRead 28993103 26.94% 79.99% # Type of FU issued
230system.cpu.iq.FU_type_0::MemWrite 21534684 20.01% 100.00% # Type of FU issued
231system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
232system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
233system.cpu.iq.FU_type_0::total 107620542 # Type of FU issued
234system.cpu.iq.rate 1.725269 # Inst issue rate
235system.cpu.iq.fu_busy_cnt 2635688 # FU busy when requested
236system.cpu.iq.fu_busy_rate 0.024491 # FU busy rate (busy events/executed inst)
237system.cpu.iq.int_inst_queue_reads 279254757 # Number of integer instruction queue reads
238system.cpu.iq.int_inst_queue_writes 124195436 # Number of integer instruction queue writes
239system.cpu.iq.int_inst_queue_wakeup_accesses 105415832 # Number of integer instruction queue wakeup accesses
240system.cpu.iq.fp_inst_queue_reads 210 # Number of floating instruction queue reads
241system.cpu.iq.fp_inst_queue_writes 218 # Number of floating instruction queue writes
242system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses
243system.cpu.iq.int_alu_accesses 110256122 # Number of integer alu accesses
244system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses
245system.cpu.iew.lsq.thread0.forwLoads 1866930 # Number of loads that had data forwarded from stores
246system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
247system.cpu.iew.lsq.thread0.squashedLoads 2440940 # Number of loads squashed
248system.cpu.iew.lsq.thread0.ignoredResponses 3458 # Number of memory responses ignored because the instruction is squashed
249system.cpu.iew.lsq.thread0.memOrderViolation 15970 # Number of memory ordering violations
250system.cpu.iew.lsq.thread0.squashedStores 1749935 # Number of stores squashed
251system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
252system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
253system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled
254system.cpu.iew.lsq.thread0.cacheBlocked 52 # Number of times an access to memory failed due to the cache being blocked
255system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
256system.cpu.iew.iewSquashCycles 1902975 # Number of cycles IEW is squashing
257system.cpu.iew.iewBlockCycles 953135 # Number of cycles IEW is blocking
258system.cpu.iew.iewUnblockCycles 28579 # Number of cycles IEW is unblocking
259system.cpu.iew.iewDispatchedInsts 112593446 # Number of instructions dispatched to IQ
260system.cpu.iew.iewDispSquashedInsts 617881 # Number of squashed instructions skipped by dispatch
261system.cpu.iew.iewDispLoadInsts 29749506 # Number of dispatched load instructions
262system.cpu.iew.iewDispStoreInsts 22307130 # Number of dispatched store instructions
263system.cpu.iew.iewDispNonSpecInsts 757118 # Number of dispatched non-speculative instructions
264system.cpu.iew.iewIQFullEvents 1133 # Number of times the IQ has become full, causing a stall
265system.cpu.iew.iewLSQFullEvents 1194 # Number of times the LSQ has become full, causing a stall
266system.cpu.iew.memOrderViolationEvents 15970 # Number of memory order violations
267system.cpu.iew.predictedTakenIncorrect 682654 # Number of branches that were predicted taken incorrectly
268system.cpu.iew.predictedNotTakenIncorrect 198883 # Number of branches that were predicted not taken incorrectly
269system.cpu.iew.branchMispredicts 881537 # Number of branch mispredicts detected at execute
270system.cpu.iew.iewExecutedInsts 106278016 # Number of executed instructions
271system.cpu.iew.iewExecLoadInsts 28622846 # Number of load instructions executed
272system.cpu.iew.iewExecSquashedInsts 1342526 # Number of squashed instructions skipped in execute
273system.cpu.iew.exec_swp 0 # number of swp insts executed
274system.cpu.iew.exec_nop 76451 # number of nop insts executed
275system.cpu.iew.exec_refs 49854993 # number of memory reference insts executed
276system.cpu.iew.exec_branches 14601868 # Number of branches executed
277system.cpu.iew.exec_stores 21232147 # Number of stores executed
278system.cpu.iew.exec_rate 1.703747 # Inst execution rate
279system.cpu.iew.wb_sent 105729046 # cumulative count of insts sent to commit
280system.cpu.iew.wb_count 105415908 # cumulative count of insts written-back
281system.cpu.iew.wb_producers 52516965 # num instructions producing a value
282system.cpu.iew.wb_consumers 101175097 # num instructions consuming a value
283system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
284system.cpu.iew.wb_rate 1.689926 # insts written-back per cycle
285system.cpu.iew.wb_fanout 0.519070 # average fanout of values written-back
286system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
287system.cpu.commit.commitCommittedInsts 70920474 # The number of committed instructions
288system.cpu.commit.commitCommittedOps 100639722 # The number of committed instructions
289system.cpu.commit.commitSquashedInsts 11954174 # The number of squashed insts skipped by commit
290system.cpu.commit.commitNonSpecStalls 703033 # The number of times commit has been forced to stall to communicate backwards
291system.cpu.commit.branchMispredicts 788567 # The number of times a branch was mispredicted
292system.cpu.commit.committed_per_cycle::samples 59169182 # Number of insts commited each cycle
293system.cpu.commit.committed_per_cycle::mean 1.700881 # Number of insts commited each cycle
294system.cpu.commit.committed_per_cycle::stdev 2.430495 # Number of insts commited each cycle
295system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
296system.cpu.commit.committed_per_cycle::0 26246833 44.36% 44.36% # Number of insts commited each cycle
297system.cpu.commit.committed_per_cycle::1 14645427 24.75% 69.11% # Number of insts commited each cycle
298system.cpu.commit.committed_per_cycle::2 4228470 7.15% 76.26% # Number of insts commited each cycle
299system.cpu.commit.committed_per_cycle::3 3643076 6.16% 82.41% # Number of insts commited each cycle
300system.cpu.commit.committed_per_cycle::4 2266929 3.83% 86.25% # Number of insts commited each cycle
301system.cpu.commit.committed_per_cycle::5 1888235 3.19% 89.44% # Number of insts commited each cycle
302system.cpu.commit.committed_per_cycle::6 703093 1.19% 90.62% # Number of insts commited each cycle
303system.cpu.commit.committed_per_cycle::7 496274 0.84% 91.46% # Number of insts commited each cycle
304system.cpu.commit.committed_per_cycle::8 5050845 8.54% 100.00% # Number of insts commited each cycle
305system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
306system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
307system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
308system.cpu.commit.committed_per_cycle::total 59169182 # Number of insts commited each cycle
309system.cpu.commit.committedInsts 70920474 # Number of instructions committed
310system.cpu.commit.committedOps 100639722 # Number of ops (including micro ops) committed
311system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
312system.cpu.commit.refs 47865761 # Number of memory references committed
313system.cpu.commit.loads 27308566 # Number of loads committed
314system.cpu.commit.membars 15920 # Number of memory barriers committed
315system.cpu.commit.branches 13670085 # Number of branches committed
316system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
317system.cpu.commit.int_insts 91478615 # Number of committed integer instructions.
318system.cpu.commit.function_calls 1679850 # Number of function calls committed.
319system.cpu.commit.bw_lim_events 5050845 # number cycles where commit BW limit reached
320system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
321system.cpu.rob.rob_reads 166686934 # The number of ROB reads
322system.cpu.rob.rob_writes 227096473 # The number of ROB writes
323system.cpu.timesIdled 61617 # Number of times that the entire CPU went into an idle state and unscheduled itself
324system.cpu.idleCycles 1306838 # Total number of cycles that the CPU has spent unscheduled due to idling
325system.cpu.committedInsts 70914922 # Number of Instructions Simulated
326system.cpu.committedOps 100634170 # Number of Ops (including micro ops) Simulated
327system.cpu.committedInsts_total 70914922 # Number of Instructions Simulated
328system.cpu.cpi 0.879631 # CPI: Cycles Per Instruction
329system.cpu.cpi_total 0.879631 # CPI: Total CPI of All Threads
330system.cpu.ipc 1.136840 # IPC: Instructions Per Cycle
331system.cpu.ipc_total 1.136840 # IPC: Total IPC of All Threads
332system.cpu.int_regfile_reads 511674990 # number of integer regfile reads
333system.cpu.int_regfile_writes 103897673 # number of integer regfile writes
334system.cpu.fp_regfile_reads 166 # number of floating regfile reads
335system.cpu.fp_regfile_writes 126 # number of floating regfile writes
336system.cpu.misc_regfile_reads 146219619 # number of misc regfile reads
337system.cpu.misc_regfile_writes 34754 # number of misc regfile writes
338system.cpu.icache.replacements 26131 # number of replacements
339system.cpu.icache.tagsinuse 1805.600642 # Cycle average of tags in use
340system.cpu.icache.total_refs 12180358 # Total number of references to valid blocks.
341system.cpu.icache.sampled_refs 28166 # Sample count of references to valid blocks.
342system.cpu.icache.avg_refs 432.448981 # Average number of references to valid blocks.
343system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
344system.cpu.icache.occ_blocks::cpu.inst 1805.600642 # Average occupied blocks per requestor
345system.cpu.icache.occ_percent::cpu.inst 0.881641 # Average percentage of cache occupancy
346system.cpu.icache.occ_percent::total 0.881641 # Average percentage of cache occupancy
347system.cpu.icache.ReadReq_hits::cpu.inst 12180359 # number of ReadReq hits
348system.cpu.icache.ReadReq_hits::total 12180359 # number of ReadReq hits
349system.cpu.icache.demand_hits::cpu.inst 12180359 # number of demand (read+write) hits
350system.cpu.icache.demand_hits::total 12180359 # number of demand (read+write) hits
351system.cpu.icache.overall_hits::cpu.inst 12180359 # number of overall hits
352system.cpu.icache.overall_hits::total 12180359 # number of overall hits
353system.cpu.icache.ReadReq_misses::cpu.inst 29272 # number of ReadReq misses
354system.cpu.icache.ReadReq_misses::total 29272 # number of ReadReq misses
355system.cpu.icache.demand_misses::cpu.inst 29272 # number of demand (read+write) misses
356system.cpu.icache.demand_misses::total 29272 # number of demand (read+write) misses
357system.cpu.icache.overall_misses::cpu.inst 29272 # number of overall misses
358system.cpu.icache.overall_misses::total 29272 # number of overall misses
359system.cpu.icache.ReadReq_miss_latency::cpu.inst 357988500 # number of ReadReq miss cycles
360system.cpu.icache.ReadReq_miss_latency::total 357988500 # number of ReadReq miss cycles
361system.cpu.icache.demand_miss_latency::cpu.inst 357988500 # number of demand (read+write) miss cycles
362system.cpu.icache.demand_miss_latency::total 357988500 # number of demand (read+write) miss cycles
363system.cpu.icache.overall_miss_latency::cpu.inst 357988500 # number of overall miss cycles
364system.cpu.icache.overall_miss_latency::total 357988500 # number of overall miss cycles
365system.cpu.icache.ReadReq_accesses::cpu.inst 12209631 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.ReadReq_accesses::total 12209631 # number of ReadReq accesses(hits+misses)
367system.cpu.icache.demand_accesses::cpu.inst 12209631 # number of demand (read+write) accesses
368system.cpu.icache.demand_accesses::total 12209631 # number of demand (read+write) accesses
369system.cpu.icache.overall_accesses::cpu.inst 12209631 # number of overall (read+write) accesses
370system.cpu.icache.overall_accesses::total 12209631 # number of overall (read+write) accesses
371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002397 # miss rate for ReadReq accesses
372system.cpu.icache.demand_miss_rate::cpu.inst 0.002397 # miss rate for demand accesses
373system.cpu.icache.overall_miss_rate::cpu.inst 0.002397 # miss rate for overall accesses
374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12229.724652 # average ReadReq miss latency
375system.cpu.icache.demand_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency
376system.cpu.icache.overall_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency
377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
381system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
382system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
383system.cpu.icache.fast_writes 0 # number of fast writes performed
384system.cpu.icache.cache_copies 0 # number of cache copies performed
385system.cpu.icache.writebacks::writebacks 1 # number of writebacks
386system.cpu.icache.writebacks::total 1 # number of writebacks
387system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1063 # number of ReadReq MSHR hits
388system.cpu.icache.ReadReq_mshr_hits::total 1063 # number of ReadReq MSHR hits
389system.cpu.icache.demand_mshr_hits::cpu.inst 1063 # number of demand (read+write) MSHR hits
390system.cpu.icache.demand_mshr_hits::total 1063 # number of demand (read+write) MSHR hits
391system.cpu.icache.overall_mshr_hits::cpu.inst 1063 # number of overall MSHR hits
392system.cpu.icache.overall_mshr_hits::total 1063 # number of overall MSHR hits
393system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28209 # number of ReadReq MSHR misses
394system.cpu.icache.ReadReq_mshr_misses::total 28209 # number of ReadReq MSHR misses
395system.cpu.icache.demand_mshr_misses::cpu.inst 28209 # number of demand (read+write) MSHR misses
396system.cpu.icache.demand_mshr_misses::total 28209 # number of demand (read+write) MSHR misses
397system.cpu.icache.overall_mshr_misses::cpu.inst 28209 # number of overall MSHR misses
398system.cpu.icache.overall_mshr_misses::total 28209 # number of overall MSHR misses
399system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 247071500 # number of ReadReq MSHR miss cycles
400system.cpu.icache.ReadReq_mshr_miss_latency::total 247071500 # number of ReadReq MSHR miss cycles
401system.cpu.icache.demand_mshr_miss_latency::cpu.inst 247071500 # number of demand (read+write) MSHR miss cycles
402system.cpu.icache.demand_mshr_miss_latency::total 247071500 # number of demand (read+write) MSHR miss cycles
403system.cpu.icache.overall_mshr_miss_latency::cpu.inst 247071500 # number of overall MSHR miss cycles
404system.cpu.icache.overall_mshr_miss_latency::total 247071500 # number of overall MSHR miss cycles
405system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for ReadReq accesses
406system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for demand accesses
407system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for overall accesses
408system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8758.605410 # average ReadReq mshr miss latency
409system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency
410system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency
411system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
412system.cpu.dcache.replacements 157892 # number of replacements
413system.cpu.dcache.tagsinuse 4072.334227 # Cycle average of tags in use
414system.cpu.dcache.total_refs 44746410 # Total number of references to valid blocks.
415system.cpu.dcache.sampled_refs 161988 # Sample count of references to valid blocks.
416system.cpu.dcache.avg_refs 276.232869 # Average number of references to valid blocks.
417system.cpu.dcache.warmup_cycle 306594000 # Cycle when the warmup percentage was hit.
418system.cpu.dcache.occ_blocks::cpu.data 4072.334227 # Average occupied blocks per requestor
419system.cpu.dcache.occ_percent::cpu.data 0.994222 # Average percentage of cache occupancy
420system.cpu.dcache.occ_percent::total 0.994222 # Average percentage of cache occupancy
421system.cpu.dcache.ReadReq_hits::cpu.data 26399659 # number of ReadReq hits
422system.cpu.dcache.ReadReq_hits::total 26399659 # number of ReadReq hits
423system.cpu.dcache.WriteReq_hits::cpu.data 18310286 # number of WriteReq hits
424system.cpu.dcache.WriteReq_hits::total 18310286 # number of WriteReq hits
425system.cpu.dcache.LoadLockedReq_hits::cpu.data 18924 # number of LoadLockedReq hits
426system.cpu.dcache.LoadLockedReq_hits::total 18924 # number of LoadLockedReq hits
427system.cpu.dcache.StoreCondReq_hits::cpu.data 17376 # number of StoreCondReq hits
428system.cpu.dcache.StoreCondReq_hits::total 17376 # number of StoreCondReq hits
429system.cpu.dcache.demand_hits::cpu.data 44709945 # number of demand (read+write) hits
430system.cpu.dcache.demand_hits::total 44709945 # number of demand (read+write) hits
431system.cpu.dcache.overall_hits::cpu.data 44709945 # number of overall hits
432system.cpu.dcache.overall_hits::total 44709945 # number of overall hits
433system.cpu.dcache.ReadReq_misses::cpu.data 108879 # number of ReadReq misses
434system.cpu.dcache.ReadReq_misses::total 108879 # number of ReadReq misses
435system.cpu.dcache.WriteReq_misses::cpu.data 1539615 # number of WriteReq misses
436system.cpu.dcache.WriteReq_misses::total 1539615 # number of WriteReq misses
437system.cpu.dcache.LoadLockedReq_misses::cpu.data 26 # number of LoadLockedReq misses
438system.cpu.dcache.LoadLockedReq_misses::total 26 # number of LoadLockedReq misses
439system.cpu.dcache.demand_misses::cpu.data 1648494 # number of demand (read+write) misses
440system.cpu.dcache.demand_misses::total 1648494 # number of demand (read+write) misses
441system.cpu.dcache.overall_misses::cpu.data 1648494 # number of overall misses
442system.cpu.dcache.overall_misses::total 1648494 # number of overall misses
443system.cpu.dcache.ReadReq_miss_latency::cpu.data 2418798500 # number of ReadReq miss cycles
444system.cpu.dcache.ReadReq_miss_latency::total 2418798500 # number of ReadReq miss cycles
445system.cpu.dcache.WriteReq_miss_latency::cpu.data 52283607500 # number of WriteReq miss cycles
446system.cpu.dcache.WriteReq_miss_latency::total 52283607500 # number of WriteReq miss cycles
447system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 349000 # number of LoadLockedReq miss cycles
448system.cpu.dcache.LoadLockedReq_miss_latency::total 349000 # number of LoadLockedReq miss cycles
449system.cpu.dcache.demand_miss_latency::cpu.data 54702406000 # number of demand (read+write) miss cycles
450system.cpu.dcache.demand_miss_latency::total 54702406000 # number of demand (read+write) miss cycles
451system.cpu.dcache.overall_miss_latency::cpu.data 54702406000 # number of overall miss cycles
452system.cpu.dcache.overall_miss_latency::total 54702406000 # number of overall miss cycles
453system.cpu.dcache.ReadReq_accesses::cpu.data 26508538 # number of ReadReq accesses(hits+misses)
454system.cpu.dcache.ReadReq_accesses::total 26508538 # number of ReadReq accesses(hits+misses)
455system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
456system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
457system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18950 # number of LoadLockedReq accesses(hits+misses)
458system.cpu.dcache.LoadLockedReq_accesses::total 18950 # number of LoadLockedReq accesses(hits+misses)
459system.cpu.dcache.StoreCondReq_accesses::cpu.data 17376 # number of StoreCondReq accesses(hits+misses)
460system.cpu.dcache.StoreCondReq_accesses::total 17376 # number of StoreCondReq accesses(hits+misses)
461system.cpu.dcache.demand_accesses::cpu.data 46358439 # number of demand (read+write) accesses
462system.cpu.dcache.demand_accesses::total 46358439 # number of demand (read+write) accesses
463system.cpu.dcache.overall_accesses::cpu.data 46358439 # number of overall (read+write) accesses
464system.cpu.dcache.overall_accesses::total 46358439 # number of overall (read+write) accesses
465system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004107 # miss rate for ReadReq accesses
466system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077563 # miss rate for WriteReq accesses
467system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001372 # miss rate for LoadLockedReq accesses
468system.cpu.dcache.demand_miss_rate::cpu.data 0.035560 # miss rate for demand accesses
469system.cpu.dcache.overall_miss_rate::cpu.data 0.035560 # miss rate for overall accesses
470system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22215.473140 # average ReadReq miss latency
471system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33958.884202 # average WriteReq miss latency
472system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.076923 # average LoadLockedReq miss latency
473system.cpu.dcache.demand_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency
474system.cpu.dcache.overall_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency
475system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
476system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked
477system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
478system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
479system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
480system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked
481system.cpu.dcache.fast_writes 0 # number of fast writes performed
482system.cpu.dcache.cache_copies 0 # number of cache copies performed
483system.cpu.dcache.writebacks::writebacks 123473 # number of writebacks
484system.cpu.dcache.writebacks::total 123473 # number of writebacks
485system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53766 # number of ReadReq MSHR hits
486system.cpu.dcache.ReadReq_mshr_hits::total 53766 # number of ReadReq MSHR hits
487system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432695 # number of WriteReq MSHR hits
488system.cpu.dcache.WriteReq_mshr_hits::total 1432695 # number of WriteReq MSHR hits
489system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 26 # number of LoadLockedReq MSHR hits
490system.cpu.dcache.LoadLockedReq_mshr_hits::total 26 # number of LoadLockedReq MSHR hits
491system.cpu.dcache.demand_mshr_hits::cpu.data 1486461 # number of demand (read+write) MSHR hits
492system.cpu.dcache.demand_mshr_hits::total 1486461 # number of demand (read+write) MSHR hits
493system.cpu.dcache.overall_mshr_hits::cpu.data 1486461 # number of overall MSHR hits
494system.cpu.dcache.overall_mshr_hits::total 1486461 # number of overall MSHR hits
495system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55113 # number of ReadReq MSHR misses
496system.cpu.dcache.ReadReq_mshr_misses::total 55113 # number of ReadReq MSHR misses
497system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106920 # number of WriteReq MSHR misses
498system.cpu.dcache.WriteReq_mshr_misses::total 106920 # number of WriteReq MSHR misses
499system.cpu.dcache.demand_mshr_misses::cpu.data 162033 # number of demand (read+write) MSHR misses
500system.cpu.dcache.demand_mshr_misses::total 162033 # number of demand (read+write) MSHR misses
501system.cpu.dcache.overall_mshr_misses::cpu.data 162033 # number of overall MSHR misses
502system.cpu.dcache.overall_mshr_misses::total 162033 # number of overall MSHR misses
503system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1035745500 # number of ReadReq MSHR miss cycles
504system.cpu.dcache.ReadReq_mshr_miss_latency::total 1035745500 # number of ReadReq MSHR miss cycles
505system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3662420000 # number of WriteReq MSHR miss cycles
506system.cpu.dcache.WriteReq_mshr_miss_latency::total 3662420000 # number of WriteReq MSHR miss cycles
507system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4698165500 # number of demand (read+write) MSHR miss cycles
508system.cpu.dcache.demand_mshr_miss_latency::total 4698165500 # number of demand (read+write) MSHR miss cycles
509system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4698165500 # number of overall MSHR miss cycles
510system.cpu.dcache.overall_mshr_miss_latency::total 4698165500 # number of overall MSHR miss cycles
511system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002079 # mshr miss rate for ReadReq accesses
512system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005386 # mshr miss rate for WriteReq accesses
513system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003495 # mshr miss rate for demand accesses
514system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003495 # mshr miss rate for overall accesses
515system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18793.125034 # average ReadReq mshr miss latency
516system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34253.834643 # average WriteReq mshr miss latency
517system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28995.115193 # average overall mshr miss latency
518system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28995.115193 # average overall mshr miss latency
519system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
520system.cpu.l2cache.replacements 114916 # number of replacements
521system.cpu.l2cache.tagsinuse 18304.706842 # Cycle average of tags in use
522system.cpu.l2cache.total_refs 72481 # Total number of references to valid blocks.
523system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks.
524system.cpu.l2cache.avg_refs 0.541817 # Average number of references to valid blocks.
525system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
526system.cpu.l2cache.occ_blocks::writebacks 15934.147051 # Average occupied blocks per requestor
527system.cpu.l2cache.occ_blocks::cpu.inst 839.668596 # Average occupied blocks per requestor
528system.cpu.l2cache.occ_blocks::cpu.data 1530.891195 # Average occupied blocks per requestor
529system.cpu.l2cache.occ_percent::writebacks 0.486272 # Average percentage of cache occupancy
530system.cpu.l2cache.occ_percent::cpu.inst 0.025625 # Average percentage of cache occupancy
531system.cpu.l2cache.occ_percent::cpu.data 0.046719 # Average percentage of cache occupancy
532system.cpu.l2cache.occ_percent::total 0.558615 # Average percentage of cache occupancy
533system.cpu.l2cache.ReadReq_hits::cpu.inst 22667 # number of ReadReq hits
534system.cpu.l2cache.ReadReq_hits::cpu.data 27904 # number of ReadReq hits
535system.cpu.l2cache.ReadReq_hits::total 50571 # number of ReadReq hits
536system.cpu.l2cache.Writeback_hits::writebacks 123474 # number of Writeback hits
537system.cpu.l2cache.Writeback_hits::total 123474 # number of Writeback hits
538system.cpu.l2cache.UpgradeReq_hits::cpu.data 14 # number of UpgradeReq hits
539system.cpu.l2cache.UpgradeReq_hits::total 14 # number of UpgradeReq hits
540system.cpu.l2cache.ReadExReq_hits::cpu.data 4310 # number of ReadExReq hits
541system.cpu.l2cache.ReadExReq_hits::total 4310 # number of ReadExReq hits
542system.cpu.l2cache.demand_hits::cpu.inst 22667 # number of demand (read+write) hits
543system.cpu.l2cache.demand_hits::cpu.data 32214 # number of demand (read+write) hits
544system.cpu.l2cache.demand_hits::total 54881 # number of demand (read+write) hits
545system.cpu.l2cache.overall_hits::cpu.inst 22667 # number of overall hits
546system.cpu.l2cache.overall_hits::cpu.data 32214 # number of overall hits
547system.cpu.l2cache.overall_hits::total 54881 # number of overall hits
548system.cpu.l2cache.ReadReq_misses::cpu.inst 5494 # number of ReadReq misses
549system.cpu.l2cache.ReadReq_misses::cpu.data 27173 # number of ReadReq misses
550system.cpu.l2cache.ReadReq_misses::total 32667 # number of ReadReq misses
551system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses
552system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses
553system.cpu.l2cache.ReadExReq_misses::cpu.data 102597 # number of ReadExReq misses
554system.cpu.l2cache.ReadExReq_misses::total 102597 # number of ReadExReq misses
555system.cpu.l2cache.demand_misses::cpu.inst 5494 # number of demand (read+write) misses
556system.cpu.l2cache.demand_misses::cpu.data 129770 # number of demand (read+write) misses
557system.cpu.l2cache.demand_misses::total 135264 # number of demand (read+write) misses
558system.cpu.l2cache.overall_misses::cpu.inst 5494 # number of overall misses
559system.cpu.l2cache.overall_misses::cpu.data 129770 # number of overall misses
560system.cpu.l2cache.overall_misses::total 135264 # number of overall misses
561system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188188000 # number of ReadReq miss cycles
562system.cpu.l2cache.ReadReq_miss_latency::cpu.data 930191000 # number of ReadReq miss cycles
563system.cpu.l2cache.ReadReq_miss_latency::total 1118379000 # number of ReadReq miss cycles
564system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3526118000 # number of ReadExReq miss cycles
565system.cpu.l2cache.ReadExReq_miss_latency::total 3526118000 # number of ReadExReq miss cycles
566system.cpu.l2cache.demand_miss_latency::cpu.inst 188188000 # number of demand (read+write) miss cycles
567system.cpu.l2cache.demand_miss_latency::cpu.data 4456309000 # number of demand (read+write) miss cycles
568system.cpu.l2cache.demand_miss_latency::total 4644497000 # number of demand (read+write) miss cycles
569system.cpu.l2cache.overall_miss_latency::cpu.inst 188188000 # number of overall miss cycles
570system.cpu.l2cache.overall_miss_latency::cpu.data 4456309000 # number of overall miss cycles
571system.cpu.l2cache.overall_miss_latency::total 4644497000 # number of overall miss cycles
572system.cpu.l2cache.ReadReq_accesses::cpu.inst 28161 # number of ReadReq accesses(hits+misses)
573system.cpu.l2cache.ReadReq_accesses::cpu.data 55077 # number of ReadReq accesses(hits+misses)
574system.cpu.l2cache.ReadReq_accesses::total 83238 # number of ReadReq accesses(hits+misses)
575system.cpu.l2cache.Writeback_accesses::writebacks 123474 # number of Writeback accesses(hits+misses)
576system.cpu.l2cache.Writeback_accesses::total 123474 # number of Writeback accesses(hits+misses)
577system.cpu.l2cache.UpgradeReq_accesses::cpu.data 44 # number of UpgradeReq accesses(hits+misses)
578system.cpu.l2cache.UpgradeReq_accesses::total 44 # number of UpgradeReq accesses(hits+misses)
579system.cpu.l2cache.ReadExReq_accesses::cpu.data 106907 # number of ReadExReq accesses(hits+misses)
580system.cpu.l2cache.ReadExReq_accesses::total 106907 # number of ReadExReq accesses(hits+misses)
581system.cpu.l2cache.demand_accesses::cpu.inst 28161 # number of demand (read+write) accesses
582system.cpu.l2cache.demand_accesses::cpu.data 161984 # number of demand (read+write) accesses
583system.cpu.l2cache.demand_accesses::total 190145 # number of demand (read+write) accesses
584system.cpu.l2cache.overall_accesses::cpu.inst 28161 # number of overall (read+write) accesses
585system.cpu.l2cache.overall_accesses::cpu.data 161984 # number of overall (read+write) accesses
586system.cpu.l2cache.overall_accesses::total 190145 # number of overall (read+write) accesses
587system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.195093 # miss rate for ReadReq accesses
588system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.493364 # miss rate for ReadReq accesses
589system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.681818 # miss rate for UpgradeReq accesses
590system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959685 # miss rate for ReadExReq accesses
591system.cpu.l2cache.demand_miss_rate::cpu.inst 0.195093 # miss rate for demand accesses
592system.cpu.l2cache.demand_miss_rate::cpu.data 0.801129 # miss rate for demand accesses
593system.cpu.l2cache.overall_miss_rate::cpu.inst 0.195093 # miss rate for overall accesses
594system.cpu.l2cache.overall_miss_rate::cpu.data 0.801129 # miss rate for overall accesses
595system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.367310 # average ReadReq miss latency
596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34232.179001 # average ReadReq miss latency
597system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.626763 # average ReadExReq miss latency
598system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency
599system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency
600system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency
601system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency
602system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
603system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
604system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
605system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
606system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
607system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
608system.cpu.l2cache.fast_writes 0 # number of fast writes performed
609system.cpu.l2cache.cache_copies 0 # number of cache copies performed
610system.cpu.l2cache.writebacks::writebacks 88457 # number of writebacks
611system.cpu.l2cache.writebacks::total 88457 # number of writebacks
612system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits
613system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits
614system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
615system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits
616system.cpu.l2cache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits
617system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
618system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits
619system.cpu.l2cache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits
620system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits
621system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5470 # number of ReadReq MSHR misses
622system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27116 # number of ReadReq MSHR misses
623system.cpu.l2cache.ReadReq_mshr_misses::total 32586 # number of ReadReq MSHR misses
624system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses
625system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses
626system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102597 # number of ReadExReq MSHR misses
627system.cpu.l2cache.ReadExReq_mshr_misses::total 102597 # number of ReadExReq MSHR misses
628system.cpu.l2cache.demand_mshr_misses::cpu.inst 5470 # number of demand (read+write) MSHR misses
629system.cpu.l2cache.demand_mshr_misses::cpu.data 129713 # number of demand (read+write) MSHR misses
630system.cpu.l2cache.demand_mshr_misses::total 135183 # number of demand (read+write) MSHR misses
631system.cpu.l2cache.overall_mshr_misses::cpu.inst 5470 # number of overall MSHR misses
632system.cpu.l2cache.overall_mshr_misses::cpu.data 129713 # number of overall MSHR misses
633system.cpu.l2cache.overall_mshr_misses::total 135183 # number of overall MSHR misses
634system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169929500 # number of ReadReq MSHR miss cycles
635system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 842885000 # number of ReadReq MSHR miss cycles
636system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1012814500 # number of ReadReq MSHR miss cycles
637system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 931000 # number of UpgradeReq MSHR miss cycles
638system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 931000 # number of UpgradeReq MSHR miss cycles
639system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3197894500 # number of ReadExReq MSHR miss cycles
640system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3197894500 # number of ReadExReq MSHR miss cycles
641system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169929500 # number of demand (read+write) MSHR miss cycles
642system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4040779500 # number of demand (read+write) MSHR miss cycles
643system.cpu.l2cache.demand_mshr_miss_latency::total 4210709000 # number of demand (read+write) MSHR miss cycles
644system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169929500 # number of overall MSHR miss cycles
645system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4040779500 # number of overall MSHR miss cycles
646system.cpu.l2cache.overall_mshr_miss_latency::total 4210709000 # number of overall MSHR miss cycles
647system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for ReadReq accesses
648system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.492329 # mshr miss rate for ReadReq accesses
649system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.681818 # mshr miss rate for UpgradeReq accesses
650system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959685 # mshr miss rate for ReadExReq accesses
651system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for demand accesses
652system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for demand accesses
653system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for overall accesses
654system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for overall accesses
655system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.722121 # average ReadReq mshr miss latency
656system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31084.415105 # average ReadReq mshr miss latency
657system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31033.333333 # average UpgradeReq mshr miss latency
658system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31169.473766 # average ReadExReq mshr miss latency
659system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency
660system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency
661system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency
662system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency
663system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
664
665---------- End Simulation Statistics ----------