1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.033525 # Number of seconds simulated
4sim_ticks 33524756000 # Number of ticks simulated
5final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 201547 # Simulator instruction rate (inst/s)
8host_op_rate 257754 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 95290096 # Simulator tick rate (ticks/s)
10host_mem_usage 324320 # Number of bytes of host memory used
11host_seconds 351.82 # Real time elapsed on the host
12sim_insts 70907652 # Number of instructions simulated
13sim_ops 90682607 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory
19system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 697984 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 697984 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 6216960 # Number of bytes written to this memory
23system.physmem.bytes_written::total 6216960 # Number of bytes written to this memory
--- 253 unchanged lines hidden (view full) ---
277system.physmem_1.preBackEnergy 8061404250 # Energy for precharge background per rank (pJ)
278system.physmem_1.totalEnergy 25406746680 # Total energy per rank (pJ)
279system.physmem_1.averagePower 757.956338 # Core power per rank (mW)
280system.physmem_1.memoryStateTime::IDLE 13314860915 # Time in different power states
281system.physmem_1.memoryStateTime::REF 1119300000 # Time in different power states
282system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
283system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states
284system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
285system.cpu.branchPred.lookups 17055826 # Number of BP lookups
286system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted
287system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect
288system.cpu.branchPred.BTBLookups 9258903 # Number of BTB lookups
289system.cpu.branchPred.BTBHits 7371283 # Number of BTB hits
290system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
291system.cpu.branchPred.BTBHitPct 79.612920 # BTB Hit Percentage
292system.cpu.branchPred.usedRAS 1853216 # Number of times the RAS was used to get a target.
293system.cpu.branchPred.RASInCorrect 101575 # Number of incorrect RAS predictions.
294system.cpu.branchPred.indirectLookups 232758 # Number of indirect predictor lookups.
295system.cpu.branchPred.indirectHits 195217 # Number of indirect target hits.
296system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses.
297system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches.
298system.cpu_clk_domain.clock 500 # Clock period in ticks
299system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
320system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
321system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
322system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
323system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
324system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
325system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
326system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
327system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
328system.cpu.dtb.walker.walks 0 # Table walker walks requested
329system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
330system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
331system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
332system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
333system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
334system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
335system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
349system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
350system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
351system.cpu.dtb.read_accesses 0 # DTB read accesses
352system.cpu.dtb.write_accesses 0 # DTB write accesses
353system.cpu.dtb.inst_accesses 0 # ITB inst accesses
354system.cpu.dtb.hits 0 # DTB hits
355system.cpu.dtb.misses 0 # DTB misses
356system.cpu.dtb.accesses 0 # DTB accesses
357system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
378system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
379system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
380system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
381system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
382system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
383system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
384system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
385system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
386system.cpu.itb.walker.walks 0 # Table walker walks requested
387system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
388system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
389system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
390system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
391system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
392system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
393system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 14 unchanged lines hidden (view full) ---
408system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
409system.cpu.itb.read_accesses 0 # DTB read accesses
410system.cpu.itb.write_accesses 0 # DTB write accesses
411system.cpu.itb.inst_accesses 0 # ITB inst accesses
412system.cpu.itb.hits 0 # DTB hits
413system.cpu.itb.misses 0 # DTB misses
414system.cpu.itb.accesses 0 # DTB accesses
415system.cpu.workload.num_syscalls 1946 # Number of system calls
416system.cpu.numCycles 67049513 # number of cpu cycles simulated
417system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
418system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
419system.cpu.fetch.icacheStallCycles 5112037 # Number of cycles fetch is stalled on an Icache miss
420system.cpu.fetch.Insts 87027076 # Number of instructions fetch has processed
421system.cpu.fetch.Branches 17055826 # Number of branches that fetch encountered
422system.cpu.fetch.predictedBranches 9419716 # Number of branches that fetch has predicted taken
423system.cpu.fetch.Cycles 60300614 # Number of cycles fetch has run and was not squashing or blocked
--- 274 unchanged lines hidden (view full) ---
698system.cpu.int_regfile_reads 102008139 # number of integer regfile reads
699system.cpu.int_regfile_writes 56630693 # number of integer regfile writes
700system.cpu.fp_regfile_reads 48 # number of floating regfile reads
701system.cpu.fp_regfile_writes 42 # number of floating regfile writes
702system.cpu.cc_regfile_reads 345209533 # number of cc regfile reads
703system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes
704system.cpu.misc_regfile_reads 44112661 # number of misc regfile reads
705system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
706system.cpu.dcache.tags.replacements 486293 # number of replacements
707system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use
708system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks.
709system.cpu.dcache.tags.sampled_refs 486805 # Sample count of references to valid blocks.
710system.cpu.dcache.tags.avg_refs 82.847407 # Average number of references to valid blocks.
711system.cpu.dcache.tags.warmup_cycle 150823500 # Cycle when the warmup percentage was hit.
712system.cpu.dcache.tags.occ_blocks::cpu.data 510.756058 # Average occupied blocks per requestor
713system.cpu.dcache.tags.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy
714system.cpu.dcache.tags.occ_percent::total 0.997570 # Average percentage of cache occupancy
715system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
716system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
717system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id
718system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
719system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses
720system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses
721system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits
722system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits
723system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits
724system.cpu.dcache.WriteReq_hits::total 18832689 # number of WriteReq hits
725system.cpu.dcache.SoftPFReq_hits::cpu.data 59994 # number of SoftPFReq hits
726system.cpu.dcache.SoftPFReq_hits::total 59994 # number of SoftPFReq hits
727system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits
728system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits
--- 114 unchanged lines hidden (view full) ---
843system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency
844system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency
845system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency
846system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency
847system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency
848system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency
849system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency
850system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency
851system.cpu.icache.tags.replacements 325000 # number of replacements
852system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use
853system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks.
854system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks.
855system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks.
856system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit.
857system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor
858system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy
859system.cpu.icache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy
860system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
861system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
862system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
863system.cpu.icache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
864system.cpu.icache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id
865system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id
866system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
867system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses
868system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses
869system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits
870system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits
871system.cpu.icache.demand_hits::cpu.inst 22083387 # number of demand (read+write) hits
872system.cpu.icache.demand_hits::total 22083387 # number of demand (read+write) hits
873system.cpu.icache.overall_hits::cpu.inst 22083387 # number of overall hits
874system.cpu.icache.overall_hits::total 22083387 # number of overall hits
875system.cpu.icache.ReadReq_misses::cpu.inst 334707 # number of ReadReq misses
876system.cpu.icache.ReadReq_misses::total 334707 # number of ReadReq misses
--- 58 unchanged lines hidden (view full) ---
935system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for overall accesses
936system.cpu.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses
937system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037 # average ReadReq mshr miss latency
938system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037 # average ReadReq mshr miss latency
939system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency
940system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency
941system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency
942system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency
943system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued
944system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified
945system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue
946system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
947system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
948system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing
949system.cpu.l2cache.tags.replacements 128177 # number of replacements
950system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use
951system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks.
952system.cpu.l2cache.tags.sampled_refs 144531 # Sample count of references to valid blocks.
953system.cpu.l2cache.tags.avg_refs 8.195986 # Average number of references to valid blocks.
954system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
955system.cpu.l2cache.tags.occ_blocks::writebacks 15883.544788 # Average occupied blocks per requestor
956system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 105.518503 # Average occupied blocks per requestor
--- 10 unchanged lines hidden (view full) ---
967system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2742 # Occupied blocks per task id
968system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12115 # Occupied blocks per task id
969system.cpu.l2cache.tags.age_task_id_blocks_1024::3 553 # Occupied blocks per task id
970system.cpu.l2cache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id
971system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001831 # Percentage of cache occupancy per task id
972system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996338 # Percentage of cache occupancy per task id
973system.cpu.l2cache.tags.tag_accesses 25089114 # Number of tag accesses
974system.cpu.l2cache.tags.data_accesses 25089114 # Number of data accesses
975system.cpu.l2cache.WritebackDirty_hits::writebacks 260314 # number of WritebackDirty hits
976system.cpu.l2cache.WritebackDirty_hits::total 260314 # number of WritebackDirty hits
977system.cpu.l2cache.WritebackClean_hits::writebacks 470737 # number of WritebackClean hits
978system.cpu.l2cache.WritebackClean_hits::total 470737 # number of WritebackClean hits
979system.cpu.l2cache.ReadExReq_hits::cpu.data 137093 # number of ReadExReq hits
980system.cpu.l2cache.ReadExReq_hits::total 137093 # number of ReadExReq hits
981system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 314576 # number of ReadCleanReq hits
982system.cpu.l2cache.ReadCleanReq_hits::total 314576 # number of ReadCleanReq hits
--- 165 unchanged lines hidden (view full) ---
1148system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency
1149system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency
1150system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter.
1151system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1152system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1153system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter.
1154system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1155system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1156system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution
1157system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution
1158system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution
1159system.cpu.toL2Bus.trans_dist::CleanEvict 79349 # Transaction distribution
1160system.cpu.toL2Bus.trans_dist::HardPFReq 142185 # Transaction distribution
1161system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
1162system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
1163system.cpu.toL2Bus.trans_dist::ReadExReq 148612 # Transaction distribution
--- 19 unchanged lines hidden (view full) ---
1183system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1184system.cpu.toL2Bus.snoop_fanout::total 1131024 # Request fanout histogram
1185system.cpu.toL2Bus.reqLayer0.occupancy 1623114500 # Layer occupancy (ticks)
1186system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%)
1187system.cpu.toL2Bus.respLayer0.occupancy 488687208 # Layer occupancy (ticks)
1188system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
1189system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks)
1190system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%)
1191system.membus.trans_dist::ReadResp 144751 # Transaction distribution
1192system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution
1193system.membus.trans_dist::CleanEvict 28117 # Transaction distribution
1194system.membus.trans_dist::UpgradeReq 16 # Transaction distribution
1195system.membus.trans_dist::ReadExReq 8337 # Transaction distribution
1196system.membus.trans_dist::ReadExResp 8337 # Transaction distribution
1197system.membus.trans_dist::ReadSharedReq 144752 # Transaction distribution
1198system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431450 # Packet count per connected master and slave (bytes)
--- 20 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.033525 # Number of seconds simulated
4sim_ticks 33524756000 # Number of ticks simulated
5final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 201547 # Simulator instruction rate (inst/s)
8host_op_rate 257754 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 95290096 # Simulator tick rate (ticks/s)
10host_mem_usage 324320 # Number of bytes of host memory used
11host_seconds 351.82 # Real time elapsed on the host
12sim_insts 70907652 # Number of instructions simulated
13sim_ops 90682607 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory
19system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 697984 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 697984 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 6216960 # Number of bytes written to this memory
23system.physmem.bytes_written::total 6216960 # Number of bytes written to this memory
--- 253 unchanged lines hidden (view full) ---
277system.physmem_1.preBackEnergy 8061404250 # Energy for precharge background per rank (pJ)
278system.physmem_1.totalEnergy 25406746680 # Total energy per rank (pJ)
279system.physmem_1.averagePower 757.956338 # Core power per rank (mW)
280system.physmem_1.memoryStateTime::IDLE 13314860915 # Time in different power states
281system.physmem_1.memoryStateTime::REF 1119300000 # Time in different power states
282system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
283system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states
284system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
285system.cpu.branchPred.lookups 17055826 # Number of BP lookups
286system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted
287system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect
288system.cpu.branchPred.BTBLookups 9258903 # Number of BTB lookups
289system.cpu.branchPred.BTBHits 7371283 # Number of BTB hits
290system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
291system.cpu.branchPred.BTBHitPct 79.612920 # BTB Hit Percentage
292system.cpu.branchPred.usedRAS 1853216 # Number of times the RAS was used to get a target.
293system.cpu.branchPred.RASInCorrect 101575 # Number of incorrect RAS predictions.
294system.cpu.branchPred.indirectLookups 232758 # Number of indirect predictor lookups.
295system.cpu.branchPred.indirectHits 195217 # Number of indirect target hits.
296system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses.
297system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches.
298system.cpu_clk_domain.clock 500 # Clock period in ticks
299system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
320system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
321system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
322system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
323system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
324system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
325system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
326system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
327system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
328system.cpu.dtb.walker.walks 0 # Table walker walks requested
329system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
330system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
331system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
332system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
333system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
334system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
335system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
349system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
350system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
351system.cpu.dtb.read_accesses 0 # DTB read accesses
352system.cpu.dtb.write_accesses 0 # DTB write accesses
353system.cpu.dtb.inst_accesses 0 # ITB inst accesses
354system.cpu.dtb.hits 0 # DTB hits
355system.cpu.dtb.misses 0 # DTB misses
356system.cpu.dtb.accesses 0 # DTB accesses
357system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
378system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
379system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
380system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
381system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
382system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
383system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
384system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
385system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
386system.cpu.itb.walker.walks 0 # Table walker walks requested
387system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
388system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
389system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
390system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
391system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
392system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
393system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 14 unchanged lines hidden (view full) ---
408system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
409system.cpu.itb.read_accesses 0 # DTB read accesses
410system.cpu.itb.write_accesses 0 # DTB write accesses
411system.cpu.itb.inst_accesses 0 # ITB inst accesses
412system.cpu.itb.hits 0 # DTB hits
413system.cpu.itb.misses 0 # DTB misses
414system.cpu.itb.accesses 0 # DTB accesses
415system.cpu.workload.num_syscalls 1946 # Number of system calls
416system.cpu.numCycles 67049513 # number of cpu cycles simulated
417system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
418system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
419system.cpu.fetch.icacheStallCycles 5112037 # Number of cycles fetch is stalled on an Icache miss
420system.cpu.fetch.Insts 87027076 # Number of instructions fetch has processed
421system.cpu.fetch.Branches 17055826 # Number of branches that fetch encountered
422system.cpu.fetch.predictedBranches 9419716 # Number of branches that fetch has predicted taken
423system.cpu.fetch.Cycles 60300614 # Number of cycles fetch has run and was not squashing or blocked
--- 274 unchanged lines hidden (view full) ---
698system.cpu.int_regfile_reads 102008139 # number of integer regfile reads
699system.cpu.int_regfile_writes 56630693 # number of integer regfile writes
700system.cpu.fp_regfile_reads 48 # number of floating regfile reads
701system.cpu.fp_regfile_writes 42 # number of floating regfile writes
702system.cpu.cc_regfile_reads 345209533 # number of cc regfile reads
703system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes
704system.cpu.misc_regfile_reads 44112661 # number of misc regfile reads
705system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
706system.cpu.dcache.tags.replacements 486293 # number of replacements
707system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use
708system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks.
709system.cpu.dcache.tags.sampled_refs 486805 # Sample count of references to valid blocks.
710system.cpu.dcache.tags.avg_refs 82.847407 # Average number of references to valid blocks.
711system.cpu.dcache.tags.warmup_cycle 150823500 # Cycle when the warmup percentage was hit.
712system.cpu.dcache.tags.occ_blocks::cpu.data 510.756058 # Average occupied blocks per requestor
713system.cpu.dcache.tags.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy
714system.cpu.dcache.tags.occ_percent::total 0.997570 # Average percentage of cache occupancy
715system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
716system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
717system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id
718system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
719system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses
720system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses
721system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits
722system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits
723system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits
724system.cpu.dcache.WriteReq_hits::total 18832689 # number of WriteReq hits
725system.cpu.dcache.SoftPFReq_hits::cpu.data 59994 # number of SoftPFReq hits
726system.cpu.dcache.SoftPFReq_hits::total 59994 # number of SoftPFReq hits
727system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits
728system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits
--- 114 unchanged lines hidden (view full) ---
843system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency
844system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency
845system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency
846system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency
847system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency
848system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency
849system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency
850system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency
851system.cpu.icache.tags.replacements 325000 # number of replacements
852system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use
853system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks.
854system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks.
855system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks.
856system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit.
857system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor
858system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy
859system.cpu.icache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy
860system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
861system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
862system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
863system.cpu.icache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
864system.cpu.icache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id
865system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id
866system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
867system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses
868system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses
869system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits
870system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits
871system.cpu.icache.demand_hits::cpu.inst 22083387 # number of demand (read+write) hits
872system.cpu.icache.demand_hits::total 22083387 # number of demand (read+write) hits
873system.cpu.icache.overall_hits::cpu.inst 22083387 # number of overall hits
874system.cpu.icache.overall_hits::total 22083387 # number of overall hits
875system.cpu.icache.ReadReq_misses::cpu.inst 334707 # number of ReadReq misses
876system.cpu.icache.ReadReq_misses::total 334707 # number of ReadReq misses
--- 58 unchanged lines hidden (view full) ---
935system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for overall accesses
936system.cpu.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses
937system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037 # average ReadReq mshr miss latency
938system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037 # average ReadReq mshr miss latency
939system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency
940system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency
941system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency
942system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency
943system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued
944system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified
945system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue
946system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
947system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
948system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing
949system.cpu.l2cache.tags.replacements 128177 # number of replacements
950system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use
951system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks.
952system.cpu.l2cache.tags.sampled_refs 144531 # Sample count of references to valid blocks.
953system.cpu.l2cache.tags.avg_refs 8.195986 # Average number of references to valid blocks.
954system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
955system.cpu.l2cache.tags.occ_blocks::writebacks 15883.544788 # Average occupied blocks per requestor
956system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 105.518503 # Average occupied blocks per requestor
--- 10 unchanged lines hidden (view full) ---
967system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2742 # Occupied blocks per task id
968system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12115 # Occupied blocks per task id
969system.cpu.l2cache.tags.age_task_id_blocks_1024::3 553 # Occupied blocks per task id
970system.cpu.l2cache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id
971system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001831 # Percentage of cache occupancy per task id
972system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996338 # Percentage of cache occupancy per task id
973system.cpu.l2cache.tags.tag_accesses 25089114 # Number of tag accesses
974system.cpu.l2cache.tags.data_accesses 25089114 # Number of data accesses
975system.cpu.l2cache.WritebackDirty_hits::writebacks 260314 # number of WritebackDirty hits
976system.cpu.l2cache.WritebackDirty_hits::total 260314 # number of WritebackDirty hits
977system.cpu.l2cache.WritebackClean_hits::writebacks 470737 # number of WritebackClean hits
978system.cpu.l2cache.WritebackClean_hits::total 470737 # number of WritebackClean hits
979system.cpu.l2cache.ReadExReq_hits::cpu.data 137093 # number of ReadExReq hits
980system.cpu.l2cache.ReadExReq_hits::total 137093 # number of ReadExReq hits
981system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 314576 # number of ReadCleanReq hits
982system.cpu.l2cache.ReadCleanReq_hits::total 314576 # number of ReadCleanReq hits
--- 165 unchanged lines hidden (view full) ---
1148system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency
1149system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency
1150system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter.
1151system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1152system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1153system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter.
1154system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1155system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1156system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution
1157system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution
1158system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution
1159system.cpu.toL2Bus.trans_dist::CleanEvict 79349 # Transaction distribution
1160system.cpu.toL2Bus.trans_dist::HardPFReq 142185 # Transaction distribution
1161system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
1162system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
1163system.cpu.toL2Bus.trans_dist::ReadExReq 148612 # Transaction distribution
--- 19 unchanged lines hidden (view full) ---
1183system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1184system.cpu.toL2Bus.snoop_fanout::total 1131024 # Request fanout histogram
1185system.cpu.toL2Bus.reqLayer0.occupancy 1623114500 # Layer occupancy (ticks)
1186system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%)
1187system.cpu.toL2Bus.respLayer0.occupancy 488687208 # Layer occupancy (ticks)
1188system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
1189system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks)
1190system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%)
1191system.membus.trans_dist::ReadResp 144751 # Transaction distribution
1192system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution
1193system.membus.trans_dist::CleanEvict 28117 # Transaction distribution
1194system.membus.trans_dist::UpgradeReq 16 # Transaction distribution
1195system.membus.trans_dist::ReadExReq 8337 # Transaction distribution
1196system.membus.trans_dist::ReadExResp 8337 # Transaction distribution
1197system.membus.trans_dist::ReadSharedReq 144752 # Transaction distribution
1198system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431450 # Packet count per connected master and slave (bytes)
--- 20 unchanged lines hidden ---