1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.023896 # Number of seconds simulated
4sim_ticks 23896420500 # Number of ticks simulated
5final_tick 23896420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 105740 # Simulator instruction rate (inst/s)
8host_op_rate 135229 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 35635051 # Simulator tick rate (ticks/s)
10host_mem_usage 262840 # Number of bytes of host memory used
11host_seconds 670.59 # Real time elapsed on the host
12sim_insts 70907629 # Number of instructions simulated
13sim_ops 90682584 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 299392 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7936704 # Number of bytes read from this memory
18system.physmem.bytes_read::total 8236096 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 299392 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 299392 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory
22system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 4678 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 124011 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 128689 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 12528738 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 332129408 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 344658147 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 12528738 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 12528738 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 224837021 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 224837021 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 224837021 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 12528738 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 332129408 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 569495168 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 128689 # Number of read requests accepted
40system.physmem.writeReqs 83950 # Number of write requests accepted
41system.physmem.readBursts 128689 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 8235648 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
45system.physmem.bytesWritten 5371072 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 8236096 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 380 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 8141 # Per bank write bursts
52system.physmem.perBankRdBursts::1 8384 # Per bank write bursts
53system.physmem.perBankRdBursts::2 8239 # Per bank write bursts
54system.physmem.perBankRdBursts::3 8150 # Per bank write bursts
55system.physmem.perBankRdBursts::4 8295 # Per bank write bursts
56system.physmem.perBankRdBursts::5 8428 # Per bank write bursts
57system.physmem.perBankRdBursts::6 8074 # Per bank write bursts
58system.physmem.perBankRdBursts::7 7958 # Per bank write bursts
59system.physmem.perBankRdBursts::8 8067 # Per bank write bursts
60system.physmem.perBankRdBursts::9 7598 # Per bank write bursts
61system.physmem.perBankRdBursts::10 7783 # Per bank write bursts
62system.physmem.perBankRdBursts::11 7813 # Per bank write bursts
63system.physmem.perBankRdBursts::12 7877 # Per bank write bursts
64system.physmem.perBankRdBursts::13 7881 # Per bank write bursts
65system.physmem.perBankRdBursts::14 7983 # Per bank write bursts
66system.physmem.perBankRdBursts::15 8011 # Per bank write bursts
67system.physmem.perBankWrBursts::0 5183 # Per bank write bursts
68system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
69system.physmem.perBankWrBursts::2 5289 # Per bank write bursts
70system.physmem.perBankWrBursts::3 5157 # Per bank write bursts
71system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
72system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
73system.physmem.perBankWrBursts::6 5198 # Per bank write bursts
74system.physmem.perBankWrBursts::7 5051 # Per bank write bursts
75system.physmem.perBankWrBursts::8 5029 # Per bank write bursts
76system.physmem.perBankWrBursts::9 5090 # Per bank write bursts
77system.physmem.perBankWrBursts::10 5246 # Per bank write bursts
78system.physmem.perBankWrBursts::11 5140 # Per bank write bursts
79system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
80system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
81system.physmem.perBankWrBursts::14 5452 # Per bank write bursts
82system.physmem.perBankWrBursts::15 5223 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 23896016500 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 128689 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 83950 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 68784 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 50927 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 6546 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 2414 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see

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139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 2057 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 3691 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 4468 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 4948 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 5202 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 5301 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 5438 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 5521 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 5545 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 5656 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 6068 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 5800 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 6220 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::32 5413 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see

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188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196system.physmem.bytesPerActivate::samples 37607 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::mean 361.810089 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::gmean 217.183531 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::stdev 344.455844 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::0-127 11970 31.83% 31.83% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::128-255 7877 20.95% 52.77% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::256-383 3759 10.00% 62.77% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::384-511 2606 6.93% 69.70% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::512-639 2473 6.58% 76.28% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::640-767 1554 4.13% 80.41% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::768-895 1216 3.23% 83.64% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::896-1023 1043 2.77% 86.41% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1024-1151 5109 13.59% 100.00% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::total 37607 # Bytes accessed per row activation
210system.physmem.rdPerTurnAround::samples 5143 # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::mean 25.009139 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::stdev 391.762417 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::0-1023 5141 99.96% 99.96% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::total 5143 # Reads before turning the bus around for writes
217system.physmem.wrPerTurnAround::samples 5143 # Writes before turning the bus around for reads
218system.physmem.wrPerTurnAround::mean 16.317908 # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::gmean 16.294258 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::stdev 0.943897 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::16 4493 87.36% 87.36% # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::17 13 0.25% 87.61% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::18 424 8.24% 95.86% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::19 146 2.84% 98.70% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::20 43 0.84% 99.53% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::21 15 0.29% 99.83% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::22 3 0.06% 99.88% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::23 1 0.02% 99.90% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::27 1 0.02% 99.94% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::28 1 0.02% 99.96% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::32 2 0.04% 100.00% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::total 5143 # Writes before turning the bus around for reads
234system.physmem.totQLat 2744774250 # Total ticks spent queuing
235system.physmem.totMemAccLat 5157561750 # Total ticks spent from burst creation until serviced by the DRAM
236system.physmem.totBusLat 643410000 # Total ticks spent in databus transfers
237system.physmem.avgQLat 21329.90 # Average queueing delay per DRAM burst
238system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
239system.physmem.avgMemAccLat 40079.90 # Average memory access latency per DRAM burst
240system.physmem.avgRdBW 344.64 # Average DRAM read bandwidth in MiByte/s
241system.physmem.avgWrBW 224.76 # Average achieved write bandwidth in MiByte/s
242system.physmem.avgRdBWSys 344.66 # Average system read bandwidth in MiByte/s
243system.physmem.avgWrBWSys 224.84 # Average system write bandwidth in MiByte/s
244system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
245system.physmem.busUtil 4.45 # Data bus utilization in percentage
246system.physmem.busUtilRead 2.69 # Data bus utilization in percentage for reads
247system.physmem.busUtilWrite 1.76 # Data bus utilization in percentage for writes
248system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing
249system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing
250system.physmem.readRowHits 112874 # Number of row buffer hits during reads
251system.physmem.writeRowHits 62123 # Number of row buffer hits during writes
252system.physmem.readRowHitRate 87.72 # Row buffer hit rate for reads
253system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes
254system.physmem.avgGap 112378.33 # Average gap between requests
255system.physmem.pageHitRate 82.30 # Row buffer hit rate, read and write combined
256system.physmem.memoryStateTime::IDLE 9567571500 # Time in different power states
257system.physmem.memoryStateTime::REF 797940000 # Time in different power states
258system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
259system.physmem.memoryStateTime::ACT 13530763500 # Time in different power states
260system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
261system.membus.throughput 569495168 # Throughput (bytes/s)
262system.membus.trans_dist::ReadReq 26431 # Transaction distribution
263system.membus.trans_dist::ReadResp 26431 # Transaction distribution
264system.membus.trans_dist::Writeback 83950 # Transaction distribution
265system.membus.trans_dist::UpgradeReq 380 # Transaction distribution
266system.membus.trans_dist::UpgradeResp 380 # Transaction distribution
267system.membus.trans_dist::ReadExReq 102258 # Transaction distribution
268system.membus.trans_dist::ReadExResp 102258 # Transaction distribution
269system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342088 # Packet count per connected master and slave (bytes)
270system.membus.pkt_count::total 342088 # Packet count per connected master and slave (bytes)
271system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13608896 # Cumulative packet size per connected master and slave (bytes)
272system.membus.tot_pkt_size::total 13608896 # Cumulative packet size per connected master and slave (bytes)
273system.membus.data_through_bus 13608896 # Total data (bytes)
274system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
275system.membus.reqLayer0.occupancy 898146000 # Layer occupancy (ticks)
276system.membus.reqLayer0.utilization 3.8 # Layer utilization (%)
277system.membus.respLayer1.occupancy 1183170872 # Layer occupancy (ticks)
278system.membus.respLayer1.utilization 5.0 # Layer utilization (%)
279system.cpu_clk_domain.clock 500 # Clock period in ticks
280system.cpu.branchPred.lookups 17877019 # Number of BP lookups
281system.cpu.branchPred.condPredicted 11927811 # Number of conditional branches predicted
282system.cpu.branchPred.condIncorrect 593439 # Number of conditional branches incorrect
283system.cpu.branchPred.BTBLookups 11204319 # Number of BTB lookups
284system.cpu.branchPred.BTBHits 8313088 # Number of BTB hits
285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
286system.cpu.branchPred.BTBHitPct 74.195388 # BTB Hit Percentage
287system.cpu.branchPred.usedRAS 1978187 # Number of times the RAS was used to get a target.
288system.cpu.branchPred.RASInCorrect 104069 # Number of incorrect RAS predictions.
289system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
290system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
291system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
292system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
293system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
294system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
295system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
296system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

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366system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
367system.cpu.itb.read_accesses 0 # DTB read accesses
368system.cpu.itb.write_accesses 0 # DTB write accesses
369system.cpu.itb.inst_accesses 0 # ITB inst accesses
370system.cpu.itb.hits 0 # DTB hits
371system.cpu.itb.misses 0 # DTB misses
372system.cpu.itb.accesses 0 # DTB accesses
373system.cpu.workload.num_syscalls 1946 # Number of system calls
374system.cpu.numCycles 47792842 # number of cpu cycles simulated
375system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
376system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
377system.cpu.fetch.icacheStallCycles 13399730 # Number of cycles fetch is stalled on an Icache miss
378system.cpu.fetch.Insts 91818563 # Number of instructions fetch has processed
379system.cpu.fetch.Branches 17877019 # Number of branches that fetch encountered
380system.cpu.fetch.predictedBranches 10291275 # Number of branches that fetch has predicted taken
381system.cpu.fetch.Cycles 33374868 # Number of cycles fetch has run and was not squashing or blocked
382system.cpu.fetch.SquashCycles 1293258 # Number of cycles fetch has spent squashing
383system.cpu.fetch.MiscStallCycles 460 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
384system.cpu.fetch.PendingTrapStallCycles 3119 # Number of stall cycles due to pending traps
385system.cpu.fetch.IcacheWaitRetryStallCycles 70 # Number of stall cycles due to full MSHR
386system.cpu.fetch.CacheLines 12485707 # Number of cache lines fetched
387system.cpu.fetch.IcacheSquashes 222370 # Number of outstanding Icache misses that were squashed
388system.cpu.fetch.rateDist::samples 47424876 # Number of instructions fetched each cycle (Total)
389system.cpu.fetch.rateDist::mean 2.444936 # Number of instructions fetched each cycle (Total)
390system.cpu.fetch.rateDist::stdev 3.221090 # Number of instructions fetched each cycle (Total)
391system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
392system.cpu.fetch.rateDist::0 25840907 54.49% 54.49% # Number of instructions fetched each cycle (Total)
393system.cpu.fetch.rateDist::1 2398343 5.06% 59.55% # Number of instructions fetched each cycle (Total)
394system.cpu.fetch.rateDist::2 2102611 4.43% 63.98% # Number of instructions fetched each cycle (Total)
395system.cpu.fetch.rateDist::3 2392037 5.04% 69.02% # Number of instructions fetched each cycle (Total)
396system.cpu.fetch.rateDist::4 1862029 3.93% 72.95% # Number of instructions fetched each cycle (Total)
397system.cpu.fetch.rateDist::5 1496992 3.16% 76.11% # Number of instructions fetched each cycle (Total)
398system.cpu.fetch.rateDist::6 1004992 2.12% 78.22% # Number of instructions fetched each cycle (Total)
399system.cpu.fetch.rateDist::7 1407650 2.97% 81.19% # Number of instructions fetched each cycle (Total)
400system.cpu.fetch.rateDist::8 8919315 18.81% 100.00% # Number of instructions fetched each cycle (Total)
401system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
402system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
403system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
404system.cpu.fetch.rateDist::total 47424876 # Number of instructions fetched each cycle (Total)
405system.cpu.fetch.branchRate 0.374052 # Number of branch fetches per cycle
406system.cpu.fetch.rate 1.921178 # Number of inst fetches per cycle
407system.cpu.decode.IdleCycles 9991238 # Number of cycles decode is idle
408system.cpu.decode.BlockedCycles 18372924 # Number of cycles decode is blocked
409system.cpu.decode.RunCycles 15962018 # Number of cycles decode is running
410system.cpu.decode.UnblockCycles 2553700 # Number of cycles decode is unblocking
411system.cpu.decode.SquashCycles 544996 # Number of cycles decode is squashing
412system.cpu.decode.BranchResolved 3514191 # Number of times decode resolved a branch
413system.cpu.decode.BranchMispred 104008 # Number of times decode detected a branch misprediction
414system.cpu.decode.DecodedInsts 110994138 # Number of instructions handled by decode
415system.cpu.decode.SquashedInsts 375319 # Number of squashed instructions handled by decode
416system.cpu.rename.SquashCycles 544996 # Number of cycles rename is squashing
417system.cpu.rename.IdleCycles 11354333 # Number of cycles rename is idle
418system.cpu.rename.BlockCycles 2895918 # Number of cycles rename is blocking
419system.cpu.rename.serializeStallCycles 1063087 # count of cycles rename stalled for serializing inst
420system.cpu.rename.RunCycles 17104266 # Number of cycles rename is running
421system.cpu.rename.UnblockCycles 14462276 # Number of cycles rename is unblocking
422system.cpu.rename.RenamedInsts 108881212 # Number of instructions processed by rename
423system.cpu.rename.ROBFullEvents 1310 # Number of times rename has blocked due to ROB full
424system.cpu.rename.IQFullEvents 1983947 # Number of times rename has blocked due to IQ full
425system.cpu.rename.LQFullEvents 2643349 # Number of times rename has blocked due to LQ full
426system.cpu.rename.SQFullEvents 9691184 # Number of times rename has blocked due to SQ full
427system.cpu.rename.RenamedOperands 114456313 # Number of destination operands rename has renamed
428system.cpu.rename.RenameLookups 501643948 # Number of register rename lookups that rename has made
429system.cpu.rename.int_rename_lookups 126478316 # Number of integer rename lookups
430system.cpu.rename.fp_rename_lookups 2998 # Number of floating rename lookups
431system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed
432system.cpu.rename.UndoneMaps 20827087 # Number of HB maps that are undone due to squashing
433system.cpu.rename.serializingInsts 24787 # count of serializing insts renamed
434system.cpu.rename.tempSerializingInsts 25137 # count of temporary serializing insts renamed
435system.cpu.rename.skidInsts 12915604 # count of insts added to the skid buffer
436system.cpu.memDep0.insertedLoads 25719384 # Number of loads inserted to the mem dependence unit.
437system.cpu.memDep0.insertedStores 23405570 # Number of stores inserted to the mem dependence unit.
438system.cpu.memDep0.conflictingLoads 6651489 # Number of conflicting loads.
439system.cpu.memDep0.conflictingStores 7812944 # Number of conflicting stores.
440system.cpu.iq.iqInstsAdded 105238243 # Number of instructions added to the IQ (excludes non-spec)
441system.cpu.iq.iqNonSpecInstsAdded 38026 # Number of non-speculative instructions added to the IQ
442system.cpu.iq.iqInstsIssued 99646497 # Number of instructions issued
443system.cpu.iq.iqSquashedInstsIssued 159437 # Number of squashed instructions issued
444system.cpu.iq.iqSquashedInstsExamined 14433434 # Number of squashed instructions iterated over during squash; mainly for profiling
445system.cpu.iq.iqSquashedOperandsExamined 35646535 # Number of squashed operands that are examined and possibly removed from graph
446system.cpu.iq.iqSquashedNonSpecRemoved 4240 # Number of squashed non-spec instructions that were removed
447system.cpu.iq.issued_per_cycle::samples 47424876 # Number of insts issued each cycle
448system.cpu.iq.issued_per_cycle::mean 2.101144 # Number of insts issued each cycle
449system.cpu.iq.issued_per_cycle::stdev 2.177334 # Number of insts issued each cycle
450system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
451system.cpu.iq.issued_per_cycle::0 16924239 35.69% 35.69% # Number of insts issued each cycle
452system.cpu.iq.issued_per_cycle::1 6535440 13.78% 49.47% # Number of insts issued each cycle
453system.cpu.iq.issued_per_cycle::2 6148782 12.97% 62.43% # Number of insts issued each cycle
454system.cpu.iq.issued_per_cycle::3 5092843 10.74% 73.17% # Number of insts issued each cycle
455system.cpu.iq.issued_per_cycle::4 5223877 11.02% 84.19% # Number of insts issued each cycle
456system.cpu.iq.issued_per_cycle::5 3271997 6.90% 91.09% # Number of insts issued each cycle
457system.cpu.iq.issued_per_cycle::6 2206801 4.65% 95.74% # Number of insts issued each cycle
458system.cpu.iq.issued_per_cycle::7 1128511 2.38% 98.12% # Number of insts issued each cycle
459system.cpu.iq.issued_per_cycle::8 892386 1.88% 100.00% # Number of insts issued each cycle
460system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
461system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
462system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
463system.cpu.iq.issued_per_cycle::total 47424876 # Number of insts issued each cycle
464system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
465system.cpu.iq.fu_full::IntAlu 215167 9.06% 9.06% # attempts to use FU when none available
466system.cpu.iq.fu_full::IntMult 0 0.00% 9.06% # attempts to use FU when none available
467system.cpu.iq.fu_full::IntDiv 0 0.00% 9.06% # attempts to use FU when none available
468system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.06% # attempts to use FU when none available
469system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.06% # attempts to use FU when none available
470system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.06% # attempts to use FU when none available
471system.cpu.iq.fu_full::FloatMult 0 0.00% 9.06% # attempts to use FU when none available
472system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.06% # attempts to use FU when none available
473system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.06% # attempts to use FU when none available
474system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.06% # attempts to use FU when none available
475system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.06% # attempts to use FU when none available
476system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.06% # attempts to use FU when none available
477system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.06% # attempts to use FU when none available
478system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.06% # attempts to use FU when none available
479system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.06% # attempts to use FU when none available
480system.cpu.iq.fu_full::SimdMult 0 0.00% 9.06% # attempts to use FU when none available
481system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.06% # attempts to use FU when none available
482system.cpu.iq.fu_full::SimdShift 0 0.00% 9.06% # attempts to use FU when none available
483system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.06% # attempts to use FU when none available
484system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.06% # attempts to use FU when none available
485system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.06% # attempts to use FU when none available
486system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.06% # attempts to use FU when none available
487system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.06% # attempts to use FU when none available
488system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.06% # attempts to use FU when none available
489system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.06% # attempts to use FU when none available
490system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.06% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.06% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.06% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.06% # attempts to use FU when none available
494system.cpu.iq.fu_full::MemRead 1190055 50.09% 59.14% # attempts to use FU when none available
495system.cpu.iq.fu_full::MemWrite 970810 40.86% 100.00% # attempts to use FU when none available
496system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
497system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
498system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
499system.cpu.iq.FU_type_0::IntAlu 51976863 52.16% 52.16% # Type of FU issued
500system.cpu.iq.FU_type_0::IntMult 92995 0.09% 52.25% # Type of FU issued
501system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued
502system.cpu.iq.FU_type_0::FloatAdd 147 0.00% 52.25% # Type of FU issued
503system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued
504system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued
505system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued
506system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued
507system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued
508system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued
509system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued
510system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued
511system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued
512system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued
513system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued
514system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued
515system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued
516system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued
517system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued
518system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued
519system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued
520system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued
521system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued
522system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued
523system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued
524system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued
525system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued
526system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued
527system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued
528system.cpu.iq.FU_type_0::MemRead 25513927 25.60% 77.86% # Type of FU issued
529system.cpu.iq.FU_type_0::MemWrite 22062558 22.14% 100.00% # Type of FU issued
530system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
531system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
532system.cpu.iq.FU_type_0::total 99646497 # Type of FU issued
533system.cpu.iq.rate 2.084967 # Inst issue rate
534system.cpu.iq.fu_busy_cnt 2376032 # FU busy when requested
535system.cpu.iq.fu_busy_rate 0.023845 # FU busy rate (busy events/executed inst)
536system.cpu.iq.int_inst_queue_reads 249252729 # Number of integer instruction queue reads
537system.cpu.iq.int_inst_queue_writes 119771582 # Number of integer instruction queue writes
538system.cpu.iq.int_inst_queue_wakeup_accesses 97191472 # Number of integer instruction queue wakeup accesses
539system.cpu.iq.fp_inst_queue_reads 610 # Number of floating instruction queue reads
540system.cpu.iq.fp_inst_queue_writes 940 # Number of floating instruction queue writes
541system.cpu.iq.fp_inst_queue_wakeup_accesses 210 # Number of floating instruction queue wakeup accesses
542system.cpu.iq.int_alu_accesses 102022220 # Number of integer alu accesses
543system.cpu.iq.fp_alu_accesses 309 # Number of floating point alu accesses
544system.cpu.iew.lsq.thread0.forwLoads 2232705 # Number of loads that had data forwarded from stores
545system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
546system.cpu.iew.lsq.thread0.squashedLoads 2853122 # Number of loads squashed
547system.cpu.iew.lsq.thread0.ignoredResponses 4762 # Number of memory responses ignored because the instruction is squashed
548system.cpu.iew.lsq.thread0.memOrderViolation 65666 # Number of memory ordering violations
549system.cpu.iew.lsq.thread0.squashedStores 2849832 # Number of stores squashed
550system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
551system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
552system.cpu.iew.lsq.thread0.rescheduledLoads 726205 # Number of loads that were rescheduled
553system.cpu.iew.lsq.thread0.cacheBlocked 82286 # Number of times an access to memory failed due to the cache being blocked
554system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
555system.cpu.iew.iewSquashCycles 544996 # Number of cycles IEW is squashing
556system.cpu.iew.iewBlockCycles 1714516 # Number of cycles IEW is blocking
557system.cpu.iew.iewUnblockCycles 834399 # Number of cycles IEW is unblocking
558system.cpu.iew.iewDispatchedInsts 105286702 # Number of instructions dispatched to IQ
559system.cpu.iew.iewDispSquashedInsts 183365 # Number of squashed instructions skipped by dispatch
560system.cpu.iew.iewDispLoadInsts 25719384 # Number of dispatched load instructions
561system.cpu.iew.iewDispStoreInsts 23405570 # Number of dispatched store instructions
562system.cpu.iew.iewDispNonSpecInsts 22106 # Number of dispatched non-speculative instructions
563system.cpu.iew.iewIQFullEvents 17305 # Number of times the IQ has become full, causing a stall
564system.cpu.iew.iewLSQFullEvents 806226 # Number of times the LSQ has become full, causing a stall
565system.cpu.iew.memOrderViolationEvents 65666 # Number of memory order violations
566system.cpu.iew.predictedTakenIncorrect 396732 # Number of branches that were predicted taken incorrectly
567system.cpu.iew.predictedNotTakenIncorrect 182672 # Number of branches that were predicted not taken incorrectly
568system.cpu.iew.branchMispredicts 579404 # Number of branch mispredicts detected at execute
569system.cpu.iew.iewExecutedInsts 98631248 # Number of executed instructions
570system.cpu.iew.iewExecLoadInsts 25214590 # Number of load instructions executed
571system.cpu.iew.iewExecSquashedInsts 1015249 # Number of squashed instructions skipped in execute
572system.cpu.iew.exec_swp 0 # number of swp insts executed
573system.cpu.iew.exec_nop 10433 # number of nop insts executed
574system.cpu.iew.exec_refs 46968385 # number of memory reference insts executed
575system.cpu.iew.exec_branches 14905400 # Number of branches executed
576system.cpu.iew.exec_stores 21753795 # Number of stores executed
577system.cpu.iew.exec_rate 2.063724 # Inst execution rate
578system.cpu.iew.wb_sent 97441036 # cumulative count of insts sent to commit
579system.cpu.iew.wb_count 97191682 # cumulative count of insts written-back
580system.cpu.iew.wb_producers 50912103 # num instructions producing a value
581system.cpu.iew.wb_consumers 98942269 # num instructions consuming a value
582system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
583system.cpu.iew.wb_rate 2.033603 # insts written-back per cycle
584system.cpu.iew.wb_fanout 0.514564 # average fanout of values written-back
585system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
586system.cpu.commit.commitSquashedInsts 14604340 # The number of squashed insts skipped by commit
587system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
588system.cpu.commit.branchMispredicts 491808 # The number of times a branch was mispredicted
589system.cpu.commit.committed_per_cycle::samples 45293214 # Number of insts commited each cycle
590system.cpu.commit.committed_per_cycle::mean 2.002246 # Number of insts commited each cycle
591system.cpu.commit.committed_per_cycle::stdev 2.787973 # Number of insts commited each cycle
592system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
593system.cpu.commit.committed_per_cycle::0 20766641 45.85% 45.85% # Number of insts commited each cycle
594system.cpu.commit.committed_per_cycle::1 9214809 20.34% 66.19% # Number of insts commited each cycle
595system.cpu.commit.committed_per_cycle::2 2670756 5.90% 72.09% # Number of insts commited each cycle
596system.cpu.commit.committed_per_cycle::3 2400198 5.30% 77.39% # Number of insts commited each cycle
597system.cpu.commit.committed_per_cycle::4 2023573 4.47% 81.86% # Number of insts commited each cycle
598system.cpu.commit.committed_per_cycle::5 972100 2.15% 84.00% # Number of insts commited each cycle
599system.cpu.commit.committed_per_cycle::6 768345 1.70% 85.70% # Number of insts commited each cycle
600system.cpu.commit.committed_per_cycle::7 447977 0.99% 86.69% # Number of insts commited each cycle
601system.cpu.commit.committed_per_cycle::8 6028815 13.31% 100.00% # Number of insts commited each cycle
602system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
603system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
604system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
605system.cpu.commit.committed_per_cycle::total 45293214 # Number of insts commited each cycle
606system.cpu.commit.committedInsts 70913181 # Number of instructions committed
607system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed
608system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
609system.cpu.commit.refs 43422000 # Number of memory references committed
610system.cpu.commit.loads 22866262 # Number of loads committed
611system.cpu.commit.membars 15920 # Number of memory barriers committed
612system.cpu.commit.branches 13741485 # Number of branches committed
613system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.

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643system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
644system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
645system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
646system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction
647system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction
648system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
649system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
650system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction
651system.cpu.commit.bw_lim_events 6028815 # number cycles where commit BW limit reached
652system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
653system.cpu.rob.rob_reads 144531576 # The number of ROB reads
654system.cpu.rob.rob_writes 212728591 # The number of ROB writes
655system.cpu.timesIdled 10876 # Number of times that the entire CPU went into an idle state and unscheduled itself
656system.cpu.idleCycles 367966 # Total number of cycles that the CPU has spent unscheduled due to idling
657system.cpu.committedInsts 70907629 # Number of Instructions Simulated
658system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated
659system.cpu.cpi 0.674016 # CPI: Cycles Per Instruction
660system.cpu.cpi_total 0.674016 # CPI: Total CPI of All Threads
661system.cpu.ipc 1.483645 # IPC: Instructions Per Cycle
662system.cpu.ipc_total 1.483645 # IPC: Total IPC of All Threads
663system.cpu.int_regfile_reads 106842718 # number of integer regfile reads
664system.cpu.int_regfile_writes 59180200 # number of integer regfile writes
665system.cpu.fp_regfile_reads 1084 # number of floating regfile reads
666system.cpu.fp_regfile_writes 924 # number of floating regfile writes
667system.cpu.cc_regfile_reads 361896749 # number of cc regfile reads
668system.cpu.cc_regfile_writes 40174850 # number of cc regfile writes
669system.cpu.misc_regfile_reads 45647350 # number of misc regfile reads
670system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
671system.cpu.toL2Bus.throughput 869793867 # Throughput (bytes/s)
672system.cpu.toL2Bus.trans_dist::ReadReq 88682 # Transaction distribution
673system.cpu.toL2Bus.trans_dist::ReadResp 88681 # Transaction distribution
674system.cpu.toL2Bus.trans_dist::Writeback 129104 # Transaction distribution
675system.cpu.toL2Bus.trans_dist::UpgradeReq 425 # Transaction distribution
676system.cpu.toL2Bus.trans_dist::UpgradeResp 425 # Transaction distribution
677system.cpu.toL2Bus.trans_dist::ReadExReq 106980 # Transaction distribution
678system.cpu.toL2Bus.trans_dist::ReadExResp 106980 # Transaction distribution
679system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66417 # Packet count per connected master and slave (bytes)
680system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454340 # Packet count per connected master and slave (bytes)
681system.cpu.toL2Bus.pkt_count::total 520757 # Packet count per connected master and slave (bytes)
682system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2108672 # Cumulative packet size per connected master and slave (bytes)
683system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18643008 # Cumulative packet size per connected master and slave (bytes)
684system.cpu.toL2Bus.tot_pkt_size::total 20751680 # Cumulative packet size per connected master and slave (bytes)
685system.cpu.toL2Bus.data_through_bus 20751680 # Total data (bytes)
686system.cpu.toL2Bus.snoop_data_through_bus 33280 # Total snoop data (bytes)
687system.cpu.toL2Bus.reqLayer0.occupancy 291703993 # Layer occupancy (ticks)
688system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
689system.cpu.toL2Bus.respLayer0.occupancy 50946473 # Layer occupancy (ticks)
690system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
691system.cpu.toL2Bus.respLayer1.occupancy 259533576 # Layer occupancy (ticks)
692system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
693system.cpu.icache.tags.replacements 31122 # number of replacements
694system.cpu.icache.tags.tagsinuse 1801.454521 # Cycle average of tags in use
695system.cpu.icache.tags.total_refs 12448339 # Total number of references to valid blocks.
696system.cpu.icache.tags.sampled_refs 33152 # Sample count of references to valid blocks.
697system.cpu.icache.tags.avg_refs 375.492851 # Average number of references to valid blocks.
698system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
699system.cpu.icache.tags.occ_blocks::cpu.inst 1801.454521 # Average occupied blocks per requestor
700system.cpu.icache.tags.occ_percent::cpu.inst 0.879616 # Average percentage of cache occupancy
701system.cpu.icache.tags.occ_percent::total 0.879616 # Average percentage of cache occupancy
702system.cpu.icache.tags.occ_task_id_blocks::1024 2030 # Occupied blocks per task id
703system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
704system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
705system.cpu.icache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id
706system.cpu.icache.tags.age_task_id_blocks_1024::4 672 # Occupied blocks per task id
707system.cpu.icache.tags.occ_task_id_percent::1024 0.991211 # Percentage of cache occupancy per task id
708system.cpu.icache.tags.tag_accesses 25004882 # Number of tag accesses
709system.cpu.icache.tags.data_accesses 25004882 # Number of data accesses
710system.cpu.icache.ReadReq_hits::cpu.inst 12448346 # number of ReadReq hits
711system.cpu.icache.ReadReq_hits::total 12448346 # number of ReadReq hits
712system.cpu.icache.demand_hits::cpu.inst 12448346 # number of demand (read+write) hits
713system.cpu.icache.demand_hits::total 12448346 # number of demand (read+write) hits
714system.cpu.icache.overall_hits::cpu.inst 12448346 # number of overall hits
715system.cpu.icache.overall_hits::total 12448346 # number of overall hits
716system.cpu.icache.ReadReq_misses::cpu.inst 37361 # number of ReadReq misses
717system.cpu.icache.ReadReq_misses::total 37361 # number of ReadReq misses
718system.cpu.icache.demand_misses::cpu.inst 37361 # number of demand (read+write) misses
719system.cpu.icache.demand_misses::total 37361 # number of demand (read+write) misses
720system.cpu.icache.overall_misses::cpu.inst 37361 # number of overall misses
721system.cpu.icache.overall_misses::total 37361 # number of overall misses
722system.cpu.icache.ReadReq_miss_latency::cpu.inst 833057215 # number of ReadReq miss cycles
723system.cpu.icache.ReadReq_miss_latency::total 833057215 # number of ReadReq miss cycles
724system.cpu.icache.demand_miss_latency::cpu.inst 833057215 # number of demand (read+write) miss cycles
725system.cpu.icache.demand_miss_latency::total 833057215 # number of demand (read+write) miss cycles
726system.cpu.icache.overall_miss_latency::cpu.inst 833057215 # number of overall miss cycles
727system.cpu.icache.overall_miss_latency::total 833057215 # number of overall miss cycles
728system.cpu.icache.ReadReq_accesses::cpu.inst 12485707 # number of ReadReq accesses(hits+misses)
729system.cpu.icache.ReadReq_accesses::total 12485707 # number of ReadReq accesses(hits+misses)
730system.cpu.icache.demand_accesses::cpu.inst 12485707 # number of demand (read+write) accesses
731system.cpu.icache.demand_accesses::total 12485707 # number of demand (read+write) accesses
732system.cpu.icache.overall_accesses::cpu.inst 12485707 # number of overall (read+write) accesses
733system.cpu.icache.overall_accesses::total 12485707 # number of overall (read+write) accesses
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735system.cpu.icache.ReadReq_miss_rate::total 0.002992 # miss rate for ReadReq accesses
736system.cpu.icache.demand_miss_rate::cpu.inst 0.002992 # miss rate for demand accesses
737system.cpu.icache.demand_miss_rate::total 0.002992 # miss rate for demand accesses
738system.cpu.icache.overall_miss_rate::cpu.inst 0.002992 # miss rate for overall accesses
739system.cpu.icache.overall_miss_rate::total 0.002992 # miss rate for overall accesses
740system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22297.508498 # average ReadReq miss latency
741system.cpu.icache.ReadReq_avg_miss_latency::total 22297.508498 # average ReadReq miss latency
742system.cpu.icache.demand_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency
743system.cpu.icache.demand_avg_miss_latency::total 22297.508498 # average overall miss latency
744system.cpu.icache.overall_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency
745system.cpu.icache.overall_avg_miss_latency::total 22297.508498 # average overall miss latency
746system.cpu.icache.blocked_cycles::no_mshrs 1054 # number of cycles access was blocked
747system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
748system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked
749system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
750system.cpu.icache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked
751system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
752system.cpu.icache.fast_writes 0 # number of fast writes performed
753system.cpu.icache.cache_copies 0 # number of cache copies performed
754system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3892 # number of ReadReq MSHR hits
755system.cpu.icache.ReadReq_mshr_hits::total 3892 # number of ReadReq MSHR hits
756system.cpu.icache.demand_mshr_hits::cpu.inst 3892 # number of demand (read+write) MSHR hits
757system.cpu.icache.demand_mshr_hits::total 3892 # number of demand (read+write) MSHR hits
758system.cpu.icache.overall_mshr_hits::cpu.inst 3892 # number of overall MSHR hits
759system.cpu.icache.overall_mshr_hits::total 3892 # number of overall MSHR hits
760system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33469 # number of ReadReq MSHR misses
761system.cpu.icache.ReadReq_mshr_misses::total 33469 # number of ReadReq MSHR misses
762system.cpu.icache.demand_mshr_misses::cpu.inst 33469 # number of demand (read+write) MSHR misses
763system.cpu.icache.demand_mshr_misses::total 33469 # number of demand (read+write) MSHR misses
764system.cpu.icache.overall_mshr_misses::cpu.inst 33469 # number of overall MSHR misses
765system.cpu.icache.overall_mshr_misses::total 33469 # number of overall MSHR misses
766system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 671681027 # number of ReadReq MSHR miss cycles
767system.cpu.icache.ReadReq_mshr_miss_latency::total 671681027 # number of ReadReq MSHR miss cycles
768system.cpu.icache.demand_mshr_miss_latency::cpu.inst 671681027 # number of demand (read+write) MSHR miss cycles
769system.cpu.icache.demand_mshr_miss_latency::total 671681027 # number of demand (read+write) MSHR miss cycles
770system.cpu.icache.overall_mshr_miss_latency::cpu.inst 671681027 # number of overall MSHR miss cycles
771system.cpu.icache.overall_mshr_miss_latency::total 671681027 # number of overall MSHR miss cycles
772system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002681 # mshr miss rate for ReadReq accesses
773system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002681 # mshr miss rate for ReadReq accesses
774system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002681 # mshr miss rate for demand accesses
775system.cpu.icache.demand_mshr_miss_rate::total 0.002681 # mshr miss rate for demand accesses
776system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002681 # mshr miss rate for overall accesses
777system.cpu.icache.overall_mshr_miss_rate::total 0.002681 # mshr miss rate for overall accesses
778system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20068.750993 # average ReadReq mshr miss latency
779system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20068.750993 # average ReadReq mshr miss latency
780system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20068.750993 # average overall mshr miss latency
781system.cpu.icache.demand_avg_mshr_miss_latency::total 20068.750993 # average overall mshr miss latency
782system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20068.750993 # average overall mshr miss latency
783system.cpu.icache.overall_avg_mshr_miss_latency::total 20068.750993 # average overall mshr miss latency
784system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
785system.cpu.l2cache.tags.replacements 95567 # number of replacements
786system.cpu.l2cache.tags.tagsinuse 29785.869326 # Cycle average of tags in use
787system.cpu.l2cache.tags.total_refs 90467 # Total number of references to valid blocks.
788system.cpu.l2cache.tags.sampled_refs 126676 # Sample count of references to valid blocks.
789system.cpu.l2cache.tags.avg_refs 0.714161 # Average number of references to valid blocks.
790system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
791system.cpu.l2cache.tags.occ_blocks::writebacks 26681.247493 # Average occupied blocks per requestor
792system.cpu.l2cache.tags.occ_blocks::cpu.inst 1364.251232 # Average occupied blocks per requestor
793system.cpu.l2cache.tags.occ_blocks::cpu.data 1740.370601 # Average occupied blocks per requestor
794system.cpu.l2cache.tags.occ_percent::writebacks 0.814247 # Average percentage of cache occupancy
795system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041634 # Average percentage of cache occupancy
796system.cpu.l2cache.tags.occ_percent::cpu.data 0.053112 # Average percentage of cache occupancy
797system.cpu.l2cache.tags.occ_percent::total 0.908993 # Average percentage of cache occupancy
798system.cpu.l2cache.tags.occ_task_id_blocks::1024 31109 # Occupied blocks per task id
799system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
800system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2594 # Occupied blocks per task id
801system.cpu.l2cache.tags.age_task_id_blocks_1024::2 24318 # Occupied blocks per task id
802system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3666 # Occupied blocks per task id
803system.cpu.l2cache.tags.age_task_id_blocks_1024::4 376 # Occupied blocks per task id
804system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949371 # Percentage of cache occupancy per task id
805system.cpu.l2cache.tags.tag_accesses 2831071 # Number of tag accesses
806system.cpu.l2cache.tags.data_accesses 2831071 # Number of data accesses
807system.cpu.l2cache.ReadReq_hits::cpu.inst 28249 # number of ReadReq hits
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809system.cpu.l2cache.ReadReq_hits::total 61659 # number of ReadReq hits
810system.cpu.l2cache.Writeback_hits::writebacks 129104 # number of Writeback hits
811system.cpu.l2cache.Writeback_hits::total 129104 # number of Writeback hits
812system.cpu.l2cache.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits
813system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits
814system.cpu.l2cache.ReadExReq_hits::cpu.data 4722 # number of ReadExReq hits
815system.cpu.l2cache.ReadExReq_hits::total 4722 # number of ReadExReq hits
816system.cpu.l2cache.demand_hits::cpu.inst 28249 # number of demand (read+write) hits
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818system.cpu.l2cache.demand_hits::total 66381 # number of demand (read+write) hits
819system.cpu.l2cache.overall_hits::cpu.inst 28249 # number of overall hits
820system.cpu.l2cache.overall_hits::cpu.data 38132 # number of overall hits
821system.cpu.l2cache.overall_hits::total 66381 # number of overall hits
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828system.cpu.l2cache.ReadExReq_misses::total 102258 # number of ReadExReq misses
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830system.cpu.l2cache.demand_misses::cpu.data 124061 # number of demand (read+write) misses
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838system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 46498 # number of UpgradeReq miss cycles
839system.cpu.l2cache.UpgradeReq_miss_latency::total 46498 # number of UpgradeReq miss cycles
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842system.cpu.l2cache.demand_miss_latency::cpu.inst 354760000 # number of demand (read+write) miss cycles
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851system.cpu.l2cache.Writeback_accesses::writebacks 129104 # number of Writeback accesses(hits+misses)
852system.cpu.l2cache.Writeback_accesses::total 129104 # number of Writeback accesses(hits+misses)
853system.cpu.l2cache.UpgradeReq_accesses::cpu.data 425 # number of UpgradeReq accesses(hits+misses)
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866system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.894118 # miss rate for UpgradeReq accesses
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877system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 92720.726506 # average ReadReq miss latency
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880system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 122.363158 # average UpgradeReq miss latency
881system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82894.000958 # average ReadExReq miss latency
882system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82894.000958 # average ReadExReq miss latency
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884system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84620.990884 # average overall miss latency
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886system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75480.851064 # average overall miss latency
887system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84620.990884 # average overall miss latency
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892system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
893system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
894system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
895system.cpu.l2cache.fast_writes 0 # number of fast writes performed
896system.cpu.l2cache.cache_copies 0 # number of cache copies performed
897system.cpu.l2cache.writebacks::writebacks 83950 # number of writebacks
898system.cpu.l2cache.writebacks::total 83950 # number of writebacks
899system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 21 # number of ReadReq MSHR hits
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937system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.894118 # mshr miss rate for UpgradeReq accesses
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940system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955861 # mshr miss rate for ReadExReq accesses
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951system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.836842 # average UpgradeReq mshr miss latency
952system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70576.705490 # average ReadExReq mshr miss latency
953system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70576.705490 # average ReadExReq mshr miss latency
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955system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72317.225891 # average overall mshr miss latency
956system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71978.978553 # average overall mshr miss latency
957system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63014.159008 # average overall mshr miss latency
958system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72317.225891 # average overall mshr miss latency
959system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71978.978553 # average overall mshr miss latency
960system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
961system.cpu.dcache.tags.replacements 158097 # number of replacements
962system.cpu.dcache.tags.tagsinuse 4066.697393 # Cycle average of tags in use
963system.cpu.dcache.tags.total_refs 40254845 # Total number of references to valid blocks.
964system.cpu.dcache.tags.sampled_refs 162193 # Sample count of references to valid blocks.
965system.cpu.dcache.tags.avg_refs 248.191013 # Average number of references to valid blocks.
966system.cpu.dcache.tags.warmup_cycle 349035000 # Cycle when the warmup percentage was hit.
967system.cpu.dcache.tags.occ_blocks::cpu.data 4066.697393 # Average occupied blocks per requestor
968system.cpu.dcache.tags.occ_percent::cpu.data 0.992846 # Average percentage of cache occupancy
969system.cpu.dcache.tags.occ_percent::total 0.992846 # Average percentage of cache occupancy
970system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
971system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
972system.cpu.dcache.tags.age_task_id_blocks_1024::1 2487 # Occupied blocks per task id
973system.cpu.dcache.tags.age_task_id_blocks_1024::2 1534 # Occupied blocks per task id
974system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
975system.cpu.dcache.tags.tag_accesses 84282165 # Number of tag accesses
976system.cpu.dcache.tags.data_accesses 84282165 # Number of data accesses
977system.cpu.dcache.ReadReq_hits::cpu.data 21874674 # number of ReadReq hits
978system.cpu.dcache.ReadReq_hits::total 21874674 # number of ReadReq hits
979system.cpu.dcache.WriteReq_hits::cpu.data 18263658 # number of WriteReq hits
980system.cpu.dcache.WriteReq_hits::total 18263658 # number of WriteReq hits
981system.cpu.dcache.SoftPFReq_hits::cpu.data 83481 # number of SoftPFReq hits
982system.cpu.dcache.SoftPFReq_hits::total 83481 # number of SoftPFReq hits
983system.cpu.dcache.LoadLockedReq_hits::cpu.data 15983 # number of LoadLockedReq hits
984system.cpu.dcache.LoadLockedReq_hits::total 15983 # number of LoadLockedReq hits
985system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
986system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
987system.cpu.dcache.demand_hits::cpu.data 40138332 # number of demand (read+write) hits
988system.cpu.dcache.demand_hits::total 40138332 # number of demand (read+write) hits
989system.cpu.dcache.overall_hits::cpu.data 40221813 # number of overall hits
990system.cpu.dcache.overall_hits::total 40221813 # number of overall hits
991system.cpu.dcache.ReadReq_misses::cpu.data 172724 # number of ReadReq misses
992system.cpu.dcache.ReadReq_misses::total 172724 # number of ReadReq misses
993system.cpu.dcache.WriteReq_misses::cpu.data 1586243 # number of WriteReq misses
994system.cpu.dcache.WriteReq_misses::total 1586243 # number of WriteReq misses
995system.cpu.dcache.SoftPFReq_misses::cpu.data 47266 # number of SoftPFReq misses
996system.cpu.dcache.SoftPFReq_misses::total 47266 # number of SoftPFReq misses
997system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses
998system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses
999system.cpu.dcache.demand_misses::cpu.data 1758967 # number of demand (read+write) misses
1000system.cpu.dcache.demand_misses::total 1758967 # number of demand (read+write) misses
1001system.cpu.dcache.overall_misses::cpu.data 1806233 # number of overall misses
1002system.cpu.dcache.overall_misses::total 1806233 # number of overall misses
1003system.cpu.dcache.ReadReq_miss_latency::cpu.data 5001907368 # number of ReadReq miss cycles
1004system.cpu.dcache.ReadReq_miss_latency::total 5001907368 # number of ReadReq miss cycles
1005system.cpu.dcache.WriteReq_miss_latency::cpu.data 128651444042 # number of WriteReq miss cycles
1006system.cpu.dcache.WriteReq_miss_latency::total 128651444042 # number of WriteReq miss cycles
1007system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1064000 # number of LoadLockedReq miss cycles
1008system.cpu.dcache.LoadLockedReq_miss_latency::total 1064000 # number of LoadLockedReq miss cycles
1009system.cpu.dcache.demand_miss_latency::cpu.data 133653351410 # number of demand (read+write) miss cycles
1010system.cpu.dcache.demand_miss_latency::total 133653351410 # number of demand (read+write) miss cycles
1011system.cpu.dcache.overall_miss_latency::cpu.data 133653351410 # number of overall miss cycles
1012system.cpu.dcache.overall_miss_latency::total 133653351410 # number of overall miss cycles
1013system.cpu.dcache.ReadReq_accesses::cpu.data 22047398 # number of ReadReq accesses(hits+misses)
1014system.cpu.dcache.ReadReq_accesses::total 22047398 # number of ReadReq accesses(hits+misses)
1015system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
1016system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
1017system.cpu.dcache.SoftPFReq_accesses::cpu.data 130747 # number of SoftPFReq accesses(hits+misses)
1018system.cpu.dcache.SoftPFReq_accesses::total 130747 # number of SoftPFReq accesses(hits+misses)
1019system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16021 # number of LoadLockedReq accesses(hits+misses)
1020system.cpu.dcache.LoadLockedReq_accesses::total 16021 # number of LoadLockedReq accesses(hits+misses)
1021system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
1022system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
1023system.cpu.dcache.demand_accesses::cpu.data 41897299 # number of demand (read+write) accesses
1024system.cpu.dcache.demand_accesses::total 41897299 # number of demand (read+write) accesses
1025system.cpu.dcache.overall_accesses::cpu.data 42028046 # number of overall (read+write) accesses
1026system.cpu.dcache.overall_accesses::total 42028046 # number of overall (read+write) accesses
1027system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007834 # miss rate for ReadReq accesses
1028system.cpu.dcache.ReadReq_miss_rate::total 0.007834 # miss rate for ReadReq accesses
1029system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079912 # miss rate for WriteReq accesses
1030system.cpu.dcache.WriteReq_miss_rate::total 0.079912 # miss rate for WriteReq accesses
1031system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.361507 # miss rate for SoftPFReq accesses
1032system.cpu.dcache.SoftPFReq_miss_rate::total 0.361507 # miss rate for SoftPFReq accesses
1033system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002372 # miss rate for LoadLockedReq accesses
1034system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002372 # miss rate for LoadLockedReq accesses
1035system.cpu.dcache.demand_miss_rate::cpu.data 0.041983 # miss rate for demand accesses
1036system.cpu.dcache.demand_miss_rate::total 0.041983 # miss rate for demand accesses
1037system.cpu.dcache.overall_miss_rate::cpu.data 0.042977 # miss rate for overall accesses
1038system.cpu.dcache.overall_miss_rate::total 0.042977 # miss rate for overall accesses
1039system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.959774 # average ReadReq miss latency
1040system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.959774 # average ReadReq miss latency
1041system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81104.499148 # average WriteReq miss latency
1042system.cpu.dcache.WriteReq_avg_miss_latency::total 81104.499148 # average WriteReq miss latency
1043system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28000 # average LoadLockedReq miss latency
1044system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28000 # average LoadLockedReq miss latency
1045system.cpu.dcache.demand_avg_miss_latency::cpu.data 75984.001638 # average overall miss latency
1046system.cpu.dcache.demand_avg_miss_latency::total 75984.001638 # average overall miss latency
1047system.cpu.dcache.overall_avg_miss_latency::cpu.data 73995.631466 # average overall miss latency
1048system.cpu.dcache.overall_avg_miss_latency::total 73995.631466 # average overall miss latency
1049system.cpu.dcache.blocked_cycles::no_mshrs 911565 # number of cycles access was blocked
1050system.cpu.dcache.blocked_cycles::no_targets 1622 # number of cycles access was blocked
1051system.cpu.dcache.blocked::no_mshrs 13218 # number of cycles access was blocked
1052system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
1053system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.963913 # average number of cycles each access was blocked
1054system.cpu.dcache.avg_blocked_cycles::no_targets 108.133333 # average number of cycles each access was blocked
1055system.cpu.dcache.fast_writes 0 # number of fast writes performed
1056system.cpu.dcache.cache_copies 0 # number of cache copies performed
1057system.cpu.dcache.writebacks::writebacks 129104 # number of writebacks
1058system.cpu.dcache.writebacks::total 129104 # number of writebacks
1059system.cpu.dcache.ReadReq_mshr_hits::cpu.data 141550 # number of ReadReq MSHR hits
1060system.cpu.dcache.ReadReq_mshr_hits::total 141550 # number of ReadReq MSHR hits
1061system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1478910 # number of WriteReq MSHR hits
1062system.cpu.dcache.WriteReq_mshr_hits::total 1478910 # number of WriteReq MSHR hits
1063system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits
1064system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits
1065system.cpu.dcache.demand_mshr_hits::cpu.data 1620460 # number of demand (read+write) MSHR hits
1066system.cpu.dcache.demand_mshr_hits::total 1620460 # number of demand (read+write) MSHR hits
1067system.cpu.dcache.overall_mshr_hits::cpu.data 1620460 # number of overall MSHR hits
1068system.cpu.dcache.overall_mshr_hits::total 1620460 # number of overall MSHR hits
1069system.cpu.dcache.ReadReq_mshr_misses::cpu.data 31174 # number of ReadReq MSHR misses
1070system.cpu.dcache.ReadReq_mshr_misses::total 31174 # number of ReadReq MSHR misses
1071system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107333 # number of WriteReq MSHR misses
1072system.cpu.dcache.WriteReq_mshr_misses::total 107333 # number of WriteReq MSHR misses
1073system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24111 # number of SoftPFReq MSHR misses
1074system.cpu.dcache.SoftPFReq_mshr_misses::total 24111 # number of SoftPFReq MSHR misses
1075system.cpu.dcache.demand_mshr_misses::cpu.data 138507 # number of demand (read+write) MSHR misses
1076system.cpu.dcache.demand_mshr_misses::total 138507 # number of demand (read+write) MSHR misses
1077system.cpu.dcache.overall_mshr_misses::cpu.data 162618 # number of overall MSHR misses
1078system.cpu.dcache.overall_mshr_misses::total 162618 # number of overall MSHR misses
1079system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 566566801 # number of ReadReq MSHR miss cycles
1080system.cpu.dcache.ReadReq_mshr_miss_latency::total 566566801 # number of ReadReq MSHR miss cycles
1081system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8639740111 # number of WriteReq MSHR miss cycles
1082system.cpu.dcache.WriteReq_mshr_miss_latency::total 8639740111 # number of WriteReq MSHR miss cycles
1083system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1848458500 # number of SoftPFReq MSHR miss cycles
1084system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1848458500 # number of SoftPFReq MSHR miss cycles
1085system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9206306912 # number of demand (read+write) MSHR miss cycles
1086system.cpu.dcache.demand_mshr_miss_latency::total 9206306912 # number of demand (read+write) MSHR miss cycles
1087system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11054765412 # number of overall MSHR miss cycles
1088system.cpu.dcache.overall_mshr_miss_latency::total 11054765412 # number of overall MSHR miss cycles
1089system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001414 # mshr miss rate for ReadReq accesses
1090system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001414 # mshr miss rate for ReadReq accesses
1091system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses
1092system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses
1093system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.184410 # mshr miss rate for SoftPFReq accesses
1094system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.184410 # mshr miss rate for SoftPFReq accesses
1095system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003306 # mshr miss rate for demand accesses
1096system.cpu.dcache.demand_mshr_miss_rate::total 0.003306 # mshr miss rate for demand accesses
1097system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003869 # mshr miss rate for overall accesses
1098system.cpu.dcache.overall_mshr_miss_rate::total 0.003869 # mshr miss rate for overall accesses
1099system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18174.337621 # average ReadReq mshr miss latency
1100system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18174.337621 # average ReadReq mshr miss latency
1101system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80494.723067 # average WriteReq mshr miss latency
1102system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80494.723067 # average WriteReq mshr miss latency
1103system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76664.530712 # average SoftPFReq mshr miss latency
1104system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76664.530712 # average SoftPFReq mshr miss latency
1105system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66468.170648 # average overall mshr miss latency
1106system.cpu.dcache.demand_avg_mshr_miss_latency::total 66468.170648 # average overall mshr miss latency
1107system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67979.961702 # average overall mshr miss latency
1108system.cpu.dcache.overall_avg_mshr_miss_latency::total 67979.961702 # average overall mshr miss latency
1109system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1110
1111---------- End Simulation Statistics ----------