1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.026596 # Number of seconds simulated
4sim_ticks 26596403000 # Number of ticks simulated
5final_tick 26596403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 110554 # Simulator instruction rate (inst/s)
8host_op_rate 156889 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 41466984 # Simulator tick rate (ticks/s)
10host_mem_usage 321816 # Number of bytes of host memory used
11host_seconds 641.39 # Real time elapsed on the host
12sim_insts 70907629 # Number of instructions simulated
13sim_ops 100626876 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 297984 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7942976 # Number of bytes read from this memory
18system.physmem.bytes_read::total 8240960 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 297984 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 297984 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory
22system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 4656 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 124109 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 128765 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 11203921 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 298648505 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 309852426 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 11203921 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 11203921 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 202000248 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 202000248 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 202000248 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 11203921 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 298648505 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 511852674 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 128766 # Number of read requests accepted
40system.physmem.writeReqs 83945 # Number of write requests accepted
41system.physmem.readBursts 128766 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 83945 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 8240704 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
45system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 8241024 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 5372480 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 300 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 8143 # Per bank write bursts
52system.physmem.perBankRdBursts::1 8388 # Per bank write bursts
53system.physmem.perBankRdBursts::2 8255 # Per bank write bursts
54system.physmem.perBankRdBursts::3 8165 # Per bank write bursts
55system.physmem.perBankRdBursts::4 8298 # Per bank write bursts
56system.physmem.perBankRdBursts::5 8451 # Per bank write bursts
57system.physmem.perBankRdBursts::6 8084 # Per bank write bursts
58system.physmem.perBankRdBursts::7 7964 # Per bank write bursts
59system.physmem.perBankRdBursts::8 8055 # Per bank write bursts
60system.physmem.perBankRdBursts::9 7611 # Per bank write bursts
61system.physmem.perBankRdBursts::10 7782 # Per bank write bursts
62system.physmem.perBankRdBursts::11 7815 # Per bank write bursts
63system.physmem.perBankRdBursts::12 7881 # Per bank write bursts
64system.physmem.perBankRdBursts::13 7884 # Per bank write bursts
65system.physmem.perBankRdBursts::14 7976 # Per bank write bursts
66system.physmem.perBankRdBursts::15 8009 # Per bank write bursts
67system.physmem.perBankWrBursts::0 5177 # Per bank write bursts
68system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
69system.physmem.perBankWrBursts::2 5289 # Per bank write bursts
70system.physmem.perBankWrBursts::3 5157 # Per bank write bursts
71system.physmem.perBankWrBursts::4 5267 # Per bank write bursts
72system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
73system.physmem.perBankWrBursts::6 5201 # Per bank write bursts
74system.physmem.perBankWrBursts::7 5049 # Per bank write bursts
75system.physmem.perBankWrBursts::8 5030 # Per bank write bursts
76system.physmem.perBankWrBursts::9 5089 # Per bank write bursts
77system.physmem.perBankWrBursts::10 5246 # Per bank write bursts
78system.physmem.perBankWrBursts::11 5144 # Per bank write bursts
79system.physmem.perBankWrBursts::12 5342 # Per bank write bursts
80system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
81system.physmem.perBankWrBursts::14 5452 # Per bank write bursts
82system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 26596386500 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 128766 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 83945 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 71874 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 54925 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 1900 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see

--- 26 unchanged lines hidden (view full) ---

139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 478 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 495 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 840 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 2288 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 3768 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 4393 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 4872 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 5159 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 5216 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 5492 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 6272 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 6389 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 5693 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 5625 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::32 5394 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::33 2900 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::34 953 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::35 409 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::36 107 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::37 92 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::38 72 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::39 63 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::40 49 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::41 50 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::42 43 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::43 37 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::44 36 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::45 31 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::46 34 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::47 26 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::49 22 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::50 20 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::51 19 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::52 19 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196system.physmem.bytesPerActivate::samples 29627 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::mean 410.695649 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::gmean 253.351666 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::stdev 359.831379 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::0-127 7793 26.30% 26.30% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::128-255 6034 20.37% 46.67% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::256-383 3130 10.56% 57.23% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::384-511 2203 7.44% 64.67% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::512-639 2053 6.93% 71.60% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::640-767 1365 4.61% 76.21% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::768-895 1045 3.53% 79.73% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::896-1023 1191 4.02% 83.75% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1024-1151 4813 16.25% 100.00% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::total 29627 # Bytes accessed per row activation
210system.physmem.rdPerTurnAround::samples 5084 # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::mean 25.322974 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::stdev 394.325536 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::0-1023 5082 99.96% 99.96% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::total 5084 # Reads before turning the bus around for writes
217system.physmem.wrPerTurnAround::samples 5084 # Writes before turning the bus around for reads
218system.physmem.wrPerTurnAround::mean 16.507474 # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::gmean 16.421096 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::stdev 2.063173 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::16 4555 89.59% 89.59% # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::17 21 0.41% 90.01% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::18 58 1.14% 91.15% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::19 170 3.34% 94.49% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::20 125 2.46% 96.95% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::21 57 1.12% 98.07% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::22 23 0.45% 98.52% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::23 15 0.30% 98.82% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::24 10 0.20% 99.02% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::25 6 0.12% 99.13% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::26 5 0.10% 99.23% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::27 5 0.10% 99.33% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::28 4 0.08% 99.41% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::29 2 0.04% 99.45% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::30 4 0.08% 99.53% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::31 2 0.04% 99.57% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::33 1 0.02% 99.59% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::35 1 0.02% 99.61% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::36 1 0.02% 99.63% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::37 1 0.02% 99.65% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::39 13 0.26% 99.90% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::40 3 0.06% 99.96% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::42 1 0.02% 99.98% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::48 1 0.02% 100.00% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::total 5084 # Writes before turning the bus around for reads
246system.physmem.totQLat 2537399000 # Total ticks spent queuing
247system.physmem.totMemAccLat 4590111500 # Total ticks spent from burst creation until serviced by the DRAM
248system.physmem.totBusLat 643805000 # Total ticks spent in databus transfers
249system.physmem.totBankLat 1408907500 # Total ticks spent accessing banks
250system.physmem.avgQLat 19706.27 # Average queueing delay per DRAM burst
251system.physmem.avgBankLat 10942.04 # Average bank access latency per DRAM burst
252system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
253system.physmem.avgMemAccLat 35648.31 # Average memory access latency per DRAM burst
254system.physmem.avgRdBW 309.84 # Average DRAM read bandwidth in MiByte/s
255system.physmem.avgWrBW 201.95 # Average achieved write bandwidth in MiByte/s
256system.physmem.avgRdBWSys 309.85 # Average system read bandwidth in MiByte/s
257system.physmem.avgWrBWSys 202.00 # Average system write bandwidth in MiByte/s
258system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
259system.physmem.busUtil 4.00 # Data bus utilization in percentage
260system.physmem.busUtilRead 2.42 # Data bus utilization in percentage for reads
261system.physmem.busUtilWrite 1.58 # Data bus utilization in percentage for writes
262system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing
263system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing
264system.physmem.readRowHits 112537 # Number of row buffer hits during reads
265system.physmem.writeRowHits 62593 # Number of row buffer hits during writes
266system.physmem.readRowHitRate 87.40 # Row buffer hit rate for reads
267system.physmem.writeRowHitRate 74.56 # Row buffer hit rate for writes
268system.physmem.avgGap 125035.31 # Average gap between requests
269system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined
270system.physmem.prechargeAllPercent 11.63 # Percentage of time for which DRAM has all the banks in precharge state
271system.membus.throughput 511852674 # Throughput (bytes/s)
272system.membus.trans_dist::ReadReq 26511 # Transaction distribution
273system.membus.trans_dist::ReadResp 26510 # Transaction distribution
274system.membus.trans_dist::Writeback 83945 # Transaction distribution
275system.membus.trans_dist::UpgradeReq 300 # Transaction distribution
276system.membus.trans_dist::UpgradeResp 300 # Transaction distribution
277system.membus.trans_dist::ReadExReq 102255 # Transaction distribution
278system.membus.trans_dist::ReadExResp 102255 # Transaction distribution
279system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342076 # Packet count per connected master and slave (bytes)
280system.membus.pkt_count::total 342076 # Packet count per connected master and slave (bytes)
281system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613440 # Cumulative packet size per connected master and slave (bytes)
282system.membus.tot_pkt_size::total 13613440 # Cumulative packet size per connected master and slave (bytes)
283system.membus.data_through_bus 13613440 # Total data (bytes)
284system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
285system.membus.reqLayer0.occupancy 934794000 # Layer occupancy (ticks)
286system.membus.reqLayer0.utilization 3.5 # Layer utilization (%)
287system.membus.respLayer1.occupancy 1201882201 # Layer occupancy (ticks)
288system.membus.respLayer1.utilization 4.5 # Layer utilization (%)
289system.cpu_clk_domain.clock 500 # Clock period in ticks
290system.cpu.branchPred.lookups 16626299 # Number of BP lookups
291system.cpu.branchPred.condPredicted 12761376 # Number of conditional branches predicted
292system.cpu.branchPred.condIncorrect 603542 # Number of conditional branches incorrect
293system.cpu.branchPred.BTBLookups 10553987 # Number of BTB lookups
294system.cpu.branchPred.BTBHits 7772041 # Number of BTB hits
295system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
296system.cpu.branchPred.BTBHitPct 73.640805 # BTB Hit Percentage
297system.cpu.branchPred.usedRAS 1823891 # Number of times the RAS was used to get a target.
298system.cpu.branchPred.RASInCorrect 112970 # Number of incorrect RAS predictions.
299system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
300system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
301system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
302system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
303system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
304system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
305system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
306system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 69 unchanged lines hidden (view full) ---

376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
377system.cpu.itb.read_accesses 0 # DTB read accesses
378system.cpu.itb.write_accesses 0 # DTB write accesses
379system.cpu.itb.inst_accesses 0 # ITB inst accesses
380system.cpu.itb.hits 0 # DTB hits
381system.cpu.itb.misses 0 # DTB misses
382system.cpu.itb.accesses 0 # DTB accesses
383system.cpu.workload.num_syscalls 1946 # Number of system calls
384system.cpu.numCycles 53192807 # number of cpu cycles simulated
385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
387system.cpu.fetch.icacheStallCycles 12548027 # Number of cycles fetch is stalled on an Icache miss
388system.cpu.fetch.Insts 85225985 # Number of instructions fetch has processed
389system.cpu.fetch.Branches 16626299 # Number of branches that fetch encountered
390system.cpu.fetch.predictedBranches 9595932 # Number of branches that fetch has predicted taken
391system.cpu.fetch.Cycles 21195811 # Number of cycles fetch has run and was not squashing or blocked
392system.cpu.fetch.SquashCycles 2371567 # Number of cycles fetch has spent squashing
393system.cpu.fetch.BlockedCycles 10764095 # Number of cycles fetch has spent blocked
394system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
395system.cpu.fetch.PendingTrapStallCycles 524 # Number of stall cycles due to pending traps
396system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
397system.cpu.fetch.CacheLines 11679981 # Number of cache lines fetched
398system.cpu.fetch.IcacheSquashes 179230 # Number of outstanding Icache misses that were squashed
399system.cpu.fetch.rateDist::samples 46249849 # Number of instructions fetched each cycle (Total)
400system.cpu.fetch.rateDist::mean 2.580108 # Number of instructions fetched each cycle (Total)
401system.cpu.fetch.rateDist::stdev 3.332376 # Number of instructions fetched each cycle (Total)
402system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
403system.cpu.fetch.rateDist::0 25074842 54.22% 54.22% # Number of instructions fetched each cycle (Total)
404system.cpu.fetch.rateDist::1 2134843 4.62% 58.83% # Number of instructions fetched each cycle (Total)
405system.cpu.fetch.rateDist::2 1965334 4.25% 63.08% # Number of instructions fetched each cycle (Total)
406system.cpu.fetch.rateDist::3 2045724 4.42% 67.50% # Number of instructions fetched each cycle (Total)
407system.cpu.fetch.rateDist::4 1467866 3.17% 70.68% # Number of instructions fetched each cycle (Total)
408system.cpu.fetch.rateDist::5 1377638 2.98% 73.66% # Number of instructions fetched each cycle (Total)
409system.cpu.fetch.rateDist::6 956719 2.07% 75.73% # Number of instructions fetched each cycle (Total)
410system.cpu.fetch.rateDist::7 1188096 2.57% 78.29% # Number of instructions fetched each cycle (Total)
411system.cpu.fetch.rateDist::8 10038787 21.71% 100.00% # Number of instructions fetched each cycle (Total)
412system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
413system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
414system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
415system.cpu.fetch.rateDist::total 46249849 # Number of instructions fetched each cycle (Total)
416system.cpu.fetch.branchRate 0.312567 # Number of branch fetches per cycle
417system.cpu.fetch.rate 1.602209 # Number of inst fetches per cycle
418system.cpu.decode.IdleCycles 14635842 # Number of cycles decode is idle
419system.cpu.decode.BlockedCycles 9109376 # Number of cycles decode is blocked
420system.cpu.decode.RunCycles 19493309 # Number of cycles decode is running
421system.cpu.decode.UnblockCycles 1372783 # Number of cycles decode is unblocking
422system.cpu.decode.SquashCycles 1638539 # Number of cycles decode is squashing
423system.cpu.decode.BranchResolved 3331010 # Number of times decode resolved a branch
424system.cpu.decode.BranchMispred 104505 # Number of times decode detected a branch misprediction
425system.cpu.decode.DecodedInsts 116880506 # Number of instructions handled by decode
426system.cpu.decode.SquashedInsts 361697 # Number of squashed instructions handled by decode
427system.cpu.rename.SquashCycles 1638539 # Number of cycles rename is squashing
428system.cpu.rename.IdleCycles 16346771 # Number of cycles rename is idle
429system.cpu.rename.BlockCycles 2652791 # Number of cycles rename is blocking
430system.cpu.rename.serializeStallCycles 1020533 # count of cycles rename stalled for serializing inst
431system.cpu.rename.RunCycles 19105290 # Number of cycles rename is running
432system.cpu.rename.UnblockCycles 5485925 # Number of cycles rename is unblocking
433system.cpu.rename.RenamedInsts 114999580 # Number of instructions processed by rename
434system.cpu.rename.ROBFullEvents 152 # Number of times rename has blocked due to ROB full
435system.cpu.rename.IQFullEvents 17445 # Number of times rename has blocked due to IQ full
436system.cpu.rename.LSQFullEvents 4623062 # Number of times rename has blocked due to LSQ full
437system.cpu.rename.FullRegisterEvents 183 # Number of times there has been no free registers
438system.cpu.rename.RenamedOperands 115318587 # Number of destination operands rename has renamed
439system.cpu.rename.RenameLookups 529932404 # Number of register rename lookups that rename has made
440system.cpu.rename.int_rename_lookups 476522297 # Number of integer rename lookups
441system.cpu.rename.fp_rename_lookups 2751 # Number of floating rename lookups
442system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
443system.cpu.rename.UndoneMaps 16185915 # Number of HB maps that are undone due to squashing
444system.cpu.rename.serializingInsts 20374 # count of serializing insts renamed
445system.cpu.rename.tempSerializingInsts 20369 # count of temporary serializing insts renamed
446system.cpu.rename.skidInsts 13024660 # count of insts added to the skid buffer
447system.cpu.memDep0.insertedLoads 29615928 # Number of loads inserted to the mem dependence unit.
448system.cpu.memDep0.insertedStores 22451967 # Number of stores inserted to the mem dependence unit.
449system.cpu.memDep0.conflictingLoads 3877153 # Number of conflicting loads.
450system.cpu.memDep0.conflictingStores 4417845 # Number of conflicting stores.
451system.cpu.iq.iqInstsAdded 111572377 # Number of instructions added to the IQ (excludes non-spec)
452system.cpu.iq.iqNonSpecInstsAdded 35991 # Number of non-speculative instructions added to the IQ
453system.cpu.iq.iqInstsIssued 107273861 # Number of instructions issued
454system.cpu.iq.iqSquashedInstsIssued 274045 # Number of squashed instructions issued
455system.cpu.iq.iqSquashedInstsExamined 10831021 # Number of squashed instructions iterated over during squash; mainly for profiling
456system.cpu.iq.iqSquashedOperandsExamined 25918238 # Number of squashed operands that are examined and possibly removed from graph
457system.cpu.iq.iqSquashedNonSpecRemoved 2205 # Number of squashed non-spec instructions that were removed
458system.cpu.iq.issued_per_cycle::samples 46249849 # Number of insts issued each cycle
459system.cpu.iq.issued_per_cycle::mean 2.319442 # Number of insts issued each cycle
460system.cpu.iq.issued_per_cycle::stdev 1.990414 # Number of insts issued each cycle
461system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
462system.cpu.iq.issued_per_cycle::0 10978806 23.74% 23.74% # Number of insts issued each cycle
463system.cpu.iq.issued_per_cycle::1 8116860 17.55% 41.29% # Number of insts issued each cycle
464system.cpu.iq.issued_per_cycle::2 7434269 16.07% 57.36% # Number of insts issued each cycle
465system.cpu.iq.issued_per_cycle::3 7097763 15.35% 72.71% # Number of insts issued each cycle
466system.cpu.iq.issued_per_cycle::4 5421519 11.72% 84.43% # Number of insts issued each cycle
467system.cpu.iq.issued_per_cycle::5 3913580 8.46% 92.89% # Number of insts issued each cycle
468system.cpu.iq.issued_per_cycle::6 1842525 3.98% 96.88% # Number of insts issued each cycle
469system.cpu.iq.issued_per_cycle::7 870168 1.88% 98.76% # Number of insts issued each cycle
470system.cpu.iq.issued_per_cycle::8 574359 1.24% 100.00% # Number of insts issued each cycle
471system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
472system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
473system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
474system.cpu.iq.issued_per_cycle::total 46249849 # Number of insts issued each cycle
475system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
476system.cpu.iq.fu_full::IntAlu 113368 4.58% 4.58% # attempts to use FU when none available
477system.cpu.iq.fu_full::IntMult 0 0.00% 4.58% # attempts to use FU when none available
478system.cpu.iq.fu_full::IntDiv 0 0.00% 4.58% # attempts to use FU when none available
479system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.58% # attempts to use FU when none available
480system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.58% # attempts to use FU when none available
481system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.58% # attempts to use FU when none available
482system.cpu.iq.fu_full::FloatMult 0 0.00% 4.58% # attempts to use FU when none available
483system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.58% # attempts to use FU when none available
484system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.58% # attempts to use FU when none available
485system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.58% # attempts to use FU when none available
486system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.58% # attempts to use FU when none available
487system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.58% # attempts to use FU when none available
488system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.58% # attempts to use FU when none available
489system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.58% # attempts to use FU when none available
490system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.58% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdMult 0 0.00% 4.58% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.58% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdShift 0 0.00% 4.58% # attempts to use FU when none available
494system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.58% # attempts to use FU when none available
495system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.58% # attempts to use FU when none available
496system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.58% # attempts to use FU when none available
497system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.58% # attempts to use FU when none available
498system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.58% # attempts to use FU when none available
499system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.58% # attempts to use FU when none available
500system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.58% # attempts to use FU when none available
501system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.58% # attempts to use FU when none available
502system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.58% # attempts to use FU when none available
503system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.58% # attempts to use FU when none available
504system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.58% # attempts to use FU when none available
505system.cpu.iq.fu_full::MemRead 1353818 54.73% 59.32% # attempts to use FU when none available
506system.cpu.iq.fu_full::MemWrite 1006223 40.68% 100.00% # attempts to use FU when none available
507system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
508system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
509system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
510system.cpu.iq.FU_type_0::IntAlu 56655592 52.81% 52.81% # Type of FU issued
511system.cpu.iq.FU_type_0::IntMult 91505 0.09% 52.90% # Type of FU issued
512system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued
513system.cpu.iq.FU_type_0::FloatAdd 217 0.00% 52.90% # Type of FU issued
514system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued
515system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued
516system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued
517system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued
518system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued
519system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued
520system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued
521system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued

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531system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued
532system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued
533system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued
534system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued
535system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued
536system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued
537system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued
538system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued
539system.cpu.iq.FU_type_0::MemRead 28893939 26.93% 79.83% # Type of FU issued
540system.cpu.iq.FU_type_0::MemWrite 21632601 20.17% 100.00% # Type of FU issued
541system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
542system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
543system.cpu.iq.FU_type_0::total 107273861 # Type of FU issued
544system.cpu.iq.rate 2.016699 # Inst issue rate
545system.cpu.iq.fu_busy_cnt 2473411 # FU busy when requested
546system.cpu.iq.fu_busy_rate 0.023057 # FU busy rate (busy events/executed inst)
547system.cpu.iq.int_inst_queue_reads 263544444 # Number of integer instruction queue reads
548system.cpu.iq.int_inst_queue_writes 122467509 # Number of integer instruction queue writes
549system.cpu.iq.int_inst_queue_wakeup_accesses 105589962 # Number of integer instruction queue wakeup accesses
550system.cpu.iq.fp_inst_queue_reads 583 # Number of floating instruction queue reads
551system.cpu.iq.fp_inst_queue_writes 918 # Number of floating instruction queue writes
552system.cpu.iq.fp_inst_queue_wakeup_accesses 177 # Number of floating instruction queue wakeup accesses
553system.cpu.iq.int_alu_accesses 109746981 # Number of integer alu accesses
554system.cpu.iq.fp_alu_accesses 291 # Number of floating point alu accesses
555system.cpu.iew.lsq.thread0.forwLoads 2178933 # Number of loads that had data forwarded from stores
556system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
557system.cpu.iew.lsq.thread0.squashedLoads 2308820 # Number of loads squashed
558system.cpu.iew.lsq.thread0.ignoredResponses 6717 # Number of memory responses ignored because the instruction is squashed
559system.cpu.iew.lsq.thread0.memOrderViolation 29962 # Number of memory ordering violations
560system.cpu.iew.lsq.thread0.squashedStores 1896229 # Number of stores squashed
561system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
562system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
563system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled
564system.cpu.iew.lsq.thread0.cacheBlocked 670 # Number of times an access to memory failed due to the cache being blocked
565system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
566system.cpu.iew.iewSquashCycles 1638539 # Number of cycles IEW is squashing
567system.cpu.iew.iewBlockCycles 1135526 # Number of cycles IEW is blocking
568system.cpu.iew.iewUnblockCycles 46796 # Number of cycles IEW is unblocking
569system.cpu.iew.iewDispatchedInsts 111618146 # Number of instructions dispatched to IQ
570system.cpu.iew.iewDispSquashedInsts 297287 # Number of squashed instructions skipped by dispatch
571system.cpu.iew.iewDispLoadInsts 29615928 # Number of dispatched load instructions
572system.cpu.iew.iewDispStoreInsts 22451967 # Number of dispatched store instructions
573system.cpu.iew.iewDispNonSpecInsts 20071 # Number of dispatched non-speculative instructions
574system.cpu.iew.iewIQFullEvents 6522 # Number of times the IQ has become full, causing a stall
575system.cpu.iew.iewLSQFullEvents 5186 # Number of times the LSQ has become full, causing a stall
576system.cpu.iew.memOrderViolationEvents 29962 # Number of memory order violations
577system.cpu.iew.predictedTakenIncorrect 392730 # Number of branches that were predicted taken incorrectly
578system.cpu.iew.predictedNotTakenIncorrect 181164 # Number of branches that were predicted not taken incorrectly
579system.cpu.iew.branchMispredicts 573894 # Number of branch mispredicts detected at execute
580system.cpu.iew.iewExecutedInsts 106245086 # Number of executed instructions
581system.cpu.iew.iewExecLoadInsts 28594669 # Number of load instructions executed
582system.cpu.iew.iewExecSquashedInsts 1028775 # Number of squashed instructions skipped in execute
583system.cpu.iew.exec_swp 0 # number of swp insts executed
584system.cpu.iew.exec_nop 9778 # number of nop insts executed
585system.cpu.iew.exec_refs 49940992 # number of memory reference insts executed
586system.cpu.iew.exec_branches 14602318 # Number of branches executed
587system.cpu.iew.exec_stores 21346323 # Number of stores executed
588system.cpu.iew.exec_rate 1.997358 # Inst execution rate
589system.cpu.iew.wb_sent 105809508 # cumulative count of insts sent to commit
590system.cpu.iew.wb_count 105590139 # cumulative count of insts written-back
591system.cpu.iew.wb_producers 53305824 # num instructions producing a value
592system.cpu.iew.wb_consumers 103866304 # num instructions consuming a value
593system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
594system.cpu.iew.wb_rate 1.985045 # insts written-back per cycle
595system.cpu.iew.wb_fanout 0.513216 # average fanout of values written-back
596system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
597system.cpu.commit.commitSquashedInsts 10986690 # The number of squashed insts skipped by commit
598system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
599system.cpu.commit.branchMispredicts 500884 # The number of times a branch was mispredicted
600system.cpu.commit.committed_per_cycle::samples 44611310 # Number of insts commited each cycle
601system.cpu.commit.committed_per_cycle::mean 2.255760 # Number of insts commited each cycle
602system.cpu.commit.committed_per_cycle::stdev 2.762475 # Number of insts commited each cycle
603system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
604system.cpu.commit.committed_per_cycle::0 15517142 34.78% 34.78% # Number of insts commited each cycle
605system.cpu.commit.committed_per_cycle::1 11686207 26.20% 60.98% # Number of insts commited each cycle
606system.cpu.commit.committed_per_cycle::2 3450926 7.74% 68.71% # Number of insts commited each cycle
607system.cpu.commit.committed_per_cycle::3 2867812 6.43% 75.14% # Number of insts commited each cycle
608system.cpu.commit.committed_per_cycle::4 1872959 4.20% 79.34% # Number of insts commited each cycle
609system.cpu.commit.committed_per_cycle::5 1945129 4.36% 83.70% # Number of insts commited each cycle
610system.cpu.commit.committed_per_cycle::6 689747 1.55% 85.25% # Number of insts commited each cycle
611system.cpu.commit.committed_per_cycle::7 566134 1.27% 86.52% # Number of insts commited each cycle
612system.cpu.commit.committed_per_cycle::8 6015254 13.48% 100.00% # Number of insts commited each cycle
613system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
614system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
615system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
616system.cpu.commit.committed_per_cycle::total 44611310 # Number of insts commited each cycle
617system.cpu.commit.committedInsts 70913181 # Number of instructions committed
618system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
619system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
620system.cpu.commit.refs 47862846 # Number of memory references committed
621system.cpu.commit.loads 27307108 # Number of loads committed
622system.cpu.commit.membars 15920 # Number of memory barriers committed
623system.cpu.commit.branches 13741485 # Number of branches committed
624system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
625system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
626system.cpu.commit.function_calls 1679850 # Number of function calls committed.
627system.cpu.commit.bw_lim_events 6015254 # number cycles where commit BW limit reached
628system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
629system.cpu.rob.rob_reads 150189875 # The number of ROB reads
630system.cpu.rob.rob_writes 224886049 # The number of ROB writes
631system.cpu.timesIdled 80066 # Number of times that the entire CPU went into an idle state and unscheduled itself
632system.cpu.idleCycles 6942958 # Total number of cycles that the CPU has spent unscheduled due to idling
633system.cpu.committedInsts 70907629 # Number of Instructions Simulated
634system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
635system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
636system.cpu.cpi 0.750170 # CPI: Cycles Per Instruction
637system.cpu.cpi_total 0.750170 # CPI: Total CPI of All Threads
638system.cpu.ipc 1.333030 # IPC: Instructions Per Cycle
639system.cpu.ipc_total 1.333030 # IPC: Total IPC of All Threads
640system.cpu.int_regfile_reads 511686083 # number of integer regfile reads
641system.cpu.int_regfile_writes 103364033 # number of integer regfile writes
642system.cpu.fp_regfile_reads 870 # number of floating regfile reads
643system.cpu.fp_regfile_writes 762 # number of floating regfile writes
644system.cpu.misc_regfile_reads 49348247 # number of misc regfile reads
645system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
646system.cpu.toL2Bus.throughput 778162370 # Throughput (bytes/s)
647system.cpu.toL2Bus.trans_dist::ReadReq 87191 # Transaction distribution
648system.cpu.toL2Bus.trans_dist::ReadResp 87190 # Transaction distribution
649system.cpu.toL2Bus.trans_dist::Writeback 129156 # Transaction distribution
650system.cpu.toL2Bus.trans_dist::UpgradeReq 314 # Transaction distribution
651system.cpu.toL2Bus.trans_dist::UpgradeResp 314 # Transaction distribution
652system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
653system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
654system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63123 # Packet count per connected master and slave (bytes)
655system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454609 # Packet count per connected master and slave (bytes)
656system.cpu.toL2Bus.pkt_count::total 517732 # Packet count per connected master and slave (bytes)
657system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2003904 # Cumulative packet size per connected master and slave (bytes)
658system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660352 # Cumulative packet size per connected master and slave (bytes)
659system.cpu.toL2Bus.tot_pkt_size::total 20664256 # Cumulative packet size per connected master and slave (bytes)
660system.cpu.toL2Bus.data_through_bus 20664256 # Total data (bytes)
661system.cpu.toL2Bus.snoop_data_through_bus 32064 # Total snoop data (bytes)
662system.cpu.toL2Bus.reqLayer0.occupancy 291006496 # Layer occupancy (ticks)
663system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
664system.cpu.toL2Bus.respLayer0.occupancy 48441979 # Layer occupancy (ticks)
665system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
666system.cpu.toL2Bus.respLayer1.occupancy 259878236 # Layer occupancy (ticks)
667system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
668system.cpu.icache.tags.replacements 29471 # number of replacements
669system.cpu.icache.tags.tagsinuse 1806.055358 # Cycle average of tags in use
670system.cpu.icache.tags.total_refs 11644351 # Total number of references to valid blocks.
671system.cpu.icache.tags.sampled_refs 31508 # Sample count of references to valid blocks.
672system.cpu.icache.tags.avg_refs 369.568078 # Average number of references to valid blocks.
673system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
674system.cpu.icache.tags.occ_blocks::cpu.inst 1806.055358 # Average occupied blocks per requestor
675system.cpu.icache.tags.occ_percent::cpu.inst 0.881863 # Average percentage of cache occupancy
676system.cpu.icache.tags.occ_percent::total 0.881863 # Average percentage of cache occupancy
677system.cpu.icache.tags.occ_task_id_blocks::1024 2037 # Occupied blocks per task id
678system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
679system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
680system.cpu.icache.tags.age_task_id_blocks_1024::3 1253 # Occupied blocks per task id
681system.cpu.icache.tags.age_task_id_blocks_1024::4 681 # Occupied blocks per task id
682system.cpu.icache.tags.occ_task_id_percent::1024 0.994629 # Percentage of cache occupancy per task id
683system.cpu.icache.tags.tag_accesses 23391772 # Number of tag accesses
684system.cpu.icache.tags.data_accesses 23391772 # Number of data accesses
685system.cpu.icache.ReadReq_hits::cpu.inst 11644361 # number of ReadReq hits
686system.cpu.icache.ReadReq_hits::total 11644361 # number of ReadReq hits
687system.cpu.icache.demand_hits::cpu.inst 11644361 # number of demand (read+write) hits
688system.cpu.icache.demand_hits::total 11644361 # number of demand (read+write) hits
689system.cpu.icache.overall_hits::cpu.inst 11644361 # number of overall hits
690system.cpu.icache.overall_hits::total 11644361 # number of overall hits
691system.cpu.icache.ReadReq_misses::cpu.inst 35619 # number of ReadReq misses
692system.cpu.icache.ReadReq_misses::total 35619 # number of ReadReq misses
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694system.cpu.icache.demand_misses::total 35619 # number of demand (read+write) misses
695system.cpu.icache.overall_misses::cpu.inst 35619 # number of overall misses
696system.cpu.icache.overall_misses::total 35619 # number of overall misses
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698system.cpu.icache.ReadReq_miss_latency::total 813918226 # number of ReadReq miss cycles
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700system.cpu.icache.demand_miss_latency::total 813918226 # number of demand (read+write) miss cycles
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702system.cpu.icache.overall_miss_latency::total 813918226 # number of overall miss cycles
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704system.cpu.icache.ReadReq_accesses::total 11679980 # number of ReadReq accesses(hits+misses)
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708system.cpu.icache.overall_accesses::total 11679980 # number of overall (read+write) accesses
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712system.cpu.icache.demand_miss_rate::total 0.003050 # miss rate for demand accesses
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714system.cpu.icache.overall_miss_rate::total 0.003050 # miss rate for overall accesses
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716system.cpu.icache.ReadReq_avg_miss_latency::total 22850.675931 # average ReadReq miss latency
717system.cpu.icache.demand_avg_miss_latency::cpu.inst 22850.675931 # average overall miss latency
718system.cpu.icache.demand_avg_miss_latency::total 22850.675931 # average overall miss latency
719system.cpu.icache.overall_avg_miss_latency::cpu.inst 22850.675931 # average overall miss latency
720system.cpu.icache.overall_avg_miss_latency::total 22850.675931 # average overall miss latency
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722system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
723system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked
724system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
725system.cpu.icache.avg_blocked_cycles::no_mshrs 52.181818 # average number of cycles each access was blocked
726system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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728system.cpu.icache.cache_copies 0 # number of cache copies performed
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731system.cpu.icache.demand_mshr_hits::cpu.inst 3807 # number of demand (read+write) MSHR hits
732system.cpu.icache.demand_mshr_hits::total 3807 # number of demand (read+write) MSHR hits
733system.cpu.icache.overall_mshr_hits::cpu.inst 3807 # number of overall MSHR hits
734system.cpu.icache.overall_mshr_hits::total 3807 # number of overall MSHR hits
735system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31812 # number of ReadReq MSHR misses
736system.cpu.icache.ReadReq_mshr_misses::total 31812 # number of ReadReq MSHR misses
737system.cpu.icache.demand_mshr_misses::cpu.inst 31812 # number of demand (read+write) MSHR misses
738system.cpu.icache.demand_mshr_misses::total 31812 # number of demand (read+write) MSHR misses
739system.cpu.icache.overall_mshr_misses::cpu.inst 31812 # number of overall MSHR misses
740system.cpu.icache.overall_mshr_misses::total 31812 # number of overall MSHR misses
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742system.cpu.icache.ReadReq_mshr_miss_latency::total 661574021 # number of ReadReq MSHR miss cycles
743system.cpu.icache.demand_mshr_miss_latency::cpu.inst 661574021 # number of demand (read+write) MSHR miss cycles
744system.cpu.icache.demand_mshr_miss_latency::total 661574021 # number of demand (read+write) MSHR miss cycles
745system.cpu.icache.overall_mshr_miss_latency::cpu.inst 661574021 # number of overall MSHR miss cycles
746system.cpu.icache.overall_mshr_miss_latency::total 661574021 # number of overall MSHR miss cycles
747system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002724 # mshr miss rate for ReadReq accesses
748system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002724 # mshr miss rate for ReadReq accesses
749system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002724 # mshr miss rate for demand accesses
750system.cpu.icache.demand_mshr_miss_rate::total 0.002724 # mshr miss rate for demand accesses
751system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002724 # mshr miss rate for overall accesses
752system.cpu.icache.overall_mshr_miss_rate::total 0.002724 # mshr miss rate for overall accesses
753system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20796.366811 # average ReadReq mshr miss latency
754system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20796.366811 # average ReadReq mshr miss latency
755system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20796.366811 # average overall mshr miss latency
756system.cpu.icache.demand_avg_mshr_miss_latency::total 20796.366811 # average overall mshr miss latency
757system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20796.366811 # average overall mshr miss latency
758system.cpu.icache.overall_avg_mshr_miss_latency::total 20796.366811 # average overall mshr miss latency
759system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
760system.cpu.l2cache.tags.replacements 95635 # number of replacements
761system.cpu.l2cache.tags.tagsinuse 29857.974256 # Cycle average of tags in use
762system.cpu.l2cache.tags.total_refs 88990 # Total number of references to valid blocks.
763system.cpu.l2cache.tags.sampled_refs 126748 # Sample count of references to valid blocks.
764system.cpu.l2cache.tags.avg_refs 0.702102 # Average number of references to valid blocks.
765system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
766system.cpu.l2cache.tags.occ_blocks::writebacks 26666.144476 # Average occupied blocks per requestor
767system.cpu.l2cache.tags.occ_blocks::cpu.inst 1368.316766 # Average occupied blocks per requestor
768system.cpu.l2cache.tags.occ_blocks::cpu.data 1823.513014 # Average occupied blocks per requestor
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771system.cpu.l2cache.tags.occ_percent::cpu.data 0.055649 # Average percentage of cache occupancy
772system.cpu.l2cache.tags.occ_percent::total 0.911193 # Average percentage of cache occupancy
773system.cpu.l2cache.tags.occ_task_id_blocks::1024 31113 # Occupied blocks per task id
774system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
775system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1837 # Occupied blocks per task id
776system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20828 # Occupied blocks per task id
777system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7917 # Occupied blocks per task id
778system.cpu.l2cache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id
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781system.cpu.l2cache.tags.data_accesses 2819349 # Number of data accesses
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786system.cpu.l2cache.Writeback_hits::total 129156 # number of Writeback hits
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790system.cpu.l2cache.ReadExReq_hits::total 4779 # number of ReadExReq hits
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794system.cpu.l2cache.overall_hits::cpu.inst 26638 # number of overall hits
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803system.cpu.l2cache.ReadExReq_misses::total 102255 # number of ReadExReq misses
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827system.cpu.l2cache.Writeback_accesses::total 129156 # number of Writeback accesses(hits+misses)
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829system.cpu.l2cache.UpgradeReq_accesses::total 314 # number of UpgradeReq accesses(hits+misses)
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842system.cpu.l2cache.UpgradeReq_miss_rate::total 0.955414 # miss rate for UpgradeReq accesses
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846system.cpu.l2cache.demand_miss_rate::cpu.data 0.764532 # miss rate for demand accesses
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852system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81387.679671 # average ReadReq miss latency
853system.cpu.l2cache.ReadReq_avg_miss_latency::total 80722.261923 # average ReadReq miss latency
854system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 78.330000 # average UpgradeReq miss latency
855system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 78.330000 # average UpgradeReq miss latency
856system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80297.445113 # average ReadExReq miss latency
857system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80297.445113 # average ReadExReq miss latency
858system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77601.647764 # average overall miss latency
859system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80489.862688 # average overall miss latency
860system.cpu.l2cache.demand_avg_miss_latency::total 80385.110173 # average overall miss latency
861system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77601.647764 # average overall miss latency
862system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80489.862688 # average overall miss latency
863system.cpu.l2cache.overall_avg_miss_latency::total 80385.110173 # average overall miss latency
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865system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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867system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
868system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
869system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
870system.cpu.l2cache.fast_writes 0 # number of fast writes performed
871system.cpu.l2cache.cache_copies 0 # number of cache copies performed
872system.cpu.l2cache.writebacks::writebacks 83945 # number of writebacks
873system.cpu.l2cache.writebacks::total 83945 # number of writebacks
874system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits
875system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
876system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
877system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits
878system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
879system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
880system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits
881system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
882system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits
883system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4656 # number of ReadReq MSHR misses
884system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21855 # number of ReadReq MSHR misses
885system.cpu.l2cache.ReadReq_mshr_misses::total 26511 # number of ReadReq MSHR misses
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887system.cpu.l2cache.UpgradeReq_mshr_misses::total 300 # number of UpgradeReq MSHR misses
888system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102255 # number of ReadExReq MSHR misses
889system.cpu.l2cache.ReadExReq_mshr_misses::total 102255 # number of ReadExReq MSHR misses
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892system.cpu.l2cache.demand_mshr_misses::total 128766 # number of demand (read+write) MSHR misses
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894system.cpu.l2cache.overall_mshr_misses::cpu.data 124110 # number of overall MSHR misses
895system.cpu.l2cache.overall_mshr_misses::total 128766 # number of overall MSHR misses
896system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303015250 # number of ReadReq MSHR miss cycles
897system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1507731500 # number of ReadReq MSHR miss cycles
898system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1810746750 # number of ReadReq MSHR miss cycles
899system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3014299 # number of UpgradeReq MSHR miss cycles
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901system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6936413750 # number of ReadExReq MSHR miss cycles
902system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6936413750 # number of ReadExReq MSHR miss cycles
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907system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8444145250 # number of overall MSHR miss cycles
908system.cpu.l2cache.overall_mshr_miss_latency::total 8747160500 # number of overall MSHR miss cycles
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910system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394644 # mshr miss rate for ReadReq accesses
911system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305814 # mshr miss rate for ReadReq accesses
912system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.955414 # mshr miss rate for UpgradeReq accesses
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915system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955351 # mshr miss rate for ReadExReq accesses
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917system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764163 # mshr miss rate for demand accesses
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920system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764163 # mshr miss rate for overall accesses
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924system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68301.714383 # average ReadReq mshr miss latency
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926system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10047.663333 # average UpgradeReq mshr miss latency
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928system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67834.470197 # average ReadExReq mshr miss latency
929system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65080.594931 # average overall mshr miss latency
930system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68037.589638 # average overall mshr miss latency
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932system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65080.594931 # average overall mshr miss latency
933system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68037.589638 # average overall mshr miss latency
934system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67930.668810 # average overall mshr miss latency
935system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
936system.cpu.dcache.tags.replacements 158316 # number of replacements
937system.cpu.dcache.tags.tagsinuse 4068.473281 # Cycle average of tags in use
938system.cpu.dcache.tags.total_refs 44361466 # Total number of references to valid blocks.
939system.cpu.dcache.tags.sampled_refs 162412 # Sample count of references to valid blocks.
940system.cpu.dcache.tags.avg_refs 273.141554 # Average number of references to valid blocks.
941system.cpu.dcache.tags.warmup_cycle 367394250 # Cycle when the warmup percentage was hit.
942system.cpu.dcache.tags.occ_blocks::cpu.data 4068.473281 # Average occupied blocks per requestor
943system.cpu.dcache.tags.occ_percent::cpu.data 0.993280 # Average percentage of cache occupancy
944system.cpu.dcache.tags.occ_percent::total 0.993280 # Average percentage of cache occupancy
945system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
946system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
947system.cpu.dcache.tags.age_task_id_blocks_1024::1 1757 # Occupied blocks per task id
948system.cpu.dcache.tags.age_task_id_blocks_1024::2 2276 # Occupied blocks per task id
949system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
950system.cpu.dcache.tags.tag_accesses 92298894 # Number of tag accesses
951system.cpu.dcache.tags.data_accesses 92298894 # Number of data accesses
952system.cpu.dcache.ReadReq_hits::cpu.data 26061245 # number of ReadReq hits
953system.cpu.dcache.ReadReq_hits::total 26061245 # number of ReadReq hits
954system.cpu.dcache.WriteReq_hits::cpu.data 18267715 # number of WriteReq hits
955system.cpu.dcache.WriteReq_hits::total 18267715 # number of WriteReq hits
956system.cpu.dcache.LoadLockedReq_hits::cpu.data 15989 # number of LoadLockedReq hits
957system.cpu.dcache.LoadLockedReq_hits::total 15989 # number of LoadLockedReq hits
958system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
959system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
960system.cpu.dcache.demand_hits::cpu.data 44328960 # number of demand (read+write) hits
961system.cpu.dcache.demand_hits::total 44328960 # number of demand (read+write) hits
962system.cpu.dcache.overall_hits::cpu.data 44328960 # number of overall hits
963system.cpu.dcache.overall_hits::total 44328960 # number of overall hits
964system.cpu.dcache.ReadReq_misses::cpu.data 125143 # number of ReadReq misses
965system.cpu.dcache.ReadReq_misses::total 125143 # number of ReadReq misses
966system.cpu.dcache.WriteReq_misses::cpu.data 1582186 # number of WriteReq misses
967system.cpu.dcache.WriteReq_misses::total 1582186 # number of WriteReq misses
968system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses
969system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses
970system.cpu.dcache.demand_misses::cpu.data 1707329 # number of demand (read+write) misses
971system.cpu.dcache.demand_misses::total 1707329 # number of demand (read+write) misses
972system.cpu.dcache.overall_misses::cpu.data 1707329 # number of overall misses
973system.cpu.dcache.overall_misses::total 1707329 # number of overall misses
974system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010352449 # number of ReadReq miss cycles
975system.cpu.dcache.ReadReq_miss_latency::total 5010352449 # number of ReadReq miss cycles
976system.cpu.dcache.WriteReq_miss_latency::cpu.data 122380602729 # number of WriteReq miss cycles
977system.cpu.dcache.WriteReq_miss_latency::total 122380602729 # number of WriteReq miss cycles
978system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 944750 # number of LoadLockedReq miss cycles
979system.cpu.dcache.LoadLockedReq_miss_latency::total 944750 # number of LoadLockedReq miss cycles
980system.cpu.dcache.demand_miss_latency::cpu.data 127390955178 # number of demand (read+write) miss cycles
981system.cpu.dcache.demand_miss_latency::total 127390955178 # number of demand (read+write) miss cycles
982system.cpu.dcache.overall_miss_latency::cpu.data 127390955178 # number of overall miss cycles
983system.cpu.dcache.overall_miss_latency::total 127390955178 # number of overall miss cycles
984system.cpu.dcache.ReadReq_accesses::cpu.data 26186388 # number of ReadReq accesses(hits+misses)
985system.cpu.dcache.ReadReq_accesses::total 26186388 # number of ReadReq accesses(hits+misses)
986system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
987system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
988system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16033 # number of LoadLockedReq accesses(hits+misses)
989system.cpu.dcache.LoadLockedReq_accesses::total 16033 # number of LoadLockedReq accesses(hits+misses)
990system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
991system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
992system.cpu.dcache.demand_accesses::cpu.data 46036289 # number of demand (read+write) accesses
993system.cpu.dcache.demand_accesses::total 46036289 # number of demand (read+write) accesses
994system.cpu.dcache.overall_accesses::cpu.data 46036289 # number of overall (read+write) accesses
995system.cpu.dcache.overall_accesses::total 46036289 # number of overall (read+write) accesses
996system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004779 # miss rate for ReadReq accesses
997system.cpu.dcache.ReadReq_miss_rate::total 0.004779 # miss rate for ReadReq accesses
998system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079708 # miss rate for WriteReq accesses
999system.cpu.dcache.WriteReq_miss_rate::total 0.079708 # miss rate for WriteReq accesses
1000system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002744 # miss rate for LoadLockedReq accesses
1001system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002744 # miss rate for LoadLockedReq accesses
1002system.cpu.dcache.demand_miss_rate::cpu.data 0.037087 # miss rate for demand accesses
1003system.cpu.dcache.demand_miss_rate::total 0.037087 # miss rate for demand accesses
1004system.cpu.dcache.overall_miss_rate::cpu.data 0.037087 # miss rate for overall accesses
1005system.cpu.dcache.overall_miss_rate::total 0.037087 # miss rate for overall accesses
1006system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40037.017244 # average ReadReq miss latency
1007system.cpu.dcache.ReadReq_avg_miss_latency::total 40037.017244 # average ReadReq miss latency
1008system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77349.061823 # average WriteReq miss latency
1009system.cpu.dcache.WriteReq_avg_miss_latency::total 77349.061823 # average WriteReq miss latency
1010system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21471.590909 # average LoadLockedReq miss latency
1011system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21471.590909 # average LoadLockedReq miss latency
1012system.cpu.dcache.demand_avg_miss_latency::cpu.data 74614.181085 # average overall miss latency
1013system.cpu.dcache.demand_avg_miss_latency::total 74614.181085 # average overall miss latency
1014system.cpu.dcache.overall_avg_miss_latency::cpu.data 74614.181085 # average overall miss latency
1015system.cpu.dcache.overall_avg_miss_latency::total 74614.181085 # average overall miss latency
1016system.cpu.dcache.blocked_cycles::no_mshrs 4179 # number of cycles access was blocked
1017system.cpu.dcache.blocked_cycles::no_targets 1300 # number of cycles access was blocked
1018system.cpu.dcache.blocked::no_mshrs 140 # number of cycles access was blocked
1019system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
1020system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.850000 # average number of cycles each access was blocked
1021system.cpu.dcache.avg_blocked_cycles::no_targets 86.666667 # average number of cycles each access was blocked
1022system.cpu.dcache.fast_writes 0 # number of fast writes performed
1023system.cpu.dcache.cache_copies 0 # number of cache copies performed
1024system.cpu.dcache.writebacks::writebacks 129156 # number of writebacks
1025system.cpu.dcache.writebacks::total 129156 # number of writebacks
1026system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69730 # number of ReadReq MSHR hits
1027system.cpu.dcache.ReadReq_mshr_hits::total 69730 # number of ReadReq MSHR hits
1028system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1474872 # number of WriteReq MSHR hits
1029system.cpu.dcache.WriteReq_mshr_hits::total 1474872 # number of WriteReq MSHR hits
1030system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits
1031system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits
1032system.cpu.dcache.demand_mshr_hits::cpu.data 1544602 # number of demand (read+write) MSHR hits
1033system.cpu.dcache.demand_mshr_hits::total 1544602 # number of demand (read+write) MSHR hits
1034system.cpu.dcache.overall_mshr_hits::cpu.data 1544602 # number of overall MSHR hits
1035system.cpu.dcache.overall_mshr_hits::total 1544602 # number of overall MSHR hits
1036system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses
1037system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses
1038system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107314 # number of WriteReq MSHR misses
1039system.cpu.dcache.WriteReq_mshr_misses::total 107314 # number of WriteReq MSHR misses
1040system.cpu.dcache.demand_mshr_misses::cpu.data 162727 # number of demand (read+write) MSHR misses
1041system.cpu.dcache.demand_mshr_misses::total 162727 # number of demand (read+write) MSHR misses
1042system.cpu.dcache.overall_mshr_misses::cpu.data 162727 # number of overall MSHR misses
1043system.cpu.dcache.overall_mshr_misses::total 162727 # number of overall MSHR misses
1044system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2176479313 # number of ReadReq MSHR miss cycles
1045system.cpu.dcache.ReadReq_mshr_miss_latency::total 2176479313 # number of ReadReq MSHR miss cycles
1046system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8375757941 # number of WriteReq MSHR miss cycles
1047system.cpu.dcache.WriteReq_mshr_miss_latency::total 8375757941 # number of WriteReq MSHR miss cycles
1048system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10552237254 # number of demand (read+write) MSHR miss cycles
1049system.cpu.dcache.demand_mshr_miss_latency::total 10552237254 # number of demand (read+write) MSHR miss cycles
1050system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10552237254 # number of overall MSHR miss cycles
1051system.cpu.dcache.overall_mshr_miss_latency::total 10552237254 # number of overall MSHR miss cycles
1052system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses
1053system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses
1054system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
1055system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
1056system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses
1057system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses
1058system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses
1059system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses
1060system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39277.413477 # average ReadReq mshr miss latency
1061system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39277.413477 # average ReadReq mshr miss latency
1062system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78049.070401 # average WriteReq mshr miss latency
1063system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78049.070401 # average WriteReq mshr miss latency
1064system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64846.259404 # average overall mshr miss latency
1065system.cpu.dcache.demand_avg_mshr_miss_latency::total 64846.259404 # average overall mshr miss latency
1066system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64846.259404 # average overall mshr miss latency
1067system.cpu.dcache.overall_avg_mshr_miss_latency::total 64846.259404 # average overall mshr miss latency
1068system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1069
1070---------- End Simulation Statistics ----------