1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.026790 # Number of seconds simulated
4sim_ticks 26790388000 # Number of ticks simulated
5final_tick 26790388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 134448 # Simulator instruction rate (inst/s)
8host_op_rate 190799 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 50797444 # Simulator tick rate (ticks/s)
10host_mem_usage 278572 # Number of bytes of host memory used
11host_seconds 527.40 # Real time elapsed on the host
12sim_insts 70907629 # Number of instructions simulated
13sim_ops 100626876 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 297344 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7942912 # Number of bytes read from this memory
18system.physmem.bytes_read::total 8240256 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 297344 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 297344 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 5371968 # Number of bytes written to this memory
22system.physmem.bytes_written::total 5371968 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 4646 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 124108 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 128754 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 83937 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 83937 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 11098906 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 296483649 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 307582555 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 11098906 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 11098906 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 200518484 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 200518484 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 200518484 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 11098906 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 296483649 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 508101040 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 128754 # Number of read requests accepted
40system.physmem.writeReqs 83937 # Number of write requests accepted
41system.physmem.readBursts 128754 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 83937 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 8240128 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue
45system.physmem.bytesWritten 5371648 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 8240256 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 5371968 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 308 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 8131 # Per bank write bursts
52system.physmem.perBankRdBursts::1 8390 # Per bank write bursts
53system.physmem.perBankRdBursts::2 8247 # Per bank write bursts
54system.physmem.perBankRdBursts::3 8163 # Per bank write bursts
55system.physmem.perBankRdBursts::4 8302 # Per bank write bursts
56system.physmem.perBankRdBursts::5 8446 # Per bank write bursts
57system.physmem.perBankRdBursts::6 8088 # Per bank write bursts
58system.physmem.perBankRdBursts::7 7962 # Per bank write bursts
59system.physmem.perBankRdBursts::8 8060 # Per bank write bursts
60system.physmem.perBankRdBursts::9 7613 # Per bank write bursts
61system.physmem.perBankRdBursts::10 7786 # Per bank write bursts
62system.physmem.perBankRdBursts::11 7812 # Per bank write bursts
63system.physmem.perBankRdBursts::12 7879 # Per bank write bursts
64system.physmem.perBankRdBursts::13 7885 # Per bank write bursts
65system.physmem.perBankRdBursts::14 7978 # Per bank write bursts
66system.physmem.perBankRdBursts::15 8010 # Per bank write bursts
67system.physmem.perBankWrBursts::0 5179 # Per bank write bursts
68system.physmem.perBankWrBursts::1 5375 # Per bank write bursts
69system.physmem.perBankWrBursts::2 5289 # Per bank write bursts
70system.physmem.perBankWrBursts::3 5157 # Per bank write bursts
71system.physmem.perBankWrBursts::4 5265 # Per bank write bursts
72system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
73system.physmem.perBankWrBursts::6 5207 # Per bank write bursts
74system.physmem.perBankWrBursts::7 5048 # Per bank write bursts
75system.physmem.perBankWrBursts::8 5029 # Per bank write bursts
76system.physmem.perBankWrBursts::9 5089 # Per bank write bursts
77system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
78system.physmem.perBankWrBursts::11 5144 # Per bank write bursts
79system.physmem.perBankWrBursts::12 5342 # Per bank write bursts
80system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
81system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
82system.physmem.perBankWrBursts::15 5226 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 26790282500 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 128754 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 83937 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 73147 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 54223 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 1319 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see

--- 11 unchanged lines hidden (view full) ---

124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132system.physmem.wrQLenPdf::0 3672 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::1 3689 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::2 3689 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::3 3683 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::5 3683 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::6 3687 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::7 3686 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 3681 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 3678 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 3681 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 3686 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 3683 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 3698 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 3751 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 3941 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 3889 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 3936 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 4300 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 5019 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 63 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
164system.physmem.bytesPerActivate::samples 37879 # Bytes accessed per row activation
165system.physmem.bytesPerActivate::mean 359.276222 # Bytes accessed per row activation
166system.physmem.bytesPerActivate::gmean 174.215706 # Bytes accessed per row activation
167system.physmem.bytesPerActivate::stdev 692.456870 # Bytes accessed per row activation
168system.physmem.bytesPerActivate::64-65 15075 39.80% 39.80% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::128-129 5750 15.18% 54.98% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::192-193 3421 9.03% 64.01% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::256-257 2320 6.12% 70.13% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::320-321 1668 4.40% 74.54% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::384-385 1547 4.08% 78.62% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::448-449 1100 2.90% 81.53% # Bytes accessed per row activation
175system.physmem.bytesPerActivate::512-513 895 2.36% 83.89% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::576-577 687 1.81% 85.70% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::640-641 539 1.42% 87.12% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::704-705 385 1.02% 88.14% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::768-769 594 1.57% 89.71% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::832-833 272 0.72% 90.43% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::896-897 354 0.93% 91.36% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::960-961 173 0.46% 91.82% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::1024-1025 239 0.63% 92.45% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::1088-1089 118 0.31% 92.76% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.41% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::1216-1217 108 0.29% 93.70% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::1280-1281 279 0.74% 94.43% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::1344-1345 118 0.31% 94.75% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::1408-1409 446 1.18% 95.92% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::1472-1473 106 0.28% 96.20% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::1536-1537 237 0.63% 96.83% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.94% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::1664-1665 118 0.31% 97.25% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1728-1729 42 0.11% 97.37% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1792-1793 85 0.22% 97.59% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1856-1857 20 0.05% 97.64% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1920-1921 62 0.16% 97.81% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.86% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::2048-2049 44 0.12% 97.98% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::2112-2113 19 0.05% 98.03% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::2176-2177 33 0.09% 98.12% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::2240-2241 16 0.04% 98.16% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::2304-2305 33 0.09% 98.25% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.27% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.33% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::2496-2497 13 0.03% 98.37% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::2560-2561 33 0.09% 98.45% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::2624-2625 14 0.04% 98.49% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::2688-2689 23 0.06% 98.55% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::2752-2753 10 0.03% 98.58% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.62% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::2880-2881 9 0.02% 98.64% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::2944-2945 18 0.05% 98.69% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::3008-3009 4 0.01% 98.70% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::3072-3073 17 0.04% 98.75% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::3136-3137 11 0.03% 98.78% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::3200-3201 19 0.05% 98.83% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.85% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::3328-3329 26 0.07% 98.92% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::3392-3393 4 0.01% 98.93% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.95% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::3520-3521 10 0.03% 98.98% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::3584-3585 5 0.01% 98.99% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::3648-3649 7 0.02% 99.01% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.04% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.05% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3840-3841 9 0.02% 99.07% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.08% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::3968-3969 16 0.04% 99.13% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.14% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::4096-4097 9 0.02% 99.17% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::4160-4161 5 0.01% 99.18% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::4224-4225 10 0.03% 99.21% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::4288-4289 10 0.03% 99.23% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.26% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::4416-4417 6 0.02% 99.28% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.31% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::4544-4545 7 0.02% 99.32% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::4608-4609 6 0.02% 99.34% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.35% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.37% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4800-4801 2 0.01% 99.37% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.40% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.41% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.44% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.45% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.47% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.48% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::5248-5249 7 0.02% 99.50% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.51% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::5376-5377 6 0.02% 99.52% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::5504-5505 7 0.02% 99.55% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.57% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.61% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.62% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::5824-5825 5 0.01% 99.63% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::5888-5889 2 0.01% 99.64% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.65% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.66% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::6144-6145 6 0.02% 99.68% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::6208-6209 6 0.02% 99.69% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.70% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.71% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::6400-6401 4 0.01% 99.73% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::6464-6465 5 0.01% 99.74% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::6656-6657 4 0.01% 99.76% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.78% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::6784-6785 5 0.01% 99.79% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.79% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.80% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.81% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.83% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.83% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.83% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.84% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.84% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.85% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.85% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.87% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.87% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.88% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.89% # Bytes accessed per row activation
289system.physmem.bytesPerActivate::8128-8129 6 0.02% 99.90% # Bytes accessed per row activation
290system.physmem.bytesPerActivate::8192-8193 37 0.10% 100.00% # Bytes accessed per row activation
291system.physmem.bytesPerActivate::total 37879 # Bytes accessed per row activation
292system.physmem.totQLat 3022726750 # Total ticks spent queuing
293system.physmem.totMemAccLat 4971045500 # Total ticks spent from burst creation until serviced by the DRAM
294system.physmem.totBusLat 643760000 # Total ticks spent in databus transfers
295system.physmem.totBankLat 1304558750 # Total ticks spent accessing banks
296system.physmem.avgQLat 23477.12 # Average queueing delay per DRAM burst
297system.physmem.avgBankLat 10132.34 # Average bank access latency per DRAM burst
298system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
299system.physmem.avgMemAccLat 38609.46 # Average memory access latency per DRAM burst
300system.physmem.avgRdBW 307.58 # Average DRAM read bandwidth in MiByte/s
301system.physmem.avgWrBW 200.51 # Average achieved write bandwidth in MiByte/s
302system.physmem.avgRdBWSys 307.58 # Average system read bandwidth in MiByte/s
303system.physmem.avgWrBWSys 200.52 # Average system write bandwidth in MiByte/s
304system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
305system.physmem.busUtil 3.97 # Data bus utilization in percentage
306system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads
307system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes
308system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing
309system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing
310system.physmem.readRowHits 117872 # Number of row buffer hits during reads
311system.physmem.writeRowHits 56933 # Number of row buffer hits during writes
312system.physmem.readRowHitRate 91.55 # Row buffer hit rate for reads
313system.physmem.writeRowHitRate 67.83 # Row buffer hit rate for writes
314system.physmem.avgGap 125958.70 # Average gap between requests
315system.physmem.pageHitRate 82.19 # Row buffer hit rate, read and write combined
316system.physmem.prechargeAllPercent 11.78 # Percentage of time for which DRAM has all the banks in precharge state
317system.membus.throughput 508101040 # Throughput (bytes/s)
318system.membus.trans_dist::ReadReq 26500 # Transaction distribution
319system.membus.trans_dist::ReadResp 26500 # Transaction distribution
320system.membus.trans_dist::Writeback 83937 # Transaction distribution
321system.membus.trans_dist::UpgradeReq 308 # Transaction distribution
322system.membus.trans_dist::UpgradeResp 308 # Transaction distribution
323system.membus.trans_dist::ReadExReq 102254 # Transaction distribution
324system.membus.trans_dist::ReadExResp 102254 # Transaction distribution
325system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes)
326system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes)
327system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13612224 # Cumulative packet size per connected master and slave (bytes)
328system.membus.tot_pkt_size::total 13612224 # Cumulative packet size per connected master and slave (bytes)
329system.membus.data_through_bus 13612224 # Total data (bytes)
330system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
331system.membus.reqLayer0.occupancy 934459500 # Layer occupancy (ticks)
332system.membus.reqLayer0.utilization 3.5 # Layer utilization (%)
333system.membus.respLayer1.occupancy 1203485442 # Layer occupancy (ticks)
334system.membus.respLayer1.utilization 4.5 # Layer utilization (%)
335system.cpu_clk_domain.clock 500 # Clock period in ticks
336system.cpu.branchPred.lookups 16615535 # Number of BP lookups
337system.cpu.branchPred.condPredicted 12754556 # Number of conditional branches predicted
338system.cpu.branchPred.condIncorrect 602333 # Number of conditional branches incorrect
339system.cpu.branchPred.BTBLookups 10795457 # Number of BTB lookups
340system.cpu.branchPred.BTBHits 7770077 # Number of BTB hits
341system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
342system.cpu.branchPred.BTBHitPct 71.975434 # BTB Hit Percentage
343system.cpu.branchPred.usedRAS 1823925 # Number of times the RAS was used to get a target.
344system.cpu.branchPred.RASInCorrect 112966 # Number of incorrect RAS predictions.
345system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
346system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
347system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
348system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
349system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
350system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
351system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
352system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
353system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
354system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
355system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
356system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
357system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
358system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
359system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
360system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
361system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
362system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
363system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
364system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
365system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
366system.cpu.dtb.inst_hits 0 # ITB inst hits
367system.cpu.dtb.inst_misses 0 # ITB inst misses
368system.cpu.dtb.read_hits 0 # DTB read hits
369system.cpu.dtb.read_misses 0 # DTB read misses
370system.cpu.dtb.write_hits 0 # DTB write hits
371system.cpu.dtb.write_misses 0 # DTB write misses
372system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
373system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

379system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
380system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
381system.cpu.dtb.read_accesses 0 # DTB read accesses
382system.cpu.dtb.write_accesses 0 # DTB write accesses
383system.cpu.dtb.inst_accesses 0 # ITB inst accesses
384system.cpu.dtb.hits 0 # DTB hits
385system.cpu.dtb.misses 0 # DTB misses
386system.cpu.dtb.accesses 0 # DTB accesses
387system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
388system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
389system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
390system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
391system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
392system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
393system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
394system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
395system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
396system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
397system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
398system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
399system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
400system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
401system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
402system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
403system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
404system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
405system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
406system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
407system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
408system.cpu.itb.inst_hits 0 # ITB inst hits
409system.cpu.itb.inst_misses 0 # ITB inst misses
410system.cpu.itb.read_hits 0 # DTB read hits
411system.cpu.itb.read_misses 0 # DTB read misses
412system.cpu.itb.write_hits 0 # DTB write hits
413system.cpu.itb.write_misses 0 # DTB write misses
414system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
415system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 6 unchanged lines hidden (view full) ---

422system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
423system.cpu.itb.read_accesses 0 # DTB read accesses
424system.cpu.itb.write_accesses 0 # DTB write accesses
425system.cpu.itb.inst_accesses 0 # ITB inst accesses
426system.cpu.itb.hits 0 # DTB hits
427system.cpu.itb.misses 0 # DTB misses
428system.cpu.itb.accesses 0 # DTB accesses
429system.cpu.workload.num_syscalls 1946 # Number of system calls
430system.cpu.numCycles 53580777 # number of cpu cycles simulated
431system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
432system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
433system.cpu.fetch.icacheStallCycles 12546836 # Number of cycles fetch is stalled on an Icache miss
434system.cpu.fetch.Insts 85170403 # Number of instructions fetch has processed
435system.cpu.fetch.Branches 16615535 # Number of branches that fetch encountered
436system.cpu.fetch.predictedBranches 9594002 # Number of branches that fetch has predicted taken
437system.cpu.fetch.Cycles 21183792 # Number of cycles fetch has run and was not squashing or blocked
438system.cpu.fetch.SquashCycles 2362024 # Number of cycles fetch has spent squashing
439system.cpu.fetch.BlockedCycles 10685029 # Number of cycles fetch has spent blocked
440system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
441system.cpu.fetch.PendingTrapStallCycles 557 # Number of stall cycles due to pending traps
442system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR
443system.cpu.fetch.CacheLines 11675856 # Number of cache lines fetched
444system.cpu.fetch.IcacheSquashes 179932 # Number of outstanding Icache misses that were squashed
445system.cpu.fetch.rateDist::samples 46149323 # Number of instructions fetched each cycle (Total)
446system.cpu.fetch.rateDist::mean 2.583841 # Number of instructions fetched each cycle (Total)
447system.cpu.fetch.rateDist::stdev 3.333163 # Number of instructions fetched each cycle (Total)
448system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
449system.cpu.fetch.rateDist::0 24986446 54.14% 54.14% # Number of instructions fetched each cycle (Total)
450system.cpu.fetch.rateDist::1 2137638 4.63% 58.77% # Number of instructions fetched each cycle (Total)
451system.cpu.fetch.rateDist::2 1962079 4.25% 63.03% # Number of instructions fetched each cycle (Total)
452system.cpu.fetch.rateDist::3 2043997 4.43% 67.46% # Number of instructions fetched each cycle (Total)
453system.cpu.fetch.rateDist::4 1466310 3.18% 70.63% # Number of instructions fetched each cycle (Total)
454system.cpu.fetch.rateDist::5 1377582 2.99% 73.62% # Number of instructions fetched each cycle (Total)
455system.cpu.fetch.rateDist::6 960310 2.08% 75.70% # Number of instructions fetched each cycle (Total)
456system.cpu.fetch.rateDist::7 1185958 2.57% 78.27% # Number of instructions fetched each cycle (Total)
457system.cpu.fetch.rateDist::8 10029003 21.73% 100.00% # Number of instructions fetched each cycle (Total)
458system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
459system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
460system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
461system.cpu.fetch.rateDist::total 46149323 # Number of instructions fetched each cycle (Total)
462system.cpu.fetch.branchRate 0.310103 # Number of branch fetches per cycle
463system.cpu.fetch.rate 1.589570 # Number of inst fetches per cycle
464system.cpu.decode.IdleCycles 14635353 # Number of cycles decode is idle
465system.cpu.decode.BlockedCycles 9029918 # Number of cycles decode is blocked
466system.cpu.decode.RunCycles 19485051 # Number of cycles decode is running
467system.cpu.decode.UnblockCycles 1368887 # Number of cycles decode is unblocking
468system.cpu.decode.SquashCycles 1630114 # Number of cycles decode is squashing
469system.cpu.decode.BranchResolved 3325603 # Number of times decode resolved a branch
470system.cpu.decode.BranchMispred 104819 # Number of times decode detected a branch misprediction
471system.cpu.decode.DecodedInsts 116788167 # Number of instructions handled by decode
472system.cpu.decode.SquashedInsts 363460 # Number of squashed instructions handled by decode
473system.cpu.rename.SquashCycles 1630114 # Number of cycles rename is squashing
474system.cpu.rename.IdleCycles 16340014 # Number of cycles rename is idle
475system.cpu.rename.BlockCycles 2585458 # Number of cycles rename is blocking
476system.cpu.rename.serializeStallCycles 1028005 # count of cycles rename stalled for serializing inst
477system.cpu.rename.RunCycles 19100045 # Number of cycles rename is running
478system.cpu.rename.UnblockCycles 5465687 # Number of cycles rename is unblocking
479system.cpu.rename.RenamedInsts 114914880 # Number of instructions processed by rename
480system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full
481system.cpu.rename.IQFullEvents 17272 # Number of times rename has blocked due to IQ full
482system.cpu.rename.LSQFullEvents 4606354 # Number of times rename has blocked due to LSQ full
483system.cpu.rename.FullRegisterEvents 316 # Number of times there has been no free registers
484system.cpu.rename.RenamedOperands 115243032 # Number of destination operands rename has renamed
485system.cpu.rename.RenameLookups 529540867 # Number of register rename lookups that rename has made
486system.cpu.rename.int_rename_lookups 476170049 # Number of integer rename lookups
487system.cpu.rename.fp_rename_lookups 2600 # Number of floating rename lookups
488system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
489system.cpu.rename.UndoneMaps 16110360 # Number of HB maps that are undone due to squashing
490system.cpu.rename.serializingInsts 20388 # count of serializing insts renamed
491system.cpu.rename.tempSerializingInsts 20384 # count of temporary serializing insts renamed
492system.cpu.rename.skidInsts 12995984 # count of insts added to the skid buffer
493system.cpu.memDep0.insertedLoads 29602749 # Number of loads inserted to the mem dependence unit.
494system.cpu.memDep0.insertedStores 22439249 # Number of stores inserted to the mem dependence unit.
495system.cpu.memDep0.conflictingLoads 3932152 # Number of conflicting loads.
496system.cpu.memDep0.conflictingStores 4401403 # Number of conflicting stores.
497system.cpu.iq.iqInstsAdded 111507434 # Number of instructions added to the IQ (excludes non-spec)
498system.cpu.iq.iqNonSpecInstsAdded 36062 # Number of non-speculative instructions added to the IQ
499system.cpu.iq.iqInstsIssued 107242523 # Number of instructions issued
500system.cpu.iq.iqSquashedInstsIssued 272405 # Number of squashed instructions issued
501system.cpu.iq.iqSquashedInstsExamined 10768427 # Number of squashed instructions iterated over during squash; mainly for profiling
502system.cpu.iq.iqSquashedOperandsExamined 25739903 # Number of squashed operands that are examined and possibly removed from graph
503system.cpu.iq.iqSquashedNonSpecRemoved 2276 # Number of squashed non-spec instructions that were removed
504system.cpu.iq.issued_per_cycle::samples 46149323 # Number of insts issued each cycle
505system.cpu.iq.issued_per_cycle::mean 2.323816 # Number of insts issued each cycle
506system.cpu.iq.issued_per_cycle::stdev 1.990206 # Number of insts issued each cycle
507system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
508system.cpu.iq.issued_per_cycle::0 10919279 23.66% 23.66% # Number of insts issued each cycle
509system.cpu.iq.issued_per_cycle::1 8079518 17.51% 41.17% # Number of insts issued each cycle
510system.cpu.iq.issued_per_cycle::2 7423472 16.09% 57.25% # Number of insts issued each cycle
511system.cpu.iq.issued_per_cycle::3 7094481 15.37% 72.63% # Number of insts issued each cycle
512system.cpu.iq.issued_per_cycle::4 5420902 11.75% 84.37% # Number of insts issued each cycle
513system.cpu.iq.issued_per_cycle::5 3930329 8.52% 92.89% # Number of insts issued each cycle
514system.cpu.iq.issued_per_cycle::6 1841974 3.99% 96.88% # Number of insts issued each cycle
515system.cpu.iq.issued_per_cycle::7 869423 1.88% 98.76% # Number of insts issued each cycle
516system.cpu.iq.issued_per_cycle::8 569945 1.24% 100.00% # Number of insts issued each cycle
517system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
518system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
519system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
520system.cpu.iq.issued_per_cycle::total 46149323 # Number of insts issued each cycle
521system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
522system.cpu.iq.fu_full::IntAlu 112279 4.53% 4.53% # attempts to use FU when none available
523system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available
524system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available
525system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available
526system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available
527system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available
528system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available
529system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available
530system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available
531system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available
532system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available
533system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available
534system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available
535system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available
536system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available
537system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available
538system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available
539system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available
540system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available
541system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available
542system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available
543system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available
544system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available
545system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available
546system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available
547system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available
548system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available
549system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available
550system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available
551system.cpu.iq.fu_full::MemRead 1361817 54.98% 59.52% # attempts to use FU when none available
552system.cpu.iq.fu_full::MemWrite 1002641 40.48% 100.00% # attempts to use FU when none available
553system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
554system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
555system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
556system.cpu.iq.FU_type_0::IntAlu 56635396 52.81% 52.81% # Type of FU issued
557system.cpu.iq.FU_type_0::IntMult 91455 0.09% 52.90% # Type of FU issued
558system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued
559system.cpu.iq.FU_type_0::FloatAdd 208 0.00% 52.90% # Type of FU issued
560system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued
561system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued
562system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued
563system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued
564system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued
565system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued
566system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued
567system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued
568system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued
569system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued
570system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued
571system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued
572system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued
573system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued
574system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued
575system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued
576system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued
577system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued
578system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued
579system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued
580system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued
581system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued
582system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued
583system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued
584system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued
585system.cpu.iq.FU_type_0::MemRead 28883502 26.93% 79.83% # Type of FU issued
586system.cpu.iq.FU_type_0::MemWrite 21631955 20.17% 100.00% # Type of FU issued
587system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
588system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
589system.cpu.iq.FU_type_0::total 107242523 # Type of FU issued
590system.cpu.iq.rate 2.001511 # Inst issue rate
591system.cpu.iq.fu_busy_cnt 2476739 # FU busy when requested
592system.cpu.iq.fu_busy_rate 0.023095 # FU busy rate (busy events/executed inst)
593system.cpu.iq.int_inst_queue_reads 263382945 # Number of integer instruction queue reads
594system.cpu.iq.int_inst_queue_writes 122340040 # Number of integer instruction queue writes
595system.cpu.iq.int_inst_queue_wakeup_accesses 105564996 # Number of integer instruction queue wakeup accesses
596system.cpu.iq.fp_inst_queue_reads 568 # Number of floating instruction queue reads
597system.cpu.iq.fp_inst_queue_writes 856 # Number of floating instruction queue writes
598system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses
599system.cpu.iq.int_alu_accesses 109718975 # Number of integer alu accesses
600system.cpu.iq.fp_alu_accesses 287 # Number of floating point alu accesses
601system.cpu.iew.lsq.thread0.forwLoads 2181751 # Number of loads that had data forwarded from stores
602system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
603system.cpu.iew.lsq.thread0.squashedLoads 2295641 # Number of loads squashed
604system.cpu.iew.lsq.thread0.ignoredResponses 6455 # Number of memory responses ignored because the instruction is squashed
605system.cpu.iew.lsq.thread0.memOrderViolation 29983 # Number of memory ordering violations
606system.cpu.iew.lsq.thread0.squashedStores 1883511 # Number of stores squashed
607system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
608system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
609system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled
610system.cpu.iew.lsq.thread0.cacheBlocked 679 # Number of times an access to memory failed due to the cache being blocked
611system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
612system.cpu.iew.iewSquashCycles 1630114 # Number of cycles IEW is squashing
613system.cpu.iew.iewBlockCycles 1093825 # Number of cycles IEW is blocking
614system.cpu.iew.iewUnblockCycles 45147 # Number of cycles IEW is unblocking
615system.cpu.iew.iewDispatchedInsts 111553302 # Number of instructions dispatched to IQ
616system.cpu.iew.iewDispSquashedInsts 294819 # Number of squashed instructions skipped by dispatch
617system.cpu.iew.iewDispLoadInsts 29602749 # Number of dispatched load instructions
618system.cpu.iew.iewDispStoreInsts 22439249 # Number of dispatched store instructions
619system.cpu.iew.iewDispNonSpecInsts 20142 # Number of dispatched non-speculative instructions
620system.cpu.iew.iewIQFullEvents 6322 # Number of times the IQ has become full, causing a stall
621system.cpu.iew.iewLSQFullEvents 5200 # Number of times the LSQ has become full, causing a stall
622system.cpu.iew.memOrderViolationEvents 29983 # Number of memory order violations
623system.cpu.iew.predictedTakenIncorrect 391827 # Number of branches that were predicted taken incorrectly
624system.cpu.iew.predictedNotTakenIncorrect 180696 # Number of branches that were predicted not taken incorrectly
625system.cpu.iew.branchMispredicts 572523 # Number of branch mispredicts detected at execute
626system.cpu.iew.iewExecutedInsts 106211851 # Number of executed instructions
627system.cpu.iew.iewExecLoadInsts 28585179 # Number of load instructions executed
628system.cpu.iew.iewExecSquashedInsts 1030672 # Number of squashed instructions skipped in execute
629system.cpu.iew.exec_swp 0 # number of swp insts executed
630system.cpu.iew.exec_nop 9806 # number of nop insts executed
631system.cpu.iew.exec_refs 49926975 # number of memory reference insts executed
632system.cpu.iew.exec_branches 14599283 # Number of branches executed
633system.cpu.iew.exec_stores 21341796 # Number of stores executed
634system.cpu.iew.exec_rate 1.982275 # Inst execution rate
635system.cpu.iew.wb_sent 105782073 # cumulative count of insts sent to commit
636system.cpu.iew.wb_count 105565164 # cumulative count of insts written-back
637system.cpu.iew.wb_producers 53316718 # num instructions producing a value
638system.cpu.iew.wb_consumers 103963305 # num instructions consuming a value
639system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
640system.cpu.iew.wb_rate 1.970206 # insts written-back per cycle
641system.cpu.iew.wb_fanout 0.512842 # average fanout of values written-back
642system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
643system.cpu.commit.commitSquashedInsts 10921742 # The number of squashed insts skipped by commit
644system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
645system.cpu.commit.branchMispredicts 499421 # The number of times a branch was mispredicted
646system.cpu.commit.committed_per_cycle::samples 44519209 # Number of insts commited each cycle
647system.cpu.commit.committed_per_cycle::mean 2.260427 # Number of insts commited each cycle
648system.cpu.commit.committed_per_cycle::stdev 2.765009 # Number of insts commited each cycle
649system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
650system.cpu.commit.committed_per_cycle::0 15470185 34.75% 34.75% # Number of insts commited each cycle
651system.cpu.commit.committed_per_cycle::1 11634994 26.13% 60.88% # Number of insts commited each cycle
652system.cpu.commit.committed_per_cycle::2 3452010 7.75% 68.64% # Number of insts commited each cycle
653system.cpu.commit.committed_per_cycle::3 2868846 6.44% 75.08% # Number of insts commited each cycle
654system.cpu.commit.committed_per_cycle::4 1865323 4.19% 79.27% # Number of insts commited each cycle
655system.cpu.commit.committed_per_cycle::5 1954753 4.39% 83.66% # Number of insts commited each cycle
656system.cpu.commit.committed_per_cycle::6 686748 1.54% 85.21% # Number of insts commited each cycle
657system.cpu.commit.committed_per_cycle::7 559469 1.26% 86.46% # Number of insts commited each cycle
658system.cpu.commit.committed_per_cycle::8 6026881 13.54% 100.00% # Number of insts commited each cycle
659system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
660system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
661system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
662system.cpu.commit.committed_per_cycle::total 44519209 # Number of insts commited each cycle
663system.cpu.commit.committedInsts 70913181 # Number of instructions committed
664system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
665system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
666system.cpu.commit.refs 47862846 # Number of memory references committed
667system.cpu.commit.loads 27307108 # Number of loads committed
668system.cpu.commit.membars 15920 # Number of memory barriers committed
669system.cpu.commit.branches 13741485 # Number of branches committed
670system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
671system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
672system.cpu.commit.function_calls 1679850 # Number of function calls committed.
673system.cpu.commit.bw_lim_events 6026881 # number cycles where commit BW limit reached
674system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
675system.cpu.rob.rob_reads 150021199 # The number of ROB reads
676system.cpu.rob.rob_writes 224747411 # The number of ROB writes
677system.cpu.timesIdled 76674 # Number of times that the entire CPU went into an idle state and unscheduled itself
678system.cpu.idleCycles 7431454 # Total number of cycles that the CPU has spent unscheduled due to idling
679system.cpu.committedInsts 70907629 # Number of Instructions Simulated
680system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
681system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
682system.cpu.cpi 0.755642 # CPI: Cycles Per Instruction
683system.cpu.cpi_total 0.755642 # CPI: Total CPI of All Threads
684system.cpu.ipc 1.323378 # IPC: Instructions Per Cycle
685system.cpu.ipc_total 1.323378 # IPC: Total IPC of All Threads
686system.cpu.int_regfile_reads 511545132 # number of integer regfile reads
687system.cpu.int_regfile_writes 103340839 # number of integer regfile writes
688system.cpu.fp_regfile_reads 806 # number of floating regfile reads
689system.cpu.fp_regfile_writes 694 # number of floating regfile writes
690system.cpu.misc_regfile_reads 49339612 # number of misc regfile reads
691system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
692system.cpu.toL2Bus.throughput 773036658 # Throughput (bytes/s)
693system.cpu.toL2Bus.trans_dist::ReadReq 87363 # Transaction distribution
694system.cpu.toL2Bus.trans_dist::ReadResp 87363 # Transaction distribution
695system.cpu.toL2Bus.trans_dist::Writeback 129182 # Transaction distribution
696system.cpu.toL2Bus.trans_dist::UpgradeReq 325 # Transaction distribution
697system.cpu.toL2Bus.trans_dist::UpgradeResp 325 # Transaction distribution
698system.cpu.toL2Bus.trans_dist::ReadExReq 107048 # Transaction distribution
699system.cpu.toL2Bus.trans_dist::ReadExResp 107048 # Transaction distribution
700system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63452 # Packet count per connected master and slave (bytes)
701system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454686 # Packet count per connected master and slave (bytes)
702system.cpu.toL2Bus.pkt_count::total 518138 # Packet count per connected master and slave (bytes)
703system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2013952 # Cumulative packet size per connected master and slave (bytes)
704system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18662976 # Cumulative packet size per connected master and slave (bytes)
705system.cpu.toL2Bus.tot_pkt_size::total 20676928 # Cumulative packet size per connected master and slave (bytes)
706system.cpu.toL2Bus.data_through_bus 20676928 # Total data (bytes)
707system.cpu.toL2Bus.snoop_data_through_bus 33024 # Total snoop data (bytes)
708system.cpu.toL2Bus.reqLayer0.occupancy 291143497 # Layer occupancy (ticks)
709system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
710system.cpu.toL2Bus.respLayer0.occupancy 48712731 # Layer occupancy (ticks)
711system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
712system.cpu.toL2Bus.respLayer1.occupancy 260354993 # Layer occupancy (ticks)
713system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
714system.cpu.icache.tags.replacements 29638 # number of replacements
715system.cpu.icache.tags.tagsinuse 1806.211071 # Cycle average of tags in use
716system.cpu.icache.tags.total_refs 11640103 # Total number of references to valid blocks.
717system.cpu.icache.tags.sampled_refs 31672 # Sample count of references to valid blocks.
718system.cpu.icache.tags.avg_refs 367.520302 # Average number of references to valid blocks.
719system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
720system.cpu.icache.tags.occ_blocks::cpu.inst 1806.211071 # Average occupied blocks per requestor
721system.cpu.icache.tags.occ_percent::cpu.inst 0.881939 # Average percentage of cache occupancy
722system.cpu.icache.tags.occ_percent::total 0.881939 # Average percentage of cache occupancy
723system.cpu.icache.tags.occ_task_id_blocks::1024 2034 # Occupied blocks per task id
724system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
725system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
726system.cpu.icache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id
727system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id
728system.cpu.icache.tags.occ_task_id_percent::1024 0.993164 # Percentage of cache occupancy per task id
729system.cpu.icache.tags.tag_accesses 23383696 # Number of tag accesses
730system.cpu.icache.tags.data_accesses 23383696 # Number of data accesses
731system.cpu.icache.ReadReq_hits::cpu.inst 11640118 # number of ReadReq hits
732system.cpu.icache.ReadReq_hits::total 11640118 # number of ReadReq hits
733system.cpu.icache.demand_hits::cpu.inst 11640118 # number of demand (read+write) hits
734system.cpu.icache.demand_hits::total 11640118 # number of demand (read+write) hits
735system.cpu.icache.overall_hits::cpu.inst 11640118 # number of overall hits
736system.cpu.icache.overall_hits::total 11640118 # number of overall hits
737system.cpu.icache.ReadReq_misses::cpu.inst 35738 # number of ReadReq misses
738system.cpu.icache.ReadReq_misses::total 35738 # number of ReadReq misses
739system.cpu.icache.demand_misses::cpu.inst 35738 # number of demand (read+write) misses
740system.cpu.icache.demand_misses::total 35738 # number of demand (read+write) misses
741system.cpu.icache.overall_misses::cpu.inst 35738 # number of overall misses
742system.cpu.icache.overall_misses::total 35738 # number of overall misses
743system.cpu.icache.ReadReq_miss_latency::cpu.inst 828271479 # number of ReadReq miss cycles
744system.cpu.icache.ReadReq_miss_latency::total 828271479 # number of ReadReq miss cycles
745system.cpu.icache.demand_miss_latency::cpu.inst 828271479 # number of demand (read+write) miss cycles
746system.cpu.icache.demand_miss_latency::total 828271479 # number of demand (read+write) miss cycles
747system.cpu.icache.overall_miss_latency::cpu.inst 828271479 # number of overall miss cycles
748system.cpu.icache.overall_miss_latency::total 828271479 # number of overall miss cycles
749system.cpu.icache.ReadReq_accesses::cpu.inst 11675856 # number of ReadReq accesses(hits+misses)
750system.cpu.icache.ReadReq_accesses::total 11675856 # number of ReadReq accesses(hits+misses)
751system.cpu.icache.demand_accesses::cpu.inst 11675856 # number of demand (read+write) accesses
752system.cpu.icache.demand_accesses::total 11675856 # number of demand (read+write) accesses
753system.cpu.icache.overall_accesses::cpu.inst 11675856 # number of overall (read+write) accesses
754system.cpu.icache.overall_accesses::total 11675856 # number of overall (read+write) accesses
755system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003061 # miss rate for ReadReq accesses
756system.cpu.icache.ReadReq_miss_rate::total 0.003061 # miss rate for ReadReq accesses
757system.cpu.icache.demand_miss_rate::cpu.inst 0.003061 # miss rate for demand accesses
758system.cpu.icache.demand_miss_rate::total 0.003061 # miss rate for demand accesses
759system.cpu.icache.overall_miss_rate::cpu.inst 0.003061 # miss rate for overall accesses
760system.cpu.icache.overall_miss_rate::total 0.003061 # miss rate for overall accesses
761system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23176.212407 # average ReadReq miss latency
762system.cpu.icache.ReadReq_avg_miss_latency::total 23176.212407 # average ReadReq miss latency
763system.cpu.icache.demand_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency
764system.cpu.icache.demand_avg_miss_latency::total 23176.212407 # average overall miss latency
765system.cpu.icache.overall_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency
766system.cpu.icache.overall_avg_miss_latency::total 23176.212407 # average overall miss latency
767system.cpu.icache.blocked_cycles::no_mshrs 856 # number of cycles access was blocked
768system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
769system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked
770system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
771system.cpu.icache.avg_blocked_cycles::no_mshrs 42.800000 # average number of cycles each access was blocked
772system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
773system.cpu.icache.fast_writes 0 # number of fast writes performed
774system.cpu.icache.cache_copies 0 # number of cache copies performed
775system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3754 # number of ReadReq MSHR hits
776system.cpu.icache.ReadReq_mshr_hits::total 3754 # number of ReadReq MSHR hits
777system.cpu.icache.demand_mshr_hits::cpu.inst 3754 # number of demand (read+write) MSHR hits
778system.cpu.icache.demand_mshr_hits::total 3754 # number of demand (read+write) MSHR hits
779system.cpu.icache.overall_mshr_hits::cpu.inst 3754 # number of overall MSHR hits
780system.cpu.icache.overall_mshr_hits::total 3754 # number of overall MSHR hits
781system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31984 # number of ReadReq MSHR misses
782system.cpu.icache.ReadReq_mshr_misses::total 31984 # number of ReadReq MSHR misses
783system.cpu.icache.demand_mshr_misses::cpu.inst 31984 # number of demand (read+write) MSHR misses
784system.cpu.icache.demand_mshr_misses::total 31984 # number of demand (read+write) MSHR misses
785system.cpu.icache.overall_mshr_misses::cpu.inst 31984 # number of overall MSHR misses
786system.cpu.icache.overall_mshr_misses::total 31984 # number of overall MSHR misses
787system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 671357769 # number of ReadReq MSHR miss cycles
788system.cpu.icache.ReadReq_mshr_miss_latency::total 671357769 # number of ReadReq MSHR miss cycles
789system.cpu.icache.demand_mshr_miss_latency::cpu.inst 671357769 # number of demand (read+write) MSHR miss cycles
790system.cpu.icache.demand_mshr_miss_latency::total 671357769 # number of demand (read+write) MSHR miss cycles
791system.cpu.icache.overall_mshr_miss_latency::cpu.inst 671357769 # number of overall MSHR miss cycles
792system.cpu.icache.overall_mshr_miss_latency::total 671357769 # number of overall MSHR miss cycles
793system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for ReadReq accesses
794system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002739 # mshr miss rate for ReadReq accesses
795system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for demand accesses
796system.cpu.icache.demand_mshr_miss_rate::total 0.002739 # mshr miss rate for demand accesses
797system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for overall accesses
798system.cpu.icache.overall_mshr_miss_rate::total 0.002739 # mshr miss rate for overall accesses
799system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20990.425494 # average ReadReq mshr miss latency
800system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20990.425494 # average ReadReq mshr miss latency
801system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20990.425494 # average overall mshr miss latency
802system.cpu.icache.demand_avg_mshr_miss_latency::total 20990.425494 # average overall mshr miss latency
803system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20990.425494 # average overall mshr miss latency
804system.cpu.icache.overall_avg_mshr_miss_latency::total 20990.425494 # average overall mshr miss latency
805system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
806system.cpu.l2cache.tags.replacements 95620 # number of replacements
807system.cpu.l2cache.tags.tagsinuse 29882.992791 # Cycle average of tags in use
808system.cpu.l2cache.tags.total_refs 89182 # Total number of references to valid blocks.
809system.cpu.l2cache.tags.sampled_refs 126734 # Sample count of references to valid blocks.
810system.cpu.l2cache.tags.avg_refs 0.703694 # Average number of references to valid blocks.
811system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
812system.cpu.l2cache.tags.occ_blocks::writebacks 26677.610156 # Average occupied blocks per requestor
813system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.039955 # Average occupied blocks per requestor
814system.cpu.l2cache.tags.occ_blocks::cpu.data 1839.342681 # Average occupied blocks per requestor
815system.cpu.l2cache.tags.occ_percent::writebacks 0.814136 # Average percentage of cache occupancy
816system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041688 # Average percentage of cache occupancy
817system.cpu.l2cache.tags.occ_percent::cpu.data 0.056132 # Average percentage of cache occupancy
818system.cpu.l2cache.tags.occ_percent::total 0.911957 # Average percentage of cache occupancy
819system.cpu.l2cache.tags.occ_task_id_blocks::1024 31114 # Occupied blocks per task id
820system.cpu.l2cache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
821system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1849 # Occupied blocks per task id
822system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20244 # Occupied blocks per task id
823system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8486 # Occupied blocks per task id
824system.cpu.l2cache.tags.age_task_id_blocks_1024::4 391 # Occupied blocks per task id
825system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949524 # Percentage of cache occupancy per task id
826system.cpu.l2cache.tags.tag_accesses 2821016 # Number of tag accesses
827system.cpu.l2cache.tags.data_accesses 2821016 # Number of data accesses
828system.cpu.l2cache.ReadReq_hits::cpu.inst 26805 # number of ReadReq hits
829system.cpu.l2cache.ReadReq_hits::cpu.data 33463 # number of ReadReq hits
830system.cpu.l2cache.ReadReq_hits::total 60268 # number of ReadReq hits
831system.cpu.l2cache.Writeback_hits::writebacks 129182 # number of Writeback hits
832system.cpu.l2cache.Writeback_hits::total 129182 # number of Writeback hits
833system.cpu.l2cache.UpgradeReq_hits::cpu.data 17 # number of UpgradeReq hits
834system.cpu.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits
835system.cpu.l2cache.ReadExReq_hits::cpu.data 4794 # number of ReadExReq hits
836system.cpu.l2cache.ReadExReq_hits::total 4794 # number of ReadExReq hits
837system.cpu.l2cache.demand_hits::cpu.inst 26805 # number of demand (read+write) hits
838system.cpu.l2cache.demand_hits::cpu.data 38257 # number of demand (read+write) hits
839system.cpu.l2cache.demand_hits::total 65062 # number of demand (read+write) hits
840system.cpu.l2cache.overall_hits::cpu.inst 26805 # number of overall hits
841system.cpu.l2cache.overall_hits::cpu.data 38257 # number of overall hits
842system.cpu.l2cache.overall_hits::total 65062 # number of overall hits
843system.cpu.l2cache.ReadReq_misses::cpu.inst 4663 # number of ReadReq misses
844system.cpu.l2cache.ReadReq_misses::cpu.data 21916 # number of ReadReq misses
845system.cpu.l2cache.ReadReq_misses::total 26579 # number of ReadReq misses
846system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses
847system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses
848system.cpu.l2cache.ReadExReq_misses::cpu.data 102254 # number of ReadExReq misses
849system.cpu.l2cache.ReadExReq_misses::total 102254 # number of ReadExReq misses
850system.cpu.l2cache.demand_misses::cpu.inst 4663 # number of demand (read+write) misses
851system.cpu.l2cache.demand_misses::cpu.data 124170 # number of demand (read+write) misses
852system.cpu.l2cache.demand_misses::total 128833 # number of demand (read+write) misses
853system.cpu.l2cache.overall_misses::cpu.inst 4663 # number of overall misses
854system.cpu.l2cache.overall_misses::cpu.data 124170 # number of overall misses
855system.cpu.l2cache.overall_misses::total 128833 # number of overall misses
856system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 370582250 # number of ReadReq miss cycles
857system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1870540500 # number of ReadReq miss cycles
858system.cpu.l2cache.ReadReq_miss_latency::total 2241122750 # number of ReadReq miss cycles
859system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles
860system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles
861system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8514187000 # number of ReadExReq miss cycles
862system.cpu.l2cache.ReadExReq_miss_latency::total 8514187000 # number of ReadExReq miss cycles
863system.cpu.l2cache.demand_miss_latency::cpu.inst 370582250 # number of demand (read+write) miss cycles
864system.cpu.l2cache.demand_miss_latency::cpu.data 10384727500 # number of demand (read+write) miss cycles
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867system.cpu.l2cache.overall_miss_latency::cpu.data 10384727500 # number of overall miss cycles
868system.cpu.l2cache.overall_miss_latency::total 10755309750 # number of overall miss cycles
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872system.cpu.l2cache.Writeback_accesses::writebacks 129182 # number of Writeback accesses(hits+misses)
873system.cpu.l2cache.Writeback_accesses::total 129182 # number of Writeback accesses(hits+misses)
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875system.cpu.l2cache.UpgradeReq_accesses::total 325 # number of UpgradeReq accesses(hits+misses)
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877system.cpu.l2cache.ReadExReq_accesses::total 107048 # number of ReadExReq accesses(hits+misses)
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885system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395746 # miss rate for ReadReq accesses
886system.cpu.l2cache.ReadReq_miss_rate::total 0.306044 # miss rate for ReadReq accesses
887system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947692 # miss rate for UpgradeReq accesses
888system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947692 # miss rate for UpgradeReq accesses
889system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955216 # miss rate for ReadExReq accesses
890system.cpu.l2cache.ReadExReq_miss_rate::total 0.955216 # miss rate for ReadExReq accesses
891system.cpu.l2cache.demand_miss_rate::cpu.inst 0.148182 # miss rate for demand accesses
892system.cpu.l2cache.demand_miss_rate::cpu.data 0.764466 # miss rate for demand accesses
893system.cpu.l2cache.demand_miss_rate::total 0.664447 # miss rate for demand accesses
894system.cpu.l2cache.overall_miss_rate::cpu.inst 0.148182 # miss rate for overall accesses
895system.cpu.l2cache.overall_miss_rate::cpu.data 0.764466 # miss rate for overall accesses
896system.cpu.l2cache.overall_miss_rate::total 0.664447 # miss rate for overall accesses
897system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79472.925155 # average ReadReq miss latency
898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85350.451725 # average ReadReq miss latency
899system.cpu.l2cache.ReadReq_avg_miss_latency::total 84319.302833 # average ReadReq miss latency
900system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 74.672078 # average UpgradeReq miss latency
901system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 74.672078 # average UpgradeReq miss latency
902system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83265.075205 # average ReadExReq miss latency
903system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83265.075205 # average ReadExReq miss latency
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905system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83633.144077 # average overall miss latency
906system.cpu.l2cache.demand_avg_miss_latency::total 83482.568519 # average overall miss latency
907system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79472.925155 # average overall miss latency
908system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83633.144077 # average overall miss latency
909system.cpu.l2cache.overall_avg_miss_latency::total 83482.568519 # average overall miss latency
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911system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
912system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
913system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
914system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
915system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
916system.cpu.l2cache.fast_writes 0 # number of fast writes performed
917system.cpu.l2cache.cache_copies 0 # number of cache copies performed
918system.cpu.l2cache.writebacks::writebacks 83937 # number of writebacks
919system.cpu.l2cache.writebacks::total 83937 # number of writebacks
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921system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
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924system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
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926system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits
927system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
928system.cpu.l2cache.overall_mshr_hits::total 79 # number of overall MSHR hits
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930system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21854 # number of ReadReq MSHR misses
931system.cpu.l2cache.ReadReq_mshr_misses::total 26500 # number of ReadReq MSHR misses
932system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses
933system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses
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935system.cpu.l2cache.ReadExReq_mshr_misses::total 102254 # number of ReadExReq MSHR misses
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940system.cpu.l2cache.overall_mshr_misses::cpu.data 124108 # number of overall MSHR misses
941system.cpu.l2cache.overall_mshr_misses::total 128754 # number of overall MSHR misses
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945system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3080308 # number of UpgradeReq MSHR miss cycles
946system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3080308 # number of UpgradeReq MSHR miss cycles
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948system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7238548000 # number of ReadExReq MSHR miss cycles
949system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 311360750 # number of demand (read+write) MSHR miss cycles
950system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8832023000 # number of demand (read+write) MSHR miss cycles
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953system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8832023000 # number of overall MSHR miss cycles
954system.cpu.l2cache.overall_mshr_miss_latency::total 9143383750 # number of overall MSHR miss cycles
955system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.147642 # mshr miss rate for ReadReq accesses
956system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394626 # mshr miss rate for ReadReq accesses
957system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305134 # mshr miss rate for ReadReq accesses
958system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947692 # mshr miss rate for UpgradeReq accesses
959system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947692 # mshr miss rate for UpgradeReq accesses
960system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955216 # mshr miss rate for ReadExReq accesses
961system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955216 # mshr miss rate for ReadExReq accesses
962system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.147642 # mshr miss rate for demand accesses
963system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764085 # mshr miss rate for demand accesses
964system.cpu.l2cache.demand_mshr_miss_rate::total 0.664040 # mshr miss rate for demand accesses
965system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.147642 # mshr miss rate for overall accesses
966system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764085 # mshr miss rate for overall accesses
967system.cpu.l2cache.overall_mshr_miss_rate::total 0.664040 # mshr miss rate for overall accesses
968system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67016.950065 # average ReadReq mshr miss latency
969system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72914.569415 # average ReadReq mshr miss latency
970system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71880.594340 # average ReadReq mshr miss latency
971system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
972system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
973system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70789.876191 # average ReadExReq mshr miss latency
974system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70789.876191 # average ReadExReq mshr miss latency
975system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67016.950065 # average overall mshr miss latency
976system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71164.010378 # average overall mshr miss latency
977system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71014.366544 # average overall mshr miss latency
978system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67016.950065 # average overall mshr miss latency
979system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71164.010378 # average overall mshr miss latency
980system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71014.366544 # average overall mshr miss latency
981system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
982system.cpu.dcache.tags.replacements 158331 # number of replacements
983system.cpu.dcache.tags.tagsinuse 4068.839586 # Cycle average of tags in use
984system.cpu.dcache.tags.total_refs 44347897 # Total number of references to valid blocks.
985system.cpu.dcache.tags.sampled_refs 162427 # Sample count of references to valid blocks.
986system.cpu.dcache.tags.avg_refs 273.032790 # Average number of references to valid blocks.
987system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit.
988system.cpu.dcache.tags.occ_blocks::cpu.data 4068.839586 # Average occupied blocks per requestor
989system.cpu.dcache.tags.occ_percent::cpu.data 0.993369 # Average percentage of cache occupancy
990system.cpu.dcache.tags.occ_percent::total 0.993369 # Average percentage of cache occupancy
991system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
992system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
993system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id
994system.cpu.dcache.tags.age_task_id_blocks_1024::2 2254 # Occupied blocks per task id
995system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
996system.cpu.dcache.tags.tag_accesses 92273995 # Number of tag accesses
997system.cpu.dcache.tags.data_accesses 92273995 # Number of data accesses
998system.cpu.dcache.ReadReq_hits::cpu.data 26048802 # number of ReadReq hits
999system.cpu.dcache.ReadReq_hits::total 26048802 # number of ReadReq hits
1000system.cpu.dcache.WriteReq_hits::cpu.data 18266579 # number of WriteReq hits
1001system.cpu.dcache.WriteReq_hits::total 18266579 # number of WriteReq hits
1002system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits
1003system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits
1004system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
1005system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
1006system.cpu.dcache.demand_hits::cpu.data 44315381 # number of demand (read+write) hits
1007system.cpu.dcache.demand_hits::total 44315381 # number of demand (read+write) hits
1008system.cpu.dcache.overall_hits::cpu.data 44315381 # number of overall hits
1009system.cpu.dcache.overall_hits::total 44315381 # number of overall hits
1010system.cpu.dcache.ReadReq_misses::cpu.data 125140 # number of ReadReq misses
1011system.cpu.dcache.ReadReq_misses::total 125140 # number of ReadReq misses
1012system.cpu.dcache.WriteReq_misses::cpu.data 1583322 # number of WriteReq misses
1013system.cpu.dcache.WriteReq_misses::total 1583322 # number of WriteReq misses
1014system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses
1015system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses
1016system.cpu.dcache.demand_misses::cpu.data 1708462 # number of demand (read+write) misses
1017system.cpu.dcache.demand_misses::total 1708462 # number of demand (read+write) misses
1018system.cpu.dcache.overall_misses::cpu.data 1708462 # number of overall misses
1019system.cpu.dcache.overall_misses::total 1708462 # number of overall misses
1020system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205484954 # number of ReadReq miss cycles
1021system.cpu.dcache.ReadReq_miss_latency::total 5205484954 # number of ReadReq miss cycles
1022system.cpu.dcache.WriteReq_miss_latency::cpu.data 127036653749 # number of WriteReq miss cycles
1023system.cpu.dcache.WriteReq_miss_latency::total 127036653749 # number of WriteReq miss cycles
1024system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 856750 # number of LoadLockedReq miss cycles
1025system.cpu.dcache.LoadLockedReq_miss_latency::total 856750 # number of LoadLockedReq miss cycles
1026system.cpu.dcache.demand_miss_latency::cpu.data 132242138703 # number of demand (read+write) miss cycles
1027system.cpu.dcache.demand_miss_latency::total 132242138703 # number of demand (read+write) miss cycles
1028system.cpu.dcache.overall_miss_latency::cpu.data 132242138703 # number of overall miss cycles
1029system.cpu.dcache.overall_miss_latency::total 132242138703 # number of overall miss cycles
1030system.cpu.dcache.ReadReq_accesses::cpu.data 26173942 # number of ReadReq accesses(hits+misses)
1031system.cpu.dcache.ReadReq_accesses::total 26173942 # number of ReadReq accesses(hits+misses)
1032system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
1033system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
1034system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16022 # number of LoadLockedReq accesses(hits+misses)
1035system.cpu.dcache.LoadLockedReq_accesses::total 16022 # number of LoadLockedReq accesses(hits+misses)
1036system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
1037system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
1038system.cpu.dcache.demand_accesses::cpu.data 46023843 # number of demand (read+write) accesses
1039system.cpu.dcache.demand_accesses::total 46023843 # number of demand (read+write) accesses
1040system.cpu.dcache.overall_accesses::cpu.data 46023843 # number of overall (read+write) accesses
1041system.cpu.dcache.overall_accesses::total 46023843 # number of overall (read+write) accesses
1042system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004781 # miss rate for ReadReq accesses
1043system.cpu.dcache.ReadReq_miss_rate::total 0.004781 # miss rate for ReadReq accesses
1044system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079765 # miss rate for WriteReq accesses
1045system.cpu.dcache.WriteReq_miss_rate::total 0.079765 # miss rate for WriteReq accesses
1046system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002559 # miss rate for LoadLockedReq accesses
1047system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002559 # miss rate for LoadLockedReq accesses
1048system.cpu.dcache.demand_miss_rate::cpu.data 0.037121 # miss rate for demand accesses
1049system.cpu.dcache.demand_miss_rate::total 0.037121 # miss rate for demand accesses
1050system.cpu.dcache.overall_miss_rate::cpu.data 0.037121 # miss rate for overall accesses
1051system.cpu.dcache.overall_miss_rate::total 0.037121 # miss rate for overall accesses
1052system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41597.290666 # average ReadReq miss latency
1053system.cpu.dcache.ReadReq_avg_miss_latency::total 41597.290666 # average ReadReq miss latency
1054system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80234.250360 # average WriteReq miss latency
1055system.cpu.dcache.WriteReq_avg_miss_latency::total 80234.250360 # average WriteReq miss latency
1056system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20896.341463 # average LoadLockedReq miss latency
1057system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20896.341463 # average LoadLockedReq miss latency
1058system.cpu.dcache.demand_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency
1059system.cpu.dcache.demand_avg_miss_latency::total 77404.202554 # average overall miss latency
1060system.cpu.dcache.overall_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency
1061system.cpu.dcache.overall_avg_miss_latency::total 77404.202554 # average overall miss latency
1062system.cpu.dcache.blocked_cycles::no_mshrs 4865 # number of cycles access was blocked
1063system.cpu.dcache.blocked_cycles::no_targets 1223 # number of cycles access was blocked
1064system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
1065system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked
1066system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.510949 # average number of cycles each access was blocked
1067system.cpu.dcache.avg_blocked_cycles::no_targets 87.357143 # average number of cycles each access was blocked
1068system.cpu.dcache.fast_writes 0 # number of fast writes performed
1069system.cpu.dcache.cache_copies 0 # number of cache copies performed
1070system.cpu.dcache.writebacks::writebacks 129182 # number of writebacks
1071system.cpu.dcache.writebacks::total 129182 # number of writebacks
1072system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69727 # number of ReadReq MSHR hits
1073system.cpu.dcache.ReadReq_mshr_hits::total 69727 # number of ReadReq MSHR hits
1074system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475983 # number of WriteReq MSHR hits
1075system.cpu.dcache.WriteReq_mshr_hits::total 1475983 # number of WriteReq MSHR hits
1076system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits
1077system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits
1078system.cpu.dcache.demand_mshr_hits::cpu.data 1545710 # number of demand (read+write) MSHR hits
1079system.cpu.dcache.demand_mshr_hits::total 1545710 # number of demand (read+write) MSHR hits
1080system.cpu.dcache.overall_mshr_hits::cpu.data 1545710 # number of overall MSHR hits
1081system.cpu.dcache.overall_mshr_hits::total 1545710 # number of overall MSHR hits
1082system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses
1083system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses
1084system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107339 # number of WriteReq MSHR misses
1085system.cpu.dcache.WriteReq_mshr_misses::total 107339 # number of WriteReq MSHR misses
1086system.cpu.dcache.demand_mshr_misses::cpu.data 162752 # number of demand (read+write) MSHR misses
1087system.cpu.dcache.demand_mshr_misses::total 162752 # number of demand (read+write) MSHR misses
1088system.cpu.dcache.overall_mshr_misses::cpu.data 162752 # number of overall MSHR misses
1089system.cpu.dcache.overall_mshr_misses::total 162752 # number of overall MSHR misses
1090system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263243564 # number of ReadReq MSHR miss cycles
1091system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263243564 # number of ReadReq MSHR miss cycles
1092system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8680214182 # number of WriteReq MSHR miss cycles
1093system.cpu.dcache.WriteReq_mshr_miss_latency::total 8680214182 # number of WriteReq MSHR miss cycles
1094system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10943457746 # number of demand (read+write) MSHR miss cycles
1095system.cpu.dcache.demand_mshr_miss_latency::total 10943457746 # number of demand (read+write) MSHR miss cycles
1096system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10943457746 # number of overall MSHR miss cycles
1097system.cpu.dcache.overall_mshr_miss_latency::total 10943457746 # number of overall MSHR miss cycles
1098system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses
1099system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses
1100system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses
1101system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses
1102system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
1103system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
1104system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
1105system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
1106system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40843.187772 # average ReadReq mshr miss latency
1107system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40843.187772 # average ReadReq mshr miss latency
1108system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80867.291311 # average WriteReq mshr miss latency
1109system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80867.291311 # average WriteReq mshr miss latency
1110system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency
1111system.cpu.dcache.demand_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency
1112system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency
1113system.cpu.dcache.overall_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency
1114system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1115
1116---------- End Simulation Statistics ----------