| config.ini (9055:38f1926fb599) | config.ini (9575:6c4d6fdf3644) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=200000000 7time_sync_spin_threshold=200000 8 9[system] 10type=SparcSystem 11children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000 12boot_osflags=a | 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=200000000 7time_sync_spin_threshold=200000 8 9[system] 10type=SparcSystem 11children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000 12boot_osflags=a |
| 13clock=2 |
|
| 13hypervisor_addr=1099243257856 14hypervisor_bin=/dist/m5/system/binaries/q_new.bin 15hypervisor_desc=system.hypervisor_desc 16hypervisor_desc_addr=133446500352 17hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=atomic | 14hypervisor_addr=1099243257856 15hypervisor_bin=/dist/m5/system/binaries/q_new.bin 16hypervisor_desc=system.hypervisor_desc 17hypervisor_desc_addr=133446500352 18hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin 19init_param=0 20kernel= 21load_addr_mask=1099511627775 22mem_mode=atomic |
| 22memories=system.partition_desc system.rom system.hypervisor_desc system.nvram system.physmem system.physmem2 | 23mem_ranges=1048576:68157439 2147483648:2415919103 24memories=system.partition_desc system.physmem system.rom system.hypervisor_desc system.physmem2 system.nvram |
| 23num_work_ids=16 24nvram=system.nvram 25nvram_addr=133429198848 26nvram_bin=/dist/m5/system/binaries/nvram1 27openboot_addr=1099243716608 28openboot_bin=/dist/m5/system/binaries/openboot_new.bin 29partition_desc=system.partition_desc 30partition_desc_addr=133445976064 --- 9 unchanged lines hidden (view full) --- 40work_cpus_ckpt_count=0 41work_end_ckpt_count=0 42work_end_exit_count=0 43work_item_id=-1 44system_port=system.membus.slave[0] 45 46[system.bridge] 47type=Bridge | 25num_work_ids=16 26nvram=system.nvram 27nvram_addr=133429198848 28nvram_bin=/dist/m5/system/binaries/nvram1 29openboot_addr=1099243716608 30openboot_bin=/dist/m5/system/binaries/openboot_new.bin 31partition_desc=system.partition_desc 32partition_desc_addr=133445976064 --- 9 unchanged lines hidden (view full) --- 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.bridge] 49type=Bridge |
| 50clock=2 |
|
| 48delay=100 | 51delay=100 |
| 49nack_delay=8 | |
| 50ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 51req_size=16 52resp_size=16 | 52ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 53req_size=16 54resp_size=16 |
| 53write_ack=false | |
| 54master=system.iobus.slave[0] 55slave=system.membus.master[2] 56 57[system.cpu] 58type=AtomicSimpleCPU | 55master=system.iobus.slave[0] 56slave=system.membus.master[2] 57 58[system.cpu] 59type=AtomicSimpleCPU |
| 59children=dtb interrupts itb tracer | 60children=dtb interrupts isa itb tracer 61branchPred=Null |
| 60checker=Null | 62checker=Null |
| 61clock=1 | 63clock=2 |
| 62cpu_id=0 | 64cpu_id=0 |
| 63defer_registration=false | |
| 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68fastmem=false 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts | 65do_checkpoint_insts=true 66do_quiesce=true 67do_statistics_insts=true 68dtb=system.cpu.dtb 69fastmem=false 70function_trace=false 71function_trace_start=0 72interrupts=system.cpu.interrupts |
| 73isa=system.cpu.isa |
|
| 72itb=system.cpu.itb 73max_insts_all_threads=0 74max_insts_any_thread=0 75max_loads_all_threads=0 76max_loads_any_thread=0 77numThreads=1 | 74itb=system.cpu.itb 75max_insts_all_threads=0 76max_insts_any_thread=0 77max_loads_all_threads=0 78max_loads_any_thread=0 79numThreads=1 |
| 78phase=0 | |
| 79profile=0 80progress_interval=0 81simulate_data_stalls=false 82simulate_inst_stalls=false | 80profile=0 81progress_interval=0 82simulate_data_stalls=false 83simulate_inst_stalls=false |
| 84switched_out=false |
|
| 83system=system 84tracer=system.cpu.tracer 85width=1 86workload= 87dcache_port=system.membus.slave[2] 88icache_port=system.membus.slave[1] 89 90[system.cpu.dtb] 91type=SparcTLB 92size=64 93 94[system.cpu.interrupts] 95type=SparcInterrupts 96 | 85system=system 86tracer=system.cpu.tracer 87width=1 88workload= 89dcache_port=system.membus.slave[2] 90icache_port=system.membus.slave[1] 91 92[system.cpu.dtb] 93type=SparcTLB 94size=64 95 96[system.cpu.interrupts] 97type=SparcInterrupts 98 |
| 99[system.cpu.isa] 100type=SparcISA 101 |
|
| 97[system.cpu.itb] 98type=SparcTLB 99size=64 100 101[system.cpu.tracer] 102type=ExeTracer 103 104[system.disk0] 105type=MmDisk 106children=image | 102[system.cpu.itb] 103type=SparcTLB 104size=64 105 106[system.cpu.tracer] 107type=ExeTracer 108 109[system.disk0] 110type=MmDisk 111children=image |
| 112clock=2 |
|
| 107image=system.disk0.image 108pio_addr=134217728000 | 113image=system.disk0.image 114pio_addr=134217728000 |
| 109pio_latency=2 | 115pio_latency=200 |
| 110system=system 111pio=system.iobus.master[14] 112 113[system.disk0.image] 114type=CowDiskImage 115children=child 116child=system.disk0.image.child 117image_file= 118read_only=false 119table_size=65536 120 121[system.disk0.image.child] 122type=RawDiskImage 123image_file=/dist/m5/system/disks/disk.s10hw2 124read_only=true 125 126[system.hypervisor_desc] 127type=SimpleMemory | 116system=system 117pio=system.iobus.master[14] 118 119[system.disk0.image] 120type=CowDiskImage 121children=child 122child=system.disk0.image.child 123image_file= 124read_only=false 125table_size=65536 126 127[system.disk0.image.child] 128type=RawDiskImage 129image_file=/dist/m5/system/disks/disk.s10hw2 130read_only=true 131 132[system.hypervisor_desc] 133type=SimpleMemory |
| 134bandwidth=0.000000 135clock=2 |
|
| 128conf_table_reported=false | 136conf_table_reported=false |
| 129file= | |
| 130in_addr_map=true 131latency=60 132latency_var=0 133null=false 134range=133446500352:133446508543 135zero=false 136port=system.membus.master[7] 137 138[system.intrctrl] 139type=IntrControl 140sys=system 141 142[system.iobus] 143type=NoncoherentBus 144block_size=64 145clock=2 146header_cycles=1 147use_default_range=false | 137in_addr_map=true 138latency=60 139latency_var=0 140null=false 141range=133446500352:133446508543 142zero=false 143port=system.membus.master[7] 144 145[system.intrctrl] 146type=IntrControl 147sys=system 148 149[system.iobus] 150type=NoncoherentBus 151block_size=64 152clock=2 153header_cycles=1 154use_default_range=false |
| 148width=64 | 155width=8 |
| 149master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio 150slave=system.bridge.master 151 152[system.membus] 153type=CoherentBus 154children=badaddr_responder 155block_size=64 156clock=2 157header_cycles=1 | 156master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio 157slave=system.bridge.master 158 159[system.membus] 160type=CoherentBus 161children=badaddr_responder 162block_size=64 163clock=2 164header_cycles=1 |
| 165system=system |
|
| 158use_default_range=false | 166use_default_range=false |
| 159width=64 | 167width=8 |
| 160default=system.membus.badaddr_responder.pio | 168default=system.membus.badaddr_responder.pio |
| 161master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] | 169master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port system.physmem2.port system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port |
| 162slave=system.system_port system.cpu.icache_port system.cpu.dcache_port 163 164[system.membus.badaddr_responder] 165type=IsaFake | 170slave=system.system_port system.cpu.icache_port system.cpu.dcache_port 171 172[system.membus.badaddr_responder] 173type=IsaFake |
| 174clock=2 |
|
| 166fake_mem=false 167pio_addr=0 | 175fake_mem=false 176pio_addr=0 |
| 168pio_latency=2 | 177pio_latency=200 |
| 169pio_size=8 170ret_bad_addr=true 171ret_data16=65535 172ret_data32=4294967295 173ret_data64=18446744073709551615 174ret_data8=255 175system=system 176update_data=false 177warn_access= 178pio=system.membus.default 179 180[system.nvram] 181type=SimpleMemory | 178pio_size=8 179ret_bad_addr=true 180ret_data16=65535 181ret_data32=4294967295 182ret_data64=18446744073709551615 183ret_data8=255 184system=system 185update_data=false 186warn_access= 187pio=system.membus.default 188 189[system.nvram] 190type=SimpleMemory |
| 191bandwidth=0.000000 192clock=2 |
|
| 182conf_table_reported=false | 193conf_table_reported=false |
| 183file= | |
| 184in_addr_map=true 185latency=60 186latency_var=0 187null=false 188range=133429198848:133429207039 189zero=false 190port=system.membus.master[6] 191 192[system.partition_desc] 193type=SimpleMemory | 194in_addr_map=true 195latency=60 196latency_var=0 197null=false 198range=133429198848:133429207039 199zero=false 200port=system.membus.master[6] 201 202[system.partition_desc] 203type=SimpleMemory |
| 204bandwidth=0.000000 205clock=2 |
|
| 194conf_table_reported=false | 206conf_table_reported=false |
| 195file= | |
| 196in_addr_map=true 197latency=60 198latency_var=0 199null=false 200range=133445976064:133445984255 201zero=false 202port=system.membus.master[8] 203 204[system.physmem] | 207in_addr_map=true 208latency=60 209latency_var=0 210null=false 211range=133445976064:133445984255 212zero=false 213port=system.membus.master[8] 214 215[system.physmem] |
| 205type=SimpleMemory | 216type=SimpleDRAM 217activation_limit=4 218addr_mapping=openmap 219banks_per_rank=8 220channels=1 221clock=2 |
| 206conf_table_reported=false | 222conf_table_reported=false |
| 207file= | |
| 208in_addr_map=true | 223in_addr_map=true |
| 209latency=60 210latency_var=0 | 224lines_per_rowbuffer=32 225mem_sched_policy=frfcfs |
| 211null=false | 226null=false |
| 227page_policy=open |
|
| 212range=1048576:68157439 | 228range=1048576:68157439 |
| 229ranks_per_channel=2 230read_buffer_size=32 231tBURST=10 232tCL=28 233tRCD=28 234tREFI=15600 235tRFC=600 236tRP=28 237tWTR=15 238tXAW=80 239write_buffer_size=32 240write_thresh_perc=70 |
|
| 213zero=true 214port=system.membus.master[3] 215 216[system.physmem2] | 241zero=true 242port=system.membus.master[3] 243 244[system.physmem2] |
| 217type=SimpleMemory | 245type=SimpleDRAM 246activation_limit=4 247addr_mapping=openmap 248banks_per_rank=8 249channels=1 250clock=2 |
| 218conf_table_reported=false | 251conf_table_reported=false |
| 219file= | |
| 220in_addr_map=true | 252in_addr_map=true |
| 221latency=60 222latency_var=0 | 253lines_per_rowbuffer=32 254mem_sched_policy=frfcfs |
| 223null=false | 255null=false |
| 256page_policy=open |
|
| 224range=2147483648:2415919103 | 257range=2147483648:2415919103 |
| 258ranks_per_channel=2 259read_buffer_size=32 260tBURST=10 261tCL=28 262tRCD=28 263tREFI=15600 264tRFC=600 265tRP=28 266tWTR=15 267tXAW=80 268write_buffer_size=32 269write_thresh_perc=70 |
|
| 225zero=true 226port=system.membus.master[4] 227 228[system.rom] 229type=SimpleMemory | 270zero=true 271port=system.membus.master[4] 272 273[system.rom] 274type=SimpleMemory |
| 275bandwidth=0.000000 276clock=2 |
|
| 230conf_table_reported=false | 277conf_table_reported=false |
| 231file= | |
| 232in_addr_map=true 233latency=60 234latency_var=0 235null=false 236range=1099243192320:1099251580927 237zero=false 238port=system.membus.master[5] 239 240[system.t1000] 241type=T1000 242children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 243intrctrl=system.intrctrl 244system=system 245 246[system.t1000.fake_clk] 247type=IsaFake | 278in_addr_map=true 279latency=60 280latency_var=0 281null=false 282range=1099243192320:1099251580927 283zero=false 284port=system.membus.master[5] 285 286[system.t1000] 287type=T1000 288children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 289intrctrl=system.intrctrl 290system=system 291 292[system.t1000.fake_clk] 293type=IsaFake |
| 294clock=2 |
|
| 248fake_mem=false 249pio_addr=644245094400 | 295fake_mem=false 296pio_addr=644245094400 |
| 250pio_latency=2 | 297pio_latency=200 |
| 251pio_size=4294967296 252ret_bad_addr=false 253ret_data16=65535 254ret_data32=4294967295 255ret_data64=18446744073709551615 256ret_data8=255 257system=system 258update_data=false 259warn_access= 260pio=system.iobus.master[0] 261 262[system.t1000.fake_jbi] 263type=IsaFake | 298pio_size=4294967296 299ret_bad_addr=false 300ret_data16=65535 301ret_data32=4294967295 302ret_data64=18446744073709551615 303ret_data8=255 304system=system 305update_data=false 306warn_access= 307pio=system.iobus.master[0] 308 309[system.t1000.fake_jbi] 310type=IsaFake |
| 311clock=2 |
|
| 264fake_mem=false 265pio_addr=549755813888 | 312fake_mem=false 313pio_addr=549755813888 |
| 266pio_latency=2 | 314pio_latency=200 |
| 267pio_size=4294967296 268ret_bad_addr=false 269ret_data16=65535 270ret_data32=4294967295 271ret_data64=18446744073709551615 272ret_data8=255 273system=system 274update_data=false 275warn_access= 276pio=system.iobus.master[11] 277 278[system.t1000.fake_l2_1] 279type=IsaFake | 315pio_size=4294967296 316ret_bad_addr=false 317ret_data16=65535 318ret_data32=4294967295 319ret_data64=18446744073709551615 320ret_data8=255 321system=system 322update_data=false 323warn_access= 324pio=system.iobus.master[11] 325 326[system.t1000.fake_l2_1] 327type=IsaFake |
| 328clock=2 |
|
| 280fake_mem=false 281pio_addr=725849473024 | 329fake_mem=false 330pio_addr=725849473024 |
| 282pio_latency=2 | 331pio_latency=200 |
| 283pio_size=8 284ret_bad_addr=false 285ret_data16=65535 286ret_data32=4294967295 287ret_data64=1 288ret_data8=255 289system=system 290update_data=true 291warn_access= 292pio=system.iobus.master[2] 293 294[system.t1000.fake_l2_2] 295type=IsaFake | 332pio_size=8 333ret_bad_addr=false 334ret_data16=65535 335ret_data32=4294967295 336ret_data64=1 337ret_data8=255 338system=system 339update_data=true 340warn_access= 341pio=system.iobus.master[2] 342 343[system.t1000.fake_l2_2] 344type=IsaFake |
| 345clock=2 |
|
| 296fake_mem=false 297pio_addr=725849473088 | 346fake_mem=false 347pio_addr=725849473088 |
| 298pio_latency=2 | 348pio_latency=200 |
| 299pio_size=8 300ret_bad_addr=false 301ret_data16=65535 302ret_data32=4294967295 303ret_data64=1 304ret_data8=255 305system=system 306update_data=true 307warn_access= 308pio=system.iobus.master[3] 309 310[system.t1000.fake_l2_3] 311type=IsaFake | 349pio_size=8 350ret_bad_addr=false 351ret_data16=65535 352ret_data32=4294967295 353ret_data64=1 354ret_data8=255 355system=system 356update_data=true 357warn_access= 358pio=system.iobus.master[3] 359 360[system.t1000.fake_l2_3] 361type=IsaFake |
| 362clock=2 |
|
| 312fake_mem=false 313pio_addr=725849473152 | 363fake_mem=false 364pio_addr=725849473152 |
| 314pio_latency=2 | 365pio_latency=200 |
| 315pio_size=8 316ret_bad_addr=false 317ret_data16=65535 318ret_data32=4294967295 319ret_data64=1 320ret_data8=255 321system=system 322update_data=true 323warn_access= 324pio=system.iobus.master[4] 325 326[system.t1000.fake_l2_4] 327type=IsaFake | 366pio_size=8 367ret_bad_addr=false 368ret_data16=65535 369ret_data32=4294967295 370ret_data64=1 371ret_data8=255 372system=system 373update_data=true 374warn_access= 375pio=system.iobus.master[4] 376 377[system.t1000.fake_l2_4] 378type=IsaFake |
| 379clock=2 |
|
| 328fake_mem=false 329pio_addr=725849473216 | 380fake_mem=false 381pio_addr=725849473216 |
| 330pio_latency=2 | 382pio_latency=200 |
| 331pio_size=8 332ret_bad_addr=false 333ret_data16=65535 334ret_data32=4294967295 335ret_data64=1 336ret_data8=255 337system=system 338update_data=true 339warn_access= 340pio=system.iobus.master[5] 341 342[system.t1000.fake_l2esr_1] 343type=IsaFake | 383pio_size=8 384ret_bad_addr=false 385ret_data16=65535 386ret_data32=4294967295 387ret_data64=1 388ret_data8=255 389system=system 390update_data=true 391warn_access= 392pio=system.iobus.master[5] 393 394[system.t1000.fake_l2esr_1] 395type=IsaFake |
| 396clock=2 |
|
| 344fake_mem=false 345pio_addr=734439407616 | 397fake_mem=false 398pio_addr=734439407616 |
| 346pio_latency=2 | 399pio_latency=200 |
| 347pio_size=8 348ret_bad_addr=false 349ret_data16=65535 350ret_data32=4294967295 351ret_data64=0 352ret_data8=255 353system=system 354update_data=true 355warn_access= 356pio=system.iobus.master[6] 357 358[system.t1000.fake_l2esr_2] 359type=IsaFake | 400pio_size=8 401ret_bad_addr=false 402ret_data16=65535 403ret_data32=4294967295 404ret_data64=0 405ret_data8=255 406system=system 407update_data=true 408warn_access= 409pio=system.iobus.master[6] 410 411[system.t1000.fake_l2esr_2] 412type=IsaFake |
| 413clock=2 |
|
| 360fake_mem=false 361pio_addr=734439407680 | 414fake_mem=false 415pio_addr=734439407680 |
| 362pio_latency=2 | 416pio_latency=200 |
| 363pio_size=8 364ret_bad_addr=false 365ret_data16=65535 366ret_data32=4294967295 367ret_data64=0 368ret_data8=255 369system=system 370update_data=true 371warn_access= 372pio=system.iobus.master[7] 373 374[system.t1000.fake_l2esr_3] 375type=IsaFake | 417pio_size=8 418ret_bad_addr=false 419ret_data16=65535 420ret_data32=4294967295 421ret_data64=0 422ret_data8=255 423system=system 424update_data=true 425warn_access= 426pio=system.iobus.master[7] 427 428[system.t1000.fake_l2esr_3] 429type=IsaFake |
| 430clock=2 |
|
| 376fake_mem=false 377pio_addr=734439407744 | 431fake_mem=false 432pio_addr=734439407744 |
| 378pio_latency=2 | 433pio_latency=200 |
| 379pio_size=8 380ret_bad_addr=false 381ret_data16=65535 382ret_data32=4294967295 383ret_data64=0 384ret_data8=255 385system=system 386update_data=true 387warn_access= 388pio=system.iobus.master[8] 389 390[system.t1000.fake_l2esr_4] 391type=IsaFake | 434pio_size=8 435ret_bad_addr=false 436ret_data16=65535 437ret_data32=4294967295 438ret_data64=0 439ret_data8=255 440system=system 441update_data=true 442warn_access= 443pio=system.iobus.master[8] 444 445[system.t1000.fake_l2esr_4] 446type=IsaFake |
| 447clock=2 |
|
| 392fake_mem=false 393pio_addr=734439407808 | 448fake_mem=false 449pio_addr=734439407808 |
| 394pio_latency=2 | 450pio_latency=200 |
| 395pio_size=8 396ret_bad_addr=false 397ret_data16=65535 398ret_data32=4294967295 399ret_data64=0 400ret_data8=255 401system=system 402update_data=true 403warn_access= 404pio=system.iobus.master[9] 405 406[system.t1000.fake_membnks] 407type=IsaFake | 451pio_size=8 452ret_bad_addr=false 453ret_data16=65535 454ret_data32=4294967295 455ret_data64=0 456ret_data8=255 457system=system 458update_data=true 459warn_access= 460pio=system.iobus.master[9] 461 462[system.t1000.fake_membnks] 463type=IsaFake |
| 464clock=2 |
|
| 408fake_mem=false 409pio_addr=648540061696 | 465fake_mem=false 466pio_addr=648540061696 |
| 410pio_latency=2 | 467pio_latency=200 |
| 411pio_size=16384 412ret_bad_addr=false 413ret_data16=65535 414ret_data32=4294967295 415ret_data64=0 416ret_data8=255 417system=system 418update_data=false 419warn_access= 420pio=system.iobus.master[1] 421 422[system.t1000.fake_ssi] 423type=IsaFake | 468pio_size=16384 469ret_bad_addr=false 470ret_data16=65535 471ret_data32=4294967295 472ret_data64=0 473ret_data8=255 474system=system 475update_data=false 476warn_access= 477pio=system.iobus.master[1] 478 479[system.t1000.fake_ssi] 480type=IsaFake |
| 481clock=2 |
|
| 424fake_mem=false 425pio_addr=1095216660480 | 482fake_mem=false 483pio_addr=1095216660480 |
| 426pio_latency=2 | 484pio_latency=200 |
| 427pio_size=268435456 428ret_bad_addr=false 429ret_data16=65535 430ret_data32=4294967295 431ret_data64=18446744073709551615 432ret_data8=255 433system=system 434update_data=false --- 4 unchanged lines hidden (view full) --- 439type=Terminal 440intr_control=system.intrctrl 441number=0 442output=true 443port=3456 444 445[system.t1000.htod] 446type=DumbTOD | 485pio_size=268435456 486ret_bad_addr=false 487ret_data16=65535 488ret_data32=4294967295 489ret_data64=18446744073709551615 490ret_data8=255 491system=system 492update_data=false --- 4 unchanged lines hidden (view full) --- 497type=Terminal 498intr_control=system.intrctrl 499number=0 500output=true 501port=3456 502 503[system.t1000.htod] 504type=DumbTOD |
| 505clock=2 |
|
| 447pio_addr=1099255906296 | 506pio_addr=1099255906296 |
| 448pio_latency=2 | 507pio_latency=200 |
| 449system=system 450time=Thu Jan 1 00:00:00 2009 451pio=system.membus.master[1] 452 453[system.t1000.hvuart] 454type=Uart8250 | 508system=system 509time=Thu Jan 1 00:00:00 2009 510pio=system.membus.master[1] 511 512[system.t1000.hvuart] 513type=Uart8250 |
| 514clock=2 |
|
| 455pio_addr=1099255955456 | 515pio_addr=1099255955456 |
| 456pio_latency=2 | 516pio_latency=200 |
| 457platform=system.t1000 458system=system 459terminal=system.t1000.hterm 460pio=system.iobus.master[13] 461 462[system.t1000.iob] 463type=Iob | 517platform=system.t1000 518system=system 519terminal=system.t1000.hterm 520pio=system.iobus.master[13] 521 522[system.t1000.iob] 523type=Iob |
| 524clock=2 |
|
| 464pio_latency=2 465platform=system.t1000 466system=system 467pio=system.membus.master[0] 468 469[system.t1000.pterm] 470type=Terminal 471intr_control=system.intrctrl 472number=0 473output=true 474port=3456 475 476[system.t1000.puart0] 477type=Uart8250 | 525pio_latency=2 526platform=system.t1000 527system=system 528pio=system.membus.master[0] 529 530[system.t1000.pterm] 531type=Terminal 532intr_control=system.intrctrl 533number=0 534output=true 535port=3456 536 537[system.t1000.puart0] 538type=Uart8250 |
| 539clock=2 |
|
| 478pio_addr=133412421632 | 540pio_addr=133412421632 |
| 479pio_latency=2 | 541pio_latency=200 |
| 480platform=system.t1000 481system=system 482terminal=system.t1000.pterm 483pio=system.iobus.master[12] 484 | 542platform=system.t1000 543system=system 544terminal=system.t1000.pterm 545pio=system.iobus.master[12] 546 |