[root]
type=Root
children=system
eventq_index=0
full_system=true
sim_quantum=0
time_sync_enable=false
time_sync_period=200000000
time_sync_spin_threshold=200000

[system]
type=SparcSystem
children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
hypervisor_addr=1099243257856
hypervisor_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin
hypervisor_desc=system.hypervisor_desc
hypervisor_desc_addr=133446500352
hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=1048576:68157439:0:0:0:0 2147483648:2415919103:0:0:0:0
memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
nvram=system.nvram
nvram_addr=133429198848
nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1
openboot_addr=1099243716608
openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
partition_desc=system.partition_desc
partition_desc_addr=133445976064
partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin
power_model=Null
readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr=1099243192320
reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin
rom=system.rom
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]

[system.bridge]
type=Bridge
clk_domain=system.clk_domain
default_p_state=UNDEFINED
delay=100
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
power_model=Null
ranges=133412421632:133412421639:0:0:0:0 134217728000:554050781183:0:0:0:0 644245094400:652835028991:0:0:0:0 725849473024:1095485095935:0:0:0:0 1099255955456:1099255955463:0:0:0:0
req_size=16
resp_size=16
master=system.iobus.slave[0]
slave=system.membus.master[2]

[system.clk_domain]
type=SrcClockDomain
clock=2
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain

[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]

[system.cpu.dtb]
type=SparcTLB
eventq_index=0
size=64

[system.cpu.interrupts]
type=SparcInterrupts
eventq_index=0

[system.cpu.isa]
type=SparcISA
eventq_index=0

[system.cpu.itb]
type=SparcTLB
eventq_index=0
size=64

[system.cpu.tracer]
type=ExeTracer
eventq_index=0

[system.cpu_clk_domain]
type=SrcClockDomain
clock=2
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain

[system.disk0]
type=MmDisk
children=image
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
image=system.disk0.image
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=134217728000
pio_latency=200
power_model=Null
system=system
pio=system.iobus.master[14]

[system.disk0.image]
type=CowDiskImage
children=child
child=system.disk0.image.child
eventq_index=0
image_file=
read_only=false
table_size=65536

[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2
read_only=true

[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=200000

[system.hypervisor_desc]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=60
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
power_model=Null
range=133446500352:133446508543:0:0:0:0
port=system.membus.master[5]

[system.intrctrl]
type=IntrControl
eventq_index=0
sys=system

[system.iobus]
type=NoncoherentXBar
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=1
frontend_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
power_model=Null
response_latency=2
use_default_range=false
width=16
master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
slave=system.bridge.master

[system.membus]
type=CoherentXBar
children=badaddr_responder snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
default=system.membus.badaddr_responder.pio
master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port

[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=0
pio_latency=200
pio_size=8
power_model=Null
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.membus.default

[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system

[system.nvram]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=60
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
power_model=Null
range=133429198848:133429207039:0:0:0:0
port=system.membus.master[4]

[system.partition_desc]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=60
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
power_model=Null
range=133445976064:133445984255:0:0:0:0
port=system.membus.master[6]

[system.physmem0]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=60
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
power_model=Null
range=1048576:68157439:0:0:0:0
port=system.membus.master[7]

[system.physmem1]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=60
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
power_model=Null
range=2147483648:2415919103:0:0:0:0
port=system.membus.master[8]

[system.rom]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=60
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
power_model=Null
range=1099243192320:1099251580927:0:0:0:0
port=system.membus.master[3]

[system.t1000]
type=T1000
children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
eventq_index=0
intrctrl=system.intrctrl
system=system

[system.t1000.fake_clk]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=644245094400
pio_latency=200
pio_size=4294967296
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[0]

[system.t1000.fake_jbi]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=549755813888
pio_latency=200
pio_size=4294967296
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[11]

[system.t1000.fake_l2_1]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=725849473024
pio_latency=200
pio_size=8
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=1
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[2]

[system.t1000.fake_l2_2]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=725849473088
pio_latency=200
pio_size=8
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=1
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[3]

[system.t1000.fake_l2_3]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=725849473152
pio_latency=200
pio_size=8
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=1
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[4]

[system.t1000.fake_l2_4]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=725849473216
pio_latency=200
pio_size=8
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=1
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[5]

[system.t1000.fake_l2esr_1]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=734439407616
pio_latency=200
pio_size=8
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=0
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[6]

[system.t1000.fake_l2esr_2]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=734439407680
pio_latency=200
pio_size=8
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=0
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[7]

[system.t1000.fake_l2esr_3]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=734439407744
pio_latency=200
pio_size=8
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=0
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[8]

[system.t1000.fake_l2esr_4]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=734439407808
pio_latency=200
pio_size=8
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=0
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[9]

[system.t1000.fake_membnks]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=648540061696
pio_latency=200
pio_size=16384
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=0
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[1]

[system.t1000.fake_ssi]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=1095216660480
pio_latency=200
pio_size=268435456
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[10]

[system.t1000.hterm]
type=Terminal
eventq_index=0
intr_control=system.intrctrl
number=0
output=true
port=3456

[system.t1000.htod]
type=DumbTOD
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=1099255906296
pio_latency=200
power_model=Null
system=system
time=Thu Jan  1 00:00:00 2009
pio=system.membus.master[1]

[system.t1000.hvuart]
type=Uart8250
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=1099255955456
pio_latency=200
platform=system.t1000
power_model=Null
system=system
terminal=system.t1000.hterm
pio=system.iobus.master[13]

[system.t1000.iob]
type=Iob
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_latency=2
platform=system.t1000
power_model=Null
system=system
pio=system.membus.master[0]

[system.t1000.pterm]
type=Terminal
eventq_index=0
intr_control=system.intrctrl
number=0
output=true
port=3456

[system.t1000.puart0]
type=Uart8250
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=2000000000
p_state_clk_gate_min=2
pio_addr=133412421632
pio_latency=200
platform=system.t1000
power_model=Null
system=system
terminal=system.t1000.pterm
pio=system.iobus.master[12]

[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000