| config.ini (8835:7c68f84d7c4e) | config.ini (8983:8800b05e1cb3) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=200000000 7time_sync_spin_threshold=200000 8 --- 5 unchanged lines hidden (view full) --- 14hypervisor_bin=/dist/m5/system/binaries/q_new.bin 15hypervisor_desc=system.hypervisor_desc 16hypervisor_desc_addr=133446500352 17hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=atomic | 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=200000000 7time_sync_spin_threshold=200000 8 --- 5 unchanged lines hidden (view full) --- 14hypervisor_bin=/dist/m5/system/binaries/q_new.bin 15hypervisor_desc=system.hypervisor_desc 16hypervisor_desc_addr=133446500352 17hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=atomic |
| 22memories=system.rom system.hypervisor_desc system.physmem2 system.nvram system.physmem system.partition_desc | 22memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem2 system.rom system.physmem |
| 23num_work_ids=16 24nvram=system.nvram 25nvram_addr=133429198848 26nvram_bin=/dist/m5/system/binaries/nvram1 27openboot_addr=1099243716608 28openboot_bin=/dist/m5/system/binaries/openboot_new.bin 29partition_desc=system.partition_desc 30partition_desc_addr=133445976064 31partition_desc_bin=/dist/m5/system/binaries/1up-md.bin | 23num_work_ids=16 24nvram=system.nvram 25nvram_addr=133429198848 26nvram_bin=/dist/m5/system/binaries/nvram1 27openboot_addr=1099243716608 28openboot_bin=/dist/m5/system/binaries/openboot_new.bin 29partition_desc=system.partition_desc 30partition_desc_addr=133445976064 31partition_desc_bin=/dist/m5/system/binaries/1up-md.bin |
| 32physmem=system.physmem | |
| 33readfile=tests/halt.sh 34reset_addr=1099243192320 35reset_bin=/dist/m5/system/binaries/reset_new.bin 36rom=system.rom 37symbolfile= 38work_begin_ckpt_count=0 39work_begin_cpu_id_exit=-1 40work_begin_exit_count=0 41work_cpus_ckpt_count=0 42work_end_ckpt_count=0 43work_end_exit_count=0 44work_item_id=-1 | 32readfile=tests/halt.sh 33reset_addr=1099243192320 34reset_bin=/dist/m5/system/binaries/reset_new.bin 35rom=system.rom 36symbolfile= 37work_begin_ckpt_count=0 38work_begin_cpu_id_exit=-1 39work_begin_exit_count=0 40work_cpus_ckpt_count=0 41work_end_ckpt_count=0 42work_end_exit_count=0 43work_item_id=-1 |
| 45system_port=system.membus.port[9] | 44system_port=system.membus.slave[0] |
| 46 47[system.bridge] 48type=Bridge 49delay=100 50nack_delay=8 51ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 52req_size=16 53resp_size=16 54write_ack=false | 45 46[system.bridge] 47type=Bridge 48delay=100 49nack_delay=8 50ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 51req_size=16 52resp_size=16 53write_ack=false |
| 55master=system.iobus.port[14] 56slave=system.membus.port[2] | 54master=system.iobus.slave[0] 55slave=system.membus.master[2] |
| 57 58[system.cpu] 59type=AtomicSimpleCPU 60children=dtb interrupts itb tracer 61checker=Null 62clock=1 63cpu_id=0 64defer_registration=false 65do_checkpoint_insts=true 66do_quiesce=true 67do_statistics_insts=true 68dtb=system.cpu.dtb | 56 57[system.cpu] 58type=AtomicSimpleCPU 59children=dtb interrupts itb tracer 60checker=Null 61clock=1 62cpu_id=0 63defer_registration=false 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb |
| 68fastmem=false |
|
| 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72itb=system.cpu.itb 73max_insts_all_threads=0 74max_insts_any_thread=0 75max_loads_all_threads=0 76max_loads_any_thread=0 77numThreads=1 78phase=0 79profile=0 80progress_interval=0 81simulate_data_stalls=false 82simulate_inst_stalls=false 83system=system 84tracer=system.cpu.tracer 85width=1 86workload= | 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72itb=system.cpu.itb 73max_insts_all_threads=0 74max_insts_any_thread=0 75max_loads_all_threads=0 76max_loads_any_thread=0 77numThreads=1 78phase=0 79profile=0 80progress_interval=0 81simulate_data_stalls=false 82simulate_inst_stalls=false 83system=system 84tracer=system.cpu.tracer 85width=1 86workload= |
| 87dcache_port=system.membus.port[11] 88icache_port=system.membus.port[10] | 87dcache_port=system.membus.slave[2] 88icache_port=system.membus.slave[1] |
| 89 90[system.cpu.dtb] 91type=SparcTLB 92size=64 93 94[system.cpu.interrupts] 95type=SparcInterrupts 96 --- 6 unchanged lines hidden (view full) --- 103 104[system.disk0] 105type=MmDisk 106children=image 107image=system.disk0.image 108pio_addr=134217728000 109pio_latency=2 110system=system | 89 90[system.cpu.dtb] 91type=SparcTLB 92size=64 93 94[system.cpu.interrupts] 95type=SparcInterrupts 96 --- 6 unchanged lines hidden (view full) --- 103 104[system.disk0] 105type=MmDisk 106children=image 107image=system.disk0.image 108pio_addr=134217728000 109pio_latency=2 110system=system |
| 111pio=system.iobus.port[15] | 111pio=system.iobus.master[14] |
| 112 113[system.disk0.image] 114type=CowDiskImage 115children=child 116child=system.disk0.image.child 117image_file= 118read_only=false 119table_size=65536 120 121[system.disk0.image.child] 122type=RawDiskImage 123image_file=/dist/m5/system/disks/disk.s10hw2 124read_only=true 125 126[system.hypervisor_desc] | 112 113[system.disk0.image] 114type=CowDiskImage 115children=child 116child=system.disk0.image.child 117image_file= 118read_only=false 119table_size=65536 120 121[system.disk0.image.child] 122type=RawDiskImage 123image_file=/dist/m5/system/disks/disk.s10hw2 124read_only=true 125 126[system.hypervisor_desc] |
| 127type=PhysicalMemory | 127type=SimpleMemory 128conf_table_reported=false |
| 128file= | 129file= |
| 130in_addr_map=true |
|
| 129latency=60 130latency_var=0 131null=false 132range=133446500352:133446508543 133zero=false | 131latency=60 132latency_var=0 133null=false 134range=133446500352:133446508543 135zero=false |
| 134port=system.membus.port[7] | 136port=system.membus.master[7] |
| 135 136[system.intrctrl] 137type=IntrControl 138sys=system 139 140[system.iobus] 141type=Bus 142block_size=64 143bus_id=0 144clock=2 145header_cycles=1 146use_default_range=false 147width=64 | 137 138[system.intrctrl] 139type=IntrControl 140sys=system 141 142[system.iobus] 143type=Bus 144block_size=64 145bus_id=0 146clock=2 147header_cycles=1 148use_default_range=false 149width=64 |
| 148port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.master system.disk0.pio | 150master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio 151slave=system.bridge.master |
| 149 150[system.membus] 151type=Bus 152children=badaddr_responder 153block_size=64 154bus_id=1 155clock=2 156header_cycles=1 157use_default_range=false 158width=64 159default=system.membus.badaddr_responder.pio | 152 153[system.membus] 154type=Bus 155children=badaddr_responder 156block_size=64 157bus_id=1 158clock=2 159header_cycles=1 160use_default_range=false 161width=64 162default=system.membus.badaddr_responder.pio |
| 160port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.system_port system.cpu.icache_port system.cpu.dcache_port | 163master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] 164slave=system.system_port system.cpu.icache_port system.cpu.dcache_port |
| 161 162[system.membus.badaddr_responder] 163type=IsaFake 164fake_mem=false 165pio_addr=0 166pio_latency=2 167pio_size=8 168ret_bad_addr=true 169ret_data16=65535 170ret_data32=4294967295 171ret_data64=18446744073709551615 172ret_data8=255 173system=system 174update_data=false 175warn_access= 176pio=system.membus.default 177 178[system.nvram] | 165 166[system.membus.badaddr_responder] 167type=IsaFake 168fake_mem=false 169pio_addr=0 170pio_latency=2 171pio_size=8 172ret_bad_addr=true 173ret_data16=65535 174ret_data32=4294967295 175ret_data64=18446744073709551615 176ret_data8=255 177system=system 178update_data=false 179warn_access= 180pio=system.membus.default 181 182[system.nvram] |
| 179type=PhysicalMemory | 183type=SimpleMemory 184conf_table_reported=false |
| 180file= | 185file= |
| 186in_addr_map=true |
|
| 181latency=60 182latency_var=0 183null=false 184range=133429198848:133429207039 185zero=false | 187latency=60 188latency_var=0 189null=false 190range=133429198848:133429207039 191zero=false |
| 186port=system.membus.port[6] | 192port=system.membus.master[6] |
| 187 188[system.partition_desc] | 193 194[system.partition_desc] |
| 189type=PhysicalMemory | 195type=SimpleMemory 196conf_table_reported=false |
| 190file= | 197file= |
| 198in_addr_map=true |
|
| 191latency=60 192latency_var=0 193null=false 194range=133445976064:133445984255 195zero=false | 199latency=60 200latency_var=0 201null=false 202range=133445976064:133445984255 203zero=false |
| 196port=system.membus.port[8] | 204port=system.membus.master[8] |
| 197 198[system.physmem] | 205 206[system.physmem] |
| 199type=PhysicalMemory | 207type=SimpleMemory 208conf_table_reported=false |
| 200file= | 209file= |
| 210in_addr_map=true |
|
| 201latency=60 202latency_var=0 203null=false 204range=1048576:68157439 205zero=true | 211latency=60 212latency_var=0 213null=false 214range=1048576:68157439 215zero=true |
| 206port=system.membus.port[3] | 216port=system.membus.master[3] |
| 207 208[system.physmem2] | 217 218[system.physmem2] |
| 209type=PhysicalMemory | 219type=SimpleMemory 220conf_table_reported=false |
| 210file= | 221file= |
| 222in_addr_map=true |
|
| 211latency=60 212latency_var=0 213null=false 214range=2147483648:2415919103 215zero=true | 223latency=60 224latency_var=0 225null=false 226range=2147483648:2415919103 227zero=true |
| 216port=system.membus.port[4] | 228port=system.membus.master[4] |
| 217 218[system.rom] | 229 230[system.rom] |
| 219type=PhysicalMemory | 231type=SimpleMemory 232conf_table_reported=false |
| 220file= | 233file= |
| 234in_addr_map=true |
|
| 221latency=60 222latency_var=0 223null=false 224range=1099243192320:1099251580927 225zero=false | 235latency=60 236latency_var=0 237null=false 238range=1099243192320:1099251580927 239zero=false |
| 226port=system.membus.port[5] | 240port=system.membus.master[5] |
| 227 228[system.t1000] 229type=T1000 230children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 231intrctrl=system.intrctrl 232system=system 233 234[system.t1000.fake_clk] --- 5 unchanged lines hidden (view full) --- 240ret_bad_addr=false 241ret_data16=65535 242ret_data32=4294967295 243ret_data64=18446744073709551615 244ret_data8=255 245system=system 246update_data=false 247warn_access= | 241 242[system.t1000] 243type=T1000 244children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 245intrctrl=system.intrctrl 246system=system 247 248[system.t1000.fake_clk] --- 5 unchanged lines hidden (view full) --- 254ret_bad_addr=false 255ret_data16=65535 256ret_data32=4294967295 257ret_data64=18446744073709551615 258ret_data8=255 259system=system 260update_data=false 261warn_access= |
| 248pio=system.iobus.port[0] | 262pio=system.iobus.master[0] |
| 249 250[system.t1000.fake_jbi] 251type=IsaFake 252fake_mem=false 253pio_addr=549755813888 254pio_latency=2 255pio_size=4294967296 256ret_bad_addr=false 257ret_data16=65535 258ret_data32=4294967295 259ret_data64=18446744073709551615 260ret_data8=255 261system=system 262update_data=false 263warn_access= | 263 264[system.t1000.fake_jbi] 265type=IsaFake 266fake_mem=false 267pio_addr=549755813888 268pio_latency=2 269pio_size=4294967296 270ret_bad_addr=false 271ret_data16=65535 272ret_data32=4294967295 273ret_data64=18446744073709551615 274ret_data8=255 275system=system 276update_data=false 277warn_access= |
| 264pio=system.iobus.port[11] | 278pio=system.iobus.master[11] |
| 265 266[system.t1000.fake_l2_1] 267type=IsaFake 268fake_mem=false 269pio_addr=725849473024 270pio_latency=2 271pio_size=8 272ret_bad_addr=false 273ret_data16=65535 274ret_data32=4294967295 275ret_data64=1 276ret_data8=255 277system=system 278update_data=true 279warn_access= | 279 280[system.t1000.fake_l2_1] 281type=IsaFake 282fake_mem=false 283pio_addr=725849473024 284pio_latency=2 285pio_size=8 286ret_bad_addr=false 287ret_data16=65535 288ret_data32=4294967295 289ret_data64=1 290ret_data8=255 291system=system 292update_data=true 293warn_access= |
| 280pio=system.iobus.port[2] | 294pio=system.iobus.master[2] |
| 281 282[system.t1000.fake_l2_2] 283type=IsaFake 284fake_mem=false 285pio_addr=725849473088 286pio_latency=2 287pio_size=8 288ret_bad_addr=false 289ret_data16=65535 290ret_data32=4294967295 291ret_data64=1 292ret_data8=255 293system=system 294update_data=true 295warn_access= | 295 296[system.t1000.fake_l2_2] 297type=IsaFake 298fake_mem=false 299pio_addr=725849473088 300pio_latency=2 301pio_size=8 302ret_bad_addr=false 303ret_data16=65535 304ret_data32=4294967295 305ret_data64=1 306ret_data8=255 307system=system 308update_data=true 309warn_access= |
| 296pio=system.iobus.port[3] | 310pio=system.iobus.master[3] |
| 297 298[system.t1000.fake_l2_3] 299type=IsaFake 300fake_mem=false 301pio_addr=725849473152 302pio_latency=2 303pio_size=8 304ret_bad_addr=false 305ret_data16=65535 306ret_data32=4294967295 307ret_data64=1 308ret_data8=255 309system=system 310update_data=true 311warn_access= | 311 312[system.t1000.fake_l2_3] 313type=IsaFake 314fake_mem=false 315pio_addr=725849473152 316pio_latency=2 317pio_size=8 318ret_bad_addr=false 319ret_data16=65535 320ret_data32=4294967295 321ret_data64=1 322ret_data8=255 323system=system 324update_data=true 325warn_access= |
| 312pio=system.iobus.port[4] | 326pio=system.iobus.master[4] |
| 313 314[system.t1000.fake_l2_4] 315type=IsaFake 316fake_mem=false 317pio_addr=725849473216 318pio_latency=2 319pio_size=8 320ret_bad_addr=false 321ret_data16=65535 322ret_data32=4294967295 323ret_data64=1 324ret_data8=255 325system=system 326update_data=true 327warn_access= | 327 328[system.t1000.fake_l2_4] 329type=IsaFake 330fake_mem=false 331pio_addr=725849473216 332pio_latency=2 333pio_size=8 334ret_bad_addr=false 335ret_data16=65535 336ret_data32=4294967295 337ret_data64=1 338ret_data8=255 339system=system 340update_data=true 341warn_access= |
| 328pio=system.iobus.port[5] | 342pio=system.iobus.master[5] |
| 329 330[system.t1000.fake_l2esr_1] 331type=IsaFake 332fake_mem=false 333pio_addr=734439407616 334pio_latency=2 335pio_size=8 336ret_bad_addr=false 337ret_data16=65535 338ret_data32=4294967295 339ret_data64=0 340ret_data8=255 341system=system 342update_data=true 343warn_access= | 343 344[system.t1000.fake_l2esr_1] 345type=IsaFake 346fake_mem=false 347pio_addr=734439407616 348pio_latency=2 349pio_size=8 350ret_bad_addr=false 351ret_data16=65535 352ret_data32=4294967295 353ret_data64=0 354ret_data8=255 355system=system 356update_data=true 357warn_access= |
| 344pio=system.iobus.port[6] | 358pio=system.iobus.master[6] |
| 345 346[system.t1000.fake_l2esr_2] 347type=IsaFake 348fake_mem=false 349pio_addr=734439407680 350pio_latency=2 351pio_size=8 352ret_bad_addr=false 353ret_data16=65535 354ret_data32=4294967295 355ret_data64=0 356ret_data8=255 357system=system 358update_data=true 359warn_access= | 359 360[system.t1000.fake_l2esr_2] 361type=IsaFake 362fake_mem=false 363pio_addr=734439407680 364pio_latency=2 365pio_size=8 366ret_bad_addr=false 367ret_data16=65535 368ret_data32=4294967295 369ret_data64=0 370ret_data8=255 371system=system 372update_data=true 373warn_access= |
| 360pio=system.iobus.port[7] | 374pio=system.iobus.master[7] |
| 361 362[system.t1000.fake_l2esr_3] 363type=IsaFake 364fake_mem=false 365pio_addr=734439407744 366pio_latency=2 367pio_size=8 368ret_bad_addr=false 369ret_data16=65535 370ret_data32=4294967295 371ret_data64=0 372ret_data8=255 373system=system 374update_data=true 375warn_access= | 375 376[system.t1000.fake_l2esr_3] 377type=IsaFake 378fake_mem=false 379pio_addr=734439407744 380pio_latency=2 381pio_size=8 382ret_bad_addr=false 383ret_data16=65535 384ret_data32=4294967295 385ret_data64=0 386ret_data8=255 387system=system 388update_data=true 389warn_access= |
| 376pio=system.iobus.port[8] | 390pio=system.iobus.master[8] |
| 377 378[system.t1000.fake_l2esr_4] 379type=IsaFake 380fake_mem=false 381pio_addr=734439407808 382pio_latency=2 383pio_size=8 384ret_bad_addr=false 385ret_data16=65535 386ret_data32=4294967295 387ret_data64=0 388ret_data8=255 389system=system 390update_data=true 391warn_access= | 391 392[system.t1000.fake_l2esr_4] 393type=IsaFake 394fake_mem=false 395pio_addr=734439407808 396pio_latency=2 397pio_size=8 398ret_bad_addr=false 399ret_data16=65535 400ret_data32=4294967295 401ret_data64=0 402ret_data8=255 403system=system 404update_data=true 405warn_access= |
| 392pio=system.iobus.port[9] | 406pio=system.iobus.master[9] |
| 393 394[system.t1000.fake_membnks] 395type=IsaFake 396fake_mem=false 397pio_addr=648540061696 398pio_latency=2 399pio_size=16384 400ret_bad_addr=false 401ret_data16=65535 402ret_data32=4294967295 403ret_data64=0 404ret_data8=255 405system=system 406update_data=false 407warn_access= | 407 408[system.t1000.fake_membnks] 409type=IsaFake 410fake_mem=false 411pio_addr=648540061696 412pio_latency=2 413pio_size=16384 414ret_bad_addr=false 415ret_data16=65535 416ret_data32=4294967295 417ret_data64=0 418ret_data8=255 419system=system 420update_data=false 421warn_access= |
| 408pio=system.iobus.port[1] | 422pio=system.iobus.master[1] |
| 409 410[system.t1000.fake_ssi] 411type=IsaFake 412fake_mem=false 413pio_addr=1095216660480 414pio_latency=2 415pio_size=268435456 416ret_bad_addr=false 417ret_data16=65535 418ret_data32=4294967295 419ret_data64=18446744073709551615 420ret_data8=255 421system=system 422update_data=false 423warn_access= | 423 424[system.t1000.fake_ssi] 425type=IsaFake 426fake_mem=false 427pio_addr=1095216660480 428pio_latency=2 429pio_size=268435456 430ret_bad_addr=false 431ret_data16=65535 432ret_data32=4294967295 433ret_data64=18446744073709551615 434ret_data8=255 435system=system 436update_data=false 437warn_access= |
| 424pio=system.iobus.port[10] | 438pio=system.iobus.master[10] |
| 425 426[system.t1000.hterm] 427type=Terminal 428intr_control=system.intrctrl 429number=0 430output=true 431port=3456 432 433[system.t1000.htod] 434type=DumbTOD 435pio_addr=1099255906296 436pio_latency=2 437system=system 438time=Thu Jan 1 00:00:00 2009 | 439 440[system.t1000.hterm] 441type=Terminal 442intr_control=system.intrctrl 443number=0 444output=true 445port=3456 446 447[system.t1000.htod] 448type=DumbTOD 449pio_addr=1099255906296 450pio_latency=2 451system=system 452time=Thu Jan 1 00:00:00 2009 |
| 439pio=system.membus.port[1] | 453pio=system.membus.master[1] |
| 440 441[system.t1000.hvuart] 442type=Uart8250 443pio_addr=1099255955456 444pio_latency=2 445platform=system.t1000 446system=system 447terminal=system.t1000.hterm | 454 455[system.t1000.hvuart] 456type=Uart8250 457pio_addr=1099255955456 458pio_latency=2 459platform=system.t1000 460system=system 461terminal=system.t1000.hterm |
| 448pio=system.iobus.port[13] | 462pio=system.iobus.master[13] |
| 449 450[system.t1000.iob] 451type=Iob 452pio_latency=2 453platform=system.t1000 454system=system | 463 464[system.t1000.iob] 465type=Iob 466pio_latency=2 467platform=system.t1000 468system=system |
| 455pio=system.membus.port[0] | 469pio=system.membus.master[0] |
| 456 457[system.t1000.pterm] 458type=Terminal 459intr_control=system.intrctrl 460number=0 461output=true 462port=3456 463 464[system.t1000.puart0] 465type=Uart8250 466pio_addr=133412421632 467pio_latency=2 468platform=system.t1000 469system=system 470terminal=system.t1000.pterm | 470 471[system.t1000.pterm] 472type=Terminal 473intr_control=system.intrctrl 474number=0 475output=true 476port=3456 477 478[system.t1000.puart0] 479type=Uart8250 480pio_addr=133412421632 481pio_latency=2 482platform=system.t1000 483system=system 484terminal=system.t1000.pterm |
| 471pio=system.iobus.port[12] | 485pio=system.iobus.master[12] |
| 472 | 486 |