| config.ini (11946:8eb1f2595a92) | config.ini (11950:8011fd8ce05c) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=200000000 --- 30 unchanged lines hidden (view full) --- 39openboot_addr=1099243716608 40openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin 41p_state_clk_gate_bins=20 42p_state_clk_gate_max=2000000000 43p_state_clk_gate_min=2 44partition_desc=system.partition_desc 45partition_desc_addr=133445976064 46partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=200000000 --- 30 unchanged lines hidden (view full) --- 39openboot_addr=1099243716608 40openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin 41p_state_clk_gate_bins=20 42p_state_clk_gate_max=2000000000 43p_state_clk_gate_min=2 44partition_desc=system.partition_desc 45partition_desc_addr=133445976064 46partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin |
| 47power_model=Null |
|
| 47readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh 48reset_addr=1099243192320 49reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin 50rom=system.rom 51symbolfile= 52thermal_components= 53thermal_model=Null 54work_begin_ckpt_count=0 --- 9 unchanged lines hidden (view full) --- 64type=Bridge 65clk_domain=system.clk_domain 66default_p_state=UNDEFINED 67delay=100 68eventq_index=0 69p_state_clk_gate_bins=20 70p_state_clk_gate_max=2000000000 71p_state_clk_gate_min=2 | 48readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh 49reset_addr=1099243192320 50reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin 51rom=system.rom 52symbolfile= 53thermal_components= 54thermal_model=Null 55work_begin_ckpt_count=0 --- 9 unchanged lines hidden (view full) --- 65type=Bridge 66clk_domain=system.clk_domain 67default_p_state=UNDEFINED 68delay=100 69eventq_index=0 70p_state_clk_gate_bins=20 71p_state_clk_gate_max=2000000000 72p_state_clk_gate_min=2 |
| 73power_model=Null |
|
| 72ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 73req_size=16 74resp_size=16 75master=system.iobus.slave[0] 76slave=system.membus.master[2] 77 78[system.clk_domain] 79type=SrcClockDomain --- 25 unchanged lines hidden (view full) --- 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109numThreads=1 110p_state_clk_gate_bins=20 111p_state_clk_gate_max=2000000000 112p_state_clk_gate_min=2 | 74ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 75req_size=16 76resp_size=16 77master=system.iobus.slave[0] 78slave=system.membus.master[2] 79 80[system.clk_domain] 81type=SrcClockDomain --- 25 unchanged lines hidden (view full) --- 107max_insts_all_threads=0 108max_insts_any_thread=0 109max_loads_all_threads=0 110max_loads_any_thread=0 111numThreads=1 112p_state_clk_gate_bins=20 113p_state_clk_gate_max=2000000000 114p_state_clk_gate_min=2 |
| 115power_model=Null |
|
| 113profile=0 114progress_interval=0 115simpoint_start_insts= 116simulate_data_stalls=false 117simulate_inst_stalls=false 118socket_id=0 119switched_out=false 120system=system --- 40 unchanged lines hidden (view full) --- 161default_p_state=UNDEFINED 162eventq_index=0 163image=system.disk0.image 164p_state_clk_gate_bins=20 165p_state_clk_gate_max=2000000000 166p_state_clk_gate_min=2 167pio_addr=134217728000 168pio_latency=200 | 116profile=0 117progress_interval=0 118simpoint_start_insts= 119simulate_data_stalls=false 120simulate_inst_stalls=false 121socket_id=0 122switched_out=false 123system=system --- 40 unchanged lines hidden (view full) --- 164default_p_state=UNDEFINED 165eventq_index=0 166image=system.disk0.image 167p_state_clk_gate_bins=20 168p_state_clk_gate_max=2000000000 169p_state_clk_gate_min=2 170pio_addr=134217728000 171pio_latency=200 |
| 172power_model=Null |
|
| 169system=system 170pio=system.iobus.master[14] 171 172[system.disk0.image] 173type=CowDiskImage 174children=child 175child=system.disk0.image.child 176eventq_index=0 --- 24 unchanged lines hidden (view full) --- 201eventq_index=0 202in_addr_map=true 203latency=60 204latency_var=0 205null=false 206p_state_clk_gate_bins=20 207p_state_clk_gate_max=2000000000 208p_state_clk_gate_min=2 | 173system=system 174pio=system.iobus.master[14] 175 176[system.disk0.image] 177type=CowDiskImage 178children=child 179child=system.disk0.image.child 180eventq_index=0 --- 24 unchanged lines hidden (view full) --- 205eventq_index=0 206in_addr_map=true 207latency=60 208latency_var=0 209null=false 210p_state_clk_gate_bins=20 211p_state_clk_gate_max=2000000000 212p_state_clk_gate_min=2 |
| 213power_model=Null |
|
| 209range=133446500352:133446508543 210port=system.membus.master[5] 211 212[system.intrctrl] 213type=IntrControl 214eventq_index=0 215sys=system 216 217[system.iobus] 218type=NoncoherentXBar 219clk_domain=system.clk_domain 220default_p_state=UNDEFINED 221eventq_index=0 222forward_latency=1 223frontend_latency=2 224p_state_clk_gate_bins=20 225p_state_clk_gate_max=2000000000 226p_state_clk_gate_min=2 | 214range=133446500352:133446508543 215port=system.membus.master[5] 216 217[system.intrctrl] 218type=IntrControl 219eventq_index=0 220sys=system 221 222[system.iobus] 223type=NoncoherentXBar 224clk_domain=system.clk_domain 225default_p_state=UNDEFINED 226eventq_index=0 227forward_latency=1 228frontend_latency=2 229p_state_clk_gate_bins=20 230p_state_clk_gate_max=2000000000 231p_state_clk_gate_min=2 |
| 232power_model=Null |
|
| 227response_latency=2 228use_default_range=false 229width=16 230master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio 231slave=system.bridge.master 232 233[system.membus] 234type=CoherentXBar 235children=badaddr_responder 236clk_domain=system.clk_domain 237default_p_state=UNDEFINED 238eventq_index=0 239forward_latency=4 240frontend_latency=3 241p_state_clk_gate_bins=20 242p_state_clk_gate_max=2000000000 243p_state_clk_gate_min=2 244point_of_coherency=true | 233response_latency=2 234use_default_range=false 235width=16 236master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio 237slave=system.bridge.master 238 239[system.membus] 240type=CoherentXBar 241children=badaddr_responder 242clk_domain=system.clk_domain 243default_p_state=UNDEFINED 244eventq_index=0 245forward_latency=4 246frontend_latency=3 247p_state_clk_gate_bins=20 248p_state_clk_gate_max=2000000000 249p_state_clk_gate_min=2 250point_of_coherency=true |
| 251power_model=Null |
|
| 245response_latency=2 246snoop_filter=Null 247snoop_response_latency=4 248system=system 249use_default_range=false 250width=16 251default=system.membus.badaddr_responder.pio 252master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port --- 6 unchanged lines hidden (view full) --- 259eventq_index=0 260fake_mem=false 261p_state_clk_gate_bins=20 262p_state_clk_gate_max=2000000000 263p_state_clk_gate_min=2 264pio_addr=0 265pio_latency=200 266pio_size=8 | 252response_latency=2 253snoop_filter=Null 254snoop_response_latency=4 255system=system 256use_default_range=false 257width=16 258default=system.membus.badaddr_responder.pio 259master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port --- 6 unchanged lines hidden (view full) --- 266eventq_index=0 267fake_mem=false 268p_state_clk_gate_bins=20 269p_state_clk_gate_max=2000000000 270p_state_clk_gate_min=2 271pio_addr=0 272pio_latency=200 273pio_size=8 |
| 274power_model=Null |
|
| 267ret_bad_addr=true 268ret_data16=65535 269ret_data32=4294967295 270ret_data64=18446744073709551615 271ret_data8=255 272system=system 273update_data=false 274warn_access= --- 8 unchanged lines hidden (view full) --- 283eventq_index=0 284in_addr_map=true 285latency=60 286latency_var=0 287null=false 288p_state_clk_gate_bins=20 289p_state_clk_gate_max=2000000000 290p_state_clk_gate_min=2 | 275ret_bad_addr=true 276ret_data16=65535 277ret_data32=4294967295 278ret_data64=18446744073709551615 279ret_data8=255 280system=system 281update_data=false 282warn_access= --- 8 unchanged lines hidden (view full) --- 291eventq_index=0 292in_addr_map=true 293latency=60 294latency_var=0 295null=false 296p_state_clk_gate_bins=20 297p_state_clk_gate_max=2000000000 298p_state_clk_gate_min=2 |
| 299power_model=Null |
|
| 291range=133429198848:133429207039 292port=system.membus.master[4] 293 294[system.partition_desc] 295type=SimpleMemory 296bandwidth=0.000000 297clk_domain=system.clk_domain 298conf_table_reported=true 299default_p_state=UNDEFINED 300eventq_index=0 301in_addr_map=true 302latency=60 303latency_var=0 304null=false 305p_state_clk_gate_bins=20 306p_state_clk_gate_max=2000000000 307p_state_clk_gate_min=2 | 300range=133429198848:133429207039 301port=system.membus.master[4] 302 303[system.partition_desc] 304type=SimpleMemory 305bandwidth=0.000000 306clk_domain=system.clk_domain 307conf_table_reported=true 308default_p_state=UNDEFINED 309eventq_index=0 310in_addr_map=true 311latency=60 312latency_var=0 313null=false 314p_state_clk_gate_bins=20 315p_state_clk_gate_max=2000000000 316p_state_clk_gate_min=2 |
| 317power_model=Null |
|
| 308range=133445976064:133445984255 309port=system.membus.master[6] 310 311[system.physmem0] 312type=SimpleMemory 313bandwidth=0.000000 314clk_domain=system.clk_domain 315conf_table_reported=true 316default_p_state=UNDEFINED 317eventq_index=0 318in_addr_map=true 319latency=60 320latency_var=0 321null=false 322p_state_clk_gate_bins=20 323p_state_clk_gate_max=2000000000 324p_state_clk_gate_min=2 | 318range=133445976064:133445984255 319port=system.membus.master[6] 320 321[system.physmem0] 322type=SimpleMemory 323bandwidth=0.000000 324clk_domain=system.clk_domain 325conf_table_reported=true 326default_p_state=UNDEFINED 327eventq_index=0 328in_addr_map=true 329latency=60 330latency_var=0 331null=false 332p_state_clk_gate_bins=20 333p_state_clk_gate_max=2000000000 334p_state_clk_gate_min=2 |
| 335power_model=Null |
|
| 325range=1048576:68157439 326port=system.membus.master[7] 327 328[system.physmem1] 329type=SimpleMemory 330bandwidth=0.000000 331clk_domain=system.clk_domain 332conf_table_reported=true 333default_p_state=UNDEFINED 334eventq_index=0 335in_addr_map=true 336latency=60 337latency_var=0 338null=false 339p_state_clk_gate_bins=20 340p_state_clk_gate_max=2000000000 341p_state_clk_gate_min=2 | 336range=1048576:68157439 337port=system.membus.master[7] 338 339[system.physmem1] 340type=SimpleMemory 341bandwidth=0.000000 342clk_domain=system.clk_domain 343conf_table_reported=true 344default_p_state=UNDEFINED 345eventq_index=0 346in_addr_map=true 347latency=60 348latency_var=0 349null=false 350p_state_clk_gate_bins=20 351p_state_clk_gate_max=2000000000 352p_state_clk_gate_min=2 |
| 353power_model=Null |
|
| 342range=2147483648:2415919103 343port=system.membus.master[8] 344 345[system.rom] 346type=SimpleMemory 347bandwidth=0.000000 348clk_domain=system.clk_domain 349conf_table_reported=true 350default_p_state=UNDEFINED 351eventq_index=0 352in_addr_map=true 353latency=60 354latency_var=0 355null=false 356p_state_clk_gate_bins=20 357p_state_clk_gate_max=2000000000 358p_state_clk_gate_min=2 | 354range=2147483648:2415919103 355port=system.membus.master[8] 356 357[system.rom] 358type=SimpleMemory 359bandwidth=0.000000 360clk_domain=system.clk_domain 361conf_table_reported=true 362default_p_state=UNDEFINED 363eventq_index=0 364in_addr_map=true 365latency=60 366latency_var=0 367null=false 368p_state_clk_gate_bins=20 369p_state_clk_gate_max=2000000000 370p_state_clk_gate_min=2 |
| 371power_model=Null |
|
| 359range=1099243192320:1099251580927 360port=system.membus.master[3] 361 362[system.t1000] 363type=T1000 364children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 365eventq_index=0 366intrctrl=system.intrctrl --- 6 unchanged lines hidden (view full) --- 373eventq_index=0 374fake_mem=false 375p_state_clk_gate_bins=20 376p_state_clk_gate_max=2000000000 377p_state_clk_gate_min=2 378pio_addr=644245094400 379pio_latency=200 380pio_size=4294967296 | 372range=1099243192320:1099251580927 373port=system.membus.master[3] 374 375[system.t1000] 376type=T1000 377children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 378eventq_index=0 379intrctrl=system.intrctrl --- 6 unchanged lines hidden (view full) --- 386eventq_index=0 387fake_mem=false 388p_state_clk_gate_bins=20 389p_state_clk_gate_max=2000000000 390p_state_clk_gate_min=2 391pio_addr=644245094400 392pio_latency=200 393pio_size=4294967296 |
| 394power_model=Null |
|
| 381ret_bad_addr=false 382ret_data16=65535 383ret_data32=4294967295 384ret_data64=18446744073709551615 385ret_data8=255 386system=system 387update_data=false 388warn_access= --- 6 unchanged lines hidden (view full) --- 395eventq_index=0 396fake_mem=false 397p_state_clk_gate_bins=20 398p_state_clk_gate_max=2000000000 399p_state_clk_gate_min=2 400pio_addr=549755813888 401pio_latency=200 402pio_size=4294967296 | 395ret_bad_addr=false 396ret_data16=65535 397ret_data32=4294967295 398ret_data64=18446744073709551615 399ret_data8=255 400system=system 401update_data=false 402warn_access= --- 6 unchanged lines hidden (view full) --- 409eventq_index=0 410fake_mem=false 411p_state_clk_gate_bins=20 412p_state_clk_gate_max=2000000000 413p_state_clk_gate_min=2 414pio_addr=549755813888 415pio_latency=200 416pio_size=4294967296 |
| 417power_model=Null |
|
| 403ret_bad_addr=false 404ret_data16=65535 405ret_data32=4294967295 406ret_data64=18446744073709551615 407ret_data8=255 408system=system 409update_data=false 410warn_access= --- 6 unchanged lines hidden (view full) --- 417eventq_index=0 418fake_mem=false 419p_state_clk_gate_bins=20 420p_state_clk_gate_max=2000000000 421p_state_clk_gate_min=2 422pio_addr=725849473024 423pio_latency=200 424pio_size=8 | 418ret_bad_addr=false 419ret_data16=65535 420ret_data32=4294967295 421ret_data64=18446744073709551615 422ret_data8=255 423system=system 424update_data=false 425warn_access= --- 6 unchanged lines hidden (view full) --- 432eventq_index=0 433fake_mem=false 434p_state_clk_gate_bins=20 435p_state_clk_gate_max=2000000000 436p_state_clk_gate_min=2 437pio_addr=725849473024 438pio_latency=200 439pio_size=8 |
| 440power_model=Null |
|
| 425ret_bad_addr=false 426ret_data16=65535 427ret_data32=4294967295 428ret_data64=1 429ret_data8=255 430system=system 431update_data=true 432warn_access= --- 6 unchanged lines hidden (view full) --- 439eventq_index=0 440fake_mem=false 441p_state_clk_gate_bins=20 442p_state_clk_gate_max=2000000000 443p_state_clk_gate_min=2 444pio_addr=725849473088 445pio_latency=200 446pio_size=8 | 441ret_bad_addr=false 442ret_data16=65535 443ret_data32=4294967295 444ret_data64=1 445ret_data8=255 446system=system 447update_data=true 448warn_access= --- 6 unchanged lines hidden (view full) --- 455eventq_index=0 456fake_mem=false 457p_state_clk_gate_bins=20 458p_state_clk_gate_max=2000000000 459p_state_clk_gate_min=2 460pio_addr=725849473088 461pio_latency=200 462pio_size=8 |
| 463power_model=Null |
|
| 447ret_bad_addr=false 448ret_data16=65535 449ret_data32=4294967295 450ret_data64=1 451ret_data8=255 452system=system 453update_data=true 454warn_access= --- 6 unchanged lines hidden (view full) --- 461eventq_index=0 462fake_mem=false 463p_state_clk_gate_bins=20 464p_state_clk_gate_max=2000000000 465p_state_clk_gate_min=2 466pio_addr=725849473152 467pio_latency=200 468pio_size=8 | 464ret_bad_addr=false 465ret_data16=65535 466ret_data32=4294967295 467ret_data64=1 468ret_data8=255 469system=system 470update_data=true 471warn_access= --- 6 unchanged lines hidden (view full) --- 478eventq_index=0 479fake_mem=false 480p_state_clk_gate_bins=20 481p_state_clk_gate_max=2000000000 482p_state_clk_gate_min=2 483pio_addr=725849473152 484pio_latency=200 485pio_size=8 |
| 486power_model=Null |
|
| 469ret_bad_addr=false 470ret_data16=65535 471ret_data32=4294967295 472ret_data64=1 473ret_data8=255 474system=system 475update_data=true 476warn_access= --- 6 unchanged lines hidden (view full) --- 483eventq_index=0 484fake_mem=false 485p_state_clk_gate_bins=20 486p_state_clk_gate_max=2000000000 487p_state_clk_gate_min=2 488pio_addr=725849473216 489pio_latency=200 490pio_size=8 | 487ret_bad_addr=false 488ret_data16=65535 489ret_data32=4294967295 490ret_data64=1 491ret_data8=255 492system=system 493update_data=true 494warn_access= --- 6 unchanged lines hidden (view full) --- 501eventq_index=0 502fake_mem=false 503p_state_clk_gate_bins=20 504p_state_clk_gate_max=2000000000 505p_state_clk_gate_min=2 506pio_addr=725849473216 507pio_latency=200 508pio_size=8 |
| 509power_model=Null |
|
| 491ret_bad_addr=false 492ret_data16=65535 493ret_data32=4294967295 494ret_data64=1 495ret_data8=255 496system=system 497update_data=true 498warn_access= --- 6 unchanged lines hidden (view full) --- 505eventq_index=0 506fake_mem=false 507p_state_clk_gate_bins=20 508p_state_clk_gate_max=2000000000 509p_state_clk_gate_min=2 510pio_addr=734439407616 511pio_latency=200 512pio_size=8 | 510ret_bad_addr=false 511ret_data16=65535 512ret_data32=4294967295 513ret_data64=1 514ret_data8=255 515system=system 516update_data=true 517warn_access= --- 6 unchanged lines hidden (view full) --- 524eventq_index=0 525fake_mem=false 526p_state_clk_gate_bins=20 527p_state_clk_gate_max=2000000000 528p_state_clk_gate_min=2 529pio_addr=734439407616 530pio_latency=200 531pio_size=8 |
| 532power_model=Null |
|
| 513ret_bad_addr=false 514ret_data16=65535 515ret_data32=4294967295 516ret_data64=0 517ret_data8=255 518system=system 519update_data=true 520warn_access= --- 6 unchanged lines hidden (view full) --- 527eventq_index=0 528fake_mem=false 529p_state_clk_gate_bins=20 530p_state_clk_gate_max=2000000000 531p_state_clk_gate_min=2 532pio_addr=734439407680 533pio_latency=200 534pio_size=8 | 533ret_bad_addr=false 534ret_data16=65535 535ret_data32=4294967295 536ret_data64=0 537ret_data8=255 538system=system 539update_data=true 540warn_access= --- 6 unchanged lines hidden (view full) --- 547eventq_index=0 548fake_mem=false 549p_state_clk_gate_bins=20 550p_state_clk_gate_max=2000000000 551p_state_clk_gate_min=2 552pio_addr=734439407680 553pio_latency=200 554pio_size=8 |
| 555power_model=Null |
|
| 535ret_bad_addr=false 536ret_data16=65535 537ret_data32=4294967295 538ret_data64=0 539ret_data8=255 540system=system 541update_data=true 542warn_access= --- 6 unchanged lines hidden (view full) --- 549eventq_index=0 550fake_mem=false 551p_state_clk_gate_bins=20 552p_state_clk_gate_max=2000000000 553p_state_clk_gate_min=2 554pio_addr=734439407744 555pio_latency=200 556pio_size=8 | 556ret_bad_addr=false 557ret_data16=65535 558ret_data32=4294967295 559ret_data64=0 560ret_data8=255 561system=system 562update_data=true 563warn_access= --- 6 unchanged lines hidden (view full) --- 570eventq_index=0 571fake_mem=false 572p_state_clk_gate_bins=20 573p_state_clk_gate_max=2000000000 574p_state_clk_gate_min=2 575pio_addr=734439407744 576pio_latency=200 577pio_size=8 |
| 578power_model=Null |
|
| 557ret_bad_addr=false 558ret_data16=65535 559ret_data32=4294967295 560ret_data64=0 561ret_data8=255 562system=system 563update_data=true 564warn_access= --- 6 unchanged lines hidden (view full) --- 571eventq_index=0 572fake_mem=false 573p_state_clk_gate_bins=20 574p_state_clk_gate_max=2000000000 575p_state_clk_gate_min=2 576pio_addr=734439407808 577pio_latency=200 578pio_size=8 | 579ret_bad_addr=false 580ret_data16=65535 581ret_data32=4294967295 582ret_data64=0 583ret_data8=255 584system=system 585update_data=true 586warn_access= --- 6 unchanged lines hidden (view full) --- 593eventq_index=0 594fake_mem=false 595p_state_clk_gate_bins=20 596p_state_clk_gate_max=2000000000 597p_state_clk_gate_min=2 598pio_addr=734439407808 599pio_latency=200 600pio_size=8 |
| 601power_model=Null |
|
| 579ret_bad_addr=false 580ret_data16=65535 581ret_data32=4294967295 582ret_data64=0 583ret_data8=255 584system=system 585update_data=true 586warn_access= --- 6 unchanged lines hidden (view full) --- 593eventq_index=0 594fake_mem=false 595p_state_clk_gate_bins=20 596p_state_clk_gate_max=2000000000 597p_state_clk_gate_min=2 598pio_addr=648540061696 599pio_latency=200 600pio_size=16384 | 602ret_bad_addr=false 603ret_data16=65535 604ret_data32=4294967295 605ret_data64=0 606ret_data8=255 607system=system 608update_data=true 609warn_access= --- 6 unchanged lines hidden (view full) --- 616eventq_index=0 617fake_mem=false 618p_state_clk_gate_bins=20 619p_state_clk_gate_max=2000000000 620p_state_clk_gate_min=2 621pio_addr=648540061696 622pio_latency=200 623pio_size=16384 |
| 624power_model=Null |
|
| 601ret_bad_addr=false 602ret_data16=65535 603ret_data32=4294967295 604ret_data64=0 605ret_data8=255 606system=system 607update_data=false 608warn_access= --- 6 unchanged lines hidden (view full) --- 615eventq_index=0 616fake_mem=false 617p_state_clk_gate_bins=20 618p_state_clk_gate_max=2000000000 619p_state_clk_gate_min=2 620pio_addr=1095216660480 621pio_latency=200 622pio_size=268435456 | 625ret_bad_addr=false 626ret_data16=65535 627ret_data32=4294967295 628ret_data64=0 629ret_data8=255 630system=system 631update_data=false 632warn_access= --- 6 unchanged lines hidden (view full) --- 639eventq_index=0 640fake_mem=false 641p_state_clk_gate_bins=20 642p_state_clk_gate_max=2000000000 643p_state_clk_gate_min=2 644pio_addr=1095216660480 645pio_latency=200 646pio_size=268435456 |
| 647power_model=Null |
|
| 623ret_bad_addr=false 624ret_data16=65535 625ret_data32=4294967295 626ret_data64=18446744073709551615 627ret_data8=255 628system=system 629update_data=false 630warn_access= --- 12 unchanged lines hidden (view full) --- 643clk_domain=system.clk_domain 644default_p_state=UNDEFINED 645eventq_index=0 646p_state_clk_gate_bins=20 647p_state_clk_gate_max=2000000000 648p_state_clk_gate_min=2 649pio_addr=1099255906296 650pio_latency=200 | 648ret_bad_addr=false 649ret_data16=65535 650ret_data32=4294967295 651ret_data64=18446744073709551615 652ret_data8=255 653system=system 654update_data=false 655warn_access= --- 12 unchanged lines hidden (view full) --- 668clk_domain=system.clk_domain 669default_p_state=UNDEFINED 670eventq_index=0 671p_state_clk_gate_bins=20 672p_state_clk_gate_max=2000000000 673p_state_clk_gate_min=2 674pio_addr=1099255906296 675pio_latency=200 |
| 676power_model=Null |
|
| 651system=system 652time=Thu Jan 1 00:00:00 2009 653pio=system.membus.master[1] 654 655[system.t1000.hvuart] 656type=Uart8250 657clk_domain=system.clk_domain 658default_p_state=UNDEFINED 659eventq_index=0 660p_state_clk_gate_bins=20 661p_state_clk_gate_max=2000000000 662p_state_clk_gate_min=2 663pio_addr=1099255955456 664pio_latency=200 665platform=system.t1000 | 677system=system 678time=Thu Jan 1 00:00:00 2009 679pio=system.membus.master[1] 680 681[system.t1000.hvuart] 682type=Uart8250 683clk_domain=system.clk_domain 684default_p_state=UNDEFINED 685eventq_index=0 686p_state_clk_gate_bins=20 687p_state_clk_gate_max=2000000000 688p_state_clk_gate_min=2 689pio_addr=1099255955456 690pio_latency=200 691platform=system.t1000 |
| 692power_model=Null |
|
| 666system=system 667terminal=system.t1000.hterm 668pio=system.iobus.master[13] 669 670[system.t1000.iob] 671type=Iob 672clk_domain=system.clk_domain 673default_p_state=UNDEFINED 674eventq_index=0 675p_state_clk_gate_bins=20 676p_state_clk_gate_max=2000000000 677p_state_clk_gate_min=2 678pio_latency=2 679platform=system.t1000 | 693system=system 694terminal=system.t1000.hterm 695pio=system.iobus.master[13] 696 697[system.t1000.iob] 698type=Iob 699clk_domain=system.clk_domain 700default_p_state=UNDEFINED 701eventq_index=0 702p_state_clk_gate_bins=20 703p_state_clk_gate_max=2000000000 704p_state_clk_gate_min=2 705pio_latency=2 706platform=system.t1000 |
| 707power_model=Null |
|
| 680system=system 681pio=system.membus.master[0] 682 683[system.t1000.pterm] 684type=Terminal 685eventq_index=0 686intr_control=system.intrctrl 687number=0 --- 6 unchanged lines hidden (view full) --- 694default_p_state=UNDEFINED 695eventq_index=0 696p_state_clk_gate_bins=20 697p_state_clk_gate_max=2000000000 698p_state_clk_gate_min=2 699pio_addr=133412421632 700pio_latency=200 701platform=system.t1000 | 708system=system 709pio=system.membus.master[0] 710 711[system.t1000.pterm] 712type=Terminal 713eventq_index=0 714intr_control=system.intrctrl 715number=0 --- 6 unchanged lines hidden (view full) --- 722default_p_state=UNDEFINED 723eventq_index=0 724p_state_clk_gate_bins=20 725p_state_clk_gate_max=2000000000 726p_state_clk_gate_min=2 727pio_addr=133412421632 728pio_latency=200 729platform=system.t1000 |
| 730power_model=Null |
|
| 702system=system 703terminal=system.t1000.pterm 704pio=system.iobus.master[12] 705 706[system.voltage_domain] 707type=VoltageDomain 708eventq_index=0 709voltage=1.000000 710 | 731system=system 732terminal=system.t1000.pterm 733pio=system.iobus.master[12] 734 735[system.voltage_domain] 736type=VoltageDomain 737eventq_index=0 738voltage=1.000000 739 |