| config.ini (11298:e535b95573c0) | config.ini (11946:8eb1f2595a92) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=200000000 9time_sync_spin_threshold=200000 10 11[system] 12type=SparcSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=200000000 9time_sync_spin_threshold=200000 10 11[system] 12type=SparcSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17default_p_state=UNDEFINED |
|
| 17eventq_index=0 18exit_on_work_items=false 19hypervisor_addr=1099243257856 | 18eventq_index=0 19exit_on_work_items=false 20hypervisor_addr=1099243257856 |
| 20hypervisor_bin=/dist/m5/system/binaries/q_new.bin | 21hypervisor_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin |
| 21hypervisor_desc=system.hypervisor_desc 22hypervisor_desc_addr=133446500352 | 22hypervisor_desc=system.hypervisor_desc 23hypervisor_desc_addr=133446500352 |
| 23hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin | 24hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin |
| 24init_param=0 25kernel= 26kernel_addr_check=true 27load_addr_mask=1099511627775 28load_offset=0 29mem_mode=atomic 30mem_ranges=1048576:68157439 2147483648:2415919103 31memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom 32mmap_using_noreserve=false 33multi_thread=false 34num_work_ids=16 35nvram=system.nvram 36nvram_addr=133429198848 | 25init_param=0 26kernel= 27kernel_addr_check=true 28load_addr_mask=1099511627775 29load_offset=0 30mem_mode=atomic 31mem_ranges=1048576:68157439 2147483648:2415919103 32memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom 33mmap_using_noreserve=false 34multi_thread=false 35num_work_ids=16 36nvram=system.nvram 37nvram_addr=133429198848 |
| 37nvram_bin=/dist/m5/system/binaries/nvram1 | 38nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1 |
| 38openboot_addr=1099243716608 | 39openboot_addr=1099243716608 |
| 39openboot_bin=/dist/m5/system/binaries/openboot_new.bin | 40openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin 41p_state_clk_gate_bins=20 42p_state_clk_gate_max=2000000000 43p_state_clk_gate_min=2 |
| 40partition_desc=system.partition_desc 41partition_desc_addr=133445976064 | 44partition_desc=system.partition_desc 45partition_desc_addr=133445976064 |
| 42partition_desc_bin=/dist/m5/system/binaries/1up-md.bin 43readfile=/z/stever/hg/gem5/tests/halt.sh | 46partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin 47readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh |
| 44reset_addr=1099243192320 | 48reset_addr=1099243192320 |
| 45reset_bin=/dist/m5/system/binaries/reset_new.bin | 49reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin |
| 46rom=system.rom 47symbolfile= | 50rom=system.rom 51symbolfile= |
| 52thermal_components= 53thermal_model=Null |
|
| 48work_begin_ckpt_count=0 49work_begin_cpu_id_exit=-1 50work_begin_exit_count=0 51work_cpus_ckpt_count=0 52work_end_ckpt_count=0 53work_end_exit_count=0 54work_item_id=-1 55system_port=system.membus.slave[0] 56 57[system.bridge] 58type=Bridge 59clk_domain=system.clk_domain | 54work_begin_ckpt_count=0 55work_begin_cpu_id_exit=-1 56work_begin_exit_count=0 57work_cpus_ckpt_count=0 58work_end_ckpt_count=0 59work_end_exit_count=0 60work_item_id=-1 61system_port=system.membus.slave[0] 62 63[system.bridge] 64type=Bridge 65clk_domain=system.clk_domain |
| 66default_p_state=UNDEFINED |
|
| 60delay=100 61eventq_index=0 | 67delay=100 68eventq_index=0 |
| 69p_state_clk_gate_bins=20 70p_state_clk_gate_max=2000000000 71p_state_clk_gate_min=2 |
|
| 62ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 63req_size=16 64resp_size=16 65master=system.iobus.slave[0] 66slave=system.membus.master[2] 67 68[system.clk_domain] 69type=SrcClockDomain --- 5 unchanged lines hidden (view full) --- 75 76[system.cpu] 77type=AtomicSimpleCPU 78children=dtb interrupts isa itb tracer 79branchPred=Null 80checker=Null 81clk_domain=system.cpu_clk_domain 82cpu_id=0 | 72ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 73req_size=16 74resp_size=16 75master=system.iobus.slave[0] 76slave=system.membus.master[2] 77 78[system.clk_domain] 79type=SrcClockDomain --- 5 unchanged lines hidden (view full) --- 85 86[system.cpu] 87type=AtomicSimpleCPU 88children=dtb interrupts isa itb tracer 89branchPred=Null 90checker=Null 91clk_domain=system.cpu_clk_domain 92cpu_id=0 |
| 93default_p_state=UNDEFINED |
|
| 83do_checkpoint_insts=true 84do_quiesce=true 85do_statistics_insts=true 86dtb=system.cpu.dtb 87eventq_index=0 88fastmem=false 89function_trace=false 90function_trace_start=0 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93itb=system.cpu.itb 94max_insts_all_threads=0 95max_insts_any_thread=0 96max_loads_all_threads=0 97max_loads_any_thread=0 98numThreads=1 | 94do_checkpoint_insts=true 95do_quiesce=true 96do_statistics_insts=true 97dtb=system.cpu.dtb 98eventq_index=0 99fastmem=false 100function_trace=false 101function_trace_start=0 102interrupts=system.cpu.interrupts 103isa=system.cpu.isa 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109numThreads=1 |
| 110p_state_clk_gate_bins=20 111p_state_clk_gate_max=2000000000 112p_state_clk_gate_min=2 |
|
| 99profile=0 100progress_interval=0 101simpoint_start_insts= 102simulate_data_stalls=false 103simulate_inst_stalls=false 104socket_id=0 105switched_out=false 106system=system --- 32 unchanged lines hidden (view full) --- 139eventq_index=0 140init_perf_level=0 141voltage_domain=system.voltage_domain 142 143[system.disk0] 144type=MmDisk 145children=image 146clk_domain=system.clk_domain | 113profile=0 114progress_interval=0 115simpoint_start_insts= 116simulate_data_stalls=false 117simulate_inst_stalls=false 118socket_id=0 119switched_out=false 120system=system --- 32 unchanged lines hidden (view full) --- 153eventq_index=0 154init_perf_level=0 155voltage_domain=system.voltage_domain 156 157[system.disk0] 158type=MmDisk 159children=image 160clk_domain=system.clk_domain |
| 161default_p_state=UNDEFINED |
|
| 147eventq_index=0 148image=system.disk0.image | 162eventq_index=0 163image=system.disk0.image |
| 164p_state_clk_gate_bins=20 165p_state_clk_gate_max=2000000000 166p_state_clk_gate_min=2 |
|
| 149pio_addr=134217728000 150pio_latency=200 151system=system 152pio=system.iobus.master[14] 153 154[system.disk0.image] 155type=CowDiskImage 156children=child 157child=system.disk0.image.child 158eventq_index=0 159image_file= 160read_only=false 161table_size=65536 162 163[system.disk0.image.child] 164type=RawDiskImage 165eventq_index=0 | 167pio_addr=134217728000 168pio_latency=200 169system=system 170pio=system.iobus.master[14] 171 172[system.disk0.image] 173type=CowDiskImage 174children=child 175child=system.disk0.image.child 176eventq_index=0 177image_file= 178read_only=false 179table_size=65536 180 181[system.disk0.image.child] 182type=RawDiskImage 183eventq_index=0 |
| 166image_file=/dist/m5/system/disks/disk.s10hw2 | 184image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2 |
| 167read_only=true 168 169[system.dvfs_handler] 170type=DVFSHandler 171domains= 172enable=false 173eventq_index=0 174sys_clk_domain=system.clk_domain 175transition_latency=200000 176 177[system.hypervisor_desc] 178type=SimpleMemory 179bandwidth=0.000000 180clk_domain=system.clk_domain 181conf_table_reported=true | 185read_only=true 186 187[system.dvfs_handler] 188type=DVFSHandler 189domains= 190enable=false 191eventq_index=0 192sys_clk_domain=system.clk_domain 193transition_latency=200000 194 195[system.hypervisor_desc] 196type=SimpleMemory 197bandwidth=0.000000 198clk_domain=system.clk_domain 199conf_table_reported=true |
| 200default_p_state=UNDEFINED |
|
| 182eventq_index=0 183in_addr_map=true 184latency=60 185latency_var=0 186null=false | 201eventq_index=0 202in_addr_map=true 203latency=60 204latency_var=0 205null=false |
| 206p_state_clk_gate_bins=20 207p_state_clk_gate_max=2000000000 208p_state_clk_gate_min=2 |
|
| 187range=133446500352:133446508543 188port=system.membus.master[5] 189 190[system.intrctrl] 191type=IntrControl 192eventq_index=0 193sys=system 194 195[system.iobus] 196type=NoncoherentXBar 197clk_domain=system.clk_domain | 209range=133446500352:133446508543 210port=system.membus.master[5] 211 212[system.intrctrl] 213type=IntrControl 214eventq_index=0 215sys=system 216 217[system.iobus] 218type=NoncoherentXBar 219clk_domain=system.clk_domain |
| 220default_p_state=UNDEFINED |
|
| 198eventq_index=0 199forward_latency=1 200frontend_latency=2 | 221eventq_index=0 222forward_latency=1 223frontend_latency=2 |
| 224p_state_clk_gate_bins=20 225p_state_clk_gate_max=2000000000 226p_state_clk_gate_min=2 |
|
| 201response_latency=2 202use_default_range=false 203width=16 204master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio 205slave=system.bridge.master 206 207[system.membus] 208type=CoherentXBar 209children=badaddr_responder 210clk_domain=system.clk_domain | 227response_latency=2 228use_default_range=false 229width=16 230master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio 231slave=system.bridge.master 232 233[system.membus] 234type=CoherentXBar 235children=badaddr_responder 236clk_domain=system.clk_domain |
| 237default_p_state=UNDEFINED |
|
| 211eventq_index=0 212forward_latency=4 213frontend_latency=3 | 238eventq_index=0 239forward_latency=4 240frontend_latency=3 |
| 241p_state_clk_gate_bins=20 242p_state_clk_gate_max=2000000000 243p_state_clk_gate_min=2 244point_of_coherency=true |
|
| 214response_latency=2 215snoop_filter=Null 216snoop_response_latency=4 217system=system 218use_default_range=false 219width=16 220default=system.membus.badaddr_responder.pio 221master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port 222slave=system.system_port system.cpu.icache_port system.cpu.dcache_port 223 224[system.membus.badaddr_responder] 225type=IsaFake 226clk_domain=system.clk_domain | 245response_latency=2 246snoop_filter=Null 247snoop_response_latency=4 248system=system 249use_default_range=false 250width=16 251default=system.membus.badaddr_responder.pio 252master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port 253slave=system.system_port system.cpu.icache_port system.cpu.dcache_port 254 255[system.membus.badaddr_responder] 256type=IsaFake 257clk_domain=system.clk_domain |
| 258default_p_state=UNDEFINED |
|
| 227eventq_index=0 228fake_mem=false | 259eventq_index=0 260fake_mem=false |
| 261p_state_clk_gate_bins=20 262p_state_clk_gate_max=2000000000 263p_state_clk_gate_min=2 |
|
| 229pio_addr=0 230pio_latency=200 231pio_size=8 232ret_bad_addr=true 233ret_data16=65535 234ret_data32=4294967295 235ret_data64=18446744073709551615 236ret_data8=255 237system=system 238update_data=false 239warn_access= 240pio=system.membus.default 241 242[system.nvram] 243type=SimpleMemory 244bandwidth=0.000000 245clk_domain=system.clk_domain 246conf_table_reported=true | 264pio_addr=0 265pio_latency=200 266pio_size=8 267ret_bad_addr=true 268ret_data16=65535 269ret_data32=4294967295 270ret_data64=18446744073709551615 271ret_data8=255 272system=system 273update_data=false 274warn_access= 275pio=system.membus.default 276 277[system.nvram] 278type=SimpleMemory 279bandwidth=0.000000 280clk_domain=system.clk_domain 281conf_table_reported=true |
| 282default_p_state=UNDEFINED |
|
| 247eventq_index=0 248in_addr_map=true 249latency=60 250latency_var=0 251null=false | 283eventq_index=0 284in_addr_map=true 285latency=60 286latency_var=0 287null=false |
| 288p_state_clk_gate_bins=20 289p_state_clk_gate_max=2000000000 290p_state_clk_gate_min=2 |
|
| 252range=133429198848:133429207039 253port=system.membus.master[4] 254 255[system.partition_desc] 256type=SimpleMemory 257bandwidth=0.000000 258clk_domain=system.clk_domain 259conf_table_reported=true | 291range=133429198848:133429207039 292port=system.membus.master[4] 293 294[system.partition_desc] 295type=SimpleMemory 296bandwidth=0.000000 297clk_domain=system.clk_domain 298conf_table_reported=true |
| 299default_p_state=UNDEFINED |
|
| 260eventq_index=0 261in_addr_map=true 262latency=60 263latency_var=0 264null=false | 300eventq_index=0 301in_addr_map=true 302latency=60 303latency_var=0 304null=false |
| 305p_state_clk_gate_bins=20 306p_state_clk_gate_max=2000000000 307p_state_clk_gate_min=2 |
|
| 265range=133445976064:133445984255 266port=system.membus.master[6] 267 268[system.physmem0] 269type=SimpleMemory 270bandwidth=0.000000 271clk_domain=system.clk_domain 272conf_table_reported=true | 308range=133445976064:133445984255 309port=system.membus.master[6] 310 311[system.physmem0] 312type=SimpleMemory 313bandwidth=0.000000 314clk_domain=system.clk_domain 315conf_table_reported=true |
| 316default_p_state=UNDEFINED |
|
| 273eventq_index=0 274in_addr_map=true 275latency=60 276latency_var=0 277null=false | 317eventq_index=0 318in_addr_map=true 319latency=60 320latency_var=0 321null=false |
| 322p_state_clk_gate_bins=20 323p_state_clk_gate_max=2000000000 324p_state_clk_gate_min=2 |
|
| 278range=1048576:68157439 279port=system.membus.master[7] 280 281[system.physmem1] 282type=SimpleMemory 283bandwidth=0.000000 284clk_domain=system.clk_domain 285conf_table_reported=true | 325range=1048576:68157439 326port=system.membus.master[7] 327 328[system.physmem1] 329type=SimpleMemory 330bandwidth=0.000000 331clk_domain=system.clk_domain 332conf_table_reported=true |
| 333default_p_state=UNDEFINED |
|
| 286eventq_index=0 287in_addr_map=true 288latency=60 289latency_var=0 290null=false | 334eventq_index=0 335in_addr_map=true 336latency=60 337latency_var=0 338null=false |
| 339p_state_clk_gate_bins=20 340p_state_clk_gate_max=2000000000 341p_state_clk_gate_min=2 |
|
| 291range=2147483648:2415919103 292port=system.membus.master[8] 293 294[system.rom] 295type=SimpleMemory 296bandwidth=0.000000 297clk_domain=system.clk_domain 298conf_table_reported=true | 342range=2147483648:2415919103 343port=system.membus.master[8] 344 345[system.rom] 346type=SimpleMemory 347bandwidth=0.000000 348clk_domain=system.clk_domain 349conf_table_reported=true |
| 350default_p_state=UNDEFINED |
|
| 299eventq_index=0 300in_addr_map=true 301latency=60 302latency_var=0 303null=false | 351eventq_index=0 352in_addr_map=true 353latency=60 354latency_var=0 355null=false |
| 356p_state_clk_gate_bins=20 357p_state_clk_gate_max=2000000000 358p_state_clk_gate_min=2 |
|
| 304range=1099243192320:1099251580927 305port=system.membus.master[3] 306 307[system.t1000] 308type=T1000 309children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 310eventq_index=0 311intrctrl=system.intrctrl 312system=system 313 314[system.t1000.fake_clk] 315type=IsaFake 316clk_domain=system.clk_domain | 359range=1099243192320:1099251580927 360port=system.membus.master[3] 361 362[system.t1000] 363type=T1000 364children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 365eventq_index=0 366intrctrl=system.intrctrl 367system=system 368 369[system.t1000.fake_clk] 370type=IsaFake 371clk_domain=system.clk_domain |
| 372default_p_state=UNDEFINED |
|
| 317eventq_index=0 318fake_mem=false | 373eventq_index=0 374fake_mem=false |
| 375p_state_clk_gate_bins=20 376p_state_clk_gate_max=2000000000 377p_state_clk_gate_min=2 |
|
| 319pio_addr=644245094400 320pio_latency=200 321pio_size=4294967296 322ret_bad_addr=false 323ret_data16=65535 324ret_data32=4294967295 325ret_data64=18446744073709551615 326ret_data8=255 327system=system 328update_data=false 329warn_access= 330pio=system.iobus.master[0] 331 332[system.t1000.fake_jbi] 333type=IsaFake 334clk_domain=system.clk_domain | 378pio_addr=644245094400 379pio_latency=200 380pio_size=4294967296 381ret_bad_addr=false 382ret_data16=65535 383ret_data32=4294967295 384ret_data64=18446744073709551615 385ret_data8=255 386system=system 387update_data=false 388warn_access= 389pio=system.iobus.master[0] 390 391[system.t1000.fake_jbi] 392type=IsaFake 393clk_domain=system.clk_domain |
| 394default_p_state=UNDEFINED |
|
| 335eventq_index=0 336fake_mem=false | 395eventq_index=0 396fake_mem=false |
| 397p_state_clk_gate_bins=20 398p_state_clk_gate_max=2000000000 399p_state_clk_gate_min=2 |
|
| 337pio_addr=549755813888 338pio_latency=200 339pio_size=4294967296 340ret_bad_addr=false 341ret_data16=65535 342ret_data32=4294967295 343ret_data64=18446744073709551615 344ret_data8=255 345system=system 346update_data=false 347warn_access= 348pio=system.iobus.master[11] 349 350[system.t1000.fake_l2_1] 351type=IsaFake 352clk_domain=system.clk_domain | 400pio_addr=549755813888 401pio_latency=200 402pio_size=4294967296 403ret_bad_addr=false 404ret_data16=65535 405ret_data32=4294967295 406ret_data64=18446744073709551615 407ret_data8=255 408system=system 409update_data=false 410warn_access= 411pio=system.iobus.master[11] 412 413[system.t1000.fake_l2_1] 414type=IsaFake 415clk_domain=system.clk_domain |
| 416default_p_state=UNDEFINED |
|
| 353eventq_index=0 354fake_mem=false | 417eventq_index=0 418fake_mem=false |
| 419p_state_clk_gate_bins=20 420p_state_clk_gate_max=2000000000 421p_state_clk_gate_min=2 |
|
| 355pio_addr=725849473024 356pio_latency=200 357pio_size=8 358ret_bad_addr=false 359ret_data16=65535 360ret_data32=4294967295 361ret_data64=1 362ret_data8=255 363system=system 364update_data=true 365warn_access= 366pio=system.iobus.master[2] 367 368[system.t1000.fake_l2_2] 369type=IsaFake 370clk_domain=system.clk_domain | 422pio_addr=725849473024 423pio_latency=200 424pio_size=8 425ret_bad_addr=false 426ret_data16=65535 427ret_data32=4294967295 428ret_data64=1 429ret_data8=255 430system=system 431update_data=true 432warn_access= 433pio=system.iobus.master[2] 434 435[system.t1000.fake_l2_2] 436type=IsaFake 437clk_domain=system.clk_domain |
| 438default_p_state=UNDEFINED |
|
| 371eventq_index=0 372fake_mem=false | 439eventq_index=0 440fake_mem=false |
| 441p_state_clk_gate_bins=20 442p_state_clk_gate_max=2000000000 443p_state_clk_gate_min=2 |
|
| 373pio_addr=725849473088 374pio_latency=200 375pio_size=8 376ret_bad_addr=false 377ret_data16=65535 378ret_data32=4294967295 379ret_data64=1 380ret_data8=255 381system=system 382update_data=true 383warn_access= 384pio=system.iobus.master[3] 385 386[system.t1000.fake_l2_3] 387type=IsaFake 388clk_domain=system.clk_domain | 444pio_addr=725849473088 445pio_latency=200 446pio_size=8 447ret_bad_addr=false 448ret_data16=65535 449ret_data32=4294967295 450ret_data64=1 451ret_data8=255 452system=system 453update_data=true 454warn_access= 455pio=system.iobus.master[3] 456 457[system.t1000.fake_l2_3] 458type=IsaFake 459clk_domain=system.clk_domain |
| 460default_p_state=UNDEFINED |
|
| 389eventq_index=0 390fake_mem=false | 461eventq_index=0 462fake_mem=false |
| 463p_state_clk_gate_bins=20 464p_state_clk_gate_max=2000000000 465p_state_clk_gate_min=2 |
|
| 391pio_addr=725849473152 392pio_latency=200 393pio_size=8 394ret_bad_addr=false 395ret_data16=65535 396ret_data32=4294967295 397ret_data64=1 398ret_data8=255 399system=system 400update_data=true 401warn_access= 402pio=system.iobus.master[4] 403 404[system.t1000.fake_l2_4] 405type=IsaFake 406clk_domain=system.clk_domain | 466pio_addr=725849473152 467pio_latency=200 468pio_size=8 469ret_bad_addr=false 470ret_data16=65535 471ret_data32=4294967295 472ret_data64=1 473ret_data8=255 474system=system 475update_data=true 476warn_access= 477pio=system.iobus.master[4] 478 479[system.t1000.fake_l2_4] 480type=IsaFake 481clk_domain=system.clk_domain |
| 482default_p_state=UNDEFINED |
|
| 407eventq_index=0 408fake_mem=false | 483eventq_index=0 484fake_mem=false |
| 485p_state_clk_gate_bins=20 486p_state_clk_gate_max=2000000000 487p_state_clk_gate_min=2 |
|
| 409pio_addr=725849473216 410pio_latency=200 411pio_size=8 412ret_bad_addr=false 413ret_data16=65535 414ret_data32=4294967295 415ret_data64=1 416ret_data8=255 417system=system 418update_data=true 419warn_access= 420pio=system.iobus.master[5] 421 422[system.t1000.fake_l2esr_1] 423type=IsaFake 424clk_domain=system.clk_domain | 488pio_addr=725849473216 489pio_latency=200 490pio_size=8 491ret_bad_addr=false 492ret_data16=65535 493ret_data32=4294967295 494ret_data64=1 495ret_data8=255 496system=system 497update_data=true 498warn_access= 499pio=system.iobus.master[5] 500 501[system.t1000.fake_l2esr_1] 502type=IsaFake 503clk_domain=system.clk_domain |
| 504default_p_state=UNDEFINED |
|
| 425eventq_index=0 426fake_mem=false | 505eventq_index=0 506fake_mem=false |
| 507p_state_clk_gate_bins=20 508p_state_clk_gate_max=2000000000 509p_state_clk_gate_min=2 |
|
| 427pio_addr=734439407616 428pio_latency=200 429pio_size=8 430ret_bad_addr=false 431ret_data16=65535 432ret_data32=4294967295 433ret_data64=0 434ret_data8=255 435system=system 436update_data=true 437warn_access= 438pio=system.iobus.master[6] 439 440[system.t1000.fake_l2esr_2] 441type=IsaFake 442clk_domain=system.clk_domain | 510pio_addr=734439407616 511pio_latency=200 512pio_size=8 513ret_bad_addr=false 514ret_data16=65535 515ret_data32=4294967295 516ret_data64=0 517ret_data8=255 518system=system 519update_data=true 520warn_access= 521pio=system.iobus.master[6] 522 523[system.t1000.fake_l2esr_2] 524type=IsaFake 525clk_domain=system.clk_domain |
| 526default_p_state=UNDEFINED |
|
| 443eventq_index=0 444fake_mem=false | 527eventq_index=0 528fake_mem=false |
| 529p_state_clk_gate_bins=20 530p_state_clk_gate_max=2000000000 531p_state_clk_gate_min=2 |
|
| 445pio_addr=734439407680 446pio_latency=200 447pio_size=8 448ret_bad_addr=false 449ret_data16=65535 450ret_data32=4294967295 451ret_data64=0 452ret_data8=255 453system=system 454update_data=true 455warn_access= 456pio=system.iobus.master[7] 457 458[system.t1000.fake_l2esr_3] 459type=IsaFake 460clk_domain=system.clk_domain | 532pio_addr=734439407680 533pio_latency=200 534pio_size=8 535ret_bad_addr=false 536ret_data16=65535 537ret_data32=4294967295 538ret_data64=0 539ret_data8=255 540system=system 541update_data=true 542warn_access= 543pio=system.iobus.master[7] 544 545[system.t1000.fake_l2esr_3] 546type=IsaFake 547clk_domain=system.clk_domain |
| 548default_p_state=UNDEFINED |
|
| 461eventq_index=0 462fake_mem=false | 549eventq_index=0 550fake_mem=false |
| 551p_state_clk_gate_bins=20 552p_state_clk_gate_max=2000000000 553p_state_clk_gate_min=2 |
|
| 463pio_addr=734439407744 464pio_latency=200 465pio_size=8 466ret_bad_addr=false 467ret_data16=65535 468ret_data32=4294967295 469ret_data64=0 470ret_data8=255 471system=system 472update_data=true 473warn_access= 474pio=system.iobus.master[8] 475 476[system.t1000.fake_l2esr_4] 477type=IsaFake 478clk_domain=system.clk_domain | 554pio_addr=734439407744 555pio_latency=200 556pio_size=8 557ret_bad_addr=false 558ret_data16=65535 559ret_data32=4294967295 560ret_data64=0 561ret_data8=255 562system=system 563update_data=true 564warn_access= 565pio=system.iobus.master[8] 566 567[system.t1000.fake_l2esr_4] 568type=IsaFake 569clk_domain=system.clk_domain |
| 570default_p_state=UNDEFINED |
|
| 479eventq_index=0 480fake_mem=false | 571eventq_index=0 572fake_mem=false |
| 573p_state_clk_gate_bins=20 574p_state_clk_gate_max=2000000000 575p_state_clk_gate_min=2 |
|
| 481pio_addr=734439407808 482pio_latency=200 483pio_size=8 484ret_bad_addr=false 485ret_data16=65535 486ret_data32=4294967295 487ret_data64=0 488ret_data8=255 489system=system 490update_data=true 491warn_access= 492pio=system.iobus.master[9] 493 494[system.t1000.fake_membnks] 495type=IsaFake 496clk_domain=system.clk_domain | 576pio_addr=734439407808 577pio_latency=200 578pio_size=8 579ret_bad_addr=false 580ret_data16=65535 581ret_data32=4294967295 582ret_data64=0 583ret_data8=255 584system=system 585update_data=true 586warn_access= 587pio=system.iobus.master[9] 588 589[system.t1000.fake_membnks] 590type=IsaFake 591clk_domain=system.clk_domain |
| 592default_p_state=UNDEFINED |
|
| 497eventq_index=0 498fake_mem=false | 593eventq_index=0 594fake_mem=false |
| 595p_state_clk_gate_bins=20 596p_state_clk_gate_max=2000000000 597p_state_clk_gate_min=2 |
|
| 499pio_addr=648540061696 500pio_latency=200 501pio_size=16384 502ret_bad_addr=false 503ret_data16=65535 504ret_data32=4294967295 505ret_data64=0 506ret_data8=255 507system=system 508update_data=false 509warn_access= 510pio=system.iobus.master[1] 511 512[system.t1000.fake_ssi] 513type=IsaFake 514clk_domain=system.clk_domain | 598pio_addr=648540061696 599pio_latency=200 600pio_size=16384 601ret_bad_addr=false 602ret_data16=65535 603ret_data32=4294967295 604ret_data64=0 605ret_data8=255 606system=system 607update_data=false 608warn_access= 609pio=system.iobus.master[1] 610 611[system.t1000.fake_ssi] 612type=IsaFake 613clk_domain=system.clk_domain |
| 614default_p_state=UNDEFINED |
|
| 515eventq_index=0 516fake_mem=false | 615eventq_index=0 616fake_mem=false |
| 617p_state_clk_gate_bins=20 618p_state_clk_gate_max=2000000000 619p_state_clk_gate_min=2 |
|
| 517pio_addr=1095216660480 518pio_latency=200 519pio_size=268435456 520ret_bad_addr=false 521ret_data16=65535 522ret_data32=4294967295 523ret_data64=18446744073709551615 524ret_data8=255 --- 8 unchanged lines hidden (view full) --- 533intr_control=system.intrctrl 534number=0 535output=true 536port=3456 537 538[system.t1000.htod] 539type=DumbTOD 540clk_domain=system.clk_domain | 620pio_addr=1095216660480 621pio_latency=200 622pio_size=268435456 623ret_bad_addr=false 624ret_data16=65535 625ret_data32=4294967295 626ret_data64=18446744073709551615 627ret_data8=255 --- 8 unchanged lines hidden (view full) --- 636intr_control=system.intrctrl 637number=0 638output=true 639port=3456 640 641[system.t1000.htod] 642type=DumbTOD 643clk_domain=system.clk_domain |
| 644default_p_state=UNDEFINED |
|
| 541eventq_index=0 | 645eventq_index=0 |
| 646p_state_clk_gate_bins=20 647p_state_clk_gate_max=2000000000 648p_state_clk_gate_min=2 |
|
| 542pio_addr=1099255906296 543pio_latency=200 544system=system 545time=Thu Jan 1 00:00:00 2009 546pio=system.membus.master[1] 547 548[system.t1000.hvuart] 549type=Uart8250 550clk_domain=system.clk_domain | 649pio_addr=1099255906296 650pio_latency=200 651system=system 652time=Thu Jan 1 00:00:00 2009 653pio=system.membus.master[1] 654 655[system.t1000.hvuart] 656type=Uart8250 657clk_domain=system.clk_domain |
| 658default_p_state=UNDEFINED |
|
| 551eventq_index=0 | 659eventq_index=0 |
| 660p_state_clk_gate_bins=20 661p_state_clk_gate_max=2000000000 662p_state_clk_gate_min=2 |
|
| 552pio_addr=1099255955456 553pio_latency=200 554platform=system.t1000 555system=system 556terminal=system.t1000.hterm 557pio=system.iobus.master[13] 558 559[system.t1000.iob] 560type=Iob 561clk_domain=system.clk_domain | 663pio_addr=1099255955456 664pio_latency=200 665platform=system.t1000 666system=system 667terminal=system.t1000.hterm 668pio=system.iobus.master[13] 669 670[system.t1000.iob] 671type=Iob 672clk_domain=system.clk_domain |
| 673default_p_state=UNDEFINED |
|
| 562eventq_index=0 | 674eventq_index=0 |
| 675p_state_clk_gate_bins=20 676p_state_clk_gate_max=2000000000 677p_state_clk_gate_min=2 |
|
| 563pio_latency=2 564platform=system.t1000 565system=system 566pio=system.membus.master[0] 567 568[system.t1000.pterm] 569type=Terminal 570eventq_index=0 571intr_control=system.intrctrl 572number=0 573output=true 574port=3456 575 576[system.t1000.puart0] 577type=Uart8250 578clk_domain=system.clk_domain | 678pio_latency=2 679platform=system.t1000 680system=system 681pio=system.membus.master[0] 682 683[system.t1000.pterm] 684type=Terminal 685eventq_index=0 686intr_control=system.intrctrl 687number=0 688output=true 689port=3456 690 691[system.t1000.puart0] 692type=Uart8250 693clk_domain=system.clk_domain |
| 694default_p_state=UNDEFINED |
|
| 579eventq_index=0 | 695eventq_index=0 |
| 696p_state_clk_gate_bins=20 697p_state_clk_gate_max=2000000000 698p_state_clk_gate_min=2 |
|
| 580pio_addr=133412421632 581pio_latency=200 582platform=system.t1000 583system=system 584terminal=system.t1000.pterm 585pio=system.iobus.master[12] 586 587[system.voltage_domain] 588type=VoltageDomain 589eventq_index=0 590voltage=1.000000 591 | 699pio_addr=133412421632 700pio_latency=200 701platform=system.t1000 702system=system 703terminal=system.t1000.pterm 704pio=system.iobus.master[12] 705 706[system.voltage_domain] 707type=VoltageDomain 708eventq_index=0 709voltage=1.000000 710 |