1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=200000000 7time_sync_spin_threshold=200000 8 9[system] 10type=SparcSystem 11children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000 12boot_osflags=a
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13clock=2 |
14hypervisor_addr=1099243257856 15hypervisor_bin=/dist/m5/system/binaries/q_new.bin 16hypervisor_desc=system.hypervisor_desc 17hypervisor_desc_addr=133446500352 18hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin 19init_param=0 20kernel= 21load_addr_mask=1099511627775 22mem_mode=atomic
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22memories=system.partition_desc system.rom system.hypervisor_desc system.nvram system.physmem system.physmem2
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23mem_ranges=1048576:68157439 2147483648:2415919103 24memories=system.partition_desc system.physmem system.rom system.hypervisor_desc system.physmem2 system.nvram |
25num_work_ids=16 26nvram=system.nvram 27nvram_addr=133429198848 28nvram_bin=/dist/m5/system/binaries/nvram1 29openboot_addr=1099243716608 30openboot_bin=/dist/m5/system/binaries/openboot_new.bin 31partition_desc=system.partition_desc 32partition_desc_addr=133445976064 33partition_desc_bin=/dist/m5/system/binaries/1up-md.bin 34readfile=tests/halt.sh 35reset_addr=1099243192320 36reset_bin=/dist/m5/system/binaries/reset_new.bin 37rom=system.rom 38symbolfile= 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.bridge] 49type=Bridge
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50clock=2 |
51delay=100
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49nack_delay=8
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52ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 53req_size=16 54resp_size=16
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53write_ack=false
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55master=system.iobus.slave[0] 56slave=system.membus.master[2] 57 58[system.cpu] 59type=AtomicSimpleCPU
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59children=dtb interrupts itb tracer
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60children=dtb interrupts isa itb tracer 61branchPred=Null |
62checker=Null
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61clock=1
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63clock=2 |
64cpu_id=0
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63defer_registration=false
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65do_checkpoint_insts=true 66do_quiesce=true 67do_statistics_insts=true 68dtb=system.cpu.dtb 69fastmem=false 70function_trace=false 71function_trace_start=0 72interrupts=system.cpu.interrupts
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73isa=system.cpu.isa |
74itb=system.cpu.itb 75max_insts_all_threads=0 76max_insts_any_thread=0 77max_loads_all_threads=0 78max_loads_any_thread=0 79numThreads=1
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78phase=0
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80profile=0 81progress_interval=0 82simulate_data_stalls=false 83simulate_inst_stalls=false
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84switched_out=false |
85system=system 86tracer=system.cpu.tracer 87width=1 88workload= 89dcache_port=system.membus.slave[2] 90icache_port=system.membus.slave[1] 91 92[system.cpu.dtb] 93type=SparcTLB 94size=64 95 96[system.cpu.interrupts] 97type=SparcInterrupts 98
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99[system.cpu.isa] 100type=SparcISA 101 |
102[system.cpu.itb] 103type=SparcTLB 104size=64 105 106[system.cpu.tracer] 107type=ExeTracer 108 109[system.disk0] 110type=MmDisk 111children=image
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112clock=2 |
113image=system.disk0.image 114pio_addr=134217728000
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109pio_latency=2
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115pio_latency=200 |
116system=system 117pio=system.iobus.master[14] 118 119[system.disk0.image] 120type=CowDiskImage 121children=child 122child=system.disk0.image.child 123image_file= 124read_only=false 125table_size=65536 126 127[system.disk0.image.child] 128type=RawDiskImage 129image_file=/dist/m5/system/disks/disk.s10hw2 130read_only=true 131 132[system.hypervisor_desc] 133type=SimpleMemory
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134bandwidth=0.000000 135clock=2 |
136conf_table_reported=false
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129file=
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137in_addr_map=true 138latency=60 139latency_var=0 140null=false 141range=133446500352:133446508543 142zero=false 143port=system.membus.master[7] 144 145[system.intrctrl] 146type=IntrControl 147sys=system 148 149[system.iobus] 150type=NoncoherentBus 151block_size=64 152clock=2 153header_cycles=1 154use_default_range=false
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148width=64
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155width=8 |
156master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio 157slave=system.bridge.master 158 159[system.membus] 160type=CoherentBus 161children=badaddr_responder 162block_size=64 163clock=2 164header_cycles=1
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165system=system |
166use_default_range=false
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159width=64
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167width=8 |
168default=system.membus.badaddr_responder.pio
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161master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0]
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169master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port system.physmem2.port system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port |
170slave=system.system_port system.cpu.icache_port system.cpu.dcache_port 171 172[system.membus.badaddr_responder] 173type=IsaFake
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174clock=2 |
175fake_mem=false 176pio_addr=0
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168pio_latency=2
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177pio_latency=200 |
178pio_size=8 179ret_bad_addr=true 180ret_data16=65535 181ret_data32=4294967295 182ret_data64=18446744073709551615 183ret_data8=255 184system=system 185update_data=false 186warn_access= 187pio=system.membus.default 188 189[system.nvram] 190type=SimpleMemory
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191bandwidth=0.000000 192clock=2 |
193conf_table_reported=false
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183file=
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194in_addr_map=true 195latency=60 196latency_var=0 197null=false 198range=133429198848:133429207039 199zero=false 200port=system.membus.master[6] 201 202[system.partition_desc] 203type=SimpleMemory
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204bandwidth=0.000000 205clock=2 |
206conf_table_reported=false
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195file=
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207in_addr_map=true 208latency=60 209latency_var=0 210null=false 211range=133445976064:133445984255 212zero=false 213port=system.membus.master[8] 214 215[system.physmem]
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205type=SimpleMemory
|
216type=SimpleDRAM 217activation_limit=4 218addr_mapping=openmap 219banks_per_rank=8 220channels=1 221clock=2 |
222conf_table_reported=false
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207file=
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223in_addr_map=true
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209latency=60
210latency_var=0
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224lines_per_rowbuffer=32 225mem_sched_policy=frfcfs |
226null=false
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227page_policy=open |
228range=1048576:68157439
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229ranks_per_channel=2 230read_buffer_size=32 231tBURST=10 232tCL=28 233tRCD=28 234tREFI=15600 235tRFC=600 236tRP=28 237tWTR=15 238tXAW=80 239write_buffer_size=32 240write_thresh_perc=70 |
241zero=true 242port=system.membus.master[3] 243 244[system.physmem2]
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217type=SimpleMemory
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245type=SimpleDRAM 246activation_limit=4 247addr_mapping=openmap 248banks_per_rank=8 249channels=1 250clock=2 |
251conf_table_reported=false
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219file=
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252in_addr_map=true
|
221latency=60
222latency_var=0
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253lines_per_rowbuffer=32 254mem_sched_policy=frfcfs |
255null=false
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256page_policy=open |
257range=2147483648:2415919103
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258ranks_per_channel=2 259read_buffer_size=32 260tBURST=10 261tCL=28 262tRCD=28 263tREFI=15600 264tRFC=600 265tRP=28 266tWTR=15 267tXAW=80 268write_buffer_size=32 269write_thresh_perc=70 |
270zero=true 271port=system.membus.master[4] 272 273[system.rom] 274type=SimpleMemory
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275bandwidth=0.000000 276clock=2 |
277conf_table_reported=false
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231file=
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278in_addr_map=true 279latency=60 280latency_var=0 281null=false 282range=1099243192320:1099251580927 283zero=false 284port=system.membus.master[5] 285 286[system.t1000] 287type=T1000 288children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0 289intrctrl=system.intrctrl 290system=system 291 292[system.t1000.fake_clk] 293type=IsaFake
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294clock=2 |
295fake_mem=false 296pio_addr=644245094400
|
250pio_latency=2
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297pio_latency=200 |
298pio_size=4294967296 299ret_bad_addr=false 300ret_data16=65535 301ret_data32=4294967295 302ret_data64=18446744073709551615 303ret_data8=255 304system=system 305update_data=false 306warn_access= 307pio=system.iobus.master[0] 308 309[system.t1000.fake_jbi] 310type=IsaFake
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311clock=2 |
312fake_mem=false 313pio_addr=549755813888
|
266pio_latency=2
|
314pio_latency=200 |
315pio_size=4294967296 316ret_bad_addr=false 317ret_data16=65535 318ret_data32=4294967295 319ret_data64=18446744073709551615 320ret_data8=255 321system=system 322update_data=false 323warn_access= 324pio=system.iobus.master[11] 325 326[system.t1000.fake_l2_1] 327type=IsaFake
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328clock=2 |
329fake_mem=false 330pio_addr=725849473024
|
282pio_latency=2
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331pio_latency=200 |
332pio_size=8 333ret_bad_addr=false 334ret_data16=65535 335ret_data32=4294967295 336ret_data64=1 337ret_data8=255 338system=system 339update_data=true 340warn_access= 341pio=system.iobus.master[2] 342 343[system.t1000.fake_l2_2] 344type=IsaFake
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345clock=2 |
346fake_mem=false 347pio_addr=725849473088
|
298pio_latency=2
|
348pio_latency=200 |
349pio_size=8 350ret_bad_addr=false 351ret_data16=65535 352ret_data32=4294967295 353ret_data64=1 354ret_data8=255 355system=system 356update_data=true 357warn_access= 358pio=system.iobus.master[3] 359 360[system.t1000.fake_l2_3] 361type=IsaFake
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362clock=2 |
363fake_mem=false 364pio_addr=725849473152
|
314pio_latency=2
|
365pio_latency=200 |
366pio_size=8 367ret_bad_addr=false 368ret_data16=65535 369ret_data32=4294967295 370ret_data64=1 371ret_data8=255 372system=system 373update_data=true 374warn_access= 375pio=system.iobus.master[4] 376 377[system.t1000.fake_l2_4] 378type=IsaFake
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379clock=2 |
380fake_mem=false 381pio_addr=725849473216
|
330pio_latency=2
|
382pio_latency=200 |
383pio_size=8 384ret_bad_addr=false 385ret_data16=65535 386ret_data32=4294967295 387ret_data64=1 388ret_data8=255 389system=system 390update_data=true 391warn_access= 392pio=system.iobus.master[5] 393 394[system.t1000.fake_l2esr_1] 395type=IsaFake
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396clock=2 |
397fake_mem=false 398pio_addr=734439407616
|
346pio_latency=2
|
399pio_latency=200 |
400pio_size=8 401ret_bad_addr=false 402ret_data16=65535 403ret_data32=4294967295 404ret_data64=0 405ret_data8=255 406system=system 407update_data=true 408warn_access= 409pio=system.iobus.master[6] 410 411[system.t1000.fake_l2esr_2] 412type=IsaFake
|
413clock=2 |
414fake_mem=false 415pio_addr=734439407680
|
362pio_latency=2
|
416pio_latency=200 |
417pio_size=8 418ret_bad_addr=false 419ret_data16=65535 420ret_data32=4294967295 421ret_data64=0 422ret_data8=255 423system=system 424update_data=true 425warn_access= 426pio=system.iobus.master[7] 427 428[system.t1000.fake_l2esr_3] 429type=IsaFake
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430clock=2 |
431fake_mem=false 432pio_addr=734439407744
|
378pio_latency=2
|
433pio_latency=200 |
434pio_size=8 435ret_bad_addr=false 436ret_data16=65535 437ret_data32=4294967295 438ret_data64=0 439ret_data8=255 440system=system 441update_data=true 442warn_access= 443pio=system.iobus.master[8] 444 445[system.t1000.fake_l2esr_4] 446type=IsaFake
|
447clock=2 |
448fake_mem=false 449pio_addr=734439407808
|
394pio_latency=2
|
450pio_latency=200 |
451pio_size=8 452ret_bad_addr=false 453ret_data16=65535 454ret_data32=4294967295 455ret_data64=0 456ret_data8=255 457system=system 458update_data=true 459warn_access= 460pio=system.iobus.master[9] 461 462[system.t1000.fake_membnks] 463type=IsaFake
|
464clock=2 |
465fake_mem=false 466pio_addr=648540061696
|
410pio_latency=2
|
467pio_latency=200 |
468pio_size=16384 469ret_bad_addr=false 470ret_data16=65535 471ret_data32=4294967295 472ret_data64=0 473ret_data8=255 474system=system 475update_data=false 476warn_access= 477pio=system.iobus.master[1] 478 479[system.t1000.fake_ssi] 480type=IsaFake
|
481clock=2 |
482fake_mem=false 483pio_addr=1095216660480
|
426pio_latency=2
|
484pio_latency=200 |
485pio_size=268435456 486ret_bad_addr=false 487ret_data16=65535 488ret_data32=4294967295 489ret_data64=18446744073709551615 490ret_data8=255 491system=system 492update_data=false 493warn_access= 494pio=system.iobus.master[10] 495 496[system.t1000.hterm] 497type=Terminal 498intr_control=system.intrctrl 499number=0 500output=true 501port=3456 502 503[system.t1000.htod] 504type=DumbTOD
|
505clock=2 |
506pio_addr=1099255906296
|
448pio_latency=2
|
507pio_latency=200 |
508system=system 509time=Thu Jan 1 00:00:00 2009 510pio=system.membus.master[1] 511 512[system.t1000.hvuart] 513type=Uart8250
|
514clock=2 |
515pio_addr=1099255955456
|
456pio_latency=2
|
516pio_latency=200 |
517platform=system.t1000 518system=system 519terminal=system.t1000.hterm 520pio=system.iobus.master[13] 521 522[system.t1000.iob] 523type=Iob
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524clock=2 |
525pio_latency=2 526platform=system.t1000 527system=system 528pio=system.membus.master[0] 529 530[system.t1000.pterm] 531type=Terminal 532intr_control=system.intrctrl 533number=0 534output=true 535port=3456 536 537[system.t1000.puart0] 538type=Uart8250
|
539clock=2 |
540pio_addr=133412421632
|
479pio_latency=2
|
541pio_latency=200 |
542platform=system.t1000 543system=system 544terminal=system.t1000.pterm 545pio=system.iobus.master[12] 546
|