1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=200000000
9time_sync_spin_threshold=200000
10
11[system]
12type=SparcSystem
13children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17default_p_state=UNDEFINED
18eventq_index=0
19exit_on_work_items=false
20hypervisor_addr=1099243257856
21hypervisor_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin
22hypervisor_desc=system.hypervisor_desc
23hypervisor_desc_addr=133446500352
24hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin
25init_param=0
26kernel=
27kernel_addr_check=true
28load_addr_mask=1099511627775
29load_offset=0
30mem_mode=atomic
| 1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=200000000
9time_sync_spin_threshold=200000
10
11[system]
12type=SparcSystem
13children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17default_p_state=UNDEFINED
18eventq_index=0
19exit_on_work_items=false
20hypervisor_addr=1099243257856
21hypervisor_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin
22hypervisor_desc=system.hypervisor_desc
23hypervisor_desc_addr=133446500352
24hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin
25init_param=0
26kernel=
27kernel_addr_check=true
28load_addr_mask=1099511627775
29load_offset=0
30mem_mode=atomic
|
31mem_ranges=1048576:68157439 2147483648:2415919103
| 31mem_ranges=1048576:68157439:0:0:0:0 2147483648:2415919103:0:0:0:0
|
32memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom
33mmap_using_noreserve=false
34multi_thread=false
35num_work_ids=16
36nvram=system.nvram
37nvram_addr=133429198848
38nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1
39openboot_addr=1099243716608
40openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin
41p_state_clk_gate_bins=20
42p_state_clk_gate_max=2000000000
43p_state_clk_gate_min=2
44partition_desc=system.partition_desc
45partition_desc_addr=133445976064
46partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin
47power_model=Null
48readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
49reset_addr=1099243192320
50reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin
51rom=system.rom
52symbolfile=
53thermal_components=
54thermal_model=Null
55work_begin_ckpt_count=0
56work_begin_cpu_id_exit=-1
57work_begin_exit_count=0
58work_cpus_ckpt_count=0
59work_end_ckpt_count=0
60work_end_exit_count=0
61work_item_id=-1
62system_port=system.membus.slave[0]
63
64[system.bridge]
65type=Bridge
66clk_domain=system.clk_domain
67default_p_state=UNDEFINED
68delay=100
69eventq_index=0
70p_state_clk_gate_bins=20
71p_state_clk_gate_max=2000000000
72p_state_clk_gate_min=2
73power_model=Null
| 32memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom
33mmap_using_noreserve=false
34multi_thread=false
35num_work_ids=16
36nvram=system.nvram
37nvram_addr=133429198848
38nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1
39openboot_addr=1099243716608
40openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin
41p_state_clk_gate_bins=20
42p_state_clk_gate_max=2000000000
43p_state_clk_gate_min=2
44partition_desc=system.partition_desc
45partition_desc_addr=133445976064
46partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin
47power_model=Null
48readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
49reset_addr=1099243192320
50reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin
51rom=system.rom
52symbolfile=
53thermal_components=
54thermal_model=Null
55work_begin_ckpt_count=0
56work_begin_cpu_id_exit=-1
57work_begin_exit_count=0
58work_cpus_ckpt_count=0
59work_end_ckpt_count=0
60work_end_exit_count=0
61work_item_id=-1
62system_port=system.membus.slave[0]
63
64[system.bridge]
65type=Bridge
66clk_domain=system.clk_domain
67default_p_state=UNDEFINED
68delay=100
69eventq_index=0
70p_state_clk_gate_bins=20
71p_state_clk_gate_max=2000000000
72p_state_clk_gate_min=2
73power_model=Null
|
74ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
| 74ranges=133412421632:133412421639:0:0:0:0 134217728000:554050781183:0:0:0:0 644245094400:652835028991:0:0:0:0 725849473024:1095485095935:0:0:0:0 1099255955456:1099255955463:0:0:0:0
|
75req_size=16
76resp_size=16
77master=system.iobus.slave[0]
78slave=system.membus.master[2]
79
80[system.clk_domain]
81type=SrcClockDomain
82clock=2
83domain_id=-1
84eventq_index=0
85init_perf_level=0
86voltage_domain=system.voltage_domain
87
88[system.cpu]
89type=AtomicSimpleCPU
90children=dtb interrupts isa itb tracer
91branchPred=Null
92checker=Null
93clk_domain=system.cpu_clk_domain
94cpu_id=0
95default_p_state=UNDEFINED
96do_checkpoint_insts=true
97do_quiesce=true
98do_statistics_insts=true
99dtb=system.cpu.dtb
100eventq_index=0
101fastmem=false
102function_trace=false
103function_trace_start=0
104interrupts=system.cpu.interrupts
105isa=system.cpu.isa
106itb=system.cpu.itb
107max_insts_all_threads=0
108max_insts_any_thread=0
109max_loads_all_threads=0
110max_loads_any_thread=0
111numThreads=1
112p_state_clk_gate_bins=20
113p_state_clk_gate_max=2000000000
114p_state_clk_gate_min=2
115power_model=Null
116profile=0
117progress_interval=0
118simpoint_start_insts=
119simulate_data_stalls=false
120simulate_inst_stalls=false
121socket_id=0
122switched_out=false
123system=system
124tracer=system.cpu.tracer
125width=1
126workload=
127dcache_port=system.membus.slave[2]
128icache_port=system.membus.slave[1]
129
130[system.cpu.dtb]
131type=SparcTLB
132eventq_index=0
133size=64
134
135[system.cpu.interrupts]
136type=SparcInterrupts
137eventq_index=0
138
139[system.cpu.isa]
140type=SparcISA
141eventq_index=0
142
143[system.cpu.itb]
144type=SparcTLB
145eventq_index=0
146size=64
147
148[system.cpu.tracer]
149type=ExeTracer
150eventq_index=0
151
152[system.cpu_clk_domain]
153type=SrcClockDomain
154clock=2
155domain_id=-1
156eventq_index=0
157init_perf_level=0
158voltage_domain=system.voltage_domain
159
160[system.disk0]
161type=MmDisk
162children=image
163clk_domain=system.clk_domain
164default_p_state=UNDEFINED
165eventq_index=0
166image=system.disk0.image
167p_state_clk_gate_bins=20
168p_state_clk_gate_max=2000000000
169p_state_clk_gate_min=2
170pio_addr=134217728000
171pio_latency=200
172power_model=Null
173system=system
174pio=system.iobus.master[14]
175
176[system.disk0.image]
177type=CowDiskImage
178children=child
179child=system.disk0.image.child
180eventq_index=0
181image_file=
182read_only=false
183table_size=65536
184
185[system.disk0.image.child]
186type=RawDiskImage
187eventq_index=0
188image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2
189read_only=true
190
191[system.dvfs_handler]
192type=DVFSHandler
193domains=
194enable=false
195eventq_index=0
196sys_clk_domain=system.clk_domain
197transition_latency=200000
198
199[system.hypervisor_desc]
200type=SimpleMemory
201bandwidth=0.000000
202clk_domain=system.clk_domain
203conf_table_reported=true
204default_p_state=UNDEFINED
205eventq_index=0
206in_addr_map=true
| 75req_size=16
76resp_size=16
77master=system.iobus.slave[0]
78slave=system.membus.master[2]
79
80[system.clk_domain]
81type=SrcClockDomain
82clock=2
83domain_id=-1
84eventq_index=0
85init_perf_level=0
86voltage_domain=system.voltage_domain
87
88[system.cpu]
89type=AtomicSimpleCPU
90children=dtb interrupts isa itb tracer
91branchPred=Null
92checker=Null
93clk_domain=system.cpu_clk_domain
94cpu_id=0
95default_p_state=UNDEFINED
96do_checkpoint_insts=true
97do_quiesce=true
98do_statistics_insts=true
99dtb=system.cpu.dtb
100eventq_index=0
101fastmem=false
102function_trace=false
103function_trace_start=0
104interrupts=system.cpu.interrupts
105isa=system.cpu.isa
106itb=system.cpu.itb
107max_insts_all_threads=0
108max_insts_any_thread=0
109max_loads_all_threads=0
110max_loads_any_thread=0
111numThreads=1
112p_state_clk_gate_bins=20
113p_state_clk_gate_max=2000000000
114p_state_clk_gate_min=2
115power_model=Null
116profile=0
117progress_interval=0
118simpoint_start_insts=
119simulate_data_stalls=false
120simulate_inst_stalls=false
121socket_id=0
122switched_out=false
123system=system
124tracer=system.cpu.tracer
125width=1
126workload=
127dcache_port=system.membus.slave[2]
128icache_port=system.membus.slave[1]
129
130[system.cpu.dtb]
131type=SparcTLB
132eventq_index=0
133size=64
134
135[system.cpu.interrupts]
136type=SparcInterrupts
137eventq_index=0
138
139[system.cpu.isa]
140type=SparcISA
141eventq_index=0
142
143[system.cpu.itb]
144type=SparcTLB
145eventq_index=0
146size=64
147
148[system.cpu.tracer]
149type=ExeTracer
150eventq_index=0
151
152[system.cpu_clk_domain]
153type=SrcClockDomain
154clock=2
155domain_id=-1
156eventq_index=0
157init_perf_level=0
158voltage_domain=system.voltage_domain
159
160[system.disk0]
161type=MmDisk
162children=image
163clk_domain=system.clk_domain
164default_p_state=UNDEFINED
165eventq_index=0
166image=system.disk0.image
167p_state_clk_gate_bins=20
168p_state_clk_gate_max=2000000000
169p_state_clk_gate_min=2
170pio_addr=134217728000
171pio_latency=200
172power_model=Null
173system=system
174pio=system.iobus.master[14]
175
176[system.disk0.image]
177type=CowDiskImage
178children=child
179child=system.disk0.image.child
180eventq_index=0
181image_file=
182read_only=false
183table_size=65536
184
185[system.disk0.image.child]
186type=RawDiskImage
187eventq_index=0
188image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2
189read_only=true
190
191[system.dvfs_handler]
192type=DVFSHandler
193domains=
194enable=false
195eventq_index=0
196sys_clk_domain=system.clk_domain
197transition_latency=200000
198
199[system.hypervisor_desc]
200type=SimpleMemory
201bandwidth=0.000000
202clk_domain=system.clk_domain
203conf_table_reported=true
204default_p_state=UNDEFINED
205eventq_index=0
206in_addr_map=true
|
| 207kvm_map=true
|
207latency=60
208latency_var=0
209null=false
210p_state_clk_gate_bins=20
211p_state_clk_gate_max=2000000000
212p_state_clk_gate_min=2
213power_model=Null
| 208latency=60
209latency_var=0
210null=false
211p_state_clk_gate_bins=20
212p_state_clk_gate_max=2000000000
213p_state_clk_gate_min=2
214power_model=Null
|
214range=133446500352:133446508543
| 215range=133446500352:133446508543:0:0:0:0
|
215port=system.membus.master[5]
216
217[system.intrctrl]
218type=IntrControl
219eventq_index=0
220sys=system
221
222[system.iobus]
223type=NoncoherentXBar
224clk_domain=system.clk_domain
225default_p_state=UNDEFINED
226eventq_index=0
227forward_latency=1
228frontend_latency=2
229p_state_clk_gate_bins=20
230p_state_clk_gate_max=2000000000
231p_state_clk_gate_min=2
232power_model=Null
233response_latency=2
234use_default_range=false
235width=16
236master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
237slave=system.bridge.master
238
239[system.membus]
240type=CoherentXBar
241children=badaddr_responder snoop_filter
242clk_domain=system.clk_domain
243default_p_state=UNDEFINED
244eventq_index=0
245forward_latency=4
246frontend_latency=3
247p_state_clk_gate_bins=20
248p_state_clk_gate_max=2000000000
249p_state_clk_gate_min=2
250point_of_coherency=true
251power_model=Null
252response_latency=2
253snoop_filter=system.membus.snoop_filter
254snoop_response_latency=4
255system=system
256use_default_range=false
257width=16
258default=system.membus.badaddr_responder.pio
259master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port
260slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
261
262[system.membus.badaddr_responder]
263type=IsaFake
264clk_domain=system.clk_domain
265default_p_state=UNDEFINED
266eventq_index=0
267fake_mem=false
268p_state_clk_gate_bins=20
269p_state_clk_gate_max=2000000000
270p_state_clk_gate_min=2
271pio_addr=0
272pio_latency=200
273pio_size=8
274power_model=Null
275ret_bad_addr=true
276ret_data16=65535
277ret_data32=4294967295
278ret_data64=18446744073709551615
279ret_data8=255
280system=system
281update_data=false
282warn_access=
283pio=system.membus.default
284
285[system.membus.snoop_filter]
286type=SnoopFilter
287eventq_index=0
288lookup_latency=1
289max_capacity=8388608
290system=system
291
292[system.nvram]
293type=SimpleMemory
294bandwidth=0.000000
295clk_domain=system.clk_domain
296conf_table_reported=true
297default_p_state=UNDEFINED
298eventq_index=0
299in_addr_map=true
| 216port=system.membus.master[5]
217
218[system.intrctrl]
219type=IntrControl
220eventq_index=0
221sys=system
222
223[system.iobus]
224type=NoncoherentXBar
225clk_domain=system.clk_domain
226default_p_state=UNDEFINED
227eventq_index=0
228forward_latency=1
229frontend_latency=2
230p_state_clk_gate_bins=20
231p_state_clk_gate_max=2000000000
232p_state_clk_gate_min=2
233power_model=Null
234response_latency=2
235use_default_range=false
236width=16
237master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
238slave=system.bridge.master
239
240[system.membus]
241type=CoherentXBar
242children=badaddr_responder snoop_filter
243clk_domain=system.clk_domain
244default_p_state=UNDEFINED
245eventq_index=0
246forward_latency=4
247frontend_latency=3
248p_state_clk_gate_bins=20
249p_state_clk_gate_max=2000000000
250p_state_clk_gate_min=2
251point_of_coherency=true
252power_model=Null
253response_latency=2
254snoop_filter=system.membus.snoop_filter
255snoop_response_latency=4
256system=system
257use_default_range=false
258width=16
259default=system.membus.badaddr_responder.pio
260master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port
261slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
262
263[system.membus.badaddr_responder]
264type=IsaFake
265clk_domain=system.clk_domain
266default_p_state=UNDEFINED
267eventq_index=0
268fake_mem=false
269p_state_clk_gate_bins=20
270p_state_clk_gate_max=2000000000
271p_state_clk_gate_min=2
272pio_addr=0
273pio_latency=200
274pio_size=8
275power_model=Null
276ret_bad_addr=true
277ret_data16=65535
278ret_data32=4294967295
279ret_data64=18446744073709551615
280ret_data8=255
281system=system
282update_data=false
283warn_access=
284pio=system.membus.default
285
286[system.membus.snoop_filter]
287type=SnoopFilter
288eventq_index=0
289lookup_latency=1
290max_capacity=8388608
291system=system
292
293[system.nvram]
294type=SimpleMemory
295bandwidth=0.000000
296clk_domain=system.clk_domain
297conf_table_reported=true
298default_p_state=UNDEFINED
299eventq_index=0
300in_addr_map=true
|
| 301kvm_map=true
|
300latency=60
301latency_var=0
302null=false
303p_state_clk_gate_bins=20
304p_state_clk_gate_max=2000000000
305p_state_clk_gate_min=2
306power_model=Null
| 302latency=60
303latency_var=0
304null=false
305p_state_clk_gate_bins=20
306p_state_clk_gate_max=2000000000
307p_state_clk_gate_min=2
308power_model=Null
|
307range=133429198848:133429207039
| 309range=133429198848:133429207039:0:0:0:0
|
308port=system.membus.master[4]
309
310[system.partition_desc]
311type=SimpleMemory
312bandwidth=0.000000
313clk_domain=system.clk_domain
314conf_table_reported=true
315default_p_state=UNDEFINED
316eventq_index=0
317in_addr_map=true
| 310port=system.membus.master[4]
311
312[system.partition_desc]
313type=SimpleMemory
314bandwidth=0.000000
315clk_domain=system.clk_domain
316conf_table_reported=true
317default_p_state=UNDEFINED
318eventq_index=0
319in_addr_map=true
|
| 320kvm_map=true
|
318latency=60
319latency_var=0
320null=false
321p_state_clk_gate_bins=20
322p_state_clk_gate_max=2000000000
323p_state_clk_gate_min=2
324power_model=Null
| 321latency=60
322latency_var=0
323null=false
324p_state_clk_gate_bins=20
325p_state_clk_gate_max=2000000000
326p_state_clk_gate_min=2
327power_model=Null
|
325range=133445976064:133445984255
| 328range=133445976064:133445984255:0:0:0:0
|
326port=system.membus.master[6]
327
328[system.physmem0]
329type=SimpleMemory
330bandwidth=0.000000
331clk_domain=system.clk_domain
332conf_table_reported=true
333default_p_state=UNDEFINED
334eventq_index=0
335in_addr_map=true
| 329port=system.membus.master[6]
330
331[system.physmem0]
332type=SimpleMemory
333bandwidth=0.000000
334clk_domain=system.clk_domain
335conf_table_reported=true
336default_p_state=UNDEFINED
337eventq_index=0
338in_addr_map=true
|
| 339kvm_map=true
|
336latency=60
337latency_var=0
338null=false
339p_state_clk_gate_bins=20
340p_state_clk_gate_max=2000000000
341p_state_clk_gate_min=2
342power_model=Null
| 340latency=60
341latency_var=0
342null=false
343p_state_clk_gate_bins=20
344p_state_clk_gate_max=2000000000
345p_state_clk_gate_min=2
346power_model=Null
|
343range=1048576:68157439
| 347range=1048576:68157439:0:0:0:0
|
344port=system.membus.master[7]
345
346[system.physmem1]
347type=SimpleMemory
348bandwidth=0.000000
349clk_domain=system.clk_domain
350conf_table_reported=true
351default_p_state=UNDEFINED
352eventq_index=0
353in_addr_map=true
| 348port=system.membus.master[7]
349
350[system.physmem1]
351type=SimpleMemory
352bandwidth=0.000000
353clk_domain=system.clk_domain
354conf_table_reported=true
355default_p_state=UNDEFINED
356eventq_index=0
357in_addr_map=true
|
| 358kvm_map=true
|
354latency=60
355latency_var=0
356null=false
357p_state_clk_gate_bins=20
358p_state_clk_gate_max=2000000000
359p_state_clk_gate_min=2
360power_model=Null
| 359latency=60
360latency_var=0
361null=false
362p_state_clk_gate_bins=20
363p_state_clk_gate_max=2000000000
364p_state_clk_gate_min=2
365power_model=Null
|
361range=2147483648:2415919103
| 366range=2147483648:2415919103:0:0:0:0
|
362port=system.membus.master[8]
363
364[system.rom]
365type=SimpleMemory
366bandwidth=0.000000
367clk_domain=system.clk_domain
368conf_table_reported=true
369default_p_state=UNDEFINED
370eventq_index=0
371in_addr_map=true
| 367port=system.membus.master[8]
368
369[system.rom]
370type=SimpleMemory
371bandwidth=0.000000
372clk_domain=system.clk_domain
373conf_table_reported=true
374default_p_state=UNDEFINED
375eventq_index=0
376in_addr_map=true
|
| 377kvm_map=true
|
372latency=60
373latency_var=0
374null=false
375p_state_clk_gate_bins=20
376p_state_clk_gate_max=2000000000
377p_state_clk_gate_min=2
378power_model=Null
| 378latency=60
379latency_var=0
380null=false
381p_state_clk_gate_bins=20
382p_state_clk_gate_max=2000000000
383p_state_clk_gate_min=2
384power_model=Null
|
379range=1099243192320:1099251580927
| 385range=1099243192320:1099251580927:0:0:0:0
|
380port=system.membus.master[3]
381
382[system.t1000]
383type=T1000
384children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
385eventq_index=0
386intrctrl=system.intrctrl
387system=system
388
389[system.t1000.fake_clk]
390type=IsaFake
391clk_domain=system.clk_domain
392default_p_state=UNDEFINED
393eventq_index=0
394fake_mem=false
395p_state_clk_gate_bins=20
396p_state_clk_gate_max=2000000000
397p_state_clk_gate_min=2
398pio_addr=644245094400
399pio_latency=200
400pio_size=4294967296
401power_model=Null
402ret_bad_addr=false
403ret_data16=65535
404ret_data32=4294967295
405ret_data64=18446744073709551615
406ret_data8=255
407system=system
408update_data=false
409warn_access=
410pio=system.iobus.master[0]
411
412[system.t1000.fake_jbi]
413type=IsaFake
414clk_domain=system.clk_domain
415default_p_state=UNDEFINED
416eventq_index=0
417fake_mem=false
418p_state_clk_gate_bins=20
419p_state_clk_gate_max=2000000000
420p_state_clk_gate_min=2
421pio_addr=549755813888
422pio_latency=200
423pio_size=4294967296
424power_model=Null
425ret_bad_addr=false
426ret_data16=65535
427ret_data32=4294967295
428ret_data64=18446744073709551615
429ret_data8=255
430system=system
431update_data=false
432warn_access=
433pio=system.iobus.master[11]
434
435[system.t1000.fake_l2_1]
436type=IsaFake
437clk_domain=system.clk_domain
438default_p_state=UNDEFINED
439eventq_index=0
440fake_mem=false
441p_state_clk_gate_bins=20
442p_state_clk_gate_max=2000000000
443p_state_clk_gate_min=2
444pio_addr=725849473024
445pio_latency=200
446pio_size=8
447power_model=Null
448ret_bad_addr=false
449ret_data16=65535
450ret_data32=4294967295
451ret_data64=1
452ret_data8=255
453system=system
454update_data=true
455warn_access=
456pio=system.iobus.master[2]
457
458[system.t1000.fake_l2_2]
459type=IsaFake
460clk_domain=system.clk_domain
461default_p_state=UNDEFINED
462eventq_index=0
463fake_mem=false
464p_state_clk_gate_bins=20
465p_state_clk_gate_max=2000000000
466p_state_clk_gate_min=2
467pio_addr=725849473088
468pio_latency=200
469pio_size=8
470power_model=Null
471ret_bad_addr=false
472ret_data16=65535
473ret_data32=4294967295
474ret_data64=1
475ret_data8=255
476system=system
477update_data=true
478warn_access=
479pio=system.iobus.master[3]
480
481[system.t1000.fake_l2_3]
482type=IsaFake
483clk_domain=system.clk_domain
484default_p_state=UNDEFINED
485eventq_index=0
486fake_mem=false
487p_state_clk_gate_bins=20
488p_state_clk_gate_max=2000000000
489p_state_clk_gate_min=2
490pio_addr=725849473152
491pio_latency=200
492pio_size=8
493power_model=Null
494ret_bad_addr=false
495ret_data16=65535
496ret_data32=4294967295
497ret_data64=1
498ret_data8=255
499system=system
500update_data=true
501warn_access=
502pio=system.iobus.master[4]
503
504[system.t1000.fake_l2_4]
505type=IsaFake
506clk_domain=system.clk_domain
507default_p_state=UNDEFINED
508eventq_index=0
509fake_mem=false
510p_state_clk_gate_bins=20
511p_state_clk_gate_max=2000000000
512p_state_clk_gate_min=2
513pio_addr=725849473216
514pio_latency=200
515pio_size=8
516power_model=Null
517ret_bad_addr=false
518ret_data16=65535
519ret_data32=4294967295
520ret_data64=1
521ret_data8=255
522system=system
523update_data=true
524warn_access=
525pio=system.iobus.master[5]
526
527[system.t1000.fake_l2esr_1]
528type=IsaFake
529clk_domain=system.clk_domain
530default_p_state=UNDEFINED
531eventq_index=0
532fake_mem=false
533p_state_clk_gate_bins=20
534p_state_clk_gate_max=2000000000
535p_state_clk_gate_min=2
536pio_addr=734439407616
537pio_latency=200
538pio_size=8
539power_model=Null
540ret_bad_addr=false
541ret_data16=65535
542ret_data32=4294967295
543ret_data64=0
544ret_data8=255
545system=system
546update_data=true
547warn_access=
548pio=system.iobus.master[6]
549
550[system.t1000.fake_l2esr_2]
551type=IsaFake
552clk_domain=system.clk_domain
553default_p_state=UNDEFINED
554eventq_index=0
555fake_mem=false
556p_state_clk_gate_bins=20
557p_state_clk_gate_max=2000000000
558p_state_clk_gate_min=2
559pio_addr=734439407680
560pio_latency=200
561pio_size=8
562power_model=Null
563ret_bad_addr=false
564ret_data16=65535
565ret_data32=4294967295
566ret_data64=0
567ret_data8=255
568system=system
569update_data=true
570warn_access=
571pio=system.iobus.master[7]
572
573[system.t1000.fake_l2esr_3]
574type=IsaFake
575clk_domain=system.clk_domain
576default_p_state=UNDEFINED
577eventq_index=0
578fake_mem=false
579p_state_clk_gate_bins=20
580p_state_clk_gate_max=2000000000
581p_state_clk_gate_min=2
582pio_addr=734439407744
583pio_latency=200
584pio_size=8
585power_model=Null
586ret_bad_addr=false
587ret_data16=65535
588ret_data32=4294967295
589ret_data64=0
590ret_data8=255
591system=system
592update_data=true
593warn_access=
594pio=system.iobus.master[8]
595
596[system.t1000.fake_l2esr_4]
597type=IsaFake
598clk_domain=system.clk_domain
599default_p_state=UNDEFINED
600eventq_index=0
601fake_mem=false
602p_state_clk_gate_bins=20
603p_state_clk_gate_max=2000000000
604p_state_clk_gate_min=2
605pio_addr=734439407808
606pio_latency=200
607pio_size=8
608power_model=Null
609ret_bad_addr=false
610ret_data16=65535
611ret_data32=4294967295
612ret_data64=0
613ret_data8=255
614system=system
615update_data=true
616warn_access=
617pio=system.iobus.master[9]
618
619[system.t1000.fake_membnks]
620type=IsaFake
621clk_domain=system.clk_domain
622default_p_state=UNDEFINED
623eventq_index=0
624fake_mem=false
625p_state_clk_gate_bins=20
626p_state_clk_gate_max=2000000000
627p_state_clk_gate_min=2
628pio_addr=648540061696
629pio_latency=200
630pio_size=16384
631power_model=Null
632ret_bad_addr=false
633ret_data16=65535
634ret_data32=4294967295
635ret_data64=0
636ret_data8=255
637system=system
638update_data=false
639warn_access=
640pio=system.iobus.master[1]
641
642[system.t1000.fake_ssi]
643type=IsaFake
644clk_domain=system.clk_domain
645default_p_state=UNDEFINED
646eventq_index=0
647fake_mem=false
648p_state_clk_gate_bins=20
649p_state_clk_gate_max=2000000000
650p_state_clk_gate_min=2
651pio_addr=1095216660480
652pio_latency=200
653pio_size=268435456
654power_model=Null
655ret_bad_addr=false
656ret_data16=65535
657ret_data32=4294967295
658ret_data64=18446744073709551615
659ret_data8=255
660system=system
661update_data=false
662warn_access=
663pio=system.iobus.master[10]
664
665[system.t1000.hterm]
666type=Terminal
667eventq_index=0
668intr_control=system.intrctrl
669number=0
670output=true
671port=3456
672
673[system.t1000.htod]
674type=DumbTOD
675clk_domain=system.clk_domain
676default_p_state=UNDEFINED
677eventq_index=0
678p_state_clk_gate_bins=20
679p_state_clk_gate_max=2000000000
680p_state_clk_gate_min=2
681pio_addr=1099255906296
682pio_latency=200
683power_model=Null
684system=system
685time=Thu Jan 1 00:00:00 2009
686pio=system.membus.master[1]
687
688[system.t1000.hvuart]
689type=Uart8250
690clk_domain=system.clk_domain
691default_p_state=UNDEFINED
692eventq_index=0
693p_state_clk_gate_bins=20
694p_state_clk_gate_max=2000000000
695p_state_clk_gate_min=2
696pio_addr=1099255955456
697pio_latency=200
698platform=system.t1000
699power_model=Null
700system=system
701terminal=system.t1000.hterm
702pio=system.iobus.master[13]
703
704[system.t1000.iob]
705type=Iob
706clk_domain=system.clk_domain
707default_p_state=UNDEFINED
708eventq_index=0
709p_state_clk_gate_bins=20
710p_state_clk_gate_max=2000000000
711p_state_clk_gate_min=2
712pio_latency=2
713platform=system.t1000
714power_model=Null
715system=system
716pio=system.membus.master[0]
717
718[system.t1000.pterm]
719type=Terminal
720eventq_index=0
721intr_control=system.intrctrl
722number=0
723output=true
724port=3456
725
726[system.t1000.puart0]
727type=Uart8250
728clk_domain=system.clk_domain
729default_p_state=UNDEFINED
730eventq_index=0
731p_state_clk_gate_bins=20
732p_state_clk_gate_max=2000000000
733p_state_clk_gate_min=2
734pio_addr=133412421632
735pio_latency=200
736platform=system.t1000
737power_model=Null
738system=system
739terminal=system.t1000.pterm
740pio=system.iobus.master[12]
741
742[system.voltage_domain]
743type=VoltageDomain
744eventq_index=0
745voltage=1.000000
746
| 386port=system.membus.master[3]
387
388[system.t1000]
389type=T1000
390children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
391eventq_index=0
392intrctrl=system.intrctrl
393system=system
394
395[system.t1000.fake_clk]
396type=IsaFake
397clk_domain=system.clk_domain
398default_p_state=UNDEFINED
399eventq_index=0
400fake_mem=false
401p_state_clk_gate_bins=20
402p_state_clk_gate_max=2000000000
403p_state_clk_gate_min=2
404pio_addr=644245094400
405pio_latency=200
406pio_size=4294967296
407power_model=Null
408ret_bad_addr=false
409ret_data16=65535
410ret_data32=4294967295
411ret_data64=18446744073709551615
412ret_data8=255
413system=system
414update_data=false
415warn_access=
416pio=system.iobus.master[0]
417
418[system.t1000.fake_jbi]
419type=IsaFake
420clk_domain=system.clk_domain
421default_p_state=UNDEFINED
422eventq_index=0
423fake_mem=false
424p_state_clk_gate_bins=20
425p_state_clk_gate_max=2000000000
426p_state_clk_gate_min=2
427pio_addr=549755813888
428pio_latency=200
429pio_size=4294967296
430power_model=Null
431ret_bad_addr=false
432ret_data16=65535
433ret_data32=4294967295
434ret_data64=18446744073709551615
435ret_data8=255
436system=system
437update_data=false
438warn_access=
439pio=system.iobus.master[11]
440
441[system.t1000.fake_l2_1]
442type=IsaFake
443clk_domain=system.clk_domain
444default_p_state=UNDEFINED
445eventq_index=0
446fake_mem=false
447p_state_clk_gate_bins=20
448p_state_clk_gate_max=2000000000
449p_state_clk_gate_min=2
450pio_addr=725849473024
451pio_latency=200
452pio_size=8
453power_model=Null
454ret_bad_addr=false
455ret_data16=65535
456ret_data32=4294967295
457ret_data64=1
458ret_data8=255
459system=system
460update_data=true
461warn_access=
462pio=system.iobus.master[2]
463
464[system.t1000.fake_l2_2]
465type=IsaFake
466clk_domain=system.clk_domain
467default_p_state=UNDEFINED
468eventq_index=0
469fake_mem=false
470p_state_clk_gate_bins=20
471p_state_clk_gate_max=2000000000
472p_state_clk_gate_min=2
473pio_addr=725849473088
474pio_latency=200
475pio_size=8
476power_model=Null
477ret_bad_addr=false
478ret_data16=65535
479ret_data32=4294967295
480ret_data64=1
481ret_data8=255
482system=system
483update_data=true
484warn_access=
485pio=system.iobus.master[3]
486
487[system.t1000.fake_l2_3]
488type=IsaFake
489clk_domain=system.clk_domain
490default_p_state=UNDEFINED
491eventq_index=0
492fake_mem=false
493p_state_clk_gate_bins=20
494p_state_clk_gate_max=2000000000
495p_state_clk_gate_min=2
496pio_addr=725849473152
497pio_latency=200
498pio_size=8
499power_model=Null
500ret_bad_addr=false
501ret_data16=65535
502ret_data32=4294967295
503ret_data64=1
504ret_data8=255
505system=system
506update_data=true
507warn_access=
508pio=system.iobus.master[4]
509
510[system.t1000.fake_l2_4]
511type=IsaFake
512clk_domain=system.clk_domain
513default_p_state=UNDEFINED
514eventq_index=0
515fake_mem=false
516p_state_clk_gate_bins=20
517p_state_clk_gate_max=2000000000
518p_state_clk_gate_min=2
519pio_addr=725849473216
520pio_latency=200
521pio_size=8
522power_model=Null
523ret_bad_addr=false
524ret_data16=65535
525ret_data32=4294967295
526ret_data64=1
527ret_data8=255
528system=system
529update_data=true
530warn_access=
531pio=system.iobus.master[5]
532
533[system.t1000.fake_l2esr_1]
534type=IsaFake
535clk_domain=system.clk_domain
536default_p_state=UNDEFINED
537eventq_index=0
538fake_mem=false
539p_state_clk_gate_bins=20
540p_state_clk_gate_max=2000000000
541p_state_clk_gate_min=2
542pio_addr=734439407616
543pio_latency=200
544pio_size=8
545power_model=Null
546ret_bad_addr=false
547ret_data16=65535
548ret_data32=4294967295
549ret_data64=0
550ret_data8=255
551system=system
552update_data=true
553warn_access=
554pio=system.iobus.master[6]
555
556[system.t1000.fake_l2esr_2]
557type=IsaFake
558clk_domain=system.clk_domain
559default_p_state=UNDEFINED
560eventq_index=0
561fake_mem=false
562p_state_clk_gate_bins=20
563p_state_clk_gate_max=2000000000
564p_state_clk_gate_min=2
565pio_addr=734439407680
566pio_latency=200
567pio_size=8
568power_model=Null
569ret_bad_addr=false
570ret_data16=65535
571ret_data32=4294967295
572ret_data64=0
573ret_data8=255
574system=system
575update_data=true
576warn_access=
577pio=system.iobus.master[7]
578
579[system.t1000.fake_l2esr_3]
580type=IsaFake
581clk_domain=system.clk_domain
582default_p_state=UNDEFINED
583eventq_index=0
584fake_mem=false
585p_state_clk_gate_bins=20
586p_state_clk_gate_max=2000000000
587p_state_clk_gate_min=2
588pio_addr=734439407744
589pio_latency=200
590pio_size=8
591power_model=Null
592ret_bad_addr=false
593ret_data16=65535
594ret_data32=4294967295
595ret_data64=0
596ret_data8=255
597system=system
598update_data=true
599warn_access=
600pio=system.iobus.master[8]
601
602[system.t1000.fake_l2esr_4]
603type=IsaFake
604clk_domain=system.clk_domain
605default_p_state=UNDEFINED
606eventq_index=0
607fake_mem=false
608p_state_clk_gate_bins=20
609p_state_clk_gate_max=2000000000
610p_state_clk_gate_min=2
611pio_addr=734439407808
612pio_latency=200
613pio_size=8
614power_model=Null
615ret_bad_addr=false
616ret_data16=65535
617ret_data32=4294967295
618ret_data64=0
619ret_data8=255
620system=system
621update_data=true
622warn_access=
623pio=system.iobus.master[9]
624
625[system.t1000.fake_membnks]
626type=IsaFake
627clk_domain=system.clk_domain
628default_p_state=UNDEFINED
629eventq_index=0
630fake_mem=false
631p_state_clk_gate_bins=20
632p_state_clk_gate_max=2000000000
633p_state_clk_gate_min=2
634pio_addr=648540061696
635pio_latency=200
636pio_size=16384
637power_model=Null
638ret_bad_addr=false
639ret_data16=65535
640ret_data32=4294967295
641ret_data64=0
642ret_data8=255
643system=system
644update_data=false
645warn_access=
646pio=system.iobus.master[1]
647
648[system.t1000.fake_ssi]
649type=IsaFake
650clk_domain=system.clk_domain
651default_p_state=UNDEFINED
652eventq_index=0
653fake_mem=false
654p_state_clk_gate_bins=20
655p_state_clk_gate_max=2000000000
656p_state_clk_gate_min=2
657pio_addr=1095216660480
658pio_latency=200
659pio_size=268435456
660power_model=Null
661ret_bad_addr=false
662ret_data16=65535
663ret_data32=4294967295
664ret_data64=18446744073709551615
665ret_data8=255
666system=system
667update_data=false
668warn_access=
669pio=system.iobus.master[10]
670
671[system.t1000.hterm]
672type=Terminal
673eventq_index=0
674intr_control=system.intrctrl
675number=0
676output=true
677port=3456
678
679[system.t1000.htod]
680type=DumbTOD
681clk_domain=system.clk_domain
682default_p_state=UNDEFINED
683eventq_index=0
684p_state_clk_gate_bins=20
685p_state_clk_gate_max=2000000000
686p_state_clk_gate_min=2
687pio_addr=1099255906296
688pio_latency=200
689power_model=Null
690system=system
691time=Thu Jan 1 00:00:00 2009
692pio=system.membus.master[1]
693
694[system.t1000.hvuart]
695type=Uart8250
696clk_domain=system.clk_domain
697default_p_state=UNDEFINED
698eventq_index=0
699p_state_clk_gate_bins=20
700p_state_clk_gate_max=2000000000
701p_state_clk_gate_min=2
702pio_addr=1099255955456
703pio_latency=200
704platform=system.t1000
705power_model=Null
706system=system
707terminal=system.t1000.hterm
708pio=system.iobus.master[13]
709
710[system.t1000.iob]
711type=Iob
712clk_domain=system.clk_domain
713default_p_state=UNDEFINED
714eventq_index=0
715p_state_clk_gate_bins=20
716p_state_clk_gate_max=2000000000
717p_state_clk_gate_min=2
718pio_latency=2
719platform=system.t1000
720power_model=Null
721system=system
722pio=system.membus.master[0]
723
724[system.t1000.pterm]
725type=Terminal
726eventq_index=0
727intr_control=system.intrctrl
728number=0
729output=true
730port=3456
731
732[system.t1000.puart0]
733type=Uart8250
734clk_domain=system.clk_domain
735default_p_state=UNDEFINED
736eventq_index=0
737p_state_clk_gate_bins=20
738p_state_clk_gate_max=2000000000
739p_state_clk_gate_min=2
740pio_addr=133412421632
741pio_latency=200
742platform=system.t1000
743power_model=Null
744system=system
745terminal=system.t1000.pterm
746pio=system.iobus.master[12]
747
748[system.voltage_domain]
749type=VoltageDomain
750eventq_index=0
751voltage=1.000000
752
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