1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=200000000
--- 14 unchanged lines hidden (view full) ---
23hypervisor_desc_addr=133446500352
24hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin
25init_param=0
26kernel=
27kernel_addr_check=true
28load_addr_mask=1099511627775
29load_offset=0
30mem_mode=atomic
31mem_ranges=1048576:68157439 2147483648:2415919103
32memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom
33mmap_using_noreserve=false
34multi_thread=false
35num_work_ids=16
36nvram=system.nvram
37nvram_addr=133429198848
38nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1
39openboot_addr=1099243716608
--- 26 unchanged lines hidden (view full) ---
66clk_domain=system.clk_domain
67default_p_state=UNDEFINED
68delay=100
69eventq_index=0
70p_state_clk_gate_bins=20
71p_state_clk_gate_max=2000000000
72p_state_clk_gate_min=2
73power_model=Null
74ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
75req_size=16
76resp_size=16
77master=system.iobus.slave[0]
78slave=system.membus.master[2]
79
80[system.clk_domain]
81type=SrcClockDomain
82clock=2
--- 116 unchanged lines hidden (view full) ---
199[system.hypervisor_desc]
200type=SimpleMemory
201bandwidth=0.000000
202clk_domain=system.clk_domain
203conf_table_reported=true
204default_p_state=UNDEFINED
205eventq_index=0
206in_addr_map=true
207latency=60
208latency_var=0
209null=false
210p_state_clk_gate_bins=20
211p_state_clk_gate_max=2000000000
212p_state_clk_gate_min=2
213power_model=Null
214range=133446500352:133446508543
215port=system.membus.master[5]
216
217[system.intrctrl]
218type=IntrControl
219eventq_index=0
220sys=system
221
222[system.iobus]
--- 69 unchanged lines hidden (view full) ---
292[system.nvram]
293type=SimpleMemory
294bandwidth=0.000000
295clk_domain=system.clk_domain
296conf_table_reported=true
297default_p_state=UNDEFINED
298eventq_index=0
299in_addr_map=true
300latency=60
301latency_var=0
302null=false
303p_state_clk_gate_bins=20
304p_state_clk_gate_max=2000000000
305p_state_clk_gate_min=2
306power_model=Null
307range=133429198848:133429207039
308port=system.membus.master[4]
309
310[system.partition_desc]
311type=SimpleMemory
312bandwidth=0.000000
313clk_domain=system.clk_domain
314conf_table_reported=true
315default_p_state=UNDEFINED
316eventq_index=0
317in_addr_map=true
318latency=60
319latency_var=0
320null=false
321p_state_clk_gate_bins=20
322p_state_clk_gate_max=2000000000
323p_state_clk_gate_min=2
324power_model=Null
325range=133445976064:133445984255
326port=system.membus.master[6]
327
328[system.physmem0]
329type=SimpleMemory
330bandwidth=0.000000
331clk_domain=system.clk_domain
332conf_table_reported=true
333default_p_state=UNDEFINED
334eventq_index=0
335in_addr_map=true
336latency=60
337latency_var=0
338null=false
339p_state_clk_gate_bins=20
340p_state_clk_gate_max=2000000000
341p_state_clk_gate_min=2
342power_model=Null
343range=1048576:68157439
344port=system.membus.master[7]
345
346[system.physmem1]
347type=SimpleMemory
348bandwidth=0.000000
349clk_domain=system.clk_domain
350conf_table_reported=true
351default_p_state=UNDEFINED
352eventq_index=0
353in_addr_map=true
354latency=60
355latency_var=0
356null=false
357p_state_clk_gate_bins=20
358p_state_clk_gate_max=2000000000
359p_state_clk_gate_min=2
360power_model=Null
361range=2147483648:2415919103
362port=system.membus.master[8]
363
364[system.rom]
365type=SimpleMemory
366bandwidth=0.000000
367clk_domain=system.clk_domain
368conf_table_reported=true
369default_p_state=UNDEFINED
370eventq_index=0
371in_addr_map=true
372latency=60
373latency_var=0
374null=false
375p_state_clk_gate_bins=20
376p_state_clk_gate_max=2000000000
377p_state_clk_gate_min=2
378power_model=Null
379range=1099243192320:1099251580927
380port=system.membus.master[3]
381
382[system.t1000]
383type=T1000
384children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
385eventq_index=0
386intrctrl=system.intrctrl
387system=system
--- 359 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=200000000
--- 14 unchanged lines hidden (view full) ---
23hypervisor_desc_addr=133446500352
24hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin
25init_param=0
26kernel=
27kernel_addr_check=true
28load_addr_mask=1099511627775
29load_offset=0
30mem_mode=atomic
31mem_ranges=1048576:68157439 2147483648:2415919103
32memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom
33mmap_using_noreserve=false
34multi_thread=false
35num_work_ids=16
36nvram=system.nvram
37nvram_addr=133429198848
38nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1
39openboot_addr=1099243716608
--- 26 unchanged lines hidden (view full) ---
66clk_domain=system.clk_domain
67default_p_state=UNDEFINED
68delay=100
69eventq_index=0
70p_state_clk_gate_bins=20
71p_state_clk_gate_max=2000000000
72p_state_clk_gate_min=2
73power_model=Null
74ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
75req_size=16
76resp_size=16
77master=system.iobus.slave[0]
78slave=system.membus.master[2]
79
80[system.clk_domain]
81type=SrcClockDomain
82clock=2
--- 116 unchanged lines hidden (view full) ---
199[system.hypervisor_desc]
200type=SimpleMemory
201bandwidth=0.000000
202clk_domain=system.clk_domain
203conf_table_reported=true
204default_p_state=UNDEFINED
205eventq_index=0
206in_addr_map=true
207latency=60
208latency_var=0
209null=false
210p_state_clk_gate_bins=20
211p_state_clk_gate_max=2000000000
212p_state_clk_gate_min=2
213power_model=Null
214range=133446500352:133446508543
215port=system.membus.master[5]
216
217[system.intrctrl]
218type=IntrControl
219eventq_index=0
220sys=system
221
222[system.iobus]
--- 69 unchanged lines hidden (view full) ---
292[system.nvram]
293type=SimpleMemory
294bandwidth=0.000000
295clk_domain=system.clk_domain
296conf_table_reported=true
297default_p_state=UNDEFINED
298eventq_index=0
299in_addr_map=true
300latency=60
301latency_var=0
302null=false
303p_state_clk_gate_bins=20
304p_state_clk_gate_max=2000000000
305p_state_clk_gate_min=2
306power_model=Null
307range=133429198848:133429207039
308port=system.membus.master[4]
309
310[system.partition_desc]
311type=SimpleMemory
312bandwidth=0.000000
313clk_domain=system.clk_domain
314conf_table_reported=true
315default_p_state=UNDEFINED
316eventq_index=0
317in_addr_map=true
318latency=60
319latency_var=0
320null=false
321p_state_clk_gate_bins=20
322p_state_clk_gate_max=2000000000
323p_state_clk_gate_min=2
324power_model=Null
325range=133445976064:133445984255
326port=system.membus.master[6]
327
328[system.physmem0]
329type=SimpleMemory
330bandwidth=0.000000
331clk_domain=system.clk_domain
332conf_table_reported=true
333default_p_state=UNDEFINED
334eventq_index=0
335in_addr_map=true
336latency=60
337latency_var=0
338null=false
339p_state_clk_gate_bins=20
340p_state_clk_gate_max=2000000000
341p_state_clk_gate_min=2
342power_model=Null
343range=1048576:68157439
344port=system.membus.master[7]
345
346[system.physmem1]
347type=SimpleMemory
348bandwidth=0.000000
349clk_domain=system.clk_domain
350conf_table_reported=true
351default_p_state=UNDEFINED
352eventq_index=0
353in_addr_map=true
354latency=60
355latency_var=0
356null=false
357p_state_clk_gate_bins=20
358p_state_clk_gate_max=2000000000
359p_state_clk_gate_min=2
360power_model=Null
361range=2147483648:2415919103
362port=system.membus.master[8]
363
364[system.rom]
365type=SimpleMemory
366bandwidth=0.000000
367clk_domain=system.clk_domain
368conf_table_reported=true
369default_p_state=UNDEFINED
370eventq_index=0
371in_addr_map=true
372latency=60
373latency_var=0
374null=false
375p_state_clk_gate_bins=20
376p_state_clk_gate_max=2000000000
377p_state_clk_gate_min=2
378power_model=Null
379range=1099243192320:1099251580927
380port=system.membus.master[3]
381
382[system.t1000]
383type=T1000
384children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
385eventq_index=0
386intrctrl=system.intrctrl
387system=system
--- 359 unchanged lines hidden ---