| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660653 # Number of seconds simulated 4sim_ticks 51660652947000 # Number of ticks simulated 5final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660653 # Number of seconds simulated 4sim_ticks 51660652947000 # Number of ticks simulated 5final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 288085 # Simulator instruction rate (inst/s) 8host_op_rate 338513 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16013200726 # Simulator tick rate (ticks/s) 10host_mem_usage 724944 # Number of bytes of host memory used 11host_seconds 3226.13 # Real time elapsed on the host | 7host_inst_rate 170651 # Simulator instruction rate (inst/s) 8host_op_rate 200523 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9485631865 # Simulator tick rate (ticks/s) 10host_mem_usage 683504 # Number of bytes of host memory used 11host_seconds 5446.20 # Real time elapsed on the host |
| 12sim_insts 929398934 # Number of instructions simulated 13sim_ops 1092086880 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory --- 413 unchanged lines hidden (view full) --- 433system.cpu.dtb.read_hits 179568747 # DTB read hits 434system.cpu.dtb.read_misses 462708 # DTB read misses 435system.cpu.dtb.write_hits 159223685 # DTB write hits 436system.cpu.dtb.write_misses 98870 # DTB write misses 437system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 438system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 439system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 440system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID | 12sim_insts 929398934 # Number of instructions simulated 13sim_ops 1092086880 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory --- 413 unchanged lines hidden (view full) --- 433system.cpu.dtb.read_hits 179568747 # DTB read hits 434system.cpu.dtb.read_misses 462708 # DTB read misses 435system.cpu.dtb.write_hits 159223685 # DTB write hits 436system.cpu.dtb.write_misses 98870 # DTB write misses 437system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 438system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 439system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 440system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID |
| 441system.cpu.dtb.flush_entries 78994 # Number of entries that have been flushed from TLB | 441system.cpu.dtb.flush_entries 78930 # Number of entries that have been flushed from TLB |
| 442system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions 443system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch 444system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 445system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions 446system.cpu.dtb.read_accesses 180031455 # DTB read accesses 447system.cpu.dtb.write_accesses 159322555 # DTB write accesses 448system.cpu.dtb.inst_accesses 0 # ITB inst accesses 449system.cpu.dtb.hits 338792432 # DTB hits --- 69 unchanged lines hidden (view full) --- 519system.cpu.itb.read_hits 0 # DTB read hits 520system.cpu.itb.read_misses 0 # DTB read misses 521system.cpu.itb.write_hits 0 # DTB write hits 522system.cpu.itb.write_misses 0 # DTB write misses 523system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 524system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 525system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 526system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID | 442system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions 443system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch 444system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 445system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions 446system.cpu.dtb.read_accesses 180031455 # DTB read accesses 447system.cpu.dtb.write_accesses 159322555 # DTB write accesses 448system.cpu.dtb.inst_accesses 0 # ITB inst accesses 449system.cpu.dtb.hits 338792432 # DTB hits --- 69 unchanged lines hidden (view full) --- 519system.cpu.itb.read_hits 0 # DTB read hits 520system.cpu.itb.read_misses 0 # DTB read misses 521system.cpu.itb.write_hits 0 # DTB write hits 522system.cpu.itb.write_misses 0 # DTB write misses 523system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 524system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 525system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 526system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID |
| 527system.cpu.itb.flush_entries 56590 # Number of entries that have been flushed from TLB | 527system.cpu.itb.flush_entries 56526 # Number of entries that have been flushed from TLB |
| 528system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 529system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 530system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 531system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions 532system.cpu.itb.read_accesses 0 # DTB read accesses 533system.cpu.itb.write_accesses 0 # DTB write accesses 534system.cpu.itb.inst_accesses 442926878 # ITB inst accesses 535system.cpu.itb.hits 442793055 # DTB hits --- 1122 unchanged lines hidden --- | 528system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 529system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 530system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 531system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions 532system.cpu.itb.read_accesses 0 # DTB read accesses 533system.cpu.itb.write_accesses 0 # DTB write accesses 534system.cpu.itb.inst_accesses 442926878 # ITB inst accesses 535system.cpu.itb.hits 442793055 # DTB hits --- 1122 unchanged lines hidden --- |