| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660653 # Number of seconds simulated 4sim_ticks 51660652947000 # Number of ticks simulated 5final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660653 # Number of seconds simulated 4sim_ticks 51660652947000 # Number of ticks simulated 5final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 260799 # Simulator instruction rate (inst/s) 8host_op_rate 306450 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14496494193 # Simulator tick rate (ticks/s) 10host_mem_usage 677256 # Number of bytes of host memory used 11host_seconds 3563.67 # Real time elapsed on the host | 7host_inst_rate 288085 # Simulator instruction rate (inst/s) 8host_op_rate 338513 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16013200726 # Simulator tick rate (ticks/s) 10host_mem_usage 724944 # Number of bytes of host memory used 11host_seconds 3226.13 # Real time elapsed on the host |
| 12sim_insts 929398934 # Number of instructions simulated 13sim_ops 1092086880 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 929398934 # Number of instructions simulated 13sim_ops 1092086880 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 394752 # Number of bytes read from this memory 21system.physmem.bytes_read::total 73038088 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 10229888 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 10229888 # Number of instructions bytes read from this memory --- 291 unchanged lines hidden (view full) --- 315system.physmem_1.preBackEnergy 29841159946500 # Energy for precharge background per rank (pJ) 316system.physmem_1.totalEnergy 34545265265805 # Total energy per rank (pJ) 317system.physmem_1.averagePower 668.695937 # Core power per rank (mW) 318system.physmem_1.memoryStateTime::IDLE 49642646529009 # Time in different power states 319system.physmem_1.memoryStateTime::REF 1725062560000 # Time in different power states 320system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 321system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states 322system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 394752 # Number of bytes read from this memory 22system.physmem.bytes_read::total 73038088 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 10229888 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 10229888 # Number of instructions bytes read from this memory --- 291 unchanged lines hidden (view full) --- 316system.physmem_1.preBackEnergy 29841159946500 # Energy for precharge background per rank (pJ) 317system.physmem_1.totalEnergy 34545265265805 # Total energy per rank (pJ) 318system.physmem_1.averagePower 668.695937 # Core power per rank (mW) 319system.physmem_1.memoryStateTime::IDLE 49642646529009 # Time in different power states 320system.physmem_1.memoryStateTime::REF 1725062560000 # Time in different power states 321system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 322system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states 323system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 324system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 323system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 326system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 327system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 328system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 329system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 330system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 331system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 332system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 337system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 338system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) | 325system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 330system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 332system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 333system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 340system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) |
| 341system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 342system.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 343system.bridge.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 339system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 340system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 341system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 342system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 343system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 344system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 345system.cpu.branchPred.lookups 256209592 # Number of BP lookups 346system.cpu.branchPred.condPredicted 178352168 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 351system.cpu.branchPred.BTBHitPct 67.398456 # BTB Hit Percentage 352system.cpu.branchPred.usedRAS 31319231 # Number of times the RAS was used to get a target. 353system.cpu.branchPred.RASInCorrect 2132154 # Number of incorrect RAS predictions. 354system.cpu.branchPred.indirectLookups 7072039 # Number of indirect predictor lookups. 355system.cpu.branchPred.indirectHits 5016643 # Number of indirect target hits. 356system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses. 357system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches. 358system.cpu_clk_domain.clock 500 # Clock period in ticks | 344system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 345system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 346system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 347system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 348system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 349system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 350system.cpu.branchPred.lookups 256209592 # Number of BP lookups 351system.cpu.branchPred.condPredicted 178352168 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 356system.cpu.branchPred.BTBHitPct 67.398456 # BTB Hit Percentage 357system.cpu.branchPred.usedRAS 31319231 # Number of times the RAS was used to get a target. 358system.cpu.branchPred.RASInCorrect 2132154 # Number of incorrect RAS predictions. 359system.cpu.branchPred.indirectLookups 7072039 # Number of indirect predictor lookups. 360system.cpu.branchPred.indirectHits 5016643 # Number of indirect target hits. 361system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses. 362system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches. 363system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 364system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 359system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 366system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 380system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 381system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 382system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 383system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 384system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 385system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 386system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 387system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 365system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 366system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 369system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 386system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 387system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 388system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 389system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 390system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 391system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 392system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 393system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 394system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 388system.cpu.dtb.walker.walks 561578 # Table walker walks requested 389system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors 390system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate 391system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181761 # Level at which table walker walks with long descriptors terminate 392system.cpu.dtb.walker.walkWaitTime::samples 561578 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::0 561578 100.00% 100.00% # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::total 561578 # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkCompletionTime::samples 202628 # Table walker service (enqueue to completion) latency --- 41 unchanged lines hidden (view full) --- 437system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 438system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions 439system.cpu.dtb.read_accesses 180031455 # DTB read accesses 440system.cpu.dtb.write_accesses 159322555 # DTB write accesses 441system.cpu.dtb.inst_accesses 0 # ITB inst accesses 442system.cpu.dtb.hits 338792432 # DTB hits 443system.cpu.dtb.misses 561578 # DTB misses 444system.cpu.dtb.accesses 339354010 # DTB accesses | 395system.cpu.dtb.walker.walks 561578 # Table walker walks requested 396system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors 397system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate 398system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181761 # Level at which table walker walks with long descriptors terminate 399system.cpu.dtb.walker.walkWaitTime::samples 561578 # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::0 561578 100.00% 100.00% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::total 561578 # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkCompletionTime::samples 202628 # Table walker service (enqueue to completion) latency --- 41 unchanged lines hidden (view full) --- 444system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 445system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions 446system.cpu.dtb.read_accesses 180031455 # DTB read accesses 447system.cpu.dtb.write_accesses 159322555 # DTB write accesses 448system.cpu.dtb.inst_accesses 0 # ITB inst accesses 449system.cpu.dtb.hits 338792432 # DTB hits 450system.cpu.dtb.misses 561578 # DTB misses 451system.cpu.dtb.accesses 339354010 # DTB accesses |
| 452system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 445system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 466system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 468system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 469system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 470system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 471system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 472system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 473system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 453system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 474system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 475system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 476system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 477system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 478system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 479system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 480system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 481system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 482system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 474system.cpu.itb.walker.walks 133823 # Table walker walks requested 475system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors 476system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate 477system.cpu.itb.walker.walksLongTerminationLevel::Level3 116932 # Level at which table walker walks with long descriptors terminate 478system.cpu.itb.walker.walkWaitTime::samples 133823 # Table walker wait (enqueue to first request) latency 479system.cpu.itb.walker.walkWaitTime::0 133823 100.00% 100.00% # Table walker wait (enqueue to first request) latency 480system.cpu.itb.walker.walkWaitTime::total 133823 # Table walker wait (enqueue to first request) latency 481system.cpu.itb.walker.walkCompletionTime::samples 117989 # Table walker service (enqueue to completion) latency --- 39 unchanged lines hidden (view full) --- 521system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions 523system.cpu.itb.read_accesses 0 # DTB read accesses 524system.cpu.itb.write_accesses 0 # DTB write accesses 525system.cpu.itb.inst_accesses 442926878 # ITB inst accesses 526system.cpu.itb.hits 442793055 # DTB hits 527system.cpu.itb.misses 133823 # DTB misses 528system.cpu.itb.accesses 442926878 # DTB accesses | 483system.cpu.itb.walker.walks 133823 # Table walker walks requested 484system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors 485system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate 486system.cpu.itb.walker.walksLongTerminationLevel::Level3 116932 # Level at which table walker walks with long descriptors terminate 487system.cpu.itb.walker.walkWaitTime::samples 133823 # Table walker wait (enqueue to first request) latency 488system.cpu.itb.walker.walkWaitTime::0 133823 100.00% 100.00% # Table walker wait (enqueue to first request) latency 489system.cpu.itb.walker.walkWaitTime::total 133823 # Table walker wait (enqueue to first request) latency 490system.cpu.itb.walker.walkCompletionTime::samples 117989 # Table walker service (enqueue to completion) latency --- 39 unchanged lines hidden (view full) --- 530system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 531system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions 532system.cpu.itb.read_accesses 0 # DTB read accesses 533system.cpu.itb.write_accesses 0 # DTB write accesses 534system.cpu.itb.inst_accesses 442926878 # ITB inst accesses 535system.cpu.itb.hits 442793055 # DTB hits 536system.cpu.itb.misses 133823 # DTB misses 537system.cpu.itb.accesses 442926878 # DTB accesses |
| 538system.cpu.numPwrStateTransitions 33032 # Number of power state transitions 539system.cpu.pwrStateClkGateDist::samples 16516 # Distribution of time spent in the clock gated state 540system.cpu.pwrStateClkGateDist::mean 3050356912.427888 # Distribution of time spent in the clock gated state 541system.cpu.pwrStateClkGateDist::stdev 59773934276.156128 # Distribution of time spent in the clock gated state 542system.cpu.pwrStateClkGateDist::underflows 7219 43.71% 43.71% # Distribution of time spent in the clock gated state 543system.cpu.pwrStateClkGateDist::1000-5e+10 9262 56.08% 99.79% # Distribution of time spent in the clock gated state 544system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state 545system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state 546system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 547system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 548system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 549system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 550system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 551system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 552system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 553system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 554system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 555system.cpu.pwrStateClkGateDist::max_value 1988777743356 # Distribution of time spent in the clock gated state 556system.cpu.pwrStateClkGateDist::total 16516 # Distribution of time spent in the clock gated state 557system.cpu.pwrStateResidencyTicks::ON 1280958181341 # Cumulative time (in ticks) in various power states 558system.cpu.pwrStateResidencyTicks::CLK_GATED 50379694765659 # Cumulative time (in ticks) in various power states |
|
| 529system.cpu.numCycles 2561963341 # number of cpu cycles simulated 530system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 531system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 532system.cpu.committedInsts 929398934 # Number of instructions committed 533system.cpu.committedOps 1092086880 # Number of ops (including micro ops) committed 534system.cpu.discardedOps 94664249 # Number of ops (including micro ops) which were discarded before commit 535system.cpu.numFetchSuspends 7656 # Number of times Execute suspended instruction fetching 536system.cpu.quiesceCycles 100760459460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 33 unchanged lines hidden (view full) --- 570system.cpu.op_class_0::MemWrite 158660847 14.53% 100.00% # Class of committed instruction 571system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 572system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 573system.cpu.op_class_0::total 1092086880 # Class of committed instruction 574system.cpu.kern.inst.arm 0 # number of arm instructions executed 575system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed 576system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked 577system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped | 559system.cpu.numCycles 2561963341 # number of cpu cycles simulated 560system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 561system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 562system.cpu.committedInsts 929398934 # Number of instructions committed 563system.cpu.committedOps 1092086880 # Number of ops (including micro ops) committed 564system.cpu.discardedOps 94664249 # Number of ops (including micro ops) which were discarded before commit 565system.cpu.numFetchSuspends 7656 # Number of times Execute suspended instruction fetching 566system.cpu.quiesceCycles 100760459460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 33 unchanged lines hidden (view full) --- 600system.cpu.op_class_0::MemWrite 158660847 14.53% 100.00% # Class of committed instruction 601system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 602system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 603system.cpu.op_class_0::total 1092086880 # Class of committed instruction 604system.cpu.kern.inst.arm 0 # number of arm instructions executed 605system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed 606system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked 607system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped |
| 608system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 578system.cpu.dcache.tags.replacements 10826762 # number of replacements 579system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use 580system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks. 581system.cpu.dcache.tags.sampled_refs 10827274 # Sample count of references to valid blocks. 582system.cpu.dcache.tags.avg_refs 29.813150 # Average number of references to valid blocks. 583system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. 584system.cpu.dcache.tags.occ_blocks::cpu.data 511.930071 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 587system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 590system.cpu.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 591system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 592system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 593system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses 594system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses | 609system.cpu.dcache.tags.replacements 10826762 # number of replacements 610system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use 611system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks. 612system.cpu.dcache.tags.sampled_refs 10827274 # Sample count of references to valid blocks. 613system.cpu.dcache.tags.avg_refs 29.813150 # Average number of references to valid blocks. 614system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. 615system.cpu.dcache.tags.occ_blocks::cpu.data 511.930071 # Average occupied blocks per requestor 616system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 617system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 618system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 619system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 620system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 621system.cpu.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 622system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 623system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 624system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses 625system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses |
| 626system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 595system.cpu.dcache.ReadReq_hits::cpu.data 165131668 # number of ReadReq hits 596system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits 597system.cpu.dcache.WriteReq_hits::cpu.data 148654336 # number of WriteReq hits 598system.cpu.dcache.WriteReq_hits::total 148654336 # number of WriteReq hits 599system.cpu.dcache.SoftPFReq_hits::cpu.data 515490 # number of SoftPFReq hits 600system.cpu.dcache.SoftPFReq_hits::total 515490 # number of SoftPFReq hits 601system.cpu.dcache.WriteLineReq_hits::cpu.data 336587 # number of WriteLineReq hits 602system.cpu.dcache.WriteLineReq_hits::total 336587 # number of WriteLineReq hits --- 174 unchanged lines hidden (view full) --- 777system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716 # average overall mshr miss latency 778system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716 # average overall mshr miss latency 779system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661 # average overall mshr miss latency 780system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661 # average overall mshr miss latency 781system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency 782system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency 783system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency 784system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency | 627system.cpu.dcache.ReadReq_hits::cpu.data 165131668 # number of ReadReq hits 628system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits 629system.cpu.dcache.WriteReq_hits::cpu.data 148654336 # number of WriteReq hits 630system.cpu.dcache.WriteReq_hits::total 148654336 # number of WriteReq hits 631system.cpu.dcache.SoftPFReq_hits::cpu.data 515490 # number of SoftPFReq hits 632system.cpu.dcache.SoftPFReq_hits::total 515490 # number of SoftPFReq hits 633system.cpu.dcache.WriteLineReq_hits::cpu.data 336587 # number of WriteLineReq hits 634system.cpu.dcache.WriteLineReq_hits::total 336587 # number of WriteLineReq hits --- 174 unchanged lines hidden (view full) --- 809system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716 # average overall mshr miss latency 810system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716 # average overall mshr miss latency 811system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661 # average overall mshr miss latency 812system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661 # average overall mshr miss latency 813system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency 814system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency 815system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency 816system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency |
| 817system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 785system.cpu.icache.tags.replacements 24339101 # number of replacements 786system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use 787system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. 788system.cpu.icache.tags.sampled_refs 24339613 # Sample count of references to valid blocks. 789system.cpu.icache.tags.avg_refs 17.178953 # Average number of references to valid blocks. 790system.cpu.icache.tags.warmup_cycle 32773385500 # Cycle when the warmup percentage was hit. 791system.cpu.icache.tags.occ_blocks::cpu.inst 511.885333 # Average occupied blocks per requestor 792system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy 793system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy 794system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 795system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 796system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 797system.cpu.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id 798system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 799system.cpu.icache.tags.tag_accesses 466808304 # Number of tag accesses 800system.cpu.icache.tags.data_accesses 466808304 # Number of data accesses | 818system.cpu.icache.tags.replacements 24339101 # number of replacements 819system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use 820system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. 821system.cpu.icache.tags.sampled_refs 24339613 # Sample count of references to valid blocks. 822system.cpu.icache.tags.avg_refs 17.178953 # Average number of references to valid blocks. 823system.cpu.icache.tags.warmup_cycle 32773385500 # Cycle when the warmup percentage was hit. 824system.cpu.icache.tags.occ_blocks::cpu.inst 511.885333 # Average occupied blocks per requestor 825system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy 826system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy 827system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 828system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 829system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 830system.cpu.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id 831system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 832system.cpu.icache.tags.tag_accesses 466808304 # Number of tag accesses 833system.cpu.icache.tags.data_accesses 466808304 # Number of data accesses |
| 834system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 801system.cpu.icache.ReadReq_hits::cpu.inst 418129059 # number of ReadReq hits 802system.cpu.icache.ReadReq_hits::total 418129059 # number of ReadReq hits 803system.cpu.icache.demand_hits::cpu.inst 418129059 # number of demand (read+write) hits 804system.cpu.icache.demand_hits::total 418129059 # number of demand (read+write) hits 805system.cpu.icache.overall_hits::cpu.inst 418129059 # number of overall hits 806system.cpu.icache.overall_hits::total 418129059 # number of overall hits 807system.cpu.icache.ReadReq_misses::cpu.inst 24339623 # number of ReadReq misses 808system.cpu.icache.ReadReq_misses::total 24339623 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 873system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 874system.cpu.icache.demand_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 875system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 876system.cpu.icache.overall_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 877system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 878system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 879system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 880system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency | 835system.cpu.icache.ReadReq_hits::cpu.inst 418129059 # number of ReadReq hits 836system.cpu.icache.ReadReq_hits::total 418129059 # number of ReadReq hits 837system.cpu.icache.demand_hits::cpu.inst 418129059 # number of demand (read+write) hits 838system.cpu.icache.demand_hits::total 418129059 # number of demand (read+write) hits 839system.cpu.icache.overall_hits::cpu.inst 418129059 # number of overall hits 840system.cpu.icache.overall_hits::total 418129059 # number of overall hits 841system.cpu.icache.ReadReq_misses::cpu.inst 24339623 # number of ReadReq misses 842system.cpu.icache.ReadReq_misses::total 24339623 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 907system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 908system.cpu.icache.demand_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 909system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 910system.cpu.icache.overall_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 911system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 912system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 913system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 914system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency |
| 915system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 881system.cpu.l2cache.tags.replacements 1529682 # number of replacements 882system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use 883system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks. 884system.cpu.l2cache.tags.sampled_refs 1592715 # Sample count of references to valid blocks. 885system.cpu.l2cache.tags.avg_refs 41.651953 # Average number of references to valid blocks. 886system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit. 887system.cpu.l2cache.tags.occ_blocks::writebacks 36843.538434 # Average occupied blocks per requestor 888system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 325.022996 # Average occupied blocks per requestor --- 14 unchanged lines hidden (view full) --- 903system.cpu.l2cache.tags.age_task_id_blocks_1024::1 461 # Occupied blocks per task id 904system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2479 # Occupied blocks per task id 905system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5541 # Occupied blocks per task id 906system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54260 # Occupied blocks per task id 907system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003632 # Percentage of cache occupancy per task id 908system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958176 # Percentage of cache occupancy per task id 909system.cpu.l2cache.tags.tag_accesses 577322417 # Number of tag accesses 910system.cpu.l2cache.tags.data_accesses 577322417 # Number of data accesses | 916system.cpu.l2cache.tags.replacements 1529682 # number of replacements 917system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use 918system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks. 919system.cpu.l2cache.tags.sampled_refs 1592715 # Sample count of references to valid blocks. 920system.cpu.l2cache.tags.avg_refs 41.651953 # Average number of references to valid blocks. 921system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit. 922system.cpu.l2cache.tags.occ_blocks::writebacks 36843.538434 # Average occupied blocks per requestor 923system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 325.022996 # Average occupied blocks per requestor --- 14 unchanged lines hidden (view full) --- 938system.cpu.l2cache.tags.age_task_id_blocks_1024::1 461 # Occupied blocks per task id 939system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2479 # Occupied blocks per task id 940system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5541 # Occupied blocks per task id 941system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54260 # Occupied blocks per task id 942system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003632 # Percentage of cache occupancy per task id 943system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958176 # Percentage of cache occupancy per task id 944system.cpu.l2cache.tags.tag_accesses 577322417 # Number of tag accesses 945system.cpu.l2cache.tags.data_accesses 577322417 # Number of data accesses |
| 946system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 911system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 919591 # number of ReadReq hits 912system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 277608 # number of ReadReq hits 913system.cpu.l2cache.ReadReq_hits::total 1197199 # number of ReadReq hits 914system.cpu.l2cache.WritebackDirty_hits::writebacks 8312311 # number of WritebackDirty hits 915system.cpu.l2cache.WritebackDirty_hits::total 8312311 # number of WritebackDirty hits 916system.cpu.l2cache.WritebackClean_hits::writebacks 24335620 # number of WritebackClean hits 917system.cpu.l2cache.WritebackClean_hits::total 24335620 # number of WritebackClean hits 918system.cpu.l2cache.UpgradeReq_hits::cpu.data 10528 # number of UpgradeReq hits --- 288 unchanged lines hidden (view full) --- 1207system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85698.351705 # average overall mshr uncacheable latency 1208system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97838.144881 # average overall mshr uncacheable latency 1209system.cpu.toL2Bus.snoop_filter.tot_requests 71082854 # Total number of requests made to the snoop filter. 1210system.cpu.toL2Bus.snoop_filter.hit_single_requests 35915919 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1211system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1212system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter. 1213system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1214system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 947system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 919591 # number of ReadReq hits 948system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 277608 # number of ReadReq hits 949system.cpu.l2cache.ReadReq_hits::total 1197199 # number of ReadReq hits 950system.cpu.l2cache.WritebackDirty_hits::writebacks 8312311 # number of WritebackDirty hits 951system.cpu.l2cache.WritebackDirty_hits::total 8312311 # number of WritebackDirty hits 952system.cpu.l2cache.WritebackClean_hits::writebacks 24335620 # number of WritebackClean hits 953system.cpu.l2cache.WritebackClean_hits::total 24335620 # number of WritebackClean hits 954system.cpu.l2cache.UpgradeReq_hits::cpu.data 10528 # number of UpgradeReq hits --- 288 unchanged lines hidden (view full) --- 1243system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85698.351705 # average overall mshr uncacheable latency 1244system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97838.144881 # average overall mshr uncacheable latency 1245system.cpu.toL2Bus.snoop_filter.tot_requests 71082854 # Total number of requests made to the snoop filter. 1246system.cpu.toL2Bus.snoop_filter.hit_single_requests 35915919 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1247system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1248system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter. 1249system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1250system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1251system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 1215system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution 1216system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution 1217system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution 1218system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution 1219system.cpu.toL2Bus.trans_dist::WritebackDirty 9712830 # Transaction distribution 1220system.cpu.toL2Bus.trans_dist::WritebackClean 24339101 # Transaction distribution 1221system.cpu.toL2Bus.trans_dist::CleanEvict 2759131 # Transaction distribution 1222system.cpu.toL2Bus.trans_dist::UpgradeReq 48504 # Transaction distribution --- 34 unchanged lines hidden (view full) --- 1257system.cpu.toL2Bus.respLayer0.occupancy 36594790182 # Layer occupancy (ticks) 1258system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1259system.cpu.toL2Bus.respLayer1.occupancy 15076717704 # Layer occupancy (ticks) 1260system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1261system.cpu.toL2Bus.respLayer2.occupancy 400149367 # Layer occupancy (ticks) 1262system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1263system.cpu.toL2Bus.respLayer3.occupancy 1245546930 # Layer occupancy (ticks) 1264system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1252system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution 1253system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution 1254system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution 1255system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution 1256system.cpu.toL2Bus.trans_dist::WritebackDirty 9712830 # Transaction distribution 1257system.cpu.toL2Bus.trans_dist::WritebackClean 24339101 # Transaction distribution 1258system.cpu.toL2Bus.trans_dist::CleanEvict 2759131 # Transaction distribution 1259system.cpu.toL2Bus.trans_dist::UpgradeReq 48504 # Transaction distribution --- 34 unchanged lines hidden (view full) --- 1294system.cpu.toL2Bus.respLayer0.occupancy 36594790182 # Layer occupancy (ticks) 1295system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1296system.cpu.toL2Bus.respLayer1.occupancy 15076717704 # Layer occupancy (ticks) 1297system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1298system.cpu.toL2Bus.respLayer2.occupancy 400149367 # Layer occupancy (ticks) 1299system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1300system.cpu.toL2Bus.respLayer3.occupancy 1245546930 # Layer occupancy (ticks) 1301system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1302system.iobus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 1265system.iobus.trans_dist::ReadReq 40324 # Transaction distribution 1266system.iobus.trans_dist::ReadResp 40324 # Transaction distribution 1267system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1268system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1269system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1270system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1271system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1272system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 60 unchanged lines hidden (view full) --- 1333system.iobus.reqLayer25.occupancy 567103107 # Layer occupancy (ticks) 1334system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1335system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1336system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1337system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) 1338system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1339system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1340system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 1303system.iobus.trans_dist::ReadReq 40324 # Transaction distribution 1304system.iobus.trans_dist::ReadResp 40324 # Transaction distribution 1305system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1306system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1307system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1308system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1309system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1310system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 60 unchanged lines hidden (view full) --- 1371system.iobus.reqLayer25.occupancy 567103107 # Layer occupancy (ticks) 1372system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1373system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1374system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1375system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) 1376system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1377system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1378system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 1379system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 1341system.iocache.tags.replacements 115484 # number of replacements 1342system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use 1343system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1344system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. 1345system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1346system.iocache.tags.warmup_cycle 13153318095000 # Cycle when the warmup percentage was hit. 1347system.iocache.tags.occ_blocks::realview.ethernet 3.521307 # Average occupied blocks per requestor 1348system.iocache.tags.occ_blocks::realview.ide 6.919947 # Average occupied blocks per requestor 1349system.iocache.tags.occ_percent::realview.ethernet 0.220082 # Average percentage of cache occupancy 1350system.iocache.tags.occ_percent::realview.ide 0.432497 # Average percentage of cache occupancy 1351system.iocache.tags.occ_percent::total 0.652578 # Average percentage of cache occupancy 1352system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1353system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1354system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1355system.iocache.tags.tag_accesses 1039884 # Number of tag accesses 1356system.iocache.tags.data_accesses 1039884 # Number of data accesses | 1380system.iocache.tags.replacements 115484 # number of replacements 1381system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use 1382system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1383system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. 1384system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1385system.iocache.tags.warmup_cycle 13153318095000 # Cycle when the warmup percentage was hit. 1386system.iocache.tags.occ_blocks::realview.ethernet 3.521307 # Average occupied blocks per requestor 1387system.iocache.tags.occ_blocks::realview.ide 6.919947 # Average occupied blocks per requestor 1388system.iocache.tags.occ_percent::realview.ethernet 0.220082 # Average percentage of cache occupancy 1389system.iocache.tags.occ_percent::realview.ide 0.432497 # Average percentage of cache occupancy 1390system.iocache.tags.occ_percent::total 0.652578 # Average percentage of cache occupancy 1391system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1392system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1393system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1394system.iocache.tags.tag_accesses 1039884 # Number of tag accesses 1395system.iocache.tags.data_accesses 1039884 # Number of data accesses |
| 1396system.iocache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 1357system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1358system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses 1359system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses 1360system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1361system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1362system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1363system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1364system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 109 unchanged lines hidden (view full) --- 1474system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482 # average WriteLineReq mshr miss latency 1475system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482 # average WriteLineReq mshr miss latency 1476system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1477system.iocache.demand_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency 1478system.iocache.demand_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency 1479system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1480system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency 1481system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency | 1397system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1398system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses 1399system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses 1400system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1401system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1402system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1403system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1404system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 109 unchanged lines hidden (view full) --- 1514system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482 # average WriteLineReq mshr miss latency 1515system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482 # average WriteLineReq mshr miss latency 1516system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1517system.iocache.demand_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency 1518system.iocache.demand_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency 1519system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1520system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency 1521system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency |
| 1522system.membus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 1482system.membus.trans_dist::ReadReq 86006 # Transaction distribution 1483system.membus.trans_dist::ReadResp 535040 # Transaction distribution 1484system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1485system.membus.trans_dist::WriteResp 33706 # Transaction distribution 1486system.membus.trans_dist::WritebackDirty 1400486 # Transaction distribution 1487system.membus.trans_dist::CleanEvict 243574 # Transaction distribution 1488system.membus.trans_dist::UpgradeReq 38729 # Transaction distribution 1489system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 1527system.membus.reqLayer2.occupancy 5639000 # Layer occupancy (ticks) 1528system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1529system.membus.reqLayer5.occupancy 9317752261 # Layer occupancy (ticks) 1530system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1531system.membus.respLayer2.occupancy 6128850630 # Layer occupancy (ticks) 1532system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1533system.membus.respLayer3.occupancy 44857615 # Layer occupancy (ticks) 1534system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 1523system.membus.trans_dist::ReadReq 86006 # Transaction distribution 1524system.membus.trans_dist::ReadResp 535040 # Transaction distribution 1525system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1526system.membus.trans_dist::WriteResp 33706 # Transaction distribution 1527system.membus.trans_dist::WritebackDirty 1400486 # Transaction distribution 1528system.membus.trans_dist::CleanEvict 243574 # Transaction distribution 1529system.membus.trans_dist::UpgradeReq 38729 # Transaction distribution 1530system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 1568system.membus.reqLayer2.occupancy 5639000 # Layer occupancy (ticks) 1569system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1570system.membus.reqLayer5.occupancy 9317752261 # Layer occupancy (ticks) 1571system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1572system.membus.respLayer2.occupancy 6128850630 # Layer occupancy (ticks) 1573system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1574system.membus.respLayer3.occupancy 44857615 # Layer occupancy (ticks) 1575system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1576system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1577system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1578system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1579system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1580system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1581system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1582system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 1535system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1536system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1537system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1538system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1539system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1540system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1583system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1584system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1585system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1586system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1587system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1588system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1589system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1590system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 1541system.realview.ethernet.txBytes 966 # Bytes Transmitted 1542system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1543system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1544system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1545system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1546system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1547system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1548system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 1575system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1576system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1577system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1578system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1579system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1580system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1581system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1582system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1591system.realview.ethernet.txBytes 966 # Bytes Transmitted 1592system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1593system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1594system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1595system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1596system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1597system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1598system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 1625system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1626system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1627system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1628system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1629system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1630system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1631system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1632system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1633system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1634system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1635system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1636system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1637system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1638system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1639system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 1583system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1584system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1585system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1586system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1640system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1641system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1642system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1643system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1644system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1645system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1646system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1647system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1648system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1649system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1650system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1651system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1652system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1653system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1654system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1655system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states |
|
| 1587 1588---------- End Simulation Statistics ---------- | 1656 1657---------- End Simulation Statistics ---------- |