| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660653 # Number of seconds simulated 4sim_ticks 51660652947000 # Number of ticks simulated 5final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660653 # Number of seconds simulated 4sim_ticks 51660652947000 # Number of ticks simulated 5final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 204210 # Simulator instruction rate (inst/s) 8host_op_rate 239956 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11350998190 # Simulator tick rate (ticks/s) 10host_mem_usage 682908 # Number of bytes of host memory used 11host_seconds 4551.20 # Real time elapsed on the host | 7host_inst_rate 286668 # Simulator instruction rate (inst/s) 8host_op_rate 336848 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15934426663 # Simulator tick rate (ticks/s) 10host_mem_usage 682904 # Number of bytes of host memory used 11host_seconds 3242.08 # Real time elapsed on the host |
| 12sim_insts 929398934 # Number of instructions simulated 13sim_ops 1092086880 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory --- 579 unchanged lines hidden (view full) --- 599system.cpu.dcache.SoftPFReq_hits::cpu.data 515490 # number of SoftPFReq hits 600system.cpu.dcache.SoftPFReq_hits::total 515490 # number of SoftPFReq hits 601system.cpu.dcache.WriteLineReq_hits::cpu.data 336587 # number of WriteLineReq hits 602system.cpu.dcache.WriteLineReq_hits::total 336587 # number of WriteLineReq hits 603system.cpu.dcache.LoadLockedReq_hits::cpu.data 3899601 # number of LoadLockedReq hits 604system.cpu.dcache.LoadLockedReq_hits::total 3899601 # number of LoadLockedReq hits 605system.cpu.dcache.StoreCondReq_hits::cpu.data 4208890 # number of StoreCondReq hits 606system.cpu.dcache.StoreCondReq_hits::total 4208890 # number of StoreCondReq hits | 12sim_insts 929398934 # Number of instructions simulated 13sim_ops 1092086880 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory --- 579 unchanged lines hidden (view full) --- 599system.cpu.dcache.SoftPFReq_hits::cpu.data 515490 # number of SoftPFReq hits 600system.cpu.dcache.SoftPFReq_hits::total 515490 # number of SoftPFReq hits 601system.cpu.dcache.WriteLineReq_hits::cpu.data 336587 # number of WriteLineReq hits 602system.cpu.dcache.WriteLineReq_hits::total 336587 # number of WriteLineReq hits 603system.cpu.dcache.LoadLockedReq_hits::cpu.data 3899601 # number of LoadLockedReq hits 604system.cpu.dcache.LoadLockedReq_hits::total 3899601 # number of LoadLockedReq hits 605system.cpu.dcache.StoreCondReq_hits::cpu.data 4208890 # number of StoreCondReq hits 606system.cpu.dcache.StoreCondReq_hits::total 4208890 # number of StoreCondReq hits |
| 607system.cpu.dcache.demand_hits::cpu.data 313786004 # number of demand (read+write) hits 608system.cpu.dcache.demand_hits::total 313786004 # number of demand (read+write) hits 609system.cpu.dcache.overall_hits::cpu.data 314301494 # number of overall hits 610system.cpu.dcache.overall_hits::total 314301494 # number of overall hits | 607system.cpu.dcache.demand_hits::cpu.data 314122591 # number of demand (read+write) hits 608system.cpu.dcache.demand_hits::total 314122591 # number of demand (read+write) hits 609system.cpu.dcache.overall_hits::cpu.data 314638081 # number of overall hits 610system.cpu.dcache.overall_hits::total 314638081 # number of overall hits |
| 611system.cpu.dcache.ReadReq_misses::cpu.data 6423881 # number of ReadReq misses 612system.cpu.dcache.ReadReq_misses::total 6423881 # number of ReadReq misses 613system.cpu.dcache.WriteReq_misses::cpu.data 4177328 # number of WriteReq misses 614system.cpu.dcache.WriteReq_misses::total 4177328 # number of WriteReq misses 615system.cpu.dcache.SoftPFReq_misses::cpu.data 1420881 # number of SoftPFReq misses 616system.cpu.dcache.SoftPFReq_misses::total 1420881 # number of SoftPFReq misses 617system.cpu.dcache.WriteLineReq_misses::cpu.data 1240100 # number of WriteLineReq misses 618system.cpu.dcache.WriteLineReq_misses::total 1240100 # number of WriteLineReq misses 619system.cpu.dcache.LoadLockedReq_misses::cpu.data 311002 # number of LoadLockedReq misses 620system.cpu.dcache.LoadLockedReq_misses::total 311002 # number of LoadLockedReq misses 621system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 622system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses | 611system.cpu.dcache.ReadReq_misses::cpu.data 6423881 # number of ReadReq misses 612system.cpu.dcache.ReadReq_misses::total 6423881 # number of ReadReq misses 613system.cpu.dcache.WriteReq_misses::cpu.data 4177328 # number of WriteReq misses 614system.cpu.dcache.WriteReq_misses::total 4177328 # number of WriteReq misses 615system.cpu.dcache.SoftPFReq_misses::cpu.data 1420881 # number of SoftPFReq misses 616system.cpu.dcache.SoftPFReq_misses::total 1420881 # number of SoftPFReq misses 617system.cpu.dcache.WriteLineReq_misses::cpu.data 1240100 # number of WriteLineReq misses 618system.cpu.dcache.WriteLineReq_misses::total 1240100 # number of WriteLineReq misses 619system.cpu.dcache.LoadLockedReq_misses::cpu.data 311002 # number of LoadLockedReq misses 620system.cpu.dcache.LoadLockedReq_misses::total 311002 # number of LoadLockedReq misses 621system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 622system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses |
| 623system.cpu.dcache.demand_misses::cpu.data 10601209 # number of demand (read+write) misses 624system.cpu.dcache.demand_misses::total 10601209 # number of demand (read+write) misses 625system.cpu.dcache.overall_misses::cpu.data 12022090 # number of overall misses 626system.cpu.dcache.overall_misses::total 12022090 # number of overall misses | 623system.cpu.dcache.demand_misses::cpu.data 11841309 # number of demand (read+write) misses 624system.cpu.dcache.demand_misses::total 11841309 # number of demand (read+write) misses 625system.cpu.dcache.overall_misses::cpu.data 13262190 # number of overall misses 626system.cpu.dcache.overall_misses::total 13262190 # number of overall misses |
| 627system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500 # number of ReadReq miss cycles 628system.cpu.dcache.ReadReq_miss_latency::total 119203222500 # number of ReadReq miss cycles 629system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500 # number of WriteReq miss cycles 630system.cpu.dcache.WriteReq_miss_latency::total 206322817500 # number of WriteReq miss cycles 631system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53471775500 # number of WriteLineReq miss cycles 632system.cpu.dcache.WriteLineReq_miss_latency::total 53471775500 # number of WriteLineReq miss cycles 633system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5200645500 # number of LoadLockedReq miss cycles 634system.cpu.dcache.LoadLockedReq_miss_latency::total 5200645500 # number of LoadLockedReq miss cycles 635system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles 636system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles | 627system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500 # number of ReadReq miss cycles 628system.cpu.dcache.ReadReq_miss_latency::total 119203222500 # number of ReadReq miss cycles 629system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500 # number of WriteReq miss cycles 630system.cpu.dcache.WriteReq_miss_latency::total 206322817500 # number of WriteReq miss cycles 631system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53471775500 # number of WriteLineReq miss cycles 632system.cpu.dcache.WriteLineReq_miss_latency::total 53471775500 # number of WriteLineReq miss cycles 633system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5200645500 # number of LoadLockedReq miss cycles 634system.cpu.dcache.LoadLockedReq_miss_latency::total 5200645500 # number of LoadLockedReq miss cycles 635system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles 636system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles |
| 637system.cpu.dcache.demand_miss_latency::cpu.data 325526040000 # number of demand (read+write) miss cycles 638system.cpu.dcache.demand_miss_latency::total 325526040000 # number of demand (read+write) miss cycles 639system.cpu.dcache.overall_miss_latency::cpu.data 325526040000 # number of overall miss cycles 640system.cpu.dcache.overall_miss_latency::total 325526040000 # number of overall miss cycles | 637system.cpu.dcache.demand_miss_latency::cpu.data 378997815500 # number of demand (read+write) miss cycles 638system.cpu.dcache.demand_miss_latency::total 378997815500 # number of demand (read+write) miss cycles 639system.cpu.dcache.overall_miss_latency::cpu.data 378997815500 # number of overall miss cycles 640system.cpu.dcache.overall_miss_latency::total 378997815500 # number of overall miss cycles |
| 641system.cpu.dcache.ReadReq_accesses::cpu.data 171555549 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.ReadReq_accesses::total 171555549 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::cpu.data 152831664 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::total 152831664 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.SoftPFReq_accesses::cpu.data 1936371 # number of SoftPFReq accesses(hits+misses) 646system.cpu.dcache.SoftPFReq_accesses::total 1936371 # number of SoftPFReq accesses(hits+misses) 647system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576687 # number of WriteLineReq accesses(hits+misses) 648system.cpu.dcache.WriteLineReq_accesses::total 1576687 # number of WriteLineReq accesses(hits+misses) 649system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4210603 # number of LoadLockedReq accesses(hits+misses) 650system.cpu.dcache.LoadLockedReq_accesses::total 4210603 # number of LoadLockedReq accesses(hits+misses) 651system.cpu.dcache.StoreCondReq_accesses::cpu.data 4208892 # number of StoreCondReq accesses(hits+misses) 652system.cpu.dcache.StoreCondReq_accesses::total 4208892 # number of StoreCondReq accesses(hits+misses) | 641system.cpu.dcache.ReadReq_accesses::cpu.data 171555549 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.ReadReq_accesses::total 171555549 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::cpu.data 152831664 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::total 152831664 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.SoftPFReq_accesses::cpu.data 1936371 # number of SoftPFReq accesses(hits+misses) 646system.cpu.dcache.SoftPFReq_accesses::total 1936371 # number of SoftPFReq accesses(hits+misses) 647system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576687 # number of WriteLineReq accesses(hits+misses) 648system.cpu.dcache.WriteLineReq_accesses::total 1576687 # number of WriteLineReq accesses(hits+misses) 649system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4210603 # number of LoadLockedReq accesses(hits+misses) 650system.cpu.dcache.LoadLockedReq_accesses::total 4210603 # number of LoadLockedReq accesses(hits+misses) 651system.cpu.dcache.StoreCondReq_accesses::cpu.data 4208892 # number of StoreCondReq accesses(hits+misses) 652system.cpu.dcache.StoreCondReq_accesses::total 4208892 # number of StoreCondReq accesses(hits+misses) |
| 653system.cpu.dcache.demand_accesses::cpu.data 324387213 # number of demand (read+write) accesses 654system.cpu.dcache.demand_accesses::total 324387213 # number of demand (read+write) accesses 655system.cpu.dcache.overall_accesses::cpu.data 326323584 # number of overall (read+write) accesses 656system.cpu.dcache.overall_accesses::total 326323584 # number of overall (read+write) accesses | 653system.cpu.dcache.demand_accesses::cpu.data 325963900 # number of demand (read+write) accesses 654system.cpu.dcache.demand_accesses::total 325963900 # number of demand (read+write) accesses 655system.cpu.dcache.overall_accesses::cpu.data 327900271 # number of overall (read+write) accesses 656system.cpu.dcache.overall_accesses::total 327900271 # number of overall (read+write) accesses |
| 657system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037445 # miss rate for ReadReq accesses 658system.cpu.dcache.ReadReq_miss_rate::total 0.037445 # miss rate for ReadReq accesses 659system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027333 # miss rate for WriteReq accesses 660system.cpu.dcache.WriteReq_miss_rate::total 0.027333 # miss rate for WriteReq accesses 661system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733786 # miss rate for SoftPFReq accesses 662system.cpu.dcache.SoftPFReq_miss_rate::total 0.733786 # miss rate for SoftPFReq accesses 663system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786523 # miss rate for WriteLineReq accesses 664system.cpu.dcache.WriteLineReq_miss_rate::total 0.786523 # miss rate for WriteLineReq accesses 665system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073862 # miss rate for LoadLockedReq accesses 666system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073862 # miss rate for LoadLockedReq accesses 667system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 668system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses | 657system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037445 # miss rate for ReadReq accesses 658system.cpu.dcache.ReadReq_miss_rate::total 0.037445 # miss rate for ReadReq accesses 659system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027333 # miss rate for WriteReq accesses 660system.cpu.dcache.WriteReq_miss_rate::total 0.027333 # miss rate for WriteReq accesses 661system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733786 # miss rate for SoftPFReq accesses 662system.cpu.dcache.SoftPFReq_miss_rate::total 0.733786 # miss rate for SoftPFReq accesses 663system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786523 # miss rate for WriteLineReq accesses 664system.cpu.dcache.WriteLineReq_miss_rate::total 0.786523 # miss rate for WriteLineReq accesses 665system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073862 # miss rate for LoadLockedReq accesses 666system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073862 # miss rate for LoadLockedReq accesses 667system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 668system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses |
| 669system.cpu.dcache.demand_miss_rate::cpu.data 0.032681 # miss rate for demand accesses 670system.cpu.dcache.demand_miss_rate::total 0.032681 # miss rate for demand accesses 671system.cpu.dcache.overall_miss_rate::cpu.data 0.036841 # miss rate for overall accesses 672system.cpu.dcache.overall_miss_rate::total 0.036841 # miss rate for overall accesses | 669system.cpu.dcache.demand_miss_rate::cpu.data 0.036327 # miss rate for demand accesses 670system.cpu.dcache.demand_miss_rate::total 0.036327 # miss rate for demand accesses 671system.cpu.dcache.overall_miss_rate::cpu.data 0.040446 # miss rate for overall accesses 672system.cpu.dcache.overall_miss_rate::total 0.040446 # miss rate for overall accesses |
| 673system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562 # average ReadReq miss latency 674system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562 # average ReadReq miss latency 675system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209 # average WriteReq miss latency 676system.cpu.dcache.WriteReq_avg_miss_latency::total 49391.098209 # average WriteReq miss latency 677system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43118.922264 # average WriteLineReq miss latency 678system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43118.922264 # average WriteLineReq miss latency 679system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259 # average LoadLockedReq miss latency 680system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259 # average LoadLockedReq miss latency 681system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency 682system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency | 673system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562 # average ReadReq miss latency 674system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562 # average ReadReq miss latency 675system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209 # average WriteReq miss latency 676system.cpu.dcache.WriteReq_avg_miss_latency::total 49391.098209 # average WriteReq miss latency 677system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43118.922264 # average WriteLineReq miss latency 678system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43118.922264 # average WriteLineReq miss latency 679system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259 # average LoadLockedReq miss latency 680system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259 # average LoadLockedReq miss latency 681system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency 682system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency |
| 683system.cpu.dcache.demand_avg_miss_latency::cpu.data 30706.501494 # average overall miss latency 684system.cpu.dcache.demand_avg_miss_latency::total 30706.501494 # average overall miss latency 685system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.325157 # average overall miss latency 686system.cpu.dcache.overall_avg_miss_latency::total 27077.325157 # average overall miss latency | 683system.cpu.dcache.demand_avg_miss_latency::cpu.data 32006.412087 # average overall miss latency 684system.cpu.dcache.demand_avg_miss_latency::total 32006.412087 # average overall miss latency 685system.cpu.dcache.overall_avg_miss_latency::cpu.data 28577.317585 # average overall miss latency 686system.cpu.dcache.overall_avg_miss_latency::total 28577.317585 # average overall miss latency |
| 687system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 688system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 690system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 692system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 687system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 688system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 690system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 692system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 693system.cpu.dcache.fast_writes 0 # number of fast writes performed 694system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 695system.cpu.dcache.writebacks::writebacks 8312311 # number of writebacks 696system.cpu.dcache.writebacks::total 8312311 # number of writebacks 697system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778551 # number of ReadReq MSHR hits 698system.cpu.dcache.ReadReq_mshr_hits::total 778551 # number of ReadReq MSHR hits 699system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841560 # number of WriteReq MSHR hits 700system.cpu.dcache.WriteReq_mshr_hits::total 1841560 # number of WriteReq MSHR hits 701system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 166 # number of WriteLineReq MSHR hits 702system.cpu.dcache.WriteLineReq_mshr_hits::total 166 # number of WriteLineReq MSHR hits 703system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69564 # number of LoadLockedReq MSHR hits 704system.cpu.dcache.LoadLockedReq_mshr_hits::total 69564 # number of LoadLockedReq MSHR hits | 693system.cpu.dcache.writebacks::writebacks 8312311 # number of writebacks 694system.cpu.dcache.writebacks::total 8312311 # number of writebacks 695system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778551 # number of ReadReq MSHR hits 696system.cpu.dcache.ReadReq_mshr_hits::total 778551 # number of ReadReq MSHR hits 697system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841560 # number of WriteReq MSHR hits 698system.cpu.dcache.WriteReq_mshr_hits::total 1841560 # number of WriteReq MSHR hits 699system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 166 # number of WriteLineReq MSHR hits 700system.cpu.dcache.WriteLineReq_mshr_hits::total 166 # number of WriteLineReq MSHR hits 701system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69564 # number of LoadLockedReq MSHR hits 702system.cpu.dcache.LoadLockedReq_mshr_hits::total 69564 # number of LoadLockedReq MSHR hits |
| 705system.cpu.dcache.demand_mshr_hits::cpu.data 2620111 # number of demand (read+write) MSHR hits 706system.cpu.dcache.demand_mshr_hits::total 2620111 # number of demand (read+write) MSHR hits 707system.cpu.dcache.overall_mshr_hits::cpu.data 2620111 # number of overall MSHR hits 708system.cpu.dcache.overall_mshr_hits::total 2620111 # number of overall MSHR hits | 703system.cpu.dcache.demand_mshr_hits::cpu.data 2620277 # number of demand (read+write) MSHR hits 704system.cpu.dcache.demand_mshr_hits::total 2620277 # number of demand (read+write) MSHR hits 705system.cpu.dcache.overall_mshr_hits::cpu.data 2620277 # number of overall MSHR hits 706system.cpu.dcache.overall_mshr_hits::total 2620277 # number of overall MSHR hits |
| 709system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5645330 # number of ReadReq MSHR misses 710system.cpu.dcache.ReadReq_mshr_misses::total 5645330 # number of ReadReq MSHR misses 711system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2335768 # number of WriteReq MSHR misses 712system.cpu.dcache.WriteReq_mshr_misses::total 2335768 # number of WriteReq MSHR misses 713system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1413353 # number of SoftPFReq MSHR misses 714system.cpu.dcache.SoftPFReq_mshr_misses::total 1413353 # number of SoftPFReq MSHR misses 715system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1239934 # number of WriteLineReq MSHR misses 716system.cpu.dcache.WriteLineReq_mshr_misses::total 1239934 # number of WriteLineReq MSHR misses 717system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241438 # number of LoadLockedReq MSHR misses 718system.cpu.dcache.LoadLockedReq_mshr_misses::total 241438 # number of LoadLockedReq MSHR misses 719system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 720system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses | 707system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5645330 # number of ReadReq MSHR misses 708system.cpu.dcache.ReadReq_mshr_misses::total 5645330 # number of ReadReq MSHR misses 709system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2335768 # number of WriteReq MSHR misses 710system.cpu.dcache.WriteReq_mshr_misses::total 2335768 # number of WriteReq MSHR misses 711system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1413353 # number of SoftPFReq MSHR misses 712system.cpu.dcache.SoftPFReq_mshr_misses::total 1413353 # number of SoftPFReq MSHR misses 713system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1239934 # number of WriteLineReq MSHR misses 714system.cpu.dcache.WriteLineReq_mshr_misses::total 1239934 # number of WriteLineReq MSHR misses 715system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241438 # number of LoadLockedReq MSHR misses 716system.cpu.dcache.LoadLockedReq_mshr_misses::total 241438 # number of LoadLockedReq MSHR misses 717system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 718system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses |
| 721system.cpu.dcache.demand_mshr_misses::cpu.data 7981098 # number of demand (read+write) MSHR misses 722system.cpu.dcache.demand_mshr_misses::total 7981098 # number of demand (read+write) MSHR misses 723system.cpu.dcache.overall_mshr_misses::cpu.data 9394451 # number of overall MSHR misses 724system.cpu.dcache.overall_mshr_misses::total 9394451 # number of overall MSHR misses | 719system.cpu.dcache.demand_mshr_misses::cpu.data 9221032 # number of demand (read+write) MSHR misses 720system.cpu.dcache.demand_mshr_misses::total 9221032 # number of demand (read+write) MSHR misses 721system.cpu.dcache.overall_mshr_misses::cpu.data 10634385 # number of overall MSHR misses 722system.cpu.dcache.overall_mshr_misses::total 10634385 # number of overall MSHR misses |
| 725system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 726system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 727system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 728system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 729system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 730system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 731system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97557432500 # number of ReadReq MSHR miss cycles 732system.cpu.dcache.ReadReq_mshr_miss_latency::total 97557432500 # number of ReadReq MSHR miss cycles 733system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109336281500 # number of WriteReq MSHR miss cycles 734system.cpu.dcache.WriteReq_mshr_miss_latency::total 109336281500 # number of WriteReq MSHR miss cycles 735system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26901290500 # number of SoftPFReq MSHR miss cycles 736system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26901290500 # number of SoftPFReq MSHR miss cycles 737system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52221764000 # number of WriteLineReq MSHR miss cycles 738system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52221764000 # number of WriteLineReq MSHR miss cycles 739system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3529658500 # number of LoadLockedReq MSHR miss cycles 740system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3529658500 # number of LoadLockedReq MSHR miss cycles 741system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles 742system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles | 723system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 724system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 725system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 726system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 727system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 728system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 729system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97557432500 # number of ReadReq MSHR miss cycles 730system.cpu.dcache.ReadReq_mshr_miss_latency::total 97557432500 # number of ReadReq MSHR miss cycles 731system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109336281500 # number of WriteReq MSHR miss cycles 732system.cpu.dcache.WriteReq_mshr_miss_latency::total 109336281500 # number of WriteReq MSHR miss cycles 733system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26901290500 # number of SoftPFReq MSHR miss cycles 734system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26901290500 # number of SoftPFReq MSHR miss cycles 735system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52221764000 # number of WriteLineReq MSHR miss cycles 736system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52221764000 # number of WriteLineReq MSHR miss cycles 737system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3529658500 # number of LoadLockedReq MSHR miss cycles 738system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3529658500 # number of LoadLockedReq MSHR miss cycles 739system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles 740system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles |
| 743system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206893714000 # number of demand (read+write) MSHR miss cycles 744system.cpu.dcache.demand_mshr_miss_latency::total 206893714000 # number of demand (read+write) MSHR miss cycles 745system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233795004500 # number of overall MSHR miss cycles 746system.cpu.dcache.overall_mshr_miss_latency::total 233795004500 # number of overall MSHR miss cycles | 741system.cpu.dcache.demand_mshr_miss_latency::cpu.data 259115478000 # number of demand (read+write) MSHR miss cycles 742system.cpu.dcache.demand_mshr_miss_latency::total 259115478000 # number of demand (read+write) MSHR miss cycles 743system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286016768500 # number of overall MSHR miss cycles 744system.cpu.dcache.overall_mshr_miss_latency::total 286016768500 # number of overall MSHR miss cycles |
| 747system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197628500 # number of ReadReq MSHR uncacheable cycles 748system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197628500 # number of ReadReq MSHR uncacheable cycles | 745system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197628500 # number of ReadReq MSHR uncacheable cycles 746system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197628500 # number of ReadReq MSHR uncacheable cycles |
| 749system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6191865500 # number of WriteReq MSHR uncacheable cycles 750system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6191865500 # number of WriteReq MSHR uncacheable cycles 751system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12389494000 # number of overall MSHR uncacheable cycles 752system.cpu.dcache.overall_mshr_uncacheable_latency::total 12389494000 # number of overall MSHR uncacheable cycles | 747system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197628500 # number of overall MSHR uncacheable cycles 748system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197628500 # number of overall MSHR uncacheable cycles |
| 753system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032907 # mshr miss rate for ReadReq accesses 754system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032907 # mshr miss rate for ReadReq accesses 755system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015283 # mshr miss rate for WriteReq accesses 756system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015283 # mshr miss rate for WriteReq accesses 757system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729898 # mshr miss rate for SoftPFReq accesses 758system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729898 # mshr miss rate for SoftPFReq accesses 759system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786417 # mshr miss rate for WriteLineReq accesses 760system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786417 # mshr miss rate for WriteLineReq accesses 761system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057340 # mshr miss rate for LoadLockedReq accesses 762system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057340 # mshr miss rate for LoadLockedReq accesses 763system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 764system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses | 749system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032907 # mshr miss rate for ReadReq accesses 750system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032907 # mshr miss rate for ReadReq accesses 751system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015283 # mshr miss rate for WriteReq accesses 752system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015283 # mshr miss rate for WriteReq accesses 753system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729898 # mshr miss rate for SoftPFReq accesses 754system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729898 # mshr miss rate for SoftPFReq accesses 755system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786417 # mshr miss rate for WriteLineReq accesses 756system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786417 # mshr miss rate for WriteLineReq accesses 757system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057340 # mshr miss rate for LoadLockedReq accesses 758system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057340 # mshr miss rate for LoadLockedReq accesses 759system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 760system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses |
| 765system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024604 # mshr miss rate for demand accesses 766system.cpu.dcache.demand_mshr_miss_rate::total 0.024604 # mshr miss rate for demand accesses 767system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028789 # mshr miss rate for overall accesses 768system.cpu.dcache.overall_mshr_miss_rate::total 0.028789 # mshr miss rate for overall accesses | 761system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028289 # mshr miss rate for demand accesses 762system.cpu.dcache.demand_mshr_miss_rate::total 0.028289 # mshr miss rate for demand accesses 763system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032432 # mshr miss rate for overall accesses 764system.cpu.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses |
| 769system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871 # average ReadReq mshr miss latency 770system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871 # average ReadReq mshr miss latency 771system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921 # average WriteReq mshr miss latency 772system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46809.563921 # average WriteReq mshr miss latency 773system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19033.667102 # average SoftPFReq mshr miss latency 774system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19033.667102 # average SoftPFReq mshr miss latency 775system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42116.567495 # average WriteLineReq mshr miss latency 776system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42116.567495 # average WriteLineReq mshr miss latency 777system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346 # average LoadLockedReq mshr miss latency 778system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346 # average LoadLockedReq mshr miss latency 779system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency 780system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency | 765system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871 # average ReadReq mshr miss latency 766system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871 # average ReadReq mshr miss latency 767system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921 # average WriteReq mshr miss latency 768system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46809.563921 # average WriteReq mshr miss latency 769system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19033.667102 # average SoftPFReq mshr miss latency 770system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19033.667102 # average SoftPFReq mshr miss latency 771system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42116.567495 # average WriteLineReq mshr miss latency 772system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42116.567495 # average WriteLineReq mshr miss latency 773system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346 # average LoadLockedReq mshr miss latency 774system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346 # average LoadLockedReq mshr miss latency 775system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency 776system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency |
| 781system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25922.963733 # average overall mshr miss latency 782system.cpu.dcache.demand_avg_mshr_miss_latency::total 25922.963733 # average overall mshr miss latency 783system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24886.499967 # average overall mshr miss latency 784system.cpu.dcache.overall_avg_mshr_miss_latency::total 24886.499967 # average overall mshr miss latency | 777system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716 # average overall mshr miss latency 778system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716 # average overall mshr miss latency 779system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661 # average overall mshr miss latency 780system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661 # average overall mshr miss latency |
| 785system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency 786system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency | 781system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency 782system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency |
| 787system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183702.174687 # average WriteReq mshr uncacheable latency 788system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183702.174687 # average WriteReq mshr uncacheable latency 789system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 183812.204205 # average overall mshr uncacheable latency 790system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 183812.204205 # average overall mshr uncacheable latency 791system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 783system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency 784system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency |
| 792system.cpu.icache.tags.replacements 24339101 # number of replacements 793system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use 794system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. 795system.cpu.icache.tags.sampled_refs 24339613 # Sample count of references to valid blocks. 796system.cpu.icache.tags.avg_refs 17.178953 # Average number of references to valid blocks. 797system.cpu.icache.tags.warmup_cycle 32773385500 # Cycle when the warmup percentage was hit. 798system.cpu.icache.tags.occ_blocks::cpu.inst 511.885333 # Average occupied blocks per requestor 799system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 842system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.629595 # average overall miss latency 843system.cpu.icache.overall_avg_miss_latency::total 13548.629595 # average overall miss latency 844system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 845system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 846system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 847system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 848system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 849system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 785system.cpu.icache.tags.replacements 24339101 # number of replacements 786system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use 787system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. 788system.cpu.icache.tags.sampled_refs 24339613 # Sample count of references to valid blocks. 789system.cpu.icache.tags.avg_refs 17.178953 # Average number of references to valid blocks. 790system.cpu.icache.tags.warmup_cycle 32773385500 # Cycle when the warmup percentage was hit. 791system.cpu.icache.tags.occ_blocks::cpu.inst 511.885333 # Average occupied blocks per requestor 792system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 835system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.629595 # average overall miss latency 836system.cpu.icache.overall_avg_miss_latency::total 13548.629595 # average overall miss latency 837system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 838system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 839system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 840system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 841system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 842system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 850system.cpu.icache.fast_writes 0 # number of fast writes performed 851system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 852system.cpu.icache.writebacks::writebacks 24339101 # number of writebacks 853system.cpu.icache.writebacks::total 24339101 # number of writebacks 854system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24339623 # number of ReadReq MSHR misses 855system.cpu.icache.ReadReq_mshr_misses::total 24339623 # number of ReadReq MSHR misses 856system.cpu.icache.demand_mshr_misses::cpu.inst 24339623 # number of demand (read+write) MSHR misses 857system.cpu.icache.demand_mshr_misses::total 24339623 # number of demand (read+write) MSHR misses 858system.cpu.icache.overall_mshr_misses::cpu.inst 24339623 # number of overall MSHR misses 859system.cpu.icache.overall_mshr_misses::total 24339623 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 882system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 883system.cpu.icache.demand_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 884system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 885system.cpu.icache.overall_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 886system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 887system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 888system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 889system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency | 843system.cpu.icache.writebacks::writebacks 24339101 # number of writebacks 844system.cpu.icache.writebacks::total 24339101 # number of writebacks 845system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24339623 # number of ReadReq MSHR misses 846system.cpu.icache.ReadReq_mshr_misses::total 24339623 # number of ReadReq MSHR misses 847system.cpu.icache.demand_mshr_misses::cpu.inst 24339623 # number of demand (read+write) MSHR misses 848system.cpu.icache.demand_mshr_misses::total 24339623 # number of demand (read+write) MSHR misses 849system.cpu.icache.overall_mshr_misses::cpu.inst 24339623 # number of overall MSHR misses 850system.cpu.icache.overall_mshr_misses::total 24339623 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 873system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 874system.cpu.icache.demand_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 875system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 876system.cpu.icache.overall_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 877system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 878system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 879system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 880system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency |
| 890system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 891system.cpu.l2cache.tags.replacements 1529682 # number of replacements 892system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use 893system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks. 894system.cpu.l2cache.tags.sampled_refs 1592715 # Sample count of references to valid blocks. 895system.cpu.l2cache.tags.avg_refs 41.651953 # Average number of references to valid blocks. 896system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit. 897system.cpu.l2cache.tags.occ_blocks::writebacks 36843.538434 # Average occupied blocks per requestor 898system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 325.022996 # Average occupied blocks per requestor --- 176 unchanged lines hidden (view full) --- 1075system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133510.013110 # average overall miss latency 1076system.cpu.l2cache.overall_avg_miss_latency::total 133443.783093 # average overall miss latency 1077system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1078system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1080system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1082system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 881system.cpu.l2cache.tags.replacements 1529682 # number of replacements 882system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use 883system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks. 884system.cpu.l2cache.tags.sampled_refs 1592715 # Sample count of references to valid blocks. 885system.cpu.l2cache.tags.avg_refs 41.651953 # Average number of references to valid blocks. 886system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit. 887system.cpu.l2cache.tags.occ_blocks::writebacks 36843.538434 # Average occupied blocks per requestor 888system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 325.022996 # Average occupied blocks per requestor --- 176 unchanged lines hidden (view full) --- 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133510.013110 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::total 133443.783093 # average overall miss latency 1067system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1068system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1069system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1070system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1071system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1072system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1083system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1084system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1085system.cpu.l2cache.writebacks::writebacks 1293856 # number of writebacks 1086system.cpu.l2cache.writebacks::total 1293856 # number of writebacks 1087system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1088system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1089system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1090system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1091system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1092system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits --- 59 unchanged lines hidden (view full) --- 1152system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 752655502 # number of overall MSHR miss cycles 1153system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 623664000 # number of overall MSHR miss cycles 1154system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13172156574 # number of overall MSHR miss cycles 1155system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119269491952 # number of overall MSHR miss cycles 1156system.cpu.l2cache.overall_mshr_miss_latency::total 133817968028 # number of overall MSHR miss cycles 1157system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles 1158system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776326000 # number of ReadReq MSHR uncacheable cycles 1159system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712400000 # number of ReadReq MSHR uncacheable cycles | 1073system.cpu.l2cache.writebacks::writebacks 1293856 # number of writebacks 1074system.cpu.l2cache.writebacks::total 1293856 # number of writebacks 1075system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1076system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1077system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1078system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1079system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1080system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits --- 59 unchanged lines hidden (view full) --- 1140system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 752655502 # number of overall MSHR miss cycles 1141system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 623664000 # number of overall MSHR miss cycles 1142system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13172156574 # number of overall MSHR miss cycles 1143system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119269491952 # number of overall MSHR miss cycles 1144system.cpu.l2cache.overall_mshr_miss_latency::total 133817968028 # number of overall MSHR miss cycles 1145system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles 1146system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776326000 # number of ReadReq MSHR uncacheable cycles 1147system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712400000 # number of ReadReq MSHR uncacheable cycles |
| 1160system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5803513500 # number of WriteReq MSHR uncacheable cycles 1161system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5803513500 # number of WriteReq MSHR uncacheable cycles | |
| 1162system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles | 1148system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles |
| 1163system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11579839500 # number of overall MSHR uncacheable cycles 1164system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17515913500 # number of overall MSHR uncacheable cycles | 1149system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5776326000 # number of overall MSHR uncacheable cycles 1150system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11712400000 # number of overall MSHR uncacheable cycles |
| 1165system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for ReadReq accesses 1166system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for ReadReq accesses 1167system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008952 # mshr miss rate for ReadReq accesses 1168system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1169system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1170system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782932 # mshr miss rate for UpgradeReq accesses 1171system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782932 # mshr miss rate for UpgradeReq accesses 1172system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses --- 39 unchanged lines hidden (view full) --- 1212system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency 1213system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency 1214system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency 1215system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency 1216system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123444.210366 # average overall mshr miss latency 1217system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency 1218system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171419.592249 # average ReadReq mshr uncacheable latency 1219system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136181.196661 # average ReadReq mshr uncacheable latency | 1151system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for ReadReq accesses 1152system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for ReadReq accesses 1153system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008952 # mshr miss rate for ReadReq accesses 1154system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1155system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1156system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782932 # mshr miss rate for UpgradeReq accesses 1157system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782932 # mshr miss rate for UpgradeReq accesses 1158system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses --- 39 unchanged lines hidden (view full) --- 1198system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency 1199system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency 1200system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency 1201system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency 1202system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123444.210366 # average overall mshr miss latency 1203system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency 1204system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171419.592249 # average ReadReq mshr uncacheable latency 1205system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136181.196661 # average ReadReq mshr uncacheable latency |
| 1220system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172180.427817 # average WriteReq mshr uncacheable latency 1221system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172180.427817 # average WriteReq mshr uncacheable latency | |
| 1222system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency | 1206system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency |
| 1223system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 171800.060828 # average overall mshr uncacheable latency 1224system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146317.106890 # average overall mshr uncacheable latency 1225system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1207system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85698.351705 # average overall mshr uncacheable latency 1208system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97838.144881 # average overall mshr uncacheable latency |
| 1226system.cpu.toL2Bus.snoop_filter.tot_requests 71082854 # Total number of requests made to the snoop filter. 1227system.cpu.toL2Bus.snoop_filter.hit_single_requests 35915919 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1228system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1229system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter. 1230system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1231system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1232system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution 1233system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution --- 140 unchanged lines hidden (view full) --- 1374system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1375system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses 1376system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses 1377system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1378system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1379system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1380system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1381system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 1209system.cpu.toL2Bus.snoop_filter.tot_requests 71082854 # Total number of requests made to the snoop filter. 1210system.cpu.toL2Bus.snoop_filter.hit_single_requests 35915919 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1211system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1212system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter. 1213system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1214system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1215system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution 1216system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution --- 140 unchanged lines hidden (view full) --- 1357system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1358system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses 1359system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses 1360system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1361system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1362system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1363system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1364system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 1382system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses 1383system.iocache.demand_misses::total 8879 # number of demand (read+write) misses | 1365system.iocache.demand_misses::realview.ide 115503 # number of demand (read+write) misses 1366system.iocache.demand_misses::total 115543 # number of demand (read+write) misses |
| 1384system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 1367system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 1385system.iocache.overall_misses::realview.ide 8839 # number of overall misses 1386system.iocache.overall_misses::total 8879 # number of overall misses | 1368system.iocache.overall_misses::realview.ide 115503 # number of overall misses 1369system.iocache.overall_misses::total 115543 # number of overall misses |
| 1387system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles 1388system.iocache.ReadReq_miss_latency::realview.ide 1644126101 # number of ReadReq miss cycles 1389system.iocache.ReadReq_miss_latency::total 1649196101 # number of ReadReq miss cycles 1390system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1391system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1392system.iocache.WriteLineReq_miss_latency::realview.ide 13411893006 # number of WriteLineReq miss cycles 1393system.iocache.WriteLineReq_miss_latency::total 13411893006 # number of WriteLineReq miss cycles 1394system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles | 1370system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles 1371system.iocache.ReadReq_miss_latency::realview.ide 1644126101 # number of ReadReq miss cycles 1372system.iocache.ReadReq_miss_latency::total 1649196101 # number of ReadReq miss cycles 1373system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1374system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1375system.iocache.WriteLineReq_miss_latency::realview.ide 13411893006 # number of WriteLineReq miss cycles 1376system.iocache.WriteLineReq_miss_latency::total 13411893006 # number of WriteLineReq miss cycles 1377system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles |
| 1395system.iocache.demand_miss_latency::realview.ide 1644126101 # number of demand (read+write) miss cycles 1396system.iocache.demand_miss_latency::total 1649547101 # number of demand (read+write) miss cycles | 1378system.iocache.demand_miss_latency::realview.ide 15056019107 # number of demand (read+write) miss cycles 1379system.iocache.demand_miss_latency::total 15061440107 # number of demand (read+write) miss cycles |
| 1397system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles | 1380system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles |
| 1398system.iocache.overall_miss_latency::realview.ide 1644126101 # number of overall miss cycles 1399system.iocache.overall_miss_latency::total 1649547101 # number of overall miss cycles | 1381system.iocache.overall_miss_latency::realview.ide 15056019107 # number of overall miss cycles 1382system.iocache.overall_miss_latency::total 15061440107 # number of overall miss cycles |
| 1400system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1401system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) 1402system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) 1403system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1404system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1405system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1406system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1407system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 1383system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1384system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) 1385system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) 1386system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1387system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1388system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1389system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1390system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 1408system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses 1409system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses | 1391system.iocache.demand_accesses::realview.ide 115503 # number of demand (read+write) accesses 1392system.iocache.demand_accesses::total 115543 # number of demand (read+write) accesses |
| 1410system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 1393system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 1411system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses 1412system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses | 1394system.iocache.overall_accesses::realview.ide 115503 # number of overall (read+write) accesses 1395system.iocache.overall_accesses::total 115543 # number of overall (read+write) accesses |
| 1413system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1414system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1415system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1416system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1417system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1418system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1419system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1420system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1426system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency 1427system.iocache.ReadReq_avg_miss_latency::realview.ide 186008.157144 # average ReadReq miss latency 1428system.iocache.ReadReq_avg_miss_latency::total 185803.977129 # average ReadReq miss latency 1429system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1430system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1431system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.640422 # average WriteLineReq miss latency 1432system.iocache.WriteLineReq_avg_miss_latency::total 125739.640422 # average WriteLineReq miss latency 1433system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency | 1396system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1397system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1398system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1399system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1400system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1401system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1402system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1403system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1409system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency 1410system.iocache.ReadReq_avg_miss_latency::realview.ide 186008.157144 # average ReadReq miss latency 1411system.iocache.ReadReq_avg_miss_latency::total 185803.977129 # average ReadReq miss latency 1412system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1413system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1414system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.640422 # average WriteLineReq miss latency 1415system.iocache.WriteLineReq_avg_miss_latency::total 125739.640422 # average WriteLineReq miss latency 1416system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency |
| 1434system.iocache.demand_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency 1435system.iocache.demand_avg_miss_latency::total 185780.729925 # average overall miss latency | 1417system.iocache.demand_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency 1418system.iocache.demand_avg_miss_latency::total 130353.548956 # average overall miss latency |
| 1436system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency | 1419system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency |
| 1437system.iocache.overall_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency 1438system.iocache.overall_avg_miss_latency::total 185780.729925 # average overall miss latency | 1420system.iocache.overall_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency 1421system.iocache.overall_avg_miss_latency::total 130353.548956 # average overall miss latency |
| 1439system.iocache.blocked_cycles::no_mshrs 32855 # number of cycles access was blocked 1440system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1441system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked 1442system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1443system.iocache.avg_blocked_cycles::no_mshrs 9.711794 # average number of cycles each access was blocked 1444system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1422system.iocache.blocked_cycles::no_mshrs 32855 # number of cycles access was blocked 1423system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1424system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked 1425system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1426system.iocache.avg_blocked_cycles::no_mshrs 9.711794 # average number of cycles each access was blocked 1427system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1445system.iocache.fast_writes 0 # number of fast writes performed 1446system.iocache.cache_copies 0 # number of cache copies performed | |
| 1447system.iocache.writebacks::writebacks 106630 # number of writebacks 1448system.iocache.writebacks::total 106630 # number of writebacks 1449system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1450system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses 1451system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses 1452system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1453system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1454system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1455system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1456system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 1428system.iocache.writebacks::writebacks 106630 # number of writebacks 1429system.iocache.writebacks::total 106630 # number of writebacks 1430system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1431system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses 1432system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses 1433system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1434system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1435system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1436system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1437system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 1457system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses 1458system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses | 1438system.iocache.demand_mshr_misses::realview.ide 115503 # number of demand (read+write) MSHR misses 1439system.iocache.demand_mshr_misses::total 115543 # number of demand (read+write) MSHR misses |
| 1459system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 1440system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 1460system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses 1461system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses | 1441system.iocache.overall_mshr_misses::realview.ide 115503 # number of overall MSHR misses 1442system.iocache.overall_mshr_misses::total 115543 # number of overall MSHR misses |
| 1462system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles 1463system.iocache.ReadReq_mshr_miss_latency::realview.ide 1202176101 # number of ReadReq MSHR miss cycles 1464system.iocache.ReadReq_mshr_miss_latency::total 1205396101 # number of ReadReq MSHR miss cycles 1465system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1466system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1467system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073547861 # number of WriteLineReq MSHR miss cycles 1468system.iocache.WriteLineReq_mshr_miss_latency::total 8073547861 # number of WriteLineReq MSHR miss cycles 1469system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles | 1443system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles 1444system.iocache.ReadReq_mshr_miss_latency::realview.ide 1202176101 # number of ReadReq MSHR miss cycles 1445system.iocache.ReadReq_mshr_miss_latency::total 1205396101 # number of ReadReq MSHR miss cycles 1446system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1447system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1448system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073547861 # number of WriteLineReq MSHR miss cycles 1449system.iocache.WriteLineReq_mshr_miss_latency::total 8073547861 # number of WriteLineReq MSHR miss cycles 1450system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles |
| 1470system.iocache.demand_mshr_miss_latency::realview.ide 1202176101 # number of demand (read+write) MSHR miss cycles 1471system.iocache.demand_mshr_miss_latency::total 1205597101 # number of demand (read+write) MSHR miss cycles | 1451system.iocache.demand_mshr_miss_latency::realview.ide 9275723962 # number of demand (read+write) MSHR miss cycles 1452system.iocache.demand_mshr_miss_latency::total 9279144962 # number of demand (read+write) MSHR miss cycles |
| 1472system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles | 1453system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles |
| 1473system.iocache.overall_mshr_miss_latency::realview.ide 1202176101 # number of overall MSHR miss cycles 1474system.iocache.overall_mshr_miss_latency::total 1205597101 # number of overall MSHR miss cycles | 1454system.iocache.overall_mshr_miss_latency::realview.ide 9275723962 # number of overall MSHR miss cycles 1455system.iocache.overall_mshr_miss_latency::total 9279144962 # number of overall MSHR miss cycles |
| 1475system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1476system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1477system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1478system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1479system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1480system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1481system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1482system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1488system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency 1489system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136008.157144 # average ReadReq mshr miss latency 1490system.iocache.ReadReq_avg_mshr_miss_latency::total 135803.977129 # average ReadReq mshr miss latency 1491system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1492system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1493system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482 # average WriteLineReq mshr miss latency 1494system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482 # average WriteLineReq mshr miss latency 1495system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency | 1456system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1457system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1458system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1459system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1460system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1461system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1462system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1463system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1469system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency 1470system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136008.157144 # average ReadReq mshr miss latency 1471system.iocache.ReadReq_avg_mshr_miss_latency::total 135803.977129 # average ReadReq mshr miss latency 1472system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1473system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1474system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482 # average WriteLineReq mshr miss latency 1475system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482 # average WriteLineReq mshr miss latency 1476system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency |
| 1496system.iocache.demand_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency 1497system.iocache.demand_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency | 1477system.iocache.demand_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency 1478system.iocache.demand_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency |
| 1498system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency | 1479system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency |
| 1499system.iocache.overall_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency 1500system.iocache.overall_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency 1501system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1480system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency 1481system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency |
| 1502system.membus.trans_dist::ReadReq 86006 # Transaction distribution 1503system.membus.trans_dist::ReadResp 535040 # Transaction distribution 1504system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1505system.membus.trans_dist::WriteResp 33706 # Transaction distribution 1506system.membus.trans_dist::WritebackDirty 1400486 # Transaction distribution 1507system.membus.trans_dist::CleanEvict 243574 # Transaction distribution 1508system.membus.trans_dist::UpgradeReq 38729 # Transaction distribution 1509system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 99 unchanged lines hidden --- | 1482system.membus.trans_dist::ReadReq 86006 # Transaction distribution 1483system.membus.trans_dist::ReadResp 535040 # Transaction distribution 1484system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1485system.membus.trans_dist::WriteResp 33706 # Transaction distribution 1486system.membus.trans_dist::WritebackDirty 1400486 # Transaction distribution 1487system.membus.trans_dist::CleanEvict 243574 # Transaction distribution 1488system.membus.trans_dist::UpgradeReq 38729 # Transaction distribution 1489system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 99 unchanged lines hidden --- |