| stats.txt (11245:1c5102c0a7a9) | stats.txt (11336:b318499f676c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 51.667482 # Number of seconds simulated 4sim_ticks 51667481628000 # Number of ticks simulated 5final_tick 51667481628000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 51.667476 # Number of seconds simulated 4sim_ticks 51667476471000 # Number of ticks simulated 5final_tick 51667476471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 173876 # Simulator instruction rate (inst/s) 8host_op_rate 204307 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9745015544 # Simulator tick rate (ticks/s) 10host_mem_usage 682548 # Number of bytes of host memory used 11host_seconds 5301.94 # Real time elapsed on the host 12sim_insts 921877826 # Number of instructions simulated 13sim_ops 1083223459 # Number of ops (including micro ops) simulated | 7host_inst_rate 274767 # Simulator instruction rate (inst/s) 8host_op_rate 322852 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15389929524 # Simulator tick rate (ticks/s) 10host_mem_usage 683068 # Number of bytes of host memory used 11host_seconds 3357.23 # Real time elapsed on the host 12sim_insts 922453344 # Number of instructions simulated 13sim_ops 1083887959 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.dtb.walker 355328 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 294720 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10221184 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 93611976 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 405568 # Number of bytes read from this memory 21system.physmem.bytes_read::total 104888776 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 10221184 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 10221184 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 87378688 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu.dtb.walker 349632 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 295488 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10205120 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 93689288 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 408000 # Number of bytes read from this memory 21system.physmem.bytes_read::total 104947528 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 10205120 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 10205120 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 87402048 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory | 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 87399268 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 5552 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 4605 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 159706 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1462700 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6337 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1638900 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1365292 # Number of write requests responded to by this memory | 26system.physmem.bytes_written::total 87422628 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 5463 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 4617 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 159455 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1463908 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6375 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1639818 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1365657 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory | 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 1367865 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 6877 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 5704 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 197826 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1811816 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7850 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2030073 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 197826 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 197826 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1691174 # Write bandwidth from this memory (bytes/s) | 35system.physmem.num_writes::total 1368230 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 6767 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 5719 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 197515 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1813313 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7897 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2031211 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 197515 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 197515 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1691626 # Write bandwidth from this memory (bytes/s) |
| 45system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) | 45system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_write::total 1691572 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1691174 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 6877 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 5704 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 197826 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1812214 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7850 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3721645 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1638900 # Number of read requests accepted 55system.physmem.writeReqs 1367865 # Number of write requests accepted 56system.physmem.readBursts 1638900 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1367865 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 104832704 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 56896 # Total number of bytes read from write queue 60system.physmem.bytesWritten 87398080 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 104888776 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 87399268 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 889 # Number of DRAM read bursts serviced by the write queue | 46system.physmem.bw_write::total 1692024 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1691626 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 6767 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 5719 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 197515 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1813711 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7897 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3723235 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1639818 # Number of read requests accepted 55system.physmem.writeReqs 1368230 # Number of write requests accepted 56system.physmem.readBursts 1639818 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1368230 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 104895040 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 53312 # Total number of bytes read from write queue 60system.physmem.bytesWritten 87421376 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 104947528 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 87422628 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 833 # Number of DRAM read bursts serviced by the write queue |
| 64system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one | 64system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one |
| 65system.physmem.neitherReadNorWriteReqs 381658 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 98450 # Per bank write bursts 67system.physmem.perBankRdBursts::1 107251 # Per bank write bursts 68system.physmem.perBankRdBursts::2 99188 # Per bank write bursts 69system.physmem.perBankRdBursts::3 95203 # Per bank write bursts 70system.physmem.perBankRdBursts::4 99955 # Per bank write bursts 71system.physmem.perBankRdBursts::5 109194 # Per bank write bursts 72system.physmem.perBankRdBursts::6 96838 # Per bank write bursts 73system.physmem.perBankRdBursts::7 98371 # Per bank write bursts 74system.physmem.perBankRdBursts::8 94736 # Per bank write bursts 75system.physmem.perBankRdBursts::9 155242 # Per bank write bursts 76system.physmem.perBankRdBursts::10 99865 # Per bank write bursts 77system.physmem.perBankRdBursts::11 104170 # Per bank write bursts 78system.physmem.perBankRdBursts::12 95009 # Per bank write bursts 79system.physmem.perBankRdBursts::13 96057 # Per bank write bursts 80system.physmem.perBankRdBursts::14 92133 # Per bank write bursts 81system.physmem.perBankRdBursts::15 96349 # Per bank write bursts 82system.physmem.perBankWrBursts::0 83734 # Per bank write bursts 83system.physmem.perBankWrBursts::1 87693 # Per bank write bursts 84system.physmem.perBankWrBursts::2 84639 # Per bank write bursts 85system.physmem.perBankWrBursts::3 83186 # Per bank write bursts 86system.physmem.perBankWrBursts::4 87134 # Per bank write bursts 87system.physmem.perBankWrBursts::5 92701 # Per bank write bursts 88system.physmem.perBankWrBursts::6 83787 # Per bank write bursts 89system.physmem.perBankWrBursts::7 85921 # Per bank write bursts 90system.physmem.perBankWrBursts::8 83051 # Per bank write bursts 91system.physmem.perBankWrBursts::9 88932 # Per bank write bursts 92system.physmem.perBankWrBursts::10 85543 # Per bank write bursts 93system.physmem.perBankWrBursts::11 89009 # Per bank write bursts 94system.physmem.perBankWrBursts::12 82580 # Per bank write bursts 95system.physmem.perBankWrBursts::13 83353 # Per bank write bursts 96system.physmem.perBankWrBursts::14 81127 # Per bank write bursts 97system.physmem.perBankWrBursts::15 83205 # Per bank write bursts | 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 99403 # Per bank write bursts 67system.physmem.perBankRdBursts::1 105228 # Per bank write bursts 68system.physmem.perBankRdBursts::2 100047 # Per bank write bursts 69system.physmem.perBankRdBursts::3 95494 # Per bank write bursts 70system.physmem.perBankRdBursts::4 102929 # Per bank write bursts 71system.physmem.perBankRdBursts::5 111535 # Per bank write bursts 72system.physmem.perBankRdBursts::6 97078 # Per bank write bursts 73system.physmem.perBankRdBursts::7 98055 # Per bank write bursts 74system.physmem.perBankRdBursts::8 92724 # Per bank write bursts 75system.physmem.perBankRdBursts::9 154002 # Per bank write bursts 76system.physmem.perBankRdBursts::10 99475 # Per bank write bursts 77system.physmem.perBankRdBursts::11 105000 # Per bank write bursts 78system.physmem.perBankRdBursts::12 94287 # Per bank write bursts 79system.physmem.perBankRdBursts::13 95690 # Per bank write bursts 80system.physmem.perBankRdBursts::14 90913 # Per bank write bursts 81system.physmem.perBankRdBursts::15 97125 # Per bank write bursts 82system.physmem.perBankWrBursts::0 83951 # Per bank write bursts 83system.physmem.perBankWrBursts::1 87043 # Per bank write bursts 84system.physmem.perBankWrBursts::2 85245 # Per bank write bursts 85system.physmem.perBankWrBursts::3 83208 # Per bank write bursts 86system.physmem.perBankWrBursts::4 88814 # Per bank write bursts 87system.physmem.perBankWrBursts::5 93904 # Per bank write bursts 88system.physmem.perBankWrBursts::6 83820 # Per bank write bursts 89system.physmem.perBankWrBursts::7 85248 # Per bank write bursts 90system.physmem.perBankWrBursts::8 81467 # Per bank write bursts 91system.physmem.perBankWrBursts::9 88240 # Per bank write bursts 92system.physmem.perBankWrBursts::10 85354 # Per bank write bursts 93system.physmem.perBankWrBursts::11 89463 # Per bank write bursts 94system.physmem.perBankWrBursts::12 82403 # Per bank write bursts 95system.physmem.perBankWrBursts::13 83577 # Per bank write bursts 96system.physmem.perBankWrBursts::14 80367 # Per bank write bursts 97system.physmem.perBankWrBursts::15 83855 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 99system.physmem.numWrRetry 16 # Number of times write queue was full causing retry 100system.physmem.totGap 51667479848500 # Total gap between requests | 99system.physmem.numWrRetry 37 # Number of times write queue was full causing retry 100system.physmem.totGap 51667474307000 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 1638885 # Read request sizes (log2) | 107system.physmem.readPktSize::6 1639803 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 1365292 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1312759 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 318962 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 959 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 345 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 478 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 511 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1145 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 673 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 324 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 336 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 152 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 107 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 73 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 1365657 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1314237 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 318417 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 337 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 465 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 530 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 537 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 676 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 362 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 180 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 67 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see |
| 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 14965 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 17095 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 65606 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 80418 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 82482 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 82286 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 83182 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 83357 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 85216 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 84108 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 84794 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 89394 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 84174 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 82879 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 91789 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 82005 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 83224 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 79922 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 737 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 475 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 485 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 517 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 349 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 386 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 336 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 305 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 376 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 223 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 220 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 299 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 210 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 199 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 153 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 148 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 138 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 113 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 131 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 101 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 78 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 647624 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 296.824083 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 173.411154 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 323.640423 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 254912 39.36% 39.36% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 156143 24.11% 63.47% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 60053 9.27% 72.74% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 34984 5.40% 78.15% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 25631 3.96% 82.10% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 18733 2.89% 85.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 14068 2.17% 87.17% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 12825 1.98% 89.15% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 70275 10.85% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 647624 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 79231 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 20.673638 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 283.409553 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-4095 79228 100.00% 100.00% # Reads before turning the bus around for writes | 162system.physmem.wrQLenPdf::15 14698 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 18189 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 67736 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 80790 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 82454 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 81257 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 81296 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 82033 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 83039 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 82637 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 83634 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 86681 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 83517 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 83880 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 94578 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 83323 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 84131 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 81331 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 2502 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 677 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 616 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 411 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 474 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 481 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 385 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 283 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 418 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 298 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 289 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 282 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 267 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 263 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 296 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 241 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 222 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 230 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 242 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 145 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 147 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 151 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 153 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 129 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 160 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 206 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 646147 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 297.635603 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 173.901229 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 324.036577 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 253673 39.26% 39.26% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 155474 24.06% 63.32% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 60360 9.34% 72.66% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 34960 5.41% 78.07% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 25496 3.95% 82.02% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 18768 2.90% 84.92% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 14047 2.17% 87.10% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 13088 2.03% 89.12% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 70281 10.88% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 646147 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 79019 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 20.741467 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 283.796699 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-4095 79016 100.00% 100.00% # Reads before turning the bus around for writes |
| 229system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes | 229system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 232system.physmem.rdPerTurnAround::total 79231 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 79231 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.235615 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 16.796201 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 6.303380 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 76926 97.09% 97.09% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 319 0.40% 97.49% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 70 0.09% 97.58% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 321 0.41% 97.99% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 45 0.06% 98.04% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 342 0.43% 98.48% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 202 0.25% 98.73% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 22 0.03% 98.76% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 52 0.07% 98.82% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 126 0.16% 98.98% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 31 0.04% 99.02% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 49 0.06% 99.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 483 0.61% 99.69% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 36 0.05% 99.74% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 14 0.02% 99.76% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 128 0.16% 99.92% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 11 0.01% 99.93% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 3 0.00% 99.94% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 3 0.00% 99.94% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 1 0.00% 99.95% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::120-123 2 0.00% 99.95% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::128-131 28 0.04% 99.99% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 2 0.00% 99.99% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::total 79231 # Writes before turning the bus around for reads 267system.physmem.totQLat 26417109815 # Total ticks spent queuing 268system.physmem.totMemAccLat 57129816065 # Total ticks spent from burst creation until serviced by the DRAM 269system.physmem.totBusLat 8190055000 # Total ticks spent in databus transfers 270system.physmem.avgQLat 16127.55 # Average queueing delay per DRAM burst | 232system.physmem.rdPerTurnAround::total 79019 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 79019 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.286463 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 16.794878 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 6.949851 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 76956 97.39% 97.39% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 330 0.42% 97.81% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 47 0.06% 97.87% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 101 0.13% 97.99% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 35 0.04% 98.04% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 85 0.11% 98.15% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 245 0.31% 98.46% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 21 0.03% 98.48% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 324 0.41% 98.89% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 69 0.09% 98.98% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 26 0.03% 99.01% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 53 0.07% 99.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 312 0.39% 99.47% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 39 0.05% 99.52% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 28 0.04% 99.56% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 118 0.15% 99.71% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 171 0.22% 99.93% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-179 6 0.01% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::total 79019 # Writes before turning the bus around for reads 274system.physmem.totQLat 26490910104 # Total ticks spent queuing 275system.physmem.totMemAccLat 57221878854 # Total ticks spent from burst creation until serviced by the DRAM 276system.physmem.totBusLat 8194925000 # Total ticks spent in databus transfers 277system.physmem.avgQLat 16163.00 # Average queueing delay per DRAM burst |
| 271system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 272system.physmem.avgMemAccLat 34877.55 # Average memory access latency per DRAM burst | 279system.physmem.avgMemAccLat 34913.00 # Average memory access latency per DRAM burst |
| 273system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s 274system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s 275system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s 276system.physmem.avgWrBWSys 1.69 # Average system write bandwidth in MiByte/s 277system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 278system.physmem.busUtil 0.03 # Data bus utilization in percentage 279system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 280system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 281system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 280system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s 281system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s 282system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s 283system.physmem.avgWrBWSys 1.69 # Average system write bandwidth in MiByte/s 284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 285system.physmem.busUtil 0.03 # Data bus utilization in percentage 286system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 287system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 288system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 282system.physmem.avgWrQLen 25.24 # Average write queue length when enqueuing 283system.physmem.readRowHits 1331553 # Number of row buffer hits during reads 284system.physmem.writeRowHits 1024428 # Number of row buffer hits during writes 285system.physmem.readRowHitRate 81.29 # Row buffer hit rate for reads 286system.physmem.writeRowHitRate 75.02 # Row buffer hit rate for writes 287system.physmem.avgGap 17183743.94 # Average gap between requests 288system.physmem.pageHitRate 78.44 # Row buffer hit rate, read and write combined 289system.physmem_0.actEnergy 2488253040 # Energy for activate commands per rank (pJ) 290system.physmem_0.preEnergy 1357677750 # Energy for precharge commands per rank (pJ) 291system.physmem_0.readEnergy 6274663200 # Energy for read commands per rank (pJ) 292system.physmem_0.writeEnergy 4463391600 # Energy for write commands per rank (pJ) | 289system.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing 290system.physmem.readRowHits 1332864 # Number of row buffer hits during reads 291system.physmem.writeRowHits 1025932 # Number of row buffer hits during writes 292system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads 293system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes 294system.physmem.avgGap 17176412.85 # Average gap between requests 295system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined 296system.physmem_0.actEnergy 2496243960 # Energy for activate commands per rank (pJ) 297system.physmem_0.preEnergy 1362037875 # Energy for precharge commands per rank (pJ) 298system.physmem_0.readEnergy 6316198200 # Energy for read commands per rank (pJ) 299system.physmem_0.writeEnergy 4479189840 # Energy for write commands per rank (pJ) |
| 293system.physmem_0.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) | 300system.physmem_0.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) |
| 294system.physmem_0.actBackEnergy 1321909933950 # Energy for active background per rank (pJ) 295system.physmem_0.preBackEnergy 29840915681250 # Energy for precharge background per rank (pJ) 296system.physmem_0.totalEnergy 34552077975270 # Total energy per rank (pJ) 297system.physmem_0.averagePower 668.739417 # Core power per rank (mW) 298system.physmem_0.memoryStateTime::IDLE 49642099754241 # Time in different power states | 301system.physmem_0.actBackEnergy 1323055672425 # Energy for active background per rank (pJ) 302system.physmem_0.preBackEnergy 29839910639250 # Energy for precharge background per rank (pJ) 303system.physmem_0.totalEnergy 34552288356030 # Total energy per rank (pJ) 304system.physmem_0.averagePower 668.743489 # Core power per rank (mW) 305system.physmem_0.memoryStateTime::IDLE 49640417958020 # Time in different power states |
| 299system.physmem_0.memoryStateTime::REF 1725290580000 # Time in different power states 300system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 306system.physmem_0.memoryStateTime::REF 1725290580000 # Time in different power states 307system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 301system.physmem_0.memoryStateTime::ACT 300090521259 # Time in different power states | 308system.physmem_0.memoryStateTime::ACT 301767793230 # Time in different power states |
| 302system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 309system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 303system.physmem_1.actEnergy 2407784400 # Energy for activate commands per rank (pJ) 304system.physmem_1.preEnergy 1313771250 # Energy for precharge commands per rank (pJ) 305system.physmem_1.readEnergy 6501775800 # Energy for read commands per rank (pJ) 306system.physmem_1.writeEnergy 4385664000 # Energy for write commands per rank (pJ) | 310system.physmem_1.actEnergy 2388627360 # Energy for activate commands per rank (pJ) 311system.physmem_1.preEnergy 1303318500 # Energy for precharge commands per rank (pJ) 312system.physmem_1.readEnergy 6467877000 # Energy for read commands per rank (pJ) 313system.physmem_1.writeEnergy 4372224480 # Energy for write commands per rank (pJ) |
| 307system.physmem_1.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) | 314system.physmem_1.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) |
| 308system.physmem_1.actBackEnergy 1318271769585 # Energy for active background per rank (pJ) 309system.physmem_1.preBackEnergy 29844107045250 # Energy for precharge background per rank (pJ) 310system.physmem_1.totalEnergy 34551656184765 # Total energy per rank (pJ) 311system.physmem_1.averagePower 668.731253 # Core power per rank (mW) 312system.physmem_1.memoryStateTime::IDLE 49647373564820 # Time in different power states | 315system.physmem_1.actBackEnergy 1316624734350 # Energy for active background per rank (pJ) 316system.physmem_1.preBackEnergy 29845551821250 # Energy for precharge background per rank (pJ) 317system.physmem_1.totalEnergy 34551376977420 # Total energy per rank (pJ) 318system.physmem_1.averagePower 668.725849 # Core power per rank (mW) 319system.physmem_1.memoryStateTime::IDLE 49649780004526 # Time in different power states |
| 313system.physmem_1.memoryStateTime::REF 1725290580000 # Time in different power states 314system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 320system.physmem_1.memoryStateTime::REF 1725290580000 # Time in different power states 321system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 315system.physmem_1.memoryStateTime::ACT 294812186430 # Time in different power states | 322system.physmem_1.memoryStateTime::ACT 292405760474 # Time in different power states |
| 316system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 317system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 318system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 319system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 320system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 321system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 322system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 323system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory --- 7 unchanged lines hidden (view full) --- 331system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 332system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 333system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 334system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 335system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 336system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 337system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 338system.cf0.dma_write_txs 1669 # Number of DMA write transactions. | 323system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 324system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 327system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 328system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 329system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 330system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory --- 7 unchanged lines hidden (view full) --- 338system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 340system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 341system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 342system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 343system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 344system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 345system.cf0.dma_write_txs 1669 # Number of DMA write transactions. |
| 339system.cpu.branchPred.lookups 252485837 # Number of BP lookups 340system.cpu.branchPred.condPredicted 176433570 # Number of conditional branches predicted 341system.cpu.branchPred.condIncorrect 11949823 # Number of conditional branches incorrect 342system.cpu.branchPred.BTBLookups 185211535 # Number of BTB lookups 343system.cpu.branchPred.BTBHits 131480802 # Number of BTB hits | 346system.cpu.branchPred.lookups 252598760 # Number of BP lookups 347system.cpu.branchPred.condPredicted 176508431 # Number of conditional branches predicted 348system.cpu.branchPred.condIncorrect 11957032 # Number of conditional branches incorrect 349system.cpu.branchPred.BTBLookups 185598793 # Number of BTB lookups 350system.cpu.branchPred.BTBHits 131565493 # Number of BTB hits |
| 344system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 351system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 345system.cpu.branchPred.BTBHitPct 70.989532 # BTB Hit Percentage 346system.cpu.branchPred.usedRAS 30949299 # Number of times the RAS was used to get a target. 347system.cpu.branchPred.RASInCorrect 2133828 # Number of incorrect RAS predictions. | 352system.cpu.branchPred.BTBHitPct 70.887041 # BTB Hit Percentage 353system.cpu.branchPred.usedRAS 30959293 # Number of times the RAS was used to get a target. 354system.cpu.branchPred.RASInCorrect 2131771 # Number of incorrect RAS predictions. |
| 348system.cpu_clk_domain.clock 500 # Clock period in ticks 349system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 370system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 371system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 372system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 373system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 374system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 375system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 376system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 377system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 355system.cpu_clk_domain.clock 500 # Clock period in ticks 356system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 377system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 378system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 379system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 380system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 381system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 382system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 383system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 384system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 378system.cpu.dtb.walker.walks 560555 # Table walker walks requested 379system.cpu.dtb.walker.walksLong 560555 # Table walker walks initiated with long descriptors 380system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20820 # Level at which table walker walks with long descriptors terminate 381system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178520 # Level at which table walker walks with long descriptors terminate 382system.cpu.dtb.walker.walkWaitTime::samples 560555 # Table walker wait (enqueue to first request) latency 383system.cpu.dtb.walker.walkWaitTime::0 560555 100.00% 100.00% # Table walker wait (enqueue to first request) latency 384system.cpu.dtb.walker.walkWaitTime::total 560555 # Table walker wait (enqueue to first request) latency 385system.cpu.dtb.walker.walkCompletionTime::samples 199340 # Table walker service (enqueue to completion) latency 386system.cpu.dtb.walker.walkCompletionTime::mean 27109.310725 # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::gmean 22940.792106 # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walkCompletionTime::stdev 20958.396260 # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::0-65535 197062 98.86% 98.86% # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::65536-131071 8 0.00% 98.86% # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::131072-196607 1944 0.98% 99.84% # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::196608-262143 53 0.03% 99.86% # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::262144-327679 116 0.06% 99.92% # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::327680-393215 50 0.03% 99.95% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::393216-458751 75 0.04% 99.98% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::458752-524287 14 0.01% 99.99% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency | 385system.cpu.dtb.walker.walks 560635 # Table walker walks requested 386system.cpu.dtb.walker.walksLong 560635 # Table walker walks initiated with long descriptors 387system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20884 # Level at which table walker walks with long descriptors terminate 388system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178593 # Level at which table walker walks with long descriptors terminate 389system.cpu.dtb.walker.walkWaitTime::samples 560635 # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkWaitTime::0 560635 100.00% 100.00% # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::total 560635 # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkCompletionTime::samples 199477 # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::mean 26985.070961 # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::gmean 22842.355807 # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::stdev 20873.513445 # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::0-65535 197251 98.88% 98.88% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.89% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::131072-196607 1888 0.95% 99.83% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::196608-262143 57 0.03% 99.86% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::262144-327679 109 0.05% 99.92% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::327680-393215 46 0.02% 99.94% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::393216-458751 97 0.05% 99.99% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 398system.cpu.dtb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency | 405system.cpu.dtb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 399system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::total 199340 # Table walker service (enqueue to completion) latency | 406system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::total 199477 # Table walker service (enqueue to completion) latency |
| 401system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution 402system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution 403system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution | 408system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution 409system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution 410system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution |
| 404system.cpu.dtb.walker.walkPageSizes::4K 178521 89.56% 89.56% # Table walker page sizes translated 405system.cpu.dtb.walker.walkPageSizes::2M 20820 10.44% 100.00% # Table walker page sizes translated 406system.cpu.dtb.walker.walkPageSizes::total 199341 # Table walker page sizes translated 407system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560555 # Table walker requests started/completed, data/inst | 411system.cpu.dtb.walker.walkPageSizes::4K 178594 89.53% 89.53% # Table walker page sizes translated 412system.cpu.dtb.walker.walkPageSizes::2M 20884 10.47% 100.00% # Table walker page sizes translated 413system.cpu.dtb.walker.walkPageSizes::total 199478 # Table walker page sizes translated 414system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560635 # Table walker requests started/completed, data/inst |
| 408system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 415system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 409system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560555 # Table walker requests started/completed, data/inst 410system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199341 # Table walker requests started/completed, data/inst | 416system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560635 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199478 # Table walker requests started/completed, data/inst |
| 411system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 418system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 412system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199341 # Table walker requests started/completed, data/inst 413system.cpu.dtb.walker.walkRequestOrigin::total 759896 # Table walker requests started/completed, data/inst | 419system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199478 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin::total 760113 # Table walker requests started/completed, data/inst |
| 414system.cpu.dtb.inst_hits 0 # ITB inst hits 415system.cpu.dtb.inst_misses 0 # ITB inst misses | 421system.cpu.dtb.inst_hits 0 # ITB inst hits 422system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 416system.cpu.dtb.read_hits 178230117 # DTB read hits 417system.cpu.dtb.read_misses 462749 # DTB read misses 418system.cpu.dtb.write_hits 157902959 # DTB write hits 419system.cpu.dtb.write_misses 97806 # DTB write misses | 423system.cpu.dtb.read_hits 178339564 # DTB read hits 424system.cpu.dtb.read_misses 462901 # DTB read misses 425system.cpu.dtb.write_hits 158016400 # DTB write hits 426system.cpu.dtb.write_misses 97734 # DTB write misses |
| 420system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 421system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 422system.cpu.dtb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID 423system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID | 427system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 428system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 429system.cpu.dtb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID 430system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID |
| 424system.cpu.dtb.flush_entries 78363 # Number of entries that have been flushed from TLB 425system.cpu.dtb.align_faults 1414 # Number of TLB faults due to alignment restrictions 426system.cpu.dtb.prefetch_faults 14783 # Number of TLB faults due to prefetch | 431system.cpu.dtb.flush_entries 78401 # Number of entries that have been flushed from TLB 432system.cpu.dtb.align_faults 1394 # Number of TLB faults due to alignment restrictions 433system.cpu.dtb.prefetch_faults 14946 # Number of TLB faults due to prefetch |
| 427system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 434system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 428system.cpu.dtb.perms_faults 23068 # Number of TLB faults due to permissions restrictions 429system.cpu.dtb.read_accesses 178692866 # DTB read accesses 430system.cpu.dtb.write_accesses 158000765 # DTB write accesses | 435system.cpu.dtb.perms_faults 23063 # Number of TLB faults due to permissions restrictions 436system.cpu.dtb.read_accesses 178802465 # DTB read accesses 437system.cpu.dtb.write_accesses 158114134 # DTB write accesses |
| 431system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 438system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 432system.cpu.dtb.hits 336133076 # DTB hits 433system.cpu.dtb.misses 560555 # DTB misses 434system.cpu.dtb.accesses 336693631 # DTB accesses | 439system.cpu.dtb.hits 336355964 # DTB hits 440system.cpu.dtb.misses 560635 # DTB misses 441system.cpu.dtb.accesses 336916599 # DTB accesses |
| 435system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 436system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 437system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 438system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 439system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 456system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 457system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 458system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 459system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 460system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 461system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 462system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 463system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 442system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 463system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 464system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 465system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 466system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 467system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 468system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 469system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 470system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 464system.cpu.itb.walker.walks 134868 # Table walker walks requested 465system.cpu.itb.walker.walksLong 134868 # Table walker walks initiated with long descriptors 466system.cpu.itb.walker.walksLongTerminationLevel::Level2 1077 # Level at which table walker walks with long descriptors terminate 467system.cpu.itb.walker.walksLongTerminationLevel::Level3 117569 # Level at which table walker walks with long descriptors terminate 468system.cpu.itb.walker.walkWaitTime::samples 134868 # Table walker wait (enqueue to first request) latency 469system.cpu.itb.walker.walkWaitTime::0 134868 100.00% 100.00% # Table walker wait (enqueue to first request) latency 470system.cpu.itb.walker.walkWaitTime::total 134868 # Table walker wait (enqueue to first request) latency 471system.cpu.itb.walker.walkCompletionTime::samples 118646 # Table walker service (enqueue to completion) latency 472system.cpu.itb.walker.walkCompletionTime::mean 30429.546719 # Table walker service (enqueue to completion) latency 473system.cpu.itb.walker.walkCompletionTime::gmean 26050.717125 # Table walker service (enqueue to completion) latency 474system.cpu.itb.walker.walkCompletionTime::stdev 23099.528150 # Table walker service (enqueue to completion) latency 475system.cpu.itb.walker.walkCompletionTime::0-65535 116148 97.89% 97.89% # Table walker service (enqueue to completion) latency 476system.cpu.itb.walker.walkCompletionTime::65536-131071 8 0.01% 97.90% # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::131072-196607 2266 1.91% 99.81% # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::196608-262143 70 0.06% 99.87% # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::262144-327679 116 0.10% 99.97% # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.98% # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::total 118646 # Table walker service (enqueue to completion) latency | 471system.cpu.itb.walker.walks 134932 # Table walker walks requested 472system.cpu.itb.walker.walksLong 134932 # Table walker walks initiated with long descriptors 473system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate 474system.cpu.itb.walker.walksLongTerminationLevel::Level3 117658 # Level at which table walker walks with long descriptors terminate 475system.cpu.itb.walker.walkWaitTime::samples 134932 # Table walker wait (enqueue to first request) latency 476system.cpu.itb.walker.walkWaitTime::0 134932 100.00% 100.00% # Table walker wait (enqueue to first request) latency 477system.cpu.itb.walker.walkWaitTime::total 134932 # Table walker wait (enqueue to first request) latency 478system.cpu.itb.walker.walkCompletionTime::samples 118737 # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::mean 30245.892182 # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::gmean 25862.614601 # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::stdev 23195.505917 # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::0-32767 58684 49.42% 49.42% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::32768-65535 57510 48.43% 97.86% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::65536-98303 2 0.00% 97.86% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::98304-131071 7 0.01% 97.87% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::131072-163839 1905 1.60% 99.47% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::163840-196607 424 0.36% 99.83% # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::196608-229375 23 0.02% 99.85% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::229376-262143 17 0.01% 99.86% # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::262144-294911 94 0.08% 99.94% # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::294912-327679 21 0.02% 99.96% # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::327680-360447 17 0.01% 99.97% # Table walker service (enqueue to completion) latency 493system.cpu.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::393216-425983 17 0.01% 99.99% # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walkCompletionTime::425984-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency 496system.cpu.itb.walker.walkCompletionTime::total 118737 # Table walker service (enqueue to completion) latency |
| 485system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution 486system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution 487system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution | 497system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution 498system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution 499system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution |
| 488system.cpu.itb.walker.walkPageSizes::4K 117569 99.09% 99.09% # Table walker page sizes translated 489system.cpu.itb.walker.walkPageSizes::2M 1077 0.91% 100.00% # Table walker page sizes translated 490system.cpu.itb.walker.walkPageSizes::total 118646 # Table walker page sizes translated | 500system.cpu.itb.walker.walkPageSizes::4K 117658 99.09% 99.09% # Table walker page sizes translated 501system.cpu.itb.walker.walkPageSizes::2M 1079 0.91% 100.00% # Table walker page sizes translated 502system.cpu.itb.walker.walkPageSizes::total 118737 # Table walker page sizes translated |
| 491system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 503system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 492system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134868 # Table walker requests started/completed, data/inst 493system.cpu.itb.walker.walkRequestOrigin_Requested::total 134868 # Table walker requests started/completed, data/inst | 504system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134932 # Table walker requests started/completed, data/inst 505system.cpu.itb.walker.walkRequestOrigin_Requested::total 134932 # Table walker requests started/completed, data/inst |
| 494system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 506system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 495system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118646 # Table walker requests started/completed, data/inst 496system.cpu.itb.walker.walkRequestOrigin_Completed::total 118646 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin::total 253514 # Table walker requests started/completed, data/inst 498system.cpu.itb.inst_hits 438855637 # ITB inst hits 499system.cpu.itb.inst_misses 134868 # ITB inst misses | 507system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118737 # Table walker requests started/completed, data/inst 508system.cpu.itb.walker.walkRequestOrigin_Completed::total 118737 # Table walker requests started/completed, data/inst 509system.cpu.itb.walker.walkRequestOrigin::total 253669 # Table walker requests started/completed, data/inst 510system.cpu.itb.inst_hits 439091546 # ITB inst hits 511system.cpu.itb.inst_misses 134932 # ITB inst misses |
| 500system.cpu.itb.read_hits 0 # DTB read hits 501system.cpu.itb.read_misses 0 # DTB read misses 502system.cpu.itb.write_hits 0 # DTB write hits 503system.cpu.itb.write_misses 0 # DTB write misses 504system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 505system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 506system.cpu.itb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID 507system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID | 512system.cpu.itb.read_hits 0 # DTB read hits 513system.cpu.itb.read_misses 0 # DTB read misses 514system.cpu.itb.write_hits 0 # DTB write hits 515system.cpu.itb.write_misses 0 # DTB write misses 516system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 517system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 518system.cpu.itb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID 519system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID |
| 508system.cpu.itb.flush_entries 56516 # Number of entries that have been flushed from TLB | 520system.cpu.itb.flush_entries 56478 # Number of entries that have been flushed from TLB |
| 509system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 510system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 511system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 521system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 522system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 523system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 512system.cpu.itb.perms_faults 359281 # Number of TLB faults due to permissions restrictions | 524system.cpu.itb.perms_faults 354973 # Number of TLB faults due to permissions restrictions |
| 513system.cpu.itb.read_accesses 0 # DTB read accesses 514system.cpu.itb.write_accesses 0 # DTB write accesses | 525system.cpu.itb.read_accesses 0 # DTB read accesses 526system.cpu.itb.write_accesses 0 # DTB write accesses |
| 515system.cpu.itb.inst_accesses 438990505 # ITB inst accesses 516system.cpu.itb.hits 438855637 # DTB hits 517system.cpu.itb.misses 134868 # DTB misses 518system.cpu.itb.accesses 438990505 # DTB accesses 519system.cpu.numCycles 2563496972 # number of cpu cycles simulated | 527system.cpu.itb.inst_accesses 439226478 # ITB inst accesses 528system.cpu.itb.hits 439091546 # DTB hits 529system.cpu.itb.misses 134932 # DTB misses 530system.cpu.itb.accesses 439226478 # DTB accesses 531system.cpu.numCycles 2564620605 # number of cpu cycles simulated |
| 520system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 521system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 532system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 533system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 522system.cpu.committedInsts 921877826 # Number of instructions committed 523system.cpu.committedOps 1083223459 # Number of ops (including micro ops) committed 524system.cpu.discardedOps 92885181 # Number of ops (including micro ops) which were discarded before commit 525system.cpu.numFetchSuspends 7623 # Number of times Execute suspended instruction fetching 526system.cpu.quiesceCycles 100772604966 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 527system.cpu.cpi 2.780734 # CPI: cycles per instruction 528system.cpu.ipc 0.359617 # IPC: instructions per cycle | 534system.cpu.committedInsts 922453344 # Number of instructions committed 535system.cpu.committedOps 1083887959 # Number of ops (including micro ops) committed 536system.cpu.discardedOps 92875630 # Number of ops (including micro ops) which were discarded before commit 537system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching 538system.cpu.quiesceCycles 100771468164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 539system.cpu.cpi 2.780217 # CPI: cycles per instruction 540system.cpu.ipc 0.359684 # IPC: instructions per cycle |
| 529system.cpu.kern.inst.arm 0 # number of arm instructions executed | 541system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 530system.cpu.kern.inst.quiesce 16483 # number of quiesce instructions executed 531system.cpu.tickCycles 1740911334 # Number of cycles that the object actually ticked 532system.cpu.idleCycles 822585638 # Total number of cycles that the object has spent stopped 533system.cpu.dcache.tags.replacements 10734176 # number of replacements 534system.cpu.dcache.tags.tagsinuse 511.930080 # Cycle average of tags in use 535system.cpu.dcache.tags.total_refs 320289523 # Total number of references to valid blocks. 536system.cpu.dcache.tags.sampled_refs 10734688 # Sample count of references to valid blocks. 537system.cpu.dcache.tags.avg_refs 29.836873 # Average number of references to valid blocks. | 542system.cpu.kern.inst.quiesce 16482 # number of quiesce instructions executed 543system.cpu.tickCycles 1741581813 # Number of cycles that the object actually ticked 544system.cpu.idleCycles 823038792 # Total number of cycles that the object has spent stopped 545system.cpu.dcache.tags.replacements 10731841 # number of replacements 546system.cpu.dcache.tags.tagsinuse 511.930081 # Cycle average of tags in use 547system.cpu.dcache.tags.total_refs 320513038 # Total number of references to valid blocks. 548system.cpu.dcache.tags.sampled_refs 10732353 # Sample count of references to valid blocks. 549system.cpu.dcache.tags.avg_refs 29.864191 # Average number of references to valid blocks. |
| 538system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. | 550system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. |
| 539system.cpu.dcache.tags.occ_blocks::cpu.data 511.930080 # Average occupied blocks per requestor | 551system.cpu.dcache.tags.occ_blocks::cpu.data 511.930081 # Average occupied blocks per requestor |
| 540system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 541system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 542system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 552system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 553system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 554system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 543system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 544system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id 545system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 546system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id | 555system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 556system.cpu.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id 557system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 558system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id |
| 547system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 559system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 548system.cpu.dcache.tags.tag_accesses 1345515853 # Number of tag accesses 549system.cpu.dcache.tags.data_accesses 1345515853 # Number of data accesses 550system.cpu.dcache.ReadReq_hits::cpu.data 163941297 # number of ReadReq hits 551system.cpu.dcache.ReadReq_hits::total 163941297 # number of ReadReq hits 552system.cpu.dcache.WriteReq_hits::cpu.data 147439641 # number of WriteReq hits 553system.cpu.dcache.WriteReq_hits::total 147439641 # number of WriteReq hits 554system.cpu.dcache.SoftPFReq_hits::cpu.data 511618 # number of SoftPFReq hits 555system.cpu.dcache.SoftPFReq_hits::total 511618 # number of SoftPFReq hits 556system.cpu.dcache.WriteLineReq_hits::cpu.data 335027 # number of WriteLineReq hits 557system.cpu.dcache.WriteLineReq_hits::total 335027 # number of WriteLineReq hits 558system.cpu.dcache.LoadLockedReq_hits::cpu.data 3852667 # number of LoadLockedReq hits 559system.cpu.dcache.LoadLockedReq_hits::total 3852667 # number of LoadLockedReq hits 560system.cpu.dcache.StoreCondReq_hits::cpu.data 4161339 # number of StoreCondReq hits 561system.cpu.dcache.StoreCondReq_hits::total 4161339 # number of StoreCondReq hits 562system.cpu.dcache.demand_hits::cpu.data 311380938 # number of demand (read+write) hits 563system.cpu.dcache.demand_hits::total 311380938 # number of demand (read+write) hits 564system.cpu.dcache.overall_hits::cpu.data 311892556 # number of overall hits 565system.cpu.dcache.overall_hits::total 311892556 # number of overall hits 566system.cpu.dcache.ReadReq_misses::cpu.data 6369353 # number of ReadReq misses 567system.cpu.dcache.ReadReq_misses::total 6369353 # number of ReadReq misses 568system.cpu.dcache.WriteReq_misses::cpu.data 4134165 # number of WriteReq misses 569system.cpu.dcache.WriteReq_misses::total 4134165 # number of WriteReq misses 570system.cpu.dcache.SoftPFReq_misses::cpu.data 1400138 # number of SoftPFReq misses 571system.cpu.dcache.SoftPFReq_misses::total 1400138 # number of SoftPFReq misses 572system.cpu.dcache.WriteLineReq_misses::cpu.data 1239654 # number of WriteLineReq misses 573system.cpu.dcache.WriteLineReq_misses::total 1239654 # number of WriteLineReq misses 574system.cpu.dcache.LoadLockedReq_misses::cpu.data 310380 # number of LoadLockedReq misses 575system.cpu.dcache.LoadLockedReq_misses::total 310380 # number of LoadLockedReq misses | 560system.cpu.dcache.tags.tag_accesses 1346389769 # Number of tag accesses 561system.cpu.dcache.tags.data_accesses 1346389769 # Number of data accesses 562system.cpu.dcache.ReadReq_hits::cpu.data 164045150 # number of ReadReq hits 563system.cpu.dcache.ReadReq_hits::total 164045150 # number of ReadReq hits 564system.cpu.dcache.WriteReq_hits::cpu.data 147553918 # number of WriteReq hits 565system.cpu.dcache.WriteReq_hits::total 147553918 # number of WriteReq hits 566system.cpu.dcache.SoftPFReq_hits::cpu.data 512343 # number of SoftPFReq hits 567system.cpu.dcache.SoftPFReq_hits::total 512343 # number of SoftPFReq hits 568system.cpu.dcache.WriteLineReq_hits::cpu.data 335860 # number of WriteLineReq hits 569system.cpu.dcache.WriteLineReq_hits::total 335860 # number of WriteLineReq hits 570system.cpu.dcache.LoadLockedReq_hits::cpu.data 3854660 # number of LoadLockedReq hits 571system.cpu.dcache.LoadLockedReq_hits::total 3854660 # number of LoadLockedReq hits 572system.cpu.dcache.StoreCondReq_hits::cpu.data 4163151 # number of StoreCondReq hits 573system.cpu.dcache.StoreCondReq_hits::total 4163151 # number of StoreCondReq hits 574system.cpu.dcache.demand_hits::cpu.data 311599068 # number of demand (read+write) hits 575system.cpu.dcache.demand_hits::total 311599068 # number of demand (read+write) hits 576system.cpu.dcache.overall_hits::cpu.data 312111411 # number of overall hits 577system.cpu.dcache.overall_hits::total 312111411 # number of overall hits 578system.cpu.dcache.ReadReq_misses::cpu.data 6370722 # number of ReadReq misses 579system.cpu.dcache.ReadReq_misses::total 6370722 # number of ReadReq misses 580system.cpu.dcache.WriteReq_misses::cpu.data 4130704 # number of WriteReq misses 581system.cpu.dcache.WriteReq_misses::total 4130704 # number of WriteReq misses 582system.cpu.dcache.SoftPFReq_misses::cpu.data 1398816 # number of SoftPFReq misses 583system.cpu.dcache.SoftPFReq_misses::total 1398816 # number of SoftPFReq misses 584system.cpu.dcache.WriteLineReq_misses::cpu.data 1238819 # number of WriteLineReq misses 585system.cpu.dcache.WriteLineReq_misses::total 1238819 # number of WriteLineReq misses 586system.cpu.dcache.LoadLockedReq_misses::cpu.data 310200 # number of LoadLockedReq misses 587system.cpu.dcache.LoadLockedReq_misses::total 310200 # number of LoadLockedReq misses |
| 576system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 577system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses | 588system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 589system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses |
| 578system.cpu.dcache.demand_misses::cpu.data 10503518 # number of demand (read+write) misses 579system.cpu.dcache.demand_misses::total 10503518 # number of demand (read+write) misses 580system.cpu.dcache.overall_misses::cpu.data 11903656 # number of overall misses 581system.cpu.dcache.overall_misses::total 11903656 # number of overall misses 582system.cpu.dcache.ReadReq_miss_latency::cpu.data 117431334000 # number of ReadReq miss cycles 583system.cpu.dcache.ReadReq_miss_latency::total 117431334000 # number of ReadReq miss cycles 584system.cpu.dcache.WriteReq_miss_latency::cpu.data 199634806500 # number of WriteReq miss cycles 585system.cpu.dcache.WriteReq_miss_latency::total 199634806500 # number of WriteReq miss cycles 586system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 84591152000 # number of WriteLineReq miss cycles 587system.cpu.dcache.WriteLineReq_miss_latency::total 84591152000 # number of WriteLineReq miss cycles 588system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5133902500 # number of LoadLockedReq miss cycles 589system.cpu.dcache.LoadLockedReq_miss_latency::total 5133902500 # number of LoadLockedReq miss cycles | 590system.cpu.dcache.demand_misses::cpu.data 10501426 # number of demand (read+write) misses 591system.cpu.dcache.demand_misses::total 10501426 # number of demand (read+write) misses 592system.cpu.dcache.overall_misses::cpu.data 11900242 # number of overall misses 593system.cpu.dcache.overall_misses::total 11900242 # number of overall misses 594system.cpu.dcache.ReadReq_miss_latency::cpu.data 117402431000 # number of ReadReq miss cycles 595system.cpu.dcache.ReadReq_miss_latency::total 117402431000 # number of ReadReq miss cycles 596system.cpu.dcache.WriteReq_miss_latency::cpu.data 199951337000 # number of WriteReq miss cycles 597system.cpu.dcache.WriteReq_miss_latency::total 199951337000 # number of WriteReq miss cycles 598system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 84556806000 # number of WriteLineReq miss cycles 599system.cpu.dcache.WriteLineReq_miss_latency::total 84556806000 # number of WriteLineReq miss cycles 600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5139718000 # number of LoadLockedReq miss cycles 601system.cpu.dcache.LoadLockedReq_miss_latency::total 5139718000 # number of LoadLockedReq miss cycles |
| 590system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles 591system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles | 602system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles 603system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles |
| 592system.cpu.dcache.demand_miss_latency::cpu.data 317066140500 # number of demand (read+write) miss cycles 593system.cpu.dcache.demand_miss_latency::total 317066140500 # number of demand (read+write) miss cycles 594system.cpu.dcache.overall_miss_latency::cpu.data 317066140500 # number of overall miss cycles 595system.cpu.dcache.overall_miss_latency::total 317066140500 # number of overall miss cycles 596system.cpu.dcache.ReadReq_accesses::cpu.data 170310650 # number of ReadReq accesses(hits+misses) 597system.cpu.dcache.ReadReq_accesses::total 170310650 # number of ReadReq accesses(hits+misses) 598system.cpu.dcache.WriteReq_accesses::cpu.data 151573806 # number of WriteReq accesses(hits+misses) 599system.cpu.dcache.WriteReq_accesses::total 151573806 # number of WriteReq accesses(hits+misses) 600system.cpu.dcache.SoftPFReq_accesses::cpu.data 1911756 # number of SoftPFReq accesses(hits+misses) 601system.cpu.dcache.SoftPFReq_accesses::total 1911756 # number of SoftPFReq accesses(hits+misses) 602system.cpu.dcache.WriteLineReq_accesses::cpu.data 1574681 # number of WriteLineReq accesses(hits+misses) 603system.cpu.dcache.WriteLineReq_accesses::total 1574681 # number of WriteLineReq accesses(hits+misses) 604system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4163047 # number of LoadLockedReq accesses(hits+misses) 605system.cpu.dcache.LoadLockedReq_accesses::total 4163047 # number of LoadLockedReq accesses(hits+misses) 606system.cpu.dcache.StoreCondReq_accesses::cpu.data 4161340 # number of StoreCondReq accesses(hits+misses) 607system.cpu.dcache.StoreCondReq_accesses::total 4161340 # number of StoreCondReq accesses(hits+misses) 608system.cpu.dcache.demand_accesses::cpu.data 321884456 # number of demand (read+write) accesses 609system.cpu.dcache.demand_accesses::total 321884456 # number of demand (read+write) accesses 610system.cpu.dcache.overall_accesses::cpu.data 323796212 # number of overall (read+write) accesses 611system.cpu.dcache.overall_accesses::total 323796212 # number of overall (read+write) accesses 612system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037398 # miss rate for ReadReq accesses 613system.cpu.dcache.ReadReq_miss_rate::total 0.037398 # miss rate for ReadReq accesses 614system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027275 # miss rate for WriteReq accesses 615system.cpu.dcache.WriteReq_miss_rate::total 0.027275 # miss rate for WriteReq accesses 616system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.732383 # miss rate for SoftPFReq accesses 617system.cpu.dcache.SoftPFReq_miss_rate::total 0.732383 # miss rate for SoftPFReq accesses 618system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787241 # miss rate for WriteLineReq accesses 619system.cpu.dcache.WriteLineReq_miss_rate::total 0.787241 # miss rate for WriteLineReq accesses 620system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074556 # miss rate for LoadLockedReq accesses 621system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074556 # miss rate for LoadLockedReq accesses | 604system.cpu.dcache.demand_miss_latency::cpu.data 317353768000 # number of demand (read+write) miss cycles 605system.cpu.dcache.demand_miss_latency::total 317353768000 # number of demand (read+write) miss cycles 606system.cpu.dcache.overall_miss_latency::cpu.data 317353768000 # number of overall miss cycles 607system.cpu.dcache.overall_miss_latency::total 317353768000 # number of overall miss cycles 608system.cpu.dcache.ReadReq_accesses::cpu.data 170415872 # number of ReadReq accesses(hits+misses) 609system.cpu.dcache.ReadReq_accesses::total 170415872 # number of ReadReq accesses(hits+misses) 610system.cpu.dcache.WriteReq_accesses::cpu.data 151684622 # number of WriteReq accesses(hits+misses) 611system.cpu.dcache.WriteReq_accesses::total 151684622 # number of WriteReq accesses(hits+misses) 612system.cpu.dcache.SoftPFReq_accesses::cpu.data 1911159 # number of SoftPFReq accesses(hits+misses) 613system.cpu.dcache.SoftPFReq_accesses::total 1911159 # number of SoftPFReq accesses(hits+misses) 614system.cpu.dcache.WriteLineReq_accesses::cpu.data 1574679 # number of WriteLineReq accesses(hits+misses) 615system.cpu.dcache.WriteLineReq_accesses::total 1574679 # number of WriteLineReq accesses(hits+misses) 616system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4164860 # number of LoadLockedReq accesses(hits+misses) 617system.cpu.dcache.LoadLockedReq_accesses::total 4164860 # number of LoadLockedReq accesses(hits+misses) 618system.cpu.dcache.StoreCondReq_accesses::cpu.data 4163152 # number of StoreCondReq accesses(hits+misses) 619system.cpu.dcache.StoreCondReq_accesses::total 4163152 # number of StoreCondReq accesses(hits+misses) 620system.cpu.dcache.demand_accesses::cpu.data 322100494 # number of demand (read+write) accesses 621system.cpu.dcache.demand_accesses::total 322100494 # number of demand (read+write) accesses 622system.cpu.dcache.overall_accesses::cpu.data 324011653 # number of overall (read+write) accesses 623system.cpu.dcache.overall_accesses::total 324011653 # number of overall (read+write) accesses 624system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037383 # miss rate for ReadReq accesses 625system.cpu.dcache.ReadReq_miss_rate::total 0.037383 # miss rate for ReadReq accesses 626system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027232 # miss rate for WriteReq accesses 627system.cpu.dcache.WriteReq_miss_rate::total 0.027232 # miss rate for WriteReq accesses 628system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.731920 # miss rate for SoftPFReq accesses 629system.cpu.dcache.SoftPFReq_miss_rate::total 0.731920 # miss rate for SoftPFReq accesses 630system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786712 # miss rate for WriteLineReq accesses 631system.cpu.dcache.WriteLineReq_miss_rate::total 0.786712 # miss rate for WriteLineReq accesses 632system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074480 # miss rate for LoadLockedReq accesses 633system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074480 # miss rate for LoadLockedReq accesses |
| 622system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 623system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses | 634system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 635system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses |
| 624system.cpu.dcache.demand_miss_rate::cpu.data 0.032631 # miss rate for demand accesses 625system.cpu.dcache.demand_miss_rate::total 0.032631 # miss rate for demand accesses 626system.cpu.dcache.overall_miss_rate::cpu.data 0.036763 # miss rate for overall accesses 627system.cpu.dcache.overall_miss_rate::total 0.036763 # miss rate for overall accesses 628system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18436.932919 # average ReadReq miss latency 629system.cpu.dcache.ReadReq_avg_miss_latency::total 18436.932919 # average ReadReq miss latency 630system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48289.027288 # average WriteReq miss latency 631system.cpu.dcache.WriteReq_avg_miss_latency::total 48289.027288 # average WriteReq miss latency 632system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68237.711490 # average WriteLineReq miss latency 633system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68237.711490 # average WriteLineReq miss latency 634system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16540.700110 # average LoadLockedReq miss latency 635system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16540.700110 # average LoadLockedReq miss latency | 636system.cpu.dcache.demand_miss_rate::cpu.data 0.032603 # miss rate for demand accesses 637system.cpu.dcache.demand_miss_rate::total 0.032603 # miss rate for demand accesses 638system.cpu.dcache.overall_miss_rate::cpu.data 0.036728 # miss rate for overall accesses 639system.cpu.dcache.overall_miss_rate::total 0.036728 # miss rate for overall accesses 640system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18428.434171 # average ReadReq miss latency 641system.cpu.dcache.ReadReq_avg_miss_latency::total 18428.434171 # average ReadReq miss latency 642system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48406.116003 # average WriteReq miss latency 643system.cpu.dcache.WriteReq_avg_miss_latency::total 48406.116003 # average WriteReq miss latency 644system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68255.980898 # average WriteLineReq miss latency 645system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68255.980898 # average WriteLineReq miss latency 646system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.045777 # average LoadLockedReq miss latency 647system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.045777 # average LoadLockedReq miss latency |
| 636system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 637system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency | 648system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 649system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency |
| 638system.cpu.dcache.demand_avg_miss_latency::cpu.data 30186.661317 # average overall miss latency 639system.cpu.dcache.demand_avg_miss_latency::total 30186.661317 # average overall miss latency 640system.cpu.dcache.overall_avg_miss_latency::cpu.data 26636.030183 # average overall miss latency 641system.cpu.dcache.overall_avg_miss_latency::total 26636.030183 # average overall miss latency | 650system.cpu.dcache.demand_avg_miss_latency::cpu.data 30220.064208 # average overall miss latency 651system.cpu.dcache.demand_avg_miss_latency::total 30220.064208 # average overall miss latency 652system.cpu.dcache.overall_avg_miss_latency::cpu.data 26667.841545 # average overall miss latency 653system.cpu.dcache.overall_avg_miss_latency::total 26667.841545 # average overall miss latency |
| 642system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 643system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 645system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 646system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 647system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.cpu.dcache.fast_writes 0 # number of fast writes performed 649system.cpu.dcache.cache_copies 0 # number of cache copies performed | 654system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 655system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 656system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 657system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 658system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 659system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 660system.cpu.dcache.fast_writes 0 # number of fast writes performed 661system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 650system.cpu.dcache.writebacks::writebacks 8245378 # number of writebacks 651system.cpu.dcache.writebacks::total 8245378 # number of writebacks 652system.cpu.dcache.ReadReq_mshr_hits::cpu.data 770684 # number of ReadReq MSHR hits 653system.cpu.dcache.ReadReq_mshr_hits::total 770684 # number of ReadReq MSHR hits 654system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1822945 # number of WriteReq MSHR hits 655system.cpu.dcache.WriteReq_mshr_hits::total 1822945 # number of WriteReq MSHR hits 656system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits 657system.cpu.dcache.WriteLineReq_mshr_hits::total 152 # number of WriteLineReq MSHR hits 658system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69756 # number of LoadLockedReq MSHR hits 659system.cpu.dcache.LoadLockedReq_mshr_hits::total 69756 # number of LoadLockedReq MSHR hits 660system.cpu.dcache.demand_mshr_hits::cpu.data 2593629 # number of demand (read+write) MSHR hits 661system.cpu.dcache.demand_mshr_hits::total 2593629 # number of demand (read+write) MSHR hits 662system.cpu.dcache.overall_mshr_hits::cpu.data 2593629 # number of overall MSHR hits 663system.cpu.dcache.overall_mshr_hits::total 2593629 # number of overall MSHR hits 664system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5598669 # number of ReadReq MSHR misses 665system.cpu.dcache.ReadReq_mshr_misses::total 5598669 # number of ReadReq MSHR misses 666system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2311220 # number of WriteReq MSHR misses 667system.cpu.dcache.WriteReq_mshr_misses::total 2311220 # number of WriteReq MSHR misses 668system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1392587 # number of SoftPFReq MSHR misses 669system.cpu.dcache.SoftPFReq_mshr_misses::total 1392587 # number of SoftPFReq MSHR misses 670system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1239502 # number of WriteLineReq MSHR misses 671system.cpu.dcache.WriteLineReq_mshr_misses::total 1239502 # number of WriteLineReq MSHR misses 672system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 240624 # number of LoadLockedReq MSHR misses 673system.cpu.dcache.LoadLockedReq_mshr_misses::total 240624 # number of LoadLockedReq MSHR misses | 662system.cpu.dcache.writebacks::writebacks 8243774 # number of writebacks 663system.cpu.dcache.writebacks::total 8243774 # number of writebacks 664system.cpu.dcache.ReadReq_mshr_hits::cpu.data 770626 # number of ReadReq MSHR hits 665system.cpu.dcache.ReadReq_mshr_hits::total 770626 # number of ReadReq MSHR hits 666system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821654 # number of WriteReq MSHR hits 667system.cpu.dcache.WriteReq_mshr_hits::total 1821654 # number of WriteReq MSHR hits 668system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 153 # number of WriteLineReq MSHR hits 669system.cpu.dcache.WriteLineReq_mshr_hits::total 153 # number of WriteLineReq MSHR hits 670system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68982 # number of LoadLockedReq MSHR hits 671system.cpu.dcache.LoadLockedReq_mshr_hits::total 68982 # number of LoadLockedReq MSHR hits 672system.cpu.dcache.demand_mshr_hits::cpu.data 2592280 # number of demand (read+write) MSHR hits 673system.cpu.dcache.demand_mshr_hits::total 2592280 # number of demand (read+write) MSHR hits 674system.cpu.dcache.overall_mshr_hits::cpu.data 2592280 # number of overall MSHR hits 675system.cpu.dcache.overall_mshr_hits::total 2592280 # number of overall MSHR hits 676system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5600096 # number of ReadReq MSHR misses 677system.cpu.dcache.ReadReq_mshr_misses::total 5600096 # number of ReadReq MSHR misses 678system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2309050 # number of WriteReq MSHR misses 679system.cpu.dcache.WriteReq_mshr_misses::total 2309050 # number of WriteReq MSHR misses 680system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1391260 # number of SoftPFReq MSHR misses 681system.cpu.dcache.SoftPFReq_mshr_misses::total 1391260 # number of SoftPFReq MSHR misses 682system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238666 # number of WriteLineReq MSHR misses 683system.cpu.dcache.WriteLineReq_mshr_misses::total 1238666 # number of WriteLineReq MSHR misses 684system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241218 # number of LoadLockedReq MSHR misses 685system.cpu.dcache.LoadLockedReq_mshr_misses::total 241218 # number of LoadLockedReq MSHR misses |
| 674system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 675system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses | 686system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 687system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses |
| 676system.cpu.dcache.demand_mshr_misses::cpu.data 7909889 # number of demand (read+write) MSHR misses 677system.cpu.dcache.demand_mshr_misses::total 7909889 # number of demand (read+write) MSHR misses 678system.cpu.dcache.overall_mshr_misses::cpu.data 9302476 # number of overall MSHR misses 679system.cpu.dcache.overall_mshr_misses::total 9302476 # number of overall MSHR misses | 688system.cpu.dcache.demand_mshr_misses::cpu.data 7909146 # number of demand (read+write) MSHR misses 689system.cpu.dcache.demand_mshr_misses::total 7909146 # number of demand (read+write) MSHR misses 690system.cpu.dcache.overall_mshr_misses::cpu.data 9300406 # number of overall MSHR misses 691system.cpu.dcache.overall_mshr_misses::total 9300406 # number of overall MSHR misses |
| 680system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 681system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 682system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 683system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 684system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 685system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses | 692system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 693system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 694system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 695system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 696system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 697system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses |
| 686system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96111391500 # number of ReadReq MSHR miss cycles 687system.cpu.dcache.ReadReq_mshr_miss_latency::total 96111391500 # number of ReadReq MSHR miss cycles 688system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105871130000 # number of WriteReq MSHR miss cycles 689system.cpu.dcache.WriteReq_mshr_miss_latency::total 105871130000 # number of WriteReq MSHR miss cycles 690system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26586103000 # number of SoftPFReq MSHR miss cycles 691system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26586103000 # number of SoftPFReq MSHR miss cycles 692system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83345106500 # number of WriteLineReq MSHR miss cycles 693system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83345106500 # number of WriteLineReq MSHR miss cycles 694system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3481164500 # number of LoadLockedReq MSHR miss cycles 695system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3481164500 # number of LoadLockedReq MSHR miss cycles | 698system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96067975500 # number of ReadReq MSHR miss cycles 699system.cpu.dcache.ReadReq_mshr_miss_latency::total 96067975500 # number of ReadReq MSHR miss cycles 700system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106000226500 # number of WriteReq MSHR miss cycles 701system.cpu.dcache.WriteReq_mshr_miss_latency::total 106000226500 # number of WriteReq MSHR miss cycles 702system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26589323500 # number of SoftPFReq MSHR miss cycles 703system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26589323500 # number of SoftPFReq MSHR miss cycles 704system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83310681500 # number of WriteLineReq MSHR miss cycles 705system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83310681500 # number of WriteLineReq MSHR miss cycles 706system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3491728500 # number of LoadLockedReq MSHR miss cycles 707system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3491728500 # number of LoadLockedReq MSHR miss cycles |
| 696system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles 697system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles | 708system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles 709system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles |
| 698system.cpu.dcache.demand_mshr_miss_latency::cpu.data 201982521500 # number of demand (read+write) MSHR miss cycles 699system.cpu.dcache.demand_mshr_miss_latency::total 201982521500 # number of demand (read+write) MSHR miss cycles 700system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228568624500 # number of overall MSHR miss cycles 701system.cpu.dcache.overall_mshr_miss_latency::total 228568624500 # number of overall MSHR miss cycles 702system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197557500 # number of ReadReq MSHR uncacheable cycles 703system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197557500 # number of ReadReq MSHR uncacheable cycles 704system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207394000 # number of WriteReq MSHR uncacheable cycles 705system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207394000 # number of WriteReq MSHR uncacheable cycles 706system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404951500 # number of overall MSHR uncacheable cycles 707system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404951500 # number of overall MSHR uncacheable cycles 708system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032873 # mshr miss rate for ReadReq accesses 709system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032873 # mshr miss rate for ReadReq accesses 710system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015248 # mshr miss rate for WriteReq accesses 711system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015248 # mshr miss rate for WriteReq accesses 712system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728433 # mshr miss rate for SoftPFReq accesses 713system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728433 # mshr miss rate for SoftPFReq accesses 714system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787145 # mshr miss rate for WriteLineReq accesses 715system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787145 # mshr miss rate for WriteLineReq accesses 716system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057800 # mshr miss rate for LoadLockedReq accesses 717system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057800 # mshr miss rate for LoadLockedReq accesses | 710system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202068202000 # number of demand (read+write) MSHR miss cycles 711system.cpu.dcache.demand_mshr_miss_latency::total 202068202000 # number of demand (read+write) MSHR miss cycles 712system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228657525500 # number of overall MSHR miss cycles 713system.cpu.dcache.overall_mshr_miss_latency::total 228657525500 # number of overall MSHR miss cycles 714system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197287500 # number of ReadReq MSHR uncacheable cycles 715system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197287500 # number of ReadReq MSHR uncacheable cycles 716system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207449000 # number of WriteReq MSHR uncacheable cycles 717system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207449000 # number of WriteReq MSHR uncacheable cycles 718system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404736500 # number of overall MSHR uncacheable cycles 719system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404736500 # number of overall MSHR uncacheable cycles 720system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032861 # mshr miss rate for ReadReq accesses 721system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032861 # mshr miss rate for ReadReq accesses 722system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015223 # mshr miss rate for WriteReq accesses 723system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015223 # mshr miss rate for WriteReq accesses 724system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.727967 # mshr miss rate for SoftPFReq accesses 725system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.727967 # mshr miss rate for SoftPFReq accesses 726system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786615 # mshr miss rate for WriteLineReq accesses 727system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786615 # mshr miss rate for WriteLineReq accesses 728system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057917 # mshr miss rate for LoadLockedReq accesses 729system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057917 # mshr miss rate for LoadLockedReq accesses |
| 718system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 719system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses | 730system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 731system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses |
| 720system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024574 # mshr miss rate for demand accesses 721system.cpu.dcache.demand_mshr_miss_rate::total 0.024574 # mshr miss rate for demand accesses 722system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028729 # mshr miss rate for overall accesses 723system.cpu.dcache.overall_mshr_miss_rate::total 0.028729 # mshr miss rate for overall accesses 724system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17166.828669 # average ReadReq mshr miss latency 725system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17166.828669 # average ReadReq mshr miss latency 726system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45807.465321 # average WriteReq mshr miss latency 727system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45807.465321 # average WriteReq mshr miss latency 728system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19091.161270 # average SoftPFReq mshr miss latency 729system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19091.161270 # average SoftPFReq mshr miss latency 730system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67240.800338 # average WriteLineReq mshr miss latency 731system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67240.800338 # average WriteLineReq mshr miss latency 732system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14467.237266 # average LoadLockedReq mshr miss latency 733system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14467.237266 # average LoadLockedReq mshr miss latency | 732system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024555 # mshr miss rate for demand accesses 733system.cpu.dcache.demand_mshr_miss_rate::total 0.024555 # mshr miss rate for demand accesses 734system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028704 # mshr miss rate for overall accesses 735system.cpu.dcache.overall_mshr_miss_rate::total 0.028704 # mshr miss rate for overall accesses 736system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17154.701544 # average ReadReq mshr miss latency 737system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17154.701544 # average ReadReq mshr miss latency 738system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45906.423204 # average WriteReq mshr miss latency 739system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45906.423204 # average WriteReq mshr miss latency 740system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19111.685451 # average SoftPFReq mshr miss latency 741system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19111.685451 # average SoftPFReq mshr miss latency 742system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67258.390478 # average WriteLineReq mshr miss latency 743system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67258.390478 # average WriteLineReq mshr miss latency 744system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14475.406064 # average LoadLockedReq mshr miss latency 745system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14475.406064 # average LoadLockedReq mshr miss latency |
| 734system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 735system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency | 746system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 747system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency |
| 736system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25535.443228 # average overall mshr miss latency 737system.cpu.dcache.demand_avg_mshr_miss_latency::total 25535.443228 # average overall mshr miss latency 738system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24570.729825 # average overall mshr miss latency 739system.cpu.dcache.overall_avg_mshr_miss_latency::total 24570.729825 # average overall mshr miss latency 740system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183920.156097 # average ReadReq mshr uncacheable latency 741system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183920.156097 # average ReadReq mshr uncacheable latency 742system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184162.879013 # average WriteReq mshr uncacheable latency 743system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184162.879013 # average WriteReq mshr uncacheable latency 744system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184041.533760 # average overall mshr uncacheable latency 745system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184041.533760 # average overall mshr uncacheable latency | 748system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25548.675167 # average overall mshr miss latency 749system.cpu.dcache.demand_avg_mshr_miss_latency::total 25548.675167 # average overall mshr miss latency 750system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24585.757385 # average overall mshr miss latency 751system.cpu.dcache.overall_avg_mshr_miss_latency::total 24585.757385 # average overall mshr miss latency 752system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183912.143514 # average ReadReq mshr uncacheable latency 753system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183912.143514 # average ReadReq mshr uncacheable latency 754system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184164.510770 # average WriteReq mshr uncacheable latency 755system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184164.510770 # average WriteReq mshr uncacheable latency 756system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184038.343991 # average overall mshr uncacheable latency 757system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184038.343991 # average overall mshr uncacheable latency |
| 746system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 758system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 747system.cpu.icache.tags.replacements 24166189 # number of replacements | 759system.cpu.icache.tags.replacements 24176986 # number of replacements |
| 748system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use | 760system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use |
| 749system.cpu.icache.tags.total_refs 414317362 # Total number of references to valid blocks. 750system.cpu.icache.tags.sampled_refs 24166701 # Sample count of references to valid blocks. 751system.cpu.icache.tags.avg_refs 17.144142 # Average number of references to valid blocks. | 761system.cpu.icache.tags.total_refs 414546703 # Total number of references to valid blocks. 762system.cpu.icache.tags.sampled_refs 24177498 # Sample count of references to valid blocks. 763system.cpu.icache.tags.avg_refs 17.145972 # Average number of references to valid blocks. |
| 752system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit. 753system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor 754system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy 755system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy 756system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 764system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit. 765system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor 766system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy 767system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy 768system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 757system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 758system.cpu.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 759system.cpu.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id | 769system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 770system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 771system.cpu.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id |
| 760system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 772system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 761system.cpu.icache.tags.tag_accesses 462650783 # Number of tag accesses 762system.cpu.icache.tags.data_accesses 462650783 # Number of data accesses 763system.cpu.icache.ReadReq_hits::cpu.inst 414317362 # number of ReadReq hits 764system.cpu.icache.ReadReq_hits::total 414317362 # number of ReadReq hits 765system.cpu.icache.demand_hits::cpu.inst 414317362 # number of demand (read+write) hits 766system.cpu.icache.demand_hits::total 414317362 # number of demand (read+write) hits 767system.cpu.icache.overall_hits::cpu.inst 414317362 # number of overall hits 768system.cpu.icache.overall_hits::total 414317362 # number of overall hits 769system.cpu.icache.ReadReq_misses::cpu.inst 24166711 # number of ReadReq misses 770system.cpu.icache.ReadReq_misses::total 24166711 # number of ReadReq misses 771system.cpu.icache.demand_misses::cpu.inst 24166711 # number of demand (read+write) misses 772system.cpu.icache.demand_misses::total 24166711 # number of demand (read+write) misses 773system.cpu.icache.overall_misses::cpu.inst 24166711 # number of overall misses 774system.cpu.icache.overall_misses::total 24166711 # number of overall misses 775system.cpu.icache.ReadReq_miss_latency::cpu.inst 327482385000 # number of ReadReq miss cycles 776system.cpu.icache.ReadReq_miss_latency::total 327482385000 # number of ReadReq miss cycles 777system.cpu.icache.demand_miss_latency::cpu.inst 327482385000 # number of demand (read+write) miss cycles 778system.cpu.icache.demand_miss_latency::total 327482385000 # number of demand (read+write) miss cycles 779system.cpu.icache.overall_miss_latency::cpu.inst 327482385000 # number of overall miss cycles 780system.cpu.icache.overall_miss_latency::total 327482385000 # number of overall miss cycles 781system.cpu.icache.ReadReq_accesses::cpu.inst 438484073 # number of ReadReq accesses(hits+misses) 782system.cpu.icache.ReadReq_accesses::total 438484073 # number of ReadReq accesses(hits+misses) 783system.cpu.icache.demand_accesses::cpu.inst 438484073 # number of demand (read+write) accesses 784system.cpu.icache.demand_accesses::total 438484073 # number of demand (read+write) accesses 785system.cpu.icache.overall_accesses::cpu.inst 438484073 # number of overall (read+write) accesses 786system.cpu.icache.overall_accesses::total 438484073 # number of overall (read+write) accesses 787system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055114 # miss rate for ReadReq accesses 788system.cpu.icache.ReadReq_miss_rate::total 0.055114 # miss rate for ReadReq accesses 789system.cpu.icache.demand_miss_rate::cpu.inst 0.055114 # miss rate for demand accesses 790system.cpu.icache.demand_miss_rate::total 0.055114 # miss rate for demand accesses 791system.cpu.icache.overall_miss_rate::cpu.inst 0.055114 # miss rate for overall accesses 792system.cpu.icache.overall_miss_rate::total 0.055114 # miss rate for overall accesses 793system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13550.970382 # average ReadReq miss latency 794system.cpu.icache.ReadReq_avg_miss_latency::total 13550.970382 # average ReadReq miss latency 795system.cpu.icache.demand_avg_miss_latency::cpu.inst 13550.970382 # average overall miss latency 796system.cpu.icache.demand_avg_miss_latency::total 13550.970382 # average overall miss latency 797system.cpu.icache.overall_avg_miss_latency::cpu.inst 13550.970382 # average overall miss latency 798system.cpu.icache.overall_avg_miss_latency::total 13550.970382 # average overall miss latency | 773system.cpu.icache.tags.tag_accesses 462901718 # Number of tag accesses 774system.cpu.icache.tags.data_accesses 462901718 # Number of data accesses 775system.cpu.icache.ReadReq_hits::cpu.inst 414546703 # number of ReadReq hits 776system.cpu.icache.ReadReq_hits::total 414546703 # number of ReadReq hits 777system.cpu.icache.demand_hits::cpu.inst 414546703 # number of demand (read+write) hits 778system.cpu.icache.demand_hits::total 414546703 # number of demand (read+write) hits 779system.cpu.icache.overall_hits::cpu.inst 414546703 # number of overall hits 780system.cpu.icache.overall_hits::total 414546703 # number of overall hits 781system.cpu.icache.ReadReq_misses::cpu.inst 24177508 # number of ReadReq misses 782system.cpu.icache.ReadReq_misses::total 24177508 # number of ReadReq misses 783system.cpu.icache.demand_misses::cpu.inst 24177508 # number of demand (read+write) misses 784system.cpu.icache.demand_misses::total 24177508 # number of demand (read+write) misses 785system.cpu.icache.overall_misses::cpu.inst 24177508 # number of overall misses 786system.cpu.icache.overall_misses::total 24177508 # number of overall misses 787system.cpu.icache.ReadReq_miss_latency::cpu.inst 327600086000 # number of ReadReq miss cycles 788system.cpu.icache.ReadReq_miss_latency::total 327600086000 # number of ReadReq miss cycles 789system.cpu.icache.demand_miss_latency::cpu.inst 327600086000 # number of demand (read+write) miss cycles 790system.cpu.icache.demand_miss_latency::total 327600086000 # number of demand (read+write) miss cycles 791system.cpu.icache.overall_miss_latency::cpu.inst 327600086000 # number of overall miss cycles 792system.cpu.icache.overall_miss_latency::total 327600086000 # number of overall miss cycles 793system.cpu.icache.ReadReq_accesses::cpu.inst 438724211 # number of ReadReq accesses(hits+misses) 794system.cpu.icache.ReadReq_accesses::total 438724211 # number of ReadReq accesses(hits+misses) 795system.cpu.icache.demand_accesses::cpu.inst 438724211 # number of demand (read+write) accesses 796system.cpu.icache.demand_accesses::total 438724211 # number of demand (read+write) accesses 797system.cpu.icache.overall_accesses::cpu.inst 438724211 # number of overall (read+write) accesses 798system.cpu.icache.overall_accesses::total 438724211 # number of overall (read+write) accesses 799system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055109 # miss rate for ReadReq accesses 800system.cpu.icache.ReadReq_miss_rate::total 0.055109 # miss rate for ReadReq accesses 801system.cpu.icache.demand_miss_rate::cpu.inst 0.055109 # miss rate for demand accesses 802system.cpu.icache.demand_miss_rate::total 0.055109 # miss rate for demand accesses 803system.cpu.icache.overall_miss_rate::cpu.inst 0.055109 # miss rate for overall accesses 804system.cpu.icache.overall_miss_rate::total 0.055109 # miss rate for overall accesses 805system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13549.787100 # average ReadReq miss latency 806system.cpu.icache.ReadReq_avg_miss_latency::total 13549.787100 # average ReadReq miss latency 807system.cpu.icache.demand_avg_miss_latency::cpu.inst 13549.787100 # average overall miss latency 808system.cpu.icache.demand_avg_miss_latency::total 13549.787100 # average overall miss latency 809system.cpu.icache.overall_avg_miss_latency::cpu.inst 13549.787100 # average overall miss latency 810system.cpu.icache.overall_avg_miss_latency::total 13549.787100 # average overall miss latency |
| 799system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 800system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 801system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 802system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 803system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 804system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 805system.cpu.icache.fast_writes 0 # number of fast writes performed 806system.cpu.icache.cache_copies 0 # number of cache copies performed | 811system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 812system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 813system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 814system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 815system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 816system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 817system.cpu.icache.fast_writes 0 # number of fast writes performed 818system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 807system.cpu.icache.writebacks::writebacks 24166189 # number of writebacks 808system.cpu.icache.writebacks::total 24166189 # number of writebacks 809system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24166711 # number of ReadReq MSHR misses 810system.cpu.icache.ReadReq_mshr_misses::total 24166711 # number of ReadReq MSHR misses 811system.cpu.icache.demand_mshr_misses::cpu.inst 24166711 # number of demand (read+write) MSHR misses 812system.cpu.icache.demand_mshr_misses::total 24166711 # number of demand (read+write) MSHR misses 813system.cpu.icache.overall_mshr_misses::cpu.inst 24166711 # number of overall MSHR misses 814system.cpu.icache.overall_mshr_misses::total 24166711 # number of overall MSHR misses | 819system.cpu.icache.writebacks::writebacks 24176986 # number of writebacks 820system.cpu.icache.writebacks::total 24176986 # number of writebacks 821system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24177508 # number of ReadReq MSHR misses 822system.cpu.icache.ReadReq_mshr_misses::total 24177508 # number of ReadReq MSHR misses 823system.cpu.icache.demand_mshr_misses::cpu.inst 24177508 # number of demand (read+write) MSHR misses 824system.cpu.icache.demand_mshr_misses::total 24177508 # number of demand (read+write) MSHR misses 825system.cpu.icache.overall_mshr_misses::cpu.inst 24177508 # number of overall MSHR misses 826system.cpu.icache.overall_mshr_misses::total 24177508 # number of overall MSHR misses |
| 815system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 816system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 817system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 818system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses | 827system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 828system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 829system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 830system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses |
| 819system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303315675000 # number of ReadReq MSHR miss cycles 820system.cpu.icache.ReadReq_mshr_miss_latency::total 303315675000 # number of ReadReq MSHR miss cycles 821system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303315675000 # number of demand (read+write) MSHR miss cycles 822system.cpu.icache.demand_mshr_miss_latency::total 303315675000 # number of demand (read+write) MSHR miss cycles 823system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303315675000 # number of overall MSHR miss cycles 824system.cpu.icache.overall_mshr_miss_latency::total 303315675000 # number of overall MSHR miss cycles | 831system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303422579000 # number of ReadReq MSHR miss cycles 832system.cpu.icache.ReadReq_mshr_miss_latency::total 303422579000 # number of ReadReq MSHR miss cycles 833system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303422579000 # number of demand (read+write) MSHR miss cycles 834system.cpu.icache.demand_mshr_miss_latency::total 303422579000 # number of demand (read+write) MSHR miss cycles 835system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303422579000 # number of overall MSHR miss cycles 836system.cpu.icache.overall_mshr_miss_latency::total 303422579000 # number of overall MSHR miss cycles |
| 825system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles 826system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles 827system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles 828system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles | 837system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles 838system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles 839system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles 840system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles |
| 829system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055114 # mshr miss rate for ReadReq accesses 830system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055114 # mshr miss rate for ReadReq accesses 831system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055114 # mshr miss rate for demand accesses 832system.cpu.icache.demand_mshr_miss_rate::total 0.055114 # mshr miss rate for demand accesses 833system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055114 # mshr miss rate for overall accesses 834system.cpu.icache.overall_mshr_miss_rate::total 0.055114 # mshr miss rate for overall accesses 835system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12550.970424 # average ReadReq mshr miss latency 836system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12550.970424 # average ReadReq mshr miss latency 837system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12550.970424 # average overall mshr miss latency 838system.cpu.icache.demand_avg_mshr_miss_latency::total 12550.970424 # average overall mshr miss latency 839system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12550.970424 # average overall mshr miss latency 840system.cpu.icache.overall_avg_mshr_miss_latency::total 12550.970424 # average overall mshr miss latency | 841system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055109 # mshr miss rate for ReadReq accesses 842system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055109 # mshr miss rate for ReadReq accesses 843system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055109 # mshr miss rate for demand accesses 844system.cpu.icache.demand_mshr_miss_rate::total 0.055109 # mshr miss rate for demand accesses 845system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055109 # mshr miss rate for overall accesses 846system.cpu.icache.overall_mshr_miss_rate::total 0.055109 # mshr miss rate for overall accesses 847system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12549.787141 # average ReadReq mshr miss latency 848system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12549.787141 # average ReadReq mshr miss latency 849system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12549.787141 # average overall mshr miss latency 850system.cpu.icache.demand_avg_mshr_miss_latency::total 12549.787141 # average overall mshr miss latency 851system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12549.787141 # average overall mshr miss latency 852system.cpu.icache.overall_avg_mshr_miss_latency::total 12549.787141 # average overall mshr miss latency |
| 841system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 842system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 843system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 844system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency 845system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 853system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 854system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 855system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 856system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency 857system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 846system.cpu.l2cache.tags.replacements 1490419 # number of replacements 847system.cpu.l2cache.tags.tagsinuse 65266.902030 # Cycle average of tags in use 848system.cpu.l2cache.tags.total_refs 65881939 # Total number of references to valid blocks. 849system.cpu.l2cache.tags.sampled_refs 1553674 # Sample count of references to valid blocks. 850system.cpu.l2cache.tags.avg_refs 42.403966 # Average number of references to valid blocks. | 858system.cpu.l2cache.tags.replacements 1490234 # number of replacements 859system.cpu.l2cache.tags.tagsinuse 65213.875092 # Cycle average of tags in use 860system.cpu.l2cache.tags.total_refs 65897094 # Total number of references to valid blocks. 861system.cpu.l2cache.tags.sampled_refs 1553867 # Sample count of references to valid blocks. 862system.cpu.l2cache.tags.avg_refs 42.408452 # Average number of references to valid blocks. |
| 851system.cpu.l2cache.tags.warmup_cycle 36600562500 # Cycle when the warmup percentage was hit. | 863system.cpu.l2cache.tags.warmup_cycle 36600562500 # Cycle when the warmup percentage was hit. |
| 852system.cpu.l2cache.tags.occ_blocks::writebacks 36961.112074 # Average occupied blocks per requestor 853system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 325.532890 # Average occupied blocks per requestor 854system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 387.132710 # Average occupied blocks per requestor 855system.cpu.l2cache.tags.occ_blocks::cpu.inst 7869.830371 # Average occupied blocks per requestor 856system.cpu.l2cache.tags.occ_blocks::cpu.data 19723.293986 # Average occupied blocks per requestor 857system.cpu.l2cache.tags.occ_percent::writebacks 0.563982 # Average percentage of cache occupancy 858system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004967 # Average percentage of cache occupancy 859system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005907 # Average percentage of cache occupancy 860system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120084 # Average percentage of cache occupancy 861system.cpu.l2cache.tags.occ_percent::cpu.data 0.300954 # Average percentage of cache occupancy 862system.cpu.l2cache.tags.occ_percent::total 0.995894 # Average percentage of cache occupancy 863system.cpu.l2cache.tags.occ_task_id_blocks::1023 269 # Occupied blocks per task id 864system.cpu.l2cache.tags.occ_task_id_blocks::1024 62986 # Occupied blocks per task id | 864system.cpu.l2cache.tags.occ_blocks::writebacks 37061.912307 # Average occupied blocks per requestor 865system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 323.258711 # Average occupied blocks per requestor 866system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 399.460797 # Average occupied blocks per requestor 867system.cpu.l2cache.tags.occ_blocks::cpu.inst 7867.228358 # Average occupied blocks per requestor 868system.cpu.l2cache.tags.occ_blocks::cpu.data 19562.014919 # Average occupied blocks per requestor 869system.cpu.l2cache.tags.occ_percent::writebacks 0.565520 # Average percentage of cache occupancy 870system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004933 # Average percentage of cache occupancy 871system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006095 # Average percentage of cache occupancy 872system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120044 # Average percentage of cache occupancy 873system.cpu.l2cache.tags.occ_percent::cpu.data 0.298493 # Average percentage of cache occupancy 874system.cpu.l2cache.tags.occ_percent::total 0.995085 # Average percentage of cache occupancy 875system.cpu.l2cache.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id 876system.cpu.l2cache.tags.occ_task_id_blocks::1024 63396 # Occupied blocks per task id |
| 865system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id | 877system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id |
| 866system.cpu.l2cache.tags.age_task_id_blocks_1023::4 268 # Occupied blocks per task id 867system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 868system.cpu.l2cache.tags.age_task_id_blocks_1024::1 528 # Occupied blocks per task id 869system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2448 # Occupied blocks per task id 870system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5559 # Occupied blocks per task id 871system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54399 # Occupied blocks per task id 872system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004105 # Percentage of cache occupancy per task id 873system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961090 # Percentage of cache occupancy per task id 874system.cpu.l2cache.tags.tag_accesses 573572775 # Number of tag accesses 875system.cpu.l2cache.tags.data_accesses 573572775 # Number of data accesses 876system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 919373 # number of ReadReq hits 877system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 282584 # number of ReadReq hits 878system.cpu.l2cache.ReadReq_hits::total 1201957 # number of ReadReq hits 879system.cpu.l2cache.WritebackDirty_hits::writebacks 8245378 # number of WritebackDirty hits 880system.cpu.l2cache.WritebackDirty_hits::total 8245378 # number of WritebackDirty hits 881system.cpu.l2cache.WritebackClean_hits::writebacks 24162502 # number of WritebackClean hits 882system.cpu.l2cache.WritebackClean_hits::total 24162502 # number of WritebackClean hits 883system.cpu.l2cache.UpgradeReq_hits::cpu.data 10423 # number of UpgradeReq hits 884system.cpu.l2cache.UpgradeReq_hits::total 10423 # number of UpgradeReq hits 885system.cpu.l2cache.ReadExReq_hits::cpu.data 1645677 # number of ReadExReq hits 886system.cpu.l2cache.ReadExReq_hits::total 1645677 # number of ReadExReq hits 887system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24059282 # number of ReadCleanReq hits 888system.cpu.l2cache.ReadCleanReq_hits::total 24059282 # number of ReadCleanReq hits 889system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6917053 # number of ReadSharedReq hits 890system.cpu.l2cache.ReadSharedReq_hits::total 6917053 # number of ReadSharedReq hits 891system.cpu.l2cache.InvalidateReq_hits::cpu.data 707885 # number of InvalidateReq hits 892system.cpu.l2cache.InvalidateReq_hits::total 707885 # number of InvalidateReq hits 893system.cpu.l2cache.demand_hits::cpu.dtb.walker 919373 # number of demand (read+write) hits 894system.cpu.l2cache.demand_hits::cpu.itb.walker 282584 # number of demand (read+write) hits 895system.cpu.l2cache.demand_hits::cpu.inst 24059282 # number of demand (read+write) hits 896system.cpu.l2cache.demand_hits::cpu.data 8562730 # number of demand (read+write) hits 897system.cpu.l2cache.demand_hits::total 33823969 # number of demand (read+write) hits 898system.cpu.l2cache.overall_hits::cpu.dtb.walker 919373 # number of overall hits 899system.cpu.l2cache.overall_hits::cpu.itb.walker 282584 # number of overall hits 900system.cpu.l2cache.overall_hits::cpu.inst 24059282 # number of overall hits 901system.cpu.l2cache.overall_hits::cpu.data 8562730 # number of overall hits 902system.cpu.l2cache.overall_hits::total 33823969 # number of overall hits 903system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5552 # number of ReadReq misses 904system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4605 # number of ReadReq misses 905system.cpu.l2cache.ReadReq_misses::total 10157 # number of ReadReq misses 906system.cpu.l2cache.UpgradeReq_misses::cpu.data 37446 # number of UpgradeReq misses 907system.cpu.l2cache.UpgradeReq_misses::total 37446 # number of UpgradeReq misses | 878system.cpu.l2cache.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id 879system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 880system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id 881system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id 882system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5534 # Occupied blocks per task id 883system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54861 # Occupied blocks per task id 884system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id 885system.cpu.l2cache.tags.occ_task_id_percent::1024 0.967346 # Percentage of cache occupancy per task id 886system.cpu.l2cache.tags.tag_accesses 573646968 # Number of tag accesses 887system.cpu.l2cache.tags.data_accesses 573646968 # Number of data accesses 888system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 914477 # number of ReadReq hits 889system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 280144 # number of ReadReq hits 890system.cpu.l2cache.ReadReq_hits::total 1194621 # number of ReadReq hits 891system.cpu.l2cache.WritebackDirty_hits::writebacks 8243774 # number of WritebackDirty hits 892system.cpu.l2cache.WritebackDirty_hits::total 8243774 # number of WritebackDirty hits 893system.cpu.l2cache.WritebackClean_hits::writebacks 24173277 # number of WritebackClean hits 894system.cpu.l2cache.WritebackClean_hits::total 24173277 # number of WritebackClean hits 895system.cpu.l2cache.UpgradeReq_hits::cpu.data 10400 # number of UpgradeReq hits 896system.cpu.l2cache.UpgradeReq_hits::total 10400 # number of UpgradeReq hits 897system.cpu.l2cache.ReadExReq_hits::cpu.data 1641430 # number of ReadExReq hits 898system.cpu.l2cache.ReadExReq_hits::total 1641430 # number of ReadExReq hits 899system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24070330 # number of ReadCleanReq hits 900system.cpu.l2cache.ReadCleanReq_hits::total 24070330 # number of ReadCleanReq hits 901system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6918127 # number of ReadSharedReq hits 902system.cpu.l2cache.ReadSharedReq_hits::total 6918127 # number of ReadSharedReq hits 903system.cpu.l2cache.InvalidateReq_hits::cpu.data 707471 # number of InvalidateReq hits 904system.cpu.l2cache.InvalidateReq_hits::total 707471 # number of InvalidateReq hits 905system.cpu.l2cache.demand_hits::cpu.dtb.walker 914477 # number of demand (read+write) hits 906system.cpu.l2cache.demand_hits::cpu.itb.walker 280144 # number of demand (read+write) hits 907system.cpu.l2cache.demand_hits::cpu.inst 24070330 # number of demand (read+write) hits 908system.cpu.l2cache.demand_hits::cpu.data 8559557 # number of demand (read+write) hits 909system.cpu.l2cache.demand_hits::total 33824508 # number of demand (read+write) hits 910system.cpu.l2cache.overall_hits::cpu.dtb.walker 914477 # number of overall hits 911system.cpu.l2cache.overall_hits::cpu.itb.walker 280144 # number of overall hits 912system.cpu.l2cache.overall_hits::cpu.inst 24070330 # number of overall hits 913system.cpu.l2cache.overall_hits::cpu.data 8559557 # number of overall hits 914system.cpu.l2cache.overall_hits::total 33824508 # number of overall hits 915system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5463 # number of ReadReq misses 916system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4617 # number of ReadReq misses 917system.cpu.l2cache.ReadReq_misses::total 10080 # number of ReadReq misses 918system.cpu.l2cache.UpgradeReq_misses::cpu.data 37497 # number of UpgradeReq misses 919system.cpu.l2cache.UpgradeReq_misses::total 37497 # number of UpgradeReq misses |
| 908system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 909system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses | 920system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 921system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses |
| 910system.cpu.l2cache.ReadExReq_misses::cpu.data 617921 # number of ReadExReq misses 911system.cpu.l2cache.ReadExReq_misses::total 617921 # number of ReadExReq misses 912system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107426 # number of ReadCleanReq misses 913system.cpu.l2cache.ReadCleanReq_misses::total 107426 # number of ReadCleanReq misses 914system.cpu.l2cache.ReadSharedReq_misses::cpu.data 314580 # number of ReadSharedReq misses 915system.cpu.l2cache.ReadSharedReq_misses::total 314580 # number of ReadSharedReq misses 916system.cpu.l2cache.InvalidateReq_misses::cpu.data 531617 # number of InvalidateReq misses 917system.cpu.l2cache.InvalidateReq_misses::total 531617 # number of InvalidateReq misses 918system.cpu.l2cache.demand_misses::cpu.dtb.walker 5552 # number of demand (read+write) misses 919system.cpu.l2cache.demand_misses::cpu.itb.walker 4605 # number of demand (read+write) misses 920system.cpu.l2cache.demand_misses::cpu.inst 107426 # number of demand (read+write) misses 921system.cpu.l2cache.demand_misses::cpu.data 932501 # number of demand (read+write) misses 922system.cpu.l2cache.demand_misses::total 1050084 # number of demand (read+write) misses 923system.cpu.l2cache.overall_misses::cpu.dtb.walker 5552 # number of overall misses 924system.cpu.l2cache.overall_misses::cpu.itb.walker 4605 # number of overall misses 925system.cpu.l2cache.overall_misses::cpu.inst 107426 # number of overall misses 926system.cpu.l2cache.overall_misses::cpu.data 932501 # number of overall misses 927system.cpu.l2cache.overall_misses::total 1050084 # number of overall misses 928system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 759647500 # number of ReadReq miss cycles 929system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 632585000 # number of ReadReq miss cycles 930system.cpu.l2cache.ReadReq_miss_latency::total 1392232500 # number of ReadReq miss cycles 931system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1488692000 # number of UpgradeReq miss cycles 932system.cpu.l2cache.UpgradeReq_miss_latency::total 1488692000 # number of UpgradeReq miss cycles | 922system.cpu.l2cache.ReadExReq_misses::cpu.data 619977 # number of ReadExReq misses 923system.cpu.l2cache.ReadExReq_misses::total 619977 # number of ReadExReq misses 924system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107175 # number of ReadCleanReq misses 925system.cpu.l2cache.ReadCleanReq_misses::total 107175 # number of ReadCleanReq misses 926system.cpu.l2cache.ReadSharedReq_misses::cpu.data 314193 # number of ReadSharedReq misses 927system.cpu.l2cache.ReadSharedReq_misses::total 314193 # number of ReadSharedReq misses 928system.cpu.l2cache.InvalidateReq_misses::cpu.data 531195 # number of InvalidateReq misses 929system.cpu.l2cache.InvalidateReq_misses::total 531195 # number of InvalidateReq misses 930system.cpu.l2cache.demand_misses::cpu.dtb.walker 5463 # number of demand (read+write) misses 931system.cpu.l2cache.demand_misses::cpu.itb.walker 4617 # number of demand (read+write) misses 932system.cpu.l2cache.demand_misses::cpu.inst 107175 # number of demand (read+write) misses 933system.cpu.l2cache.demand_misses::cpu.data 934170 # number of demand (read+write) misses 934system.cpu.l2cache.demand_misses::total 1051425 # number of demand (read+write) misses 935system.cpu.l2cache.overall_misses::cpu.dtb.walker 5463 # number of overall misses 936system.cpu.l2cache.overall_misses::cpu.itb.walker 4617 # number of overall misses 937system.cpu.l2cache.overall_misses::cpu.inst 107175 # number of overall misses 938system.cpu.l2cache.overall_misses::cpu.data 934170 # number of overall misses 939system.cpu.l2cache.overall_misses::total 1051425 # number of overall misses 940system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 750857500 # number of ReadReq miss cycles 941system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 630554000 # number of ReadReq miss cycles 942system.cpu.l2cache.ReadReq_miss_latency::total 1381411500 # number of ReadReq miss cycles 943system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1438781000 # number of UpgradeReq miss cycles 944system.cpu.l2cache.UpgradeReq_miss_latency::total 1438781000 # number of UpgradeReq miss cycles |
| 933system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles 934system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles | 945system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles 946system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles |
| 935system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81962510000 # number of ReadExReq miss cycles 936system.cpu.l2cache.ReadExReq_miss_latency::total 81962510000 # number of ReadExReq miss cycles 937system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14211686500 # number of ReadCleanReq miss cycles 938system.cpu.l2cache.ReadCleanReq_miss_latency::total 14211686500 # number of ReadCleanReq miss cycles 939system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 42390625000 # number of ReadSharedReq miss cycles 940system.cpu.l2cache.ReadSharedReq_miss_latency::total 42390625000 # number of ReadSharedReq miss cycles 941system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 73785023000 # number of InvalidateReq miss cycles 942system.cpu.l2cache.InvalidateReq_miss_latency::total 73785023000 # number of InvalidateReq miss cycles 943system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 759647500 # number of demand (read+write) miss cycles 944system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 632585000 # number of demand (read+write) miss cycles 945system.cpu.l2cache.demand_miss_latency::cpu.inst 14211686500 # number of demand (read+write) miss cycles 946system.cpu.l2cache.demand_miss_latency::cpu.data 124353135000 # number of demand (read+write) miss cycles 947system.cpu.l2cache.demand_miss_latency::total 139957054000 # number of demand (read+write) miss cycles 948system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 759647500 # number of overall miss cycles 949system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 632585000 # number of overall miss cycles 950system.cpu.l2cache.overall_miss_latency::cpu.inst 14211686500 # number of overall miss cycles 951system.cpu.l2cache.overall_miss_latency::cpu.data 124353135000 # number of overall miss cycles 952system.cpu.l2cache.overall_miss_latency::total 139957054000 # number of overall miss cycles 953system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 924925 # number of ReadReq accesses(hits+misses) 954system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 287189 # number of ReadReq accesses(hits+misses) 955system.cpu.l2cache.ReadReq_accesses::total 1212114 # number of ReadReq accesses(hits+misses) 956system.cpu.l2cache.WritebackDirty_accesses::writebacks 8245378 # number of WritebackDirty accesses(hits+misses) 957system.cpu.l2cache.WritebackDirty_accesses::total 8245378 # number of WritebackDirty accesses(hits+misses) 958system.cpu.l2cache.WritebackClean_accesses::writebacks 24162502 # number of WritebackClean accesses(hits+misses) 959system.cpu.l2cache.WritebackClean_accesses::total 24162502 # number of WritebackClean accesses(hits+misses) 960system.cpu.l2cache.UpgradeReq_accesses::cpu.data 47869 # number of UpgradeReq accesses(hits+misses) 961system.cpu.l2cache.UpgradeReq_accesses::total 47869 # number of UpgradeReq accesses(hits+misses) | 947system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82239355500 # number of ReadExReq miss cycles 948system.cpu.l2cache.ReadExReq_miss_latency::total 82239355500 # number of ReadExReq miss cycles 949system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14186388500 # number of ReadCleanReq miss cycles 950system.cpu.l2cache.ReadCleanReq_miss_latency::total 14186388500 # number of ReadCleanReq miss cycles 951system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 42349642500 # number of ReadSharedReq miss cycles 952system.cpu.l2cache.ReadSharedReq_miss_latency::total 42349642500 # number of ReadSharedReq miss cycles 953system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 73756780500 # number of InvalidateReq miss cycles 954system.cpu.l2cache.InvalidateReq_miss_latency::total 73756780500 # number of InvalidateReq miss cycles 955system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 750857500 # number of demand (read+write) miss cycles 956system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 630554000 # number of demand (read+write) miss cycles 957system.cpu.l2cache.demand_miss_latency::cpu.inst 14186388500 # number of demand (read+write) miss cycles 958system.cpu.l2cache.demand_miss_latency::cpu.data 124588998000 # number of demand (read+write) miss cycles 959system.cpu.l2cache.demand_miss_latency::total 140156798000 # number of demand (read+write) miss cycles 960system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 750857500 # number of overall miss cycles 961system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 630554000 # number of overall miss cycles 962system.cpu.l2cache.overall_miss_latency::cpu.inst 14186388500 # number of overall miss cycles 963system.cpu.l2cache.overall_miss_latency::cpu.data 124588998000 # number of overall miss cycles 964system.cpu.l2cache.overall_miss_latency::total 140156798000 # number of overall miss cycles 965system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 919940 # number of ReadReq accesses(hits+misses) 966system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 284761 # number of ReadReq accesses(hits+misses) 967system.cpu.l2cache.ReadReq_accesses::total 1204701 # number of ReadReq accesses(hits+misses) 968system.cpu.l2cache.WritebackDirty_accesses::writebacks 8243774 # number of WritebackDirty accesses(hits+misses) 969system.cpu.l2cache.WritebackDirty_accesses::total 8243774 # number of WritebackDirty accesses(hits+misses) 970system.cpu.l2cache.WritebackClean_accesses::writebacks 24173277 # number of WritebackClean accesses(hits+misses) 971system.cpu.l2cache.WritebackClean_accesses::total 24173277 # number of WritebackClean accesses(hits+misses) 972system.cpu.l2cache.UpgradeReq_accesses::cpu.data 47897 # number of UpgradeReq accesses(hits+misses) 973system.cpu.l2cache.UpgradeReq_accesses::total 47897 # number of UpgradeReq accesses(hits+misses) |
| 962system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 963system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) | 974system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 975system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) |
| 964system.cpu.l2cache.ReadExReq_accesses::cpu.data 2263598 # number of ReadExReq accesses(hits+misses) 965system.cpu.l2cache.ReadExReq_accesses::total 2263598 # number of ReadExReq accesses(hits+misses) 966system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24166708 # number of ReadCleanReq accesses(hits+misses) 967system.cpu.l2cache.ReadCleanReq_accesses::total 24166708 # number of ReadCleanReq accesses(hits+misses) 968system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7231633 # number of ReadSharedReq accesses(hits+misses) 969system.cpu.l2cache.ReadSharedReq_accesses::total 7231633 # number of ReadSharedReq accesses(hits+misses) 970system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1239502 # number of InvalidateReq accesses(hits+misses) 971system.cpu.l2cache.InvalidateReq_accesses::total 1239502 # number of InvalidateReq accesses(hits+misses) 972system.cpu.l2cache.demand_accesses::cpu.dtb.walker 924925 # number of demand (read+write) accesses 973system.cpu.l2cache.demand_accesses::cpu.itb.walker 287189 # number of demand (read+write) accesses 974system.cpu.l2cache.demand_accesses::cpu.inst 24166708 # number of demand (read+write) accesses 975system.cpu.l2cache.demand_accesses::cpu.data 9495231 # number of demand (read+write) accesses 976system.cpu.l2cache.demand_accesses::total 34874053 # number of demand (read+write) accesses 977system.cpu.l2cache.overall_accesses::cpu.dtb.walker 924925 # number of overall (read+write) accesses 978system.cpu.l2cache.overall_accesses::cpu.itb.walker 287189 # number of overall (read+write) accesses 979system.cpu.l2cache.overall_accesses::cpu.inst 24166708 # number of overall (read+write) accesses 980system.cpu.l2cache.overall_accesses::cpu.data 9495231 # number of overall (read+write) accesses 981system.cpu.l2cache.overall_accesses::total 34874053 # number of overall (read+write) accesses 982system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006003 # miss rate for ReadReq accesses 983system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.016035 # miss rate for ReadReq accesses 984system.cpu.l2cache.ReadReq_miss_rate::total 0.008380 # miss rate for ReadReq accesses 985system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782260 # miss rate for UpgradeReq accesses 986system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782260 # miss rate for UpgradeReq accesses | 976system.cpu.l2cache.ReadExReq_accesses::cpu.data 2261407 # number of ReadExReq accesses(hits+misses) 977system.cpu.l2cache.ReadExReq_accesses::total 2261407 # number of ReadExReq accesses(hits+misses) 978system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24177505 # number of ReadCleanReq accesses(hits+misses) 979system.cpu.l2cache.ReadCleanReq_accesses::total 24177505 # number of ReadCleanReq accesses(hits+misses) 980system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7232320 # number of ReadSharedReq accesses(hits+misses) 981system.cpu.l2cache.ReadSharedReq_accesses::total 7232320 # number of ReadSharedReq accesses(hits+misses) 982system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1238666 # number of InvalidateReq accesses(hits+misses) 983system.cpu.l2cache.InvalidateReq_accesses::total 1238666 # number of InvalidateReq accesses(hits+misses) 984system.cpu.l2cache.demand_accesses::cpu.dtb.walker 919940 # number of demand (read+write) accesses 985system.cpu.l2cache.demand_accesses::cpu.itb.walker 284761 # number of demand (read+write) accesses 986system.cpu.l2cache.demand_accesses::cpu.inst 24177505 # number of demand (read+write) accesses 987system.cpu.l2cache.demand_accesses::cpu.data 9493727 # number of demand (read+write) accesses 988system.cpu.l2cache.demand_accesses::total 34875933 # number of demand (read+write) accesses 989system.cpu.l2cache.overall_accesses::cpu.dtb.walker 919940 # number of overall (read+write) accesses 990system.cpu.l2cache.overall_accesses::cpu.itb.walker 284761 # number of overall (read+write) accesses 991system.cpu.l2cache.overall_accesses::cpu.inst 24177505 # number of overall (read+write) accesses 992system.cpu.l2cache.overall_accesses::cpu.data 9493727 # number of overall (read+write) accesses 993system.cpu.l2cache.overall_accesses::total 34875933 # number of overall (read+write) accesses 994system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.005938 # miss rate for ReadReq accesses 995system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.016214 # miss rate for ReadReq accesses 996system.cpu.l2cache.ReadReq_miss_rate::total 0.008367 # miss rate for ReadReq accesses 997system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782867 # miss rate for UpgradeReq accesses 998system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782867 # miss rate for UpgradeReq accesses |
| 987system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 988system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 999system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1000system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 989system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.272982 # miss rate for ReadExReq accesses 990system.cpu.l2cache.ReadExReq_miss_rate::total 0.272982 # miss rate for ReadExReq accesses 991system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004445 # miss rate for ReadCleanReq accesses 992system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004445 # miss rate for ReadCleanReq accesses 993system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043501 # miss rate for ReadSharedReq accesses 994system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043501 # miss rate for ReadSharedReq accesses 995system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.428896 # miss rate for InvalidateReq accesses 996system.cpu.l2cache.InvalidateReq_miss_rate::total 0.428896 # miss rate for InvalidateReq accesses 997system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006003 # miss rate for demand accesses 998system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.016035 # miss rate for demand accesses 999system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004445 # miss rate for demand accesses 1000system.cpu.l2cache.demand_miss_rate::cpu.data 0.098207 # miss rate for demand accesses 1001system.cpu.l2cache.demand_miss_rate::total 0.030111 # miss rate for demand accesses 1002system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006003 # miss rate for overall accesses 1003system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.016035 # miss rate for overall accesses 1004system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004445 # miss rate for overall accesses 1005system.cpu.l2cache.overall_miss_rate::cpu.data 0.098207 # miss rate for overall accesses 1006system.cpu.l2cache.overall_miss_rate::total 0.030111 # miss rate for overall accesses 1007system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136824.117435 # average ReadReq miss latency 1008system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137369.163952 # average ReadReq miss latency 1009system.cpu.l2cache.ReadReq_avg_miss_latency::total 137071.231663 # average ReadReq miss latency 1010system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39755.701544 # average UpgradeReq miss latency 1011system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39755.701544 # average UpgradeReq miss latency | 1001system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.274155 # miss rate for ReadExReq accesses 1002system.cpu.l2cache.ReadExReq_miss_rate::total 0.274155 # miss rate for ReadExReq accesses 1003system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004433 # miss rate for ReadCleanReq accesses 1004system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004433 # miss rate for ReadCleanReq accesses 1005system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043443 # miss rate for ReadSharedReq accesses 1006system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043443 # miss rate for ReadSharedReq accesses 1007system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.428844 # miss rate for InvalidateReq accesses 1008system.cpu.l2cache.InvalidateReq_miss_rate::total 0.428844 # miss rate for InvalidateReq accesses 1009system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.005938 # miss rate for demand accesses 1010system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.016214 # miss rate for demand accesses 1011system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004433 # miss rate for demand accesses 1012system.cpu.l2cache.demand_miss_rate::cpu.data 0.098399 # miss rate for demand accesses 1013system.cpu.l2cache.demand_miss_rate::total 0.030148 # miss rate for demand accesses 1014system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.005938 # miss rate for overall accesses 1015system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.016214 # miss rate for overall accesses 1016system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004433 # miss rate for overall accesses 1017system.cpu.l2cache.overall_miss_rate::cpu.data 0.098399 # miss rate for overall accesses 1018system.cpu.l2cache.overall_miss_rate::total 0.030148 # miss rate for overall accesses 1019system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137444.169870 # average ReadReq miss latency 1020system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136572.233052 # average ReadReq miss latency 1021system.cpu.l2cache.ReadReq_avg_miss_latency::total 137044.791667 # average ReadReq miss latency 1022system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38370.562978 # average UpgradeReq miss latency 1023system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38370.562978 # average UpgradeReq miss latency |
| 1012system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1013system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency | 1024system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1025system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency |
| 1014system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132642.376614 # average ReadExReq miss latency 1015system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132642.376614 # average ReadExReq miss latency 1016system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132292.801556 # average ReadCleanReq miss latency 1017system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132292.801556 # average ReadCleanReq miss latency 1018system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134753.083476 # average ReadSharedReq miss latency 1019system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134753.083476 # average ReadSharedReq miss latency 1020system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138793.573193 # average InvalidateReq miss latency 1021system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138793.573193 # average InvalidateReq miss latency 1022system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136824.117435 # average overall miss latency 1023system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137369.163952 # average overall miss latency 1024system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132292.801556 # average overall miss latency 1025system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133354.425357 # average overall miss latency 1026system.cpu.l2cache.demand_avg_miss_latency::total 133281.769839 # average overall miss latency 1027system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136824.117435 # average overall miss latency 1028system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137369.163952 # average overall miss latency 1029system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132292.801556 # average overall miss latency 1030system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133354.425357 # average overall miss latency 1031system.cpu.l2cache.overall_avg_miss_latency::total 133281.769839 # average overall miss latency | 1026system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132649.042626 # average ReadExReq miss latency 1027system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132649.042626 # average ReadExReq miss latency 1028system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132366.582692 # average ReadCleanReq miss latency 1029system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132366.582692 # average ReadCleanReq miss latency 1030system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134788.625144 # average ReadSharedReq miss latency 1031system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134788.625144 # average ReadSharedReq miss latency 1032system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138850.667834 # average InvalidateReq miss latency 1033system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138850.667834 # average InvalidateReq miss latency 1034system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137444.169870 # average overall miss latency 1035system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136572.233052 # average overall miss latency 1036system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132366.582692 # average overall miss latency 1037system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133368.656668 # average overall miss latency 1038system.cpu.l2cache.demand_avg_miss_latency::total 133301.755237 # average overall miss latency 1039system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137444.169870 # average overall miss latency 1040system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136572.233052 # average overall miss latency 1041system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132366.582692 # average overall miss latency 1042system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133368.656668 # average overall miss latency 1043system.cpu.l2cache.overall_avg_miss_latency::total 133301.755237 # average overall miss latency |
| 1032system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1033system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1034system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1035system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1036system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1037system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1038system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1039system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1044system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1045system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1046system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1047system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1048system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1049system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1050system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1051system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1040system.cpu.l2cache.writebacks::writebacks 1258661 # number of writebacks 1041system.cpu.l2cache.writebacks::total 1258661 # number of writebacks | 1052system.cpu.l2cache.writebacks::writebacks 1259026 # number of writebacks 1053system.cpu.l2cache.writebacks::total 1259026 # number of writebacks |
| 1042system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1043system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits | 1054system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1055system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits |
| 1044system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits 1045system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits | 1056system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1057system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits |
| 1046system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits | 1058system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits |
| 1047system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits 1048system.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits | 1059system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1060system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits |
| 1049system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits | 1061system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits |
| 1050system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits 1051system.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits 1052system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5552 # number of ReadReq MSHR misses 1053system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4605 # number of ReadReq MSHR misses 1054system.cpu.l2cache.ReadReq_mshr_misses::total 10157 # number of ReadReq MSHR misses | 1062system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1063system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 1064system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5463 # number of ReadReq MSHR misses 1065system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4617 # number of ReadReq MSHR misses 1066system.cpu.l2cache.ReadReq_mshr_misses::total 10080 # number of ReadReq MSHR misses |
| 1055system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses 1056system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses | 1067system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses 1068system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses |
| 1057system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37446 # number of UpgradeReq MSHR misses 1058system.cpu.l2cache.UpgradeReq_mshr_misses::total 37446 # number of UpgradeReq MSHR misses | 1069system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37497 # number of UpgradeReq MSHR misses 1070system.cpu.l2cache.UpgradeReq_mshr_misses::total 37497 # number of UpgradeReq MSHR misses |
| 1059system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1060system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses | 1071system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1072system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses |
| 1061system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 617921 # number of ReadExReq MSHR misses 1062system.cpu.l2cache.ReadExReq_mshr_misses::total 617921 # number of ReadExReq MSHR misses 1063system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107423 # number of ReadCleanReq MSHR misses 1064system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107423 # number of ReadCleanReq MSHR misses 1065system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 314558 # number of ReadSharedReq MSHR misses 1066system.cpu.l2cache.ReadSharedReq_mshr_misses::total 314558 # number of ReadSharedReq MSHR misses 1067system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 531617 # number of InvalidateReq MSHR misses 1068system.cpu.l2cache.InvalidateReq_mshr_misses::total 531617 # number of InvalidateReq MSHR misses 1069system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5552 # number of demand (read+write) MSHR misses 1070system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4605 # number of demand (read+write) MSHR misses 1071system.cpu.l2cache.demand_mshr_misses::cpu.inst 107423 # number of demand (read+write) MSHR misses 1072system.cpu.l2cache.demand_mshr_misses::cpu.data 932479 # number of demand (read+write) MSHR misses 1073system.cpu.l2cache.demand_mshr_misses::total 1050059 # number of demand (read+write) MSHR misses 1074system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5552 # number of overall MSHR misses 1075system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4605 # number of overall MSHR misses 1076system.cpu.l2cache.overall_mshr_misses::cpu.inst 107423 # number of overall MSHR misses 1077system.cpu.l2cache.overall_mshr_misses::cpu.data 932479 # number of overall MSHR misses 1078system.cpu.l2cache.overall_mshr_misses::total 1050059 # number of overall MSHR misses | 1073system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 619977 # number of ReadExReq MSHR misses 1074system.cpu.l2cache.ReadExReq_mshr_misses::total 619977 # number of ReadExReq MSHR misses 1075system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107172 # number of ReadCleanReq MSHR misses 1076system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107172 # number of ReadCleanReq MSHR misses 1077system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 314172 # number of ReadSharedReq MSHR misses 1078system.cpu.l2cache.ReadSharedReq_mshr_misses::total 314172 # number of ReadSharedReq MSHR misses 1079system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 531195 # number of InvalidateReq MSHR misses 1080system.cpu.l2cache.InvalidateReq_mshr_misses::total 531195 # number of InvalidateReq MSHR misses 1081system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5463 # number of demand (read+write) MSHR misses 1082system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4617 # number of demand (read+write) MSHR misses 1083system.cpu.l2cache.demand_mshr_misses::cpu.inst 107172 # number of demand (read+write) MSHR misses 1084system.cpu.l2cache.demand_mshr_misses::cpu.data 934149 # number of demand (read+write) MSHR misses 1085system.cpu.l2cache.demand_mshr_misses::total 1051401 # number of demand (read+write) MSHR misses 1086system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5463 # number of overall MSHR misses 1087system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4617 # number of overall MSHR misses 1088system.cpu.l2cache.overall_mshr_misses::cpu.inst 107172 # number of overall MSHR misses 1089system.cpu.l2cache.overall_mshr_misses::cpu.data 934149 # number of overall MSHR misses 1090system.cpu.l2cache.overall_mshr_misses::total 1051401 # number of overall MSHR misses |
| 1079system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 1080system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 1081system.cpu.l2cache.ReadReq_mshr_uncacheable::total 86006 # number of ReadReq MSHR uncacheable 1082system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 1083system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 1084system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 1085system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 1086system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119712 # number of overall MSHR uncacheable misses | 1091system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 1092system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 1093system.cpu.l2cache.ReadReq_mshr_uncacheable::total 86006 # number of ReadReq MSHR uncacheable 1094system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 1095system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 1096system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 1097system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 1098system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119712 # number of overall MSHR uncacheable misses |
| 1087system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 704127500 # number of ReadReq MSHR miss cycles 1088system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 586535000 # number of ReadReq MSHR miss cycles 1089system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1290662500 # number of ReadReq MSHR miss cycles 1090system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2650319500 # number of UpgradeReq MSHR miss cycles 1091system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2650319500 # number of UpgradeReq MSHR miss cycles | 1099system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 696227500 # number of ReadReq MSHR miss cycles 1100system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 584384000 # number of ReadReq MSHR miss cycles 1101system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1280611500 # number of ReadReq MSHR miss cycles 1102system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2550264500 # number of UpgradeReq MSHR miss cycles 1103system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2550264500 # number of UpgradeReq MSHR miss cycles |
| 1092system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles 1093system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles | 1104system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles 1105system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles |
| 1094system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 75783300000 # number of ReadExReq MSHR miss cycles 1095system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 75783300000 # number of ReadExReq MSHR miss cycles 1096system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13137194000 # number of ReadCleanReq MSHR miss cycles 1097system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13137194000 # number of ReadCleanReq MSHR miss cycles 1098system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 39242637500 # number of ReadSharedReq MSHR miss cycles 1099system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 39242637500 # number of ReadSharedReq MSHR miss cycles 1100system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 68468853000 # number of InvalidateReq MSHR miss cycles 1101system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 68468853000 # number of InvalidateReq MSHR miss cycles 1102system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 704127500 # number of demand (read+write) MSHR miss cycles 1103system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 586535000 # number of demand (read+write) MSHR miss cycles 1104system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13137194000 # number of demand (read+write) MSHR miss cycles 1105system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115025937500 # number of demand (read+write) MSHR miss cycles 1106system.cpu.l2cache.demand_mshr_miss_latency::total 129453794000 # number of demand (read+write) MSHR miss cycles 1107system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 704127500 # number of overall MSHR miss cycles 1108system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 586535000 # number of overall MSHR miss cycles 1109system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13137194000 # number of overall MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115025937500 # number of overall MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::total 129453794000 # number of overall MSHR miss cycles | 1106system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 76039573524 # number of ReadExReq MSHR miss cycles 1107system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 76039573524 # number of ReadExReq MSHR miss cycles 1108system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13114406000 # number of ReadCleanReq MSHR miss cycles 1109system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13114406000 # number of ReadCleanReq MSHR miss cycles 1110system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 39205480000 # number of ReadSharedReq MSHR miss cycles 1111system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 39205480000 # number of ReadSharedReq MSHR miss cycles 1112system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 68444830500 # number of InvalidateReq MSHR miss cycles 1113system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 68444830500 # number of InvalidateReq MSHR miss cycles 1114system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 696227500 # number of demand (read+write) MSHR miss cycles 1115system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 584384000 # number of demand (read+write) MSHR miss cycles 1116system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13114406000 # number of demand (read+write) MSHR miss cycles 1117system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115245053524 # number of demand (read+write) MSHR miss cycles 1118system.cpu.l2cache.demand_mshr_miss_latency::total 129640071024 # number of demand (read+write) MSHR miss cycles 1119system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 696227500 # number of overall MSHR miss cycles 1120system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 584384000 # number of overall MSHR miss cycles 1121system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13114406000 # number of overall MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115245053524 # number of overall MSHR miss cycles 1123system.cpu.l2cache.overall_mshr_miss_latency::total 129640071024 # number of overall MSHR miss cycles |
| 1112system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles | 1124system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles |
| 1113system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776284500 # number of ReadReq MSHR uncacheable cycles 1114system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712358500 # number of ReadReq MSHR uncacheable cycles 1115system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5819171500 # number of WriteReq MSHR uncacheable cycles 1116system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5819171500 # number of WriteReq MSHR uncacheable cycles | 1125system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776017500 # number of ReadReq MSHR uncacheable cycles 1126system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712091500 # number of ReadReq MSHR uncacheable cycles 1127system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5819225500 # number of WriteReq MSHR uncacheable cycles 1128system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5819225500 # number of WriteReq MSHR uncacheable cycles |
| 1117system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles | 1129system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles |
| 1118system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11595456000 # number of overall MSHR uncacheable cycles 1119system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17531530000 # number of overall MSHR uncacheable cycles 1120system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006003 # mshr miss rate for ReadReq accesses 1121system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.016035 # mshr miss rate for ReadReq accesses 1122system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008380 # mshr miss rate for ReadReq accesses | 1130system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11595243000 # number of overall MSHR uncacheable cycles 1131system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17531317000 # number of overall MSHR uncacheable cycles 1132system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for ReadReq accesses 1133system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for ReadReq accesses 1134system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008367 # mshr miss rate for ReadReq accesses |
| 1123system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1124system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 1135system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1136system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 1125system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782260 # mshr miss rate for UpgradeReq accesses 1126system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782260 # mshr miss rate for UpgradeReq accesses | 1137system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782867 # mshr miss rate for UpgradeReq accesses 1138system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782867 # mshr miss rate for UpgradeReq accesses |
| 1127system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1128system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1139system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1140system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 1129system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.272982 # mshr miss rate for ReadExReq accesses 1130system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.272982 # mshr miss rate for ReadExReq accesses 1131system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004445 # mshr miss rate for ReadCleanReq accesses 1132system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004445 # mshr miss rate for ReadCleanReq accesses 1133system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043498 # mshr miss rate for ReadSharedReq accesses 1134system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043498 # mshr miss rate for ReadSharedReq accesses 1135system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.428896 # mshr miss rate for InvalidateReq accesses 1136system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.428896 # mshr miss rate for InvalidateReq accesses 1137system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006003 # mshr miss rate for demand accesses 1138system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016035 # mshr miss rate for demand accesses 1139system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004445 # mshr miss rate for demand accesses 1140system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.098205 # mshr miss rate for demand accesses 1141system.cpu.l2cache.demand_mshr_miss_rate::total 0.030110 # mshr miss rate for demand accesses 1142system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006003 # mshr miss rate for overall accesses 1143system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016035 # mshr miss rate for overall accesses 1144system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004445 # mshr miss rate for overall accesses 1145system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.098205 # mshr miss rate for overall accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::total 0.030110 # mshr miss rate for overall accesses 1147system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435 # average ReadReq mshr miss latency 1148system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127369.163952 # average ReadReq mshr miss latency 1149system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127071.231663 # average ReadReq mshr miss latency 1150system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70777.105699 # average UpgradeReq mshr miss latency 1151system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70777.105699 # average UpgradeReq mshr miss latency | 1141system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.274155 # mshr miss rate for ReadExReq accesses 1142system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.274155 # mshr miss rate for ReadExReq accesses 1143system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for ReadCleanReq accesses 1144system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004433 # mshr miss rate for ReadCleanReq accesses 1145system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043440 # mshr miss rate for ReadSharedReq accesses 1146system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043440 # mshr miss rate for ReadSharedReq accesses 1147system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.428844 # mshr miss rate for InvalidateReq accesses 1148system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.428844 # mshr miss rate for InvalidateReq accesses 1149system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for demand accesses 1150system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for demand accesses 1151system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for demand accesses 1152system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.098396 # mshr miss rate for demand accesses 1153system.cpu.l2cache.demand_mshr_miss_rate::total 0.030147 # mshr miss rate for demand accesses 1154system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for overall accesses 1155system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for overall accesses 1156system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for overall accesses 1157system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.098396 # mshr miss rate for overall accesses 1158system.cpu.l2cache.overall_mshr_miss_rate::total 0.030147 # mshr miss rate for overall accesses 1159system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average ReadReq mshr miss latency 1160system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average ReadReq mshr miss latency 1161system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127044.791667 # average ReadReq mshr miss latency 1162system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.494333 # average UpgradeReq mshr miss latency 1163system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.494333 # average UpgradeReq mshr miss latency |
| 1152system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1153system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency | 1164system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1165system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency |
| 1154system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122642.376614 # average ReadExReq mshr miss latency 1155system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122642.376614 # average ReadExReq mshr miss latency 1156system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122294.052484 # average ReadCleanReq mshr miss latency 1157system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122294.052484 # average ReadCleanReq mshr miss latency 1158system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124754.854431 # average ReadSharedReq mshr miss latency 1159system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124754.854431 # average ReadSharedReq mshr miss latency 1160system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128793.573193 # average InvalidateReq mshr miss latency 1161system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128793.573193 # average InvalidateReq mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435 # average overall mshr miss latency 1163system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127369.163952 # average overall mshr miss latency 1164system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122294.052484 # average overall mshr miss latency 1165system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123354.989764 # average overall mshr miss latency 1166system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123282.400322 # average overall mshr miss latency 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435 # average overall mshr miss latency 1168system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127369.163952 # average overall mshr miss latency 1169system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122294.052484 # average overall mshr miss latency 1170system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123354.989764 # average overall mshr miss latency 1171system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123282.400322 # average overall mshr miss latency | 1166system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122649.023309 # average ReadExReq mshr miss latency 1167system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122649.023309 # average ReadExReq mshr miss latency 1168system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122367.838615 # average ReadCleanReq mshr miss latency 1169system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122367.838615 # average ReadCleanReq mshr miss latency 1170system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124789.860331 # average ReadSharedReq mshr miss latency 1171system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124789.860331 # average ReadSharedReq mshr miss latency 1172system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128850.667834 # average InvalidateReq mshr miss latency 1173system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128850.667834 # average InvalidateReq mshr miss latency 1174system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency 1177system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency 1178system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency 1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency 1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency 1183system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency |
| 1172system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency | 1184system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency |
| 1173system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171418.360685 # average ReadReq mshr uncacheable latency 1174system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136180.714136 # average ReadReq mshr uncacheable latency 1175system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172644.974189 # average WriteReq mshr uncacheable latency 1176system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172644.974189 # average WriteReq mshr uncacheable latency | 1185system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171410.437131 # average ReadReq mshr uncacheable latency 1186system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136177.609702 # average ReadReq mshr uncacheable latency 1187system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172646.576277 # average WriteReq mshr uncacheable latency 1188system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172646.576277 # average WriteReq mshr uncacheable latency |
| 1177system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency | 1189system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency |
| 1178system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.749329 # average overall mshr uncacheable latency 1179system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.557471 # average overall mshr uncacheable latency | 1190system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172028.589232 # average overall mshr uncacheable latency 1191system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146445.778201 # average overall mshr uncacheable latency |
| 1180system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1192system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1181system.cpu.toL2Bus.snoop_filter.tot_requests 70542716 # Total number of requests made to the snoop filter. 1182system.cpu.toL2Bus.snoop_filter.hit_single_requests 35641283 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1183system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4403 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1184system.cpu.toL2Bus.snoop_filter.tot_snoops 2298 # Total number of snoops made to the snoop filter. 1185system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2298 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1193system.cpu.toL2Bus.snoop_filter.tot_requests 70561172 # Total number of requests made to the snoop filter. 1194system.cpu.toL2Bus.snoop_filter.hit_single_requests 35651281 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1195system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4392 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1196system.cpu.toL2Bus.snoop_filter.tot_snoops 2272 # Total number of snoops made to the snoop filter. 1197system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1186system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1198system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1187system.cpu.toL2Bus.trans_dist::ReadReq 1728705 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::ReadResp 33127830 # Transaction distribution | 1199system.cpu.toL2Bus.trans_dist::ReadReq 1729330 # Transaction distribution 1200system.cpu.toL2Bus.trans_dist::ReadResp 33139930 # Transaction distribution |
| 1189system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution | 1201system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution 1202system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution |
| 1191system.cpu.toL2Bus.trans_dist::WritebackDirty 9610686 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::WritebackClean 24162502 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::CleanEvict 2728698 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::UpgradeReq 47872 # Transaction distribution | 1203system.cpu.toL2Bus.trans_dist::WritebackDirty 9609467 # Transaction distribution 1204system.cpu.toL2Bus.trans_dist::WritebackClean 24176986 # Transaction distribution 1205system.cpu.toL2Bus.trans_dist::CleanEvict 2728127 # Transaction distribution 1206system.cpu.toL2Bus.trans_dist::UpgradeReq 47900 # Transaction distribution |
| 1195system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution | 1207system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution |
| 1196system.cpu.toL2Bus.trans_dist::UpgradeResp 47873 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::ReadExReq 2263598 # Transaction distribution 1198system.cpu.toL2Bus.trans_dist::ReadExResp 2263598 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::ReadCleanReq 24166711 # Transaction distribution 1200system.cpu.toL2Bus.trans_dist::ReadSharedReq 7240510 # Transaction distribution 1201system.cpu.toL2Bus.trans_dist::InvalidateReq 1346166 # Transaction distribution 1202system.cpu.toL2Bus.trans_dist::InvalidateResp 1239502 # Transaction distribution 1203system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72600538 # Packet count per connected master and slave (bytes) 1204system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32434260 # Packet count per connected master and slave (bytes) 1205system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 690132 # Packet count per connected master and slave (bytes) 1206system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2164681 # Packet count per connected master and slave (bytes) 1207system.cpu.toL2Bus.pkt_count::total 107889611 # Packet count per connected master and slave (bytes) 1208system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3096417152 # Cumulative packet size per connected master and slave (bytes) 1209system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135639442 # Cumulative packet size per connected master and slave (bytes) 1210system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2297512 # Cumulative packet size per connected master and slave (bytes) 1211system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7399400 # Cumulative packet size per connected master and slave (bytes) 1212system.cpu.toL2Bus.pkt_size::total 4241753506 # Cumulative packet size per connected master and slave (bytes) 1213system.cpu.toL2Bus.snoops 2152838 # Total snoops (count) 1214system.cpu.toL2Bus.snoop_fanout::samples 38433190 # Request fanout histogram 1215system.cpu.toL2Bus.snoop_fanout::mean 0.018207 # Request fanout histogram 1216system.cpu.toL2Bus.snoop_fanout::stdev 0.133699 # Request fanout histogram | 1208system.cpu.toL2Bus.trans_dist::UpgradeResp 47901 # Transaction distribution 1209system.cpu.toL2Bus.trans_dist::ReadExReq 2261407 # Transaction distribution 1210system.cpu.toL2Bus.trans_dist::ReadExResp 2261407 # Transaction distribution 1211system.cpu.toL2Bus.trans_dist::ReadCleanReq 24177508 # Transaction distribution 1212system.cpu.toL2Bus.trans_dist::ReadSharedReq 7241194 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::InvalidateReq 1345330 # Transaction distribution 1214system.cpu.toL2Bus.trans_dist::InvalidateResp 1238666 # Transaction distribution 1215system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72636616 # Packet count per connected master and slave (bytes) 1216system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32428005 # Packet count per connected master and slave (bytes) 1217system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 687897 # Packet count per connected master and slave (bytes) 1218system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2160128 # Packet count per connected master and slave (bytes) 1219system.cpu.toL2Bus.pkt_count::total 107912646 # Packet count per connected master and slave (bytes) 1220system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3098035136 # Cumulative packet size per connected master and slave (bytes) 1221system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135439954 # Cumulative packet size per connected master and slave (bytes) 1222system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2278088 # Cumulative packet size per connected master and slave (bytes) 1223system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7359520 # Cumulative packet size per connected master and slave (bytes) 1224system.cpu.toL2Bus.pkt_size::total 4243112698 # Cumulative packet size per connected master and slave (bytes) 1225system.cpu.toL2Bus.snoops 2160696 # Total snoops (count) 1226system.cpu.toL2Bus.snoop_fanout::samples 38442129 # Request fanout histogram 1227system.cpu.toL2Bus.snoop_fanout::mean 0.018241 # Request fanout histogram 1228system.cpu.toL2Bus.snoop_fanout::stdev 0.133822 # Request fanout histogram |
| 1217system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1229system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1218system.cpu.toL2Bus.snoop_fanout::0 37733441 98.18% 98.18% # Request fanout histogram 1219system.cpu.toL2Bus.snoop_fanout::1 699749 1.82% 100.00% # Request fanout histogram | 1230system.cpu.toL2Bus.snoop_fanout::0 37740909 98.18% 98.18% # Request fanout histogram 1231system.cpu.toL2Bus.snoop_fanout::1 701220 1.82% 100.00% # Request fanout histogram |
| 1220system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1221system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1222system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1223system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1232system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1233system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1234system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1235system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1224system.cpu.toL2Bus.snoop_fanout::total 38433190 # Request fanout histogram 1225system.cpu.toL2Bus.reqLayer0.occupancy 68234466996 # Layer occupancy (ticks) | 1236system.cpu.toL2Bus.snoop_fanout::total 38442129 # Request fanout histogram 1237system.cpu.toL2Bus.reqLayer0.occupancy 68252447493 # Layer occupancy (ticks) |
| 1226system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1238system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1227system.cpu.toL2Bus.snoopLayer0.occupancy 1477892 # Layer occupancy (ticks) | 1239system.cpu.toL2Bus.snoopLayer0.occupancy 1464392 # Layer occupancy (ticks) |
| 1228system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1240system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1229system.cpu.toL2Bus.respLayer0.occupancy 36335720582 # Layer occupancy (ticks) | 1241system.cpu.toL2Bus.respLayer0.occupancy 36351871671 # Layer occupancy (ticks) |
| 1230system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1242system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1231system.cpu.toL2Bus.respLayer1.occupancy 14937837927 # Layer occupancy (ticks) | 1243system.cpu.toL2Bus.respLayer1.occupancy 14935181922 # Layer occupancy (ticks) |
| 1232system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1244system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1233system.cpu.toL2Bus.respLayer2.occupancy 402991902 # Layer occupancy (ticks) | 1245system.cpu.toL2Bus.respLayer2.occupancy 403175920 # Layer occupancy (ticks) |
| 1234system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1246system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1235system.cpu.toL2Bus.respLayer3.occupancy 1239794423 # Layer occupancy (ticks) | 1247system.cpu.toL2Bus.respLayer3.occupancy 1240232910 # Layer occupancy (ticks) |
| 1236system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1248system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1237system.iobus.trans_dist::ReadReq 40325 # Transaction distribution 1238system.iobus.trans_dist::ReadResp 40325 # Transaction distribution | 1249system.iobus.trans_dist::ReadReq 40322 # Transaction distribution 1250system.iobus.trans_dist::ReadResp 40322 # Transaction distribution |
| 1239system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1240system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1241system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1242system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1243system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1244system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1245system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1246system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1247system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1248system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1249system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1250system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1251system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1252system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1253system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1254system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) | 1251system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1252system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1253system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1254system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1255system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1256system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1257system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1258system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1259system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1260system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1261system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1262system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1263system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1264system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1265system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1266system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) |
| 1255system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) 1256system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) | 1267system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) 1268system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) |
| 1257system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1258system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 1269system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1270system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
| 1259system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) | 1271system.iobus.pkt_count::total 353786 # Packet count per connected master and slave (bytes) |
| 1260system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1263system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1264system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1265system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1266system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1267system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1268system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1269system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1270system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1271system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1272system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1273system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) | 1272system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1273system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1274system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1275system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1276system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1277system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1278system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1279system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1280system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1281system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1282system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1283system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1284system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1285system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) |
| 1274system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) 1275system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) | 1286system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) 1287system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) |
| 1276system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1277system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 1288system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1289system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
| 1278system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) 1279system.iobus.reqLayer0.occupancy 42167500 # Layer occupancy (ticks) | 1290system.iobus.pkt_size::total 7492360 # Cumulative packet size per connected master and slave (bytes) 1291system.iobus.reqLayer0.occupancy 42165000 # Layer occupancy (ticks) |
| 1280system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1281system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1282system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1283system.iobus.reqLayer2.occupancy 332500 # Layer occupancy (ticks) 1284system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1285system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 1286system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1287system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1293system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1294system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1295system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 1296system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1297system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) 1298system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1299system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 1300system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 1292system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1293system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1294system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1295system.iobus.reqLayer2.occupancy 332500 # Layer occupancy (ticks) 1296system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1297system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 1298system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1299system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1305system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1306system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1307system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 1308system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1309system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) 1310system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1311system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 1312system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 1301system.iobus.reqLayer23.occupancy 25751500 # Layer occupancy (ticks) | 1313system.iobus.reqLayer23.occupancy 25683500 # Layer occupancy (ticks) |
| 1302system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1314system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 1303system.iobus.reqLayer24.occupancy 34145500 # Layer occupancy (ticks) | 1315system.iobus.reqLayer24.occupancy 34144500 # Layer occupancy (ticks) |
| 1304system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1316system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1305system.iobus.reqLayer25.occupancy 565709151 # Layer occupancy (ticks) | 1317system.iobus.reqLayer25.occupancy 567247076 # Layer occupancy (ticks) |
| 1306system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1307system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1308system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1318system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1319system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1320system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1309system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) | 1321system.iobus.respLayer3.occupancy 147762000 # Layer occupancy (ticks) |
| 1310system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1311system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1312system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 1322system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1323system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1324system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 1313system.iocache.tags.replacements 115486 # number of replacements 1314system.iocache.tags.tagsinuse 10.440009 # Cycle average of tags in use | 1325system.iocache.tags.replacements 115483 # number of replacements 1326system.iocache.tags.tagsinuse 10.440004 # Cycle average of tags in use |
| 1315system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 1327system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 1316system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. | 1328system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. |
| 1317system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 1329system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
| 1318system.iocache.tags.warmup_cycle 13160148730000 # Cycle when the warmup percentage was hit. 1319system.iocache.tags.occ_blocks::realview.ethernet 3.520855 # Average occupied blocks per requestor 1320system.iocache.tags.occ_blocks::realview.ide 6.919154 # Average occupied blocks per requestor | 1330system.iocache.tags.warmup_cycle 13160148727000 # Cycle when the warmup percentage was hit. 1331system.iocache.tags.occ_blocks::realview.ethernet 3.520843 # Average occupied blocks per requestor 1332system.iocache.tags.occ_blocks::realview.ide 6.919161 # Average occupied blocks per requestor |
| 1321system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy | 1333system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy |
| 1322system.iocache.tags.occ_percent::realview.ide 0.432447 # Average percentage of cache occupancy 1323system.iocache.tags.occ_percent::total 0.652501 # Average percentage of cache occupancy | 1334system.iocache.tags.occ_percent::realview.ide 0.432448 # Average percentage of cache occupancy 1335system.iocache.tags.occ_percent::total 0.652500 # Average percentage of cache occupancy |
| 1324system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1325system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1326system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1336system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1337system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1338system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1327system.iocache.tags.tag_accesses 1039893 # Number of tag accesses 1328system.iocache.tags.data_accesses 1039893 # Number of data accesses | 1339system.iocache.tags.tag_accesses 1039866 # Number of tag accesses 1340system.iocache.tags.data_accesses 1039866 # Number of data accesses |
| 1329system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 1341system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
| 1330system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses 1331system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses | 1342system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses 1343system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses |
| 1332system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1333system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1334system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1335system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1336system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 1344system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1345system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1346system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1347system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1348system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 1337system.iocache.demand_misses::realview.ide 8840 # number of demand (read+write) misses 1338system.iocache.demand_misses::total 8880 # number of demand (read+write) misses | 1349system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses 1350system.iocache.demand_misses::total 8877 # number of demand (read+write) misses |
| 1339system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 1351system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 1340system.iocache.overall_misses::realview.ide 8840 # number of overall misses 1341system.iocache.overall_misses::total 8880 # number of overall misses | 1352system.iocache.overall_misses::realview.ide 8837 # number of overall misses 1353system.iocache.overall_misses::total 8877 # number of overall misses |
| 1342system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles | 1354system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles |
| 1343system.iocache.ReadReq_miss_latency::realview.ide 1638496114 # number of ReadReq miss cycles 1344system.iocache.ReadReq_miss_latency::total 1643565614 # number of ReadReq miss cycles | 1355system.iocache.ReadReq_miss_latency::realview.ide 1647976559 # number of ReadReq miss cycles 1356system.iocache.ReadReq_miss_latency::total 1653046059 # number of ReadReq miss cycles |
| 1345system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1346system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles | 1357system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1358system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles |
| 1347system.iocache.WriteLineReq_miss_latency::realview.ide 13864020537 # number of WriteLineReq miss cycles 1348system.iocache.WriteLineReq_miss_latency::total 13864020537 # number of WriteLineReq miss cycles | 1359system.iocache.WriteLineReq_miss_latency::realview.ide 13408898017 # number of WriteLineReq miss cycles 1360system.iocache.WriteLineReq_miss_latency::total 13408898017 # number of WriteLineReq miss cycles |
| 1349system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles | 1361system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles |
| 1350system.iocache.demand_miss_latency::realview.ide 1638496114 # number of demand (read+write) miss cycles 1351system.iocache.demand_miss_latency::total 1643916614 # number of demand (read+write) miss cycles | 1362system.iocache.demand_miss_latency::realview.ide 1647976559 # number of demand (read+write) miss cycles 1363system.iocache.demand_miss_latency::total 1653397059 # number of demand (read+write) miss cycles |
| 1352system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles | 1364system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles |
| 1353system.iocache.overall_miss_latency::realview.ide 1638496114 # number of overall miss cycles 1354system.iocache.overall_miss_latency::total 1643916614 # number of overall miss cycles | 1365system.iocache.overall_miss_latency::realview.ide 1647976559 # number of overall miss cycles 1366system.iocache.overall_miss_latency::total 1653397059 # number of overall miss cycles |
| 1355system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 1367system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
| 1356system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) 1357system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) | 1368system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) 1369system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) |
| 1358system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1359system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1360system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1361system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1362system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 1370system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1371system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1372system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1373system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1374system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 1363system.iocache.demand_accesses::realview.ide 8840 # number of demand (read+write) accesses 1364system.iocache.demand_accesses::total 8880 # number of demand (read+write) accesses | 1375system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses 1376system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses |
| 1365system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 1377system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 1366system.iocache.overall_accesses::realview.ide 8840 # number of overall (read+write) accesses 1367system.iocache.overall_accesses::total 8880 # number of overall (read+write) accesses | 1378system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses 1379system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses |
| 1368system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1369system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1370system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1371system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1372system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1373system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1374system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1375system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1376system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1377system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1378system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1379system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1380system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1381system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency | 1380system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1381system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1382system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1383system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1384system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1385system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1386system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1387system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1388system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1389system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1390system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1391system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1392system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1393system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency |
| 1382system.iocache.ReadReq_avg_miss_latency::realview.ide 185350.239140 # average ReadReq miss latency 1383system.iocache.ReadReq_avg_miss_latency::total 185148.768052 # average ReadReq miss latency | 1394system.iocache.ReadReq_avg_miss_latency::realview.ide 186485.974765 # average ReadReq miss latency 1395system.iocache.ReadReq_avg_miss_latency::total 186279.700135 # average ReadReq miss latency |
| 1384system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1385system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency | 1396system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1397system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency |
| 1386system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129978.441995 # average WriteLineReq miss latency 1387system.iocache.WriteLineReq_avg_miss_latency::total 129978.441995 # average WriteLineReq miss latency | 1398system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125711.561698 # average WriteLineReq miss latency 1399system.iocache.WriteLineReq_avg_miss_latency::total 125711.561698 # average WriteLineReq miss latency |
| 1388system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency | 1400system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency |
| 1389system.iocache.demand_avg_miss_latency::realview.ide 185350.239140 # average overall miss latency 1390system.iocache.demand_avg_miss_latency::total 185125.744820 # average overall miss latency | 1401system.iocache.demand_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency 1402system.iocache.demand_avg_miss_latency::total 186256.286921 # average overall miss latency |
| 1391system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency | 1403system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency |
| 1392system.iocache.overall_avg_miss_latency::realview.ide 185350.239140 # average overall miss latency 1393system.iocache.overall_avg_miss_latency::total 185125.744820 # average overall miss latency 1394system.iocache.blocked_cycles::no_mshrs 33657 # number of cycles access was blocked | 1404system.iocache.overall_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency 1405system.iocache.overall_avg_miss_latency::total 186256.286921 # average overall miss latency 1406system.iocache.blocked_cycles::no_mshrs 33362 # number of cycles access was blocked |
| 1395system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1407system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1396system.iocache.blocked::no_mshrs 3502 # number of cycles access was blocked | 1408system.iocache.blocked::no_mshrs 3432 # number of cycles access was blocked |
| 1397system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1409system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1398system.iocache.avg_blocked_cycles::no_mshrs 9.610794 # average number of cycles each access was blocked | 1410system.iocache.avg_blocked_cycles::no_mshrs 9.720862 # average number of cycles each access was blocked |
| 1399system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1400system.iocache.fast_writes 0 # number of fast writes performed 1401system.iocache.cache_copies 0 # number of cache copies performed 1402system.iocache.writebacks::writebacks 106631 # number of writebacks 1403system.iocache.writebacks::total 106631 # number of writebacks 1404system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses | 1411system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1412system.iocache.fast_writes 0 # number of fast writes performed 1413system.iocache.cache_copies 0 # number of cache copies performed 1414system.iocache.writebacks::writebacks 106631 # number of writebacks 1415system.iocache.writebacks::total 106631 # number of writebacks 1416system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses |
| 1405system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses 1406system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses | 1417system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses 1418system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses |
| 1407system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1408system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1409system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1410system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1411system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 1419system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1420system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1421system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1422system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1423system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 1412system.iocache.demand_mshr_misses::realview.ide 8840 # number of demand (read+write) MSHR misses 1413system.iocache.demand_mshr_misses::total 8880 # number of demand (read+write) MSHR misses | 1424system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses 1425system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses |
| 1414system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 1426system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 1415system.iocache.overall_mshr_misses::realview.ide 8840 # number of overall MSHR misses 1416system.iocache.overall_mshr_misses::total 8880 # number of overall MSHR misses | 1427system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses 1428system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses |
| 1417system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles | 1429system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles |
| 1418system.iocache.ReadReq_mshr_miss_latency::realview.ide 1196496114 # number of ReadReq MSHR miss cycles 1419system.iocache.ReadReq_mshr_miss_latency::total 1199715614 # number of ReadReq MSHR miss cycles | 1430system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206126559 # number of ReadReq MSHR miss cycles 1431system.iocache.ReadReq_mshr_miss_latency::total 1209346059 # number of ReadReq MSHR miss cycles |
| 1420system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1421system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles | 1432system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1433system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles |
| 1422system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8530820537 # number of WriteLineReq MSHR miss cycles 1423system.iocache.WriteLineReq_mshr_miss_latency::total 8530820537 # number of WriteLineReq MSHR miss cycles | 1434system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8070540171 # number of WriteLineReq MSHR miss cycles 1435system.iocache.WriteLineReq_mshr_miss_latency::total 8070540171 # number of WriteLineReq MSHR miss cycles |
| 1424system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles | 1436system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles |
| 1425system.iocache.demand_mshr_miss_latency::realview.ide 1196496114 # number of demand (read+write) MSHR miss cycles 1426system.iocache.demand_mshr_miss_latency::total 1199916614 # number of demand (read+write) MSHR miss cycles | 1437system.iocache.demand_mshr_miss_latency::realview.ide 1206126559 # number of demand (read+write) MSHR miss cycles 1438system.iocache.demand_mshr_miss_latency::total 1209547059 # number of demand (read+write) MSHR miss cycles |
| 1427system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles | 1439system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles |
| 1428system.iocache.overall_mshr_miss_latency::realview.ide 1196496114 # number of overall MSHR miss cycles 1429system.iocache.overall_mshr_miss_latency::total 1199916614 # number of overall MSHR miss cycles | 1440system.iocache.overall_mshr_miss_latency::realview.ide 1206126559 # number of overall MSHR miss cycles 1441system.iocache.overall_mshr_miss_latency::total 1209547059 # number of overall MSHR miss cycles |
| 1430system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1431system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1432system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1433system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1434system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1435system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1436system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1437system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1438system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1439system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1440system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1441system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1442system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1443system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency | 1442system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1443system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1444system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1445system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1446system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1447system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1448system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1449system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1450system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1451system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1452system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1453system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1454system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1455system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency |
| 1444system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135350.239140 # average ReadReq mshr miss latency 1445system.iocache.ReadReq_avg_mshr_miss_latency::total 135148.768052 # average ReadReq mshr miss latency | 1456system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136485.974765 # average ReadReq mshr miss latency 1457system.iocache.ReadReq_avg_mshr_miss_latency::total 136279.700135 # average ReadReq mshr miss latency |
| 1446system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1447system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency | 1458system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1459system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency |
| 1448system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79978.441995 # average WriteLineReq mshr miss latency 1449system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.441995 # average WriteLineReq mshr miss latency | 1460system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75663.205683 # average WriteLineReq mshr miss latency 1461system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75663.205683 # average WriteLineReq mshr miss latency |
| 1450system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency | 1462system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency |
| 1451system.iocache.demand_avg_mshr_miss_latency::realview.ide 135350.239140 # average overall mshr miss latency 1452system.iocache.demand_avg_mshr_miss_latency::total 135125.744820 # average overall mshr miss latency | 1463system.iocache.demand_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency 1464system.iocache.demand_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency |
| 1453system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency | 1465system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency |
| 1454system.iocache.overall_avg_mshr_miss_latency::realview.ide 135350.239140 # average overall mshr miss latency 1455system.iocache.overall_avg_mshr_miss_latency::total 135125.744820 # average overall mshr miss latency | 1466system.iocache.overall_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency 1467system.iocache.overall_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency |
| 1456system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1457system.membus.trans_dist::ReadReq 86006 # Transaction distribution | 1468system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1469system.membus.trans_dist::ReadReq 86006 # Transaction distribution |
| 1458system.membus.trans_dist::ReadResp 527021 # Transaction distribution | 1470system.membus.trans_dist::ReadResp 526304 # Transaction distribution |
| 1459system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1460system.membus.trans_dist::WriteResp 33706 # Transaction distribution | 1471system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1472system.membus.trans_dist::WriteResp 33706 # Transaction distribution |
| 1461system.membus.trans_dist::WritebackDirty 1365292 # Transaction distribution 1462system.membus.trans_dist::CleanEvict 236782 # Transaction distribution 1463system.membus.trans_dist::UpgradeReq 38218 # Transaction distribution | 1473system.membus.trans_dist::WritebackDirty 1365657 # Transaction distribution 1474system.membus.trans_dist::CleanEvict 238956 # Transaction distribution 1475system.membus.trans_dist::UpgradeReq 38308 # Transaction distribution |
| 1464system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution | 1476system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution |
| 1465system.membus.trans_dist::UpgradeResp 38219 # Transaction distribution 1466system.membus.trans_dist::ReadExReq 1148769 # Transaction distribution 1467system.membus.trans_dist::ReadExResp 1148769 # Transaction distribution 1468system.membus.trans_dist::ReadSharedReq 441015 # Transaction distribution | 1477system.membus.trans_dist::UpgradeResp 7 # Transaction distribution 1478system.membus.trans_dist::ReadExReq 1150364 # Transaction distribution 1479system.membus.trans_dist::ReadExResp 1150364 # Transaction distribution 1480system.membus.trans_dist::ReadSharedReq 440298 # Transaction distribution |
| 1469system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution | 1481system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution |
| 1470system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution | |
| 1471system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1472system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1473system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) | 1482system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1483system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1484system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) |
| 1474system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4836672 # Packet count per connected master and slave (bytes) 1475system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4966324 # Packet count per connected master and slave (bytes) 1476system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341304 # Packet count per connected master and slave (bytes) 1477system.membus.pkt_count_system.iocache.mem_side::total 341304 # Packet count per connected master and slave (bytes) 1478system.membus.pkt_count::total 5307628 # Packet count per connected master and slave (bytes) | 1485system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4800126 # Packet count per connected master and slave (bytes) 1486system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4929778 # Packet count per connected master and slave (bytes) 1487system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237399 # Packet count per connected master and slave (bytes) 1488system.membus.pkt_count_system.iocache.mem_side::total 237399 # Packet count per connected master and slave (bytes) 1489system.membus.pkt_count::total 5167177 # Packet count per connected master and slave (bytes) |
| 1479system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1480system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1481system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) | 1490system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1491system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1492system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) |
| 1482system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185058092 # Cumulative packet size per connected master and slave (bytes) 1483system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185228498 # Cumulative packet size per connected master and slave (bytes) 1484system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7229952 # Cumulative packet size per connected master and slave (bytes) 1485system.membus.pkt_size_system.iocache.mem_side::total 7229952 # Cumulative packet size per connected master and slave (bytes) 1486system.membus.pkt_size::total 192458450 # Cumulative packet size per connected master and slave (bytes) 1487system.membus.snoops 3204 # Total snoops (count) 1488system.membus.snoop_fanout::samples 3459197 # Request fanout histogram | 1493system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185137772 # Cumulative packet size per connected master and slave (bytes) 1494system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185308178 # Cumulative packet size per connected master and slave (bytes) 1495system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232384 # Cumulative packet size per connected master and slave (bytes) 1496system.membus.pkt_size_system.iocache.mem_side::total 7232384 # Cumulative packet size per connected master and slave (bytes) 1497system.membus.pkt_size::total 192540562 # Cumulative packet size per connected master and slave (bytes) 1498system.membus.snoops 3164 # Total snoops (count) 1499system.membus.snoop_fanout::samples 3459998 # Request fanout histogram |
| 1489system.membus.snoop_fanout::mean 1 # Request fanout histogram 1490system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1491system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1492system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1500system.membus.snoop_fanout::mean 1 # Request fanout histogram 1501system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1502system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1503system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1493system.membus.snoop_fanout::1 3459197 100.00% 100.00% # Request fanout histogram | 1504system.membus.snoop_fanout::1 3459998 100.00% 100.00% # Request fanout histogram |
| 1494system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1495system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1496system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1497system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1505system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1506system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1507system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1508system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1498system.membus.snoop_fanout::total 3459197 # Request fanout histogram 1499system.membus.reqLayer0.occupancy 102492500 # Layer occupancy (ticks) | 1509system.membus.snoop_fanout::total 3459998 # Request fanout histogram 1510system.membus.reqLayer0.occupancy 102421000 # Layer occupancy (ticks) |
| 1500system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1501system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1502system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1511system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1512system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1513system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1503system.membus.reqLayer2.occupancy 5497000 # Layer occupancy (ticks) | 1514system.membus.reqLayer2.occupancy 5498500 # Layer occupancy (ticks) |
| 1504system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1515system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1505system.membus.reqLayer5.occupancy 9250665962 # Layer occupancy (ticks) | 1516system.membus.reqLayer5.occupancy 9252697708 # Layer occupancy (ticks) |
| 1506system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1517system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1507system.membus.respLayer2.occupancy 8763516637 # Layer occupancy (ticks) | 1518system.membus.respLayer2.occupancy 8691723530 # Layer occupancy (ticks) |
| 1508system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1519system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1509system.membus.respLayer3.occupancy 227782427 # Layer occupancy (ticks) | 1520system.membus.respLayer3.occupancy 44915426 # Layer occupancy (ticks) |
| 1510system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1511system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1512system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1513system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1514system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1515system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1516system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1517system.realview.ethernet.txBytes 966 # Bytes Transmitted --- 47 unchanged lines hidden --- | 1521system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1522system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1523system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1524system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1525system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1526system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1527system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1528system.realview.ethernet.txBytes 966 # Bytes Transmitted --- 47 unchanged lines hidden --- |