| stats.txt (10753:48a72150f82c) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.609999 # Number of seconds simulated 4sim_ticks 51609998980000 # Number of ticks simulated 5final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.609999 # Number of seconds simulated 4sim_ticks 51609998980000 # Number of ticks simulated 5final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 125549 # Simulator instruction rate (inst/s) 8host_op_rate 147521 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6837484784 # Simulator tick rate (ticks/s) 10host_mem_usage 653616 # Number of bytes of host memory used 11host_seconds 7548.10 # Real time elapsed on the host | 7host_inst_rate 182485 # Simulator instruction rate (inst/s) 8host_op_rate 214421 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9938249935 # Simulator tick rate (ticks/s) 10host_mem_usage 720032 # Number of bytes of host memory used 11host_seconds 5193.07 # Real time elapsed on the host |
| 12sim_insts 947659008 # Number of instructions simulated 13sim_ops 1113505098 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 398592 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 332160 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10228032 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 65553800 # Number of bytes read from this memory --- 658 unchanged lines hidden (view full) --- 678system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246202 # number of LoadLockedReq MSHR misses 679system.cpu.dcache.LoadLockedReq_mshr_misses::total 246202 # number of LoadLockedReq MSHR misses 680system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 681system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 682system.cpu.dcache.demand_mshr_misses::cpu.data 8185275 # number of demand (read+write) MSHR misses 683system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses 684system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses 685system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses | 12sim_insts 947659008 # Number of instructions simulated 13sim_ops 1113505098 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 398592 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 332160 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10228032 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 65553800 # Number of bytes read from this memory --- 658 unchanged lines hidden (view full) --- 678system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246202 # number of LoadLockedReq MSHR misses 679system.cpu.dcache.LoadLockedReq_mshr_misses::total 246202 # number of LoadLockedReq MSHR misses 680system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 681system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 682system.cpu.dcache.demand_mshr_misses::cpu.data 8185275 # number of demand (read+write) MSHR misses 683system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses 684system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses 685system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses |
| 686system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable 687system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable 688system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable 689system.cpu.dcache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable 690system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses 691system.cpu.dcache.overall_mshr_uncacheable_misses::total 67401 # number of overall MSHR uncacheable misses |
|
| 686system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles 687system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles 688system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles 689system.cpu.dcache.WriteReq_mshr_miss_latency::total 78901247228 # number of WriteReq MSHR miss cycles 690system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22730570766 # number of SoftPFReq MSHR miss cycles 691system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22730570766 # number of SoftPFReq MSHR miss cycles 692system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33591268829 # number of WriteInvalidateReq MSHR miss cycles 693system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33591268829 # number of WriteInvalidateReq MSHR miss cycles --- 38 unchanged lines hidden (view full) --- 732system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13163.919294 # average LoadLockedReq mshr miss latency 733system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13163.919294 # average LoadLockedReq mshr miss latency 734system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency 735system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency 736system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416 # average overall mshr miss latency 737system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency 738system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency 739system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency | 692system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::total 78901247228 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22730570766 # number of SoftPFReq MSHR miss cycles 697system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22730570766 # number of SoftPFReq MSHR miss cycles 698system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33591268829 # number of WriteInvalidateReq MSHR miss cycles 699system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33591268829 # number of WriteInvalidateReq MSHR miss cycles --- 38 unchanged lines hidden (view full) --- 738system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13163.919294 # average LoadLockedReq mshr miss latency 739system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13163.919294 # average LoadLockedReq mshr miss latency 740system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency 741system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency 742system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416 # average overall mshr miss latency 743system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency 744system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency 745system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency |
| 740system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 741system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 742system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 743system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 744system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 745system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 746system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170695.156458 # average ReadReq mshr uncacheable latency 747system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170695.156458 # average ReadReq mshr uncacheable latency 748system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166484.683281 # average WriteReq mshr uncacheable latency 749system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166484.683281 # average WriteReq mshr uncacheable latency 750system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168589.638759 # average overall mshr uncacheable latency 751system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168589.638759 # average overall mshr uncacheable latency |
| 746system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 747system.cpu.icache.tags.replacements 24538707 # number of replacements 748system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use 749system.cpu.icache.tags.total_refs 427825373 # Total number of references to valid blocks. 750system.cpu.icache.tags.sampled_refs 24539219 # Sample count of references to valid blocks. 751system.cpu.icache.tags.avg_refs 17.434352 # Average number of references to valid blocks. 752system.cpu.icache.tags.warmup_cycle 22330853250 # Cycle when the warmup percentage was hit. 753system.cpu.icache.tags.occ_blocks::cpu.inst 511.926996 # Average occupied blocks per requestor --- 51 unchanged lines hidden (view full) --- 805system.cpu.icache.fast_writes 0 # number of fast writes performed 806system.cpu.icache.cache_copies 0 # number of cache copies performed 807system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24539229 # number of ReadReq MSHR misses 808system.cpu.icache.ReadReq_mshr_misses::total 24539229 # number of ReadReq MSHR misses 809system.cpu.icache.demand_mshr_misses::cpu.inst 24539229 # number of demand (read+write) MSHR misses 810system.cpu.icache.demand_mshr_misses::total 24539229 # number of demand (read+write) MSHR misses 811system.cpu.icache.overall_mshr_misses::cpu.inst 24539229 # number of overall MSHR misses 812system.cpu.icache.overall_mshr_misses::total 24539229 # number of overall MSHR misses | 752system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 753system.cpu.icache.tags.replacements 24538707 # number of replacements 754system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use 755system.cpu.icache.tags.total_refs 427825373 # Total number of references to valid blocks. 756system.cpu.icache.tags.sampled_refs 24539219 # Sample count of references to valid blocks. 757system.cpu.icache.tags.avg_refs 17.434352 # Average number of references to valid blocks. 758system.cpu.icache.tags.warmup_cycle 22330853250 # Cycle when the warmup percentage was hit. 759system.cpu.icache.tags.occ_blocks::cpu.inst 511.926996 # Average occupied blocks per requestor --- 51 unchanged lines hidden (view full) --- 811system.cpu.icache.fast_writes 0 # number of fast writes performed 812system.cpu.icache.cache_copies 0 # number of cache copies performed 813system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24539229 # number of ReadReq MSHR misses 814system.cpu.icache.ReadReq_mshr_misses::total 24539229 # number of ReadReq MSHR misses 815system.cpu.icache.demand_mshr_misses::cpu.inst 24539229 # number of demand (read+write) MSHR misses 816system.cpu.icache.demand_mshr_misses::total 24539229 # number of demand (read+write) MSHR misses 817system.cpu.icache.overall_mshr_misses::cpu.inst 24539229 # number of overall MSHR misses 818system.cpu.icache.overall_mshr_misses::total 24539229 # number of overall MSHR misses |
| 819system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable 820system.cpu.icache.ReadReq_mshr_uncacheable::total 52294 # number of ReadReq MSHR uncacheable 821system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses 822system.cpu.icache.overall_mshr_uncacheable_misses::total 52294 # number of overall MSHR uncacheable misses |
|
| 813system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082 # number of ReadReq MSHR miss cycles 814system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082 # number of ReadReq MSHR miss cycles 815system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082 # number of demand (read+write) MSHR miss cycles 816system.cpu.icache.demand_mshr_miss_latency::total 290116862082 # number of demand (read+write) MSHR miss cycles 817system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290116862082 # number of overall MSHR miss cycles 818system.cpu.icache.overall_mshr_miss_latency::total 290116862082 # number of overall MSHR miss cycles 819system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4024065500 # number of ReadReq MSHR uncacheable cycles 820system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4024065500 # number of ReadReq MSHR uncacheable cycles --- 6 unchanged lines hidden (view full) --- 827system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for overall accesses 828system.cpu.icache.overall_mshr_miss_rate::total 0.054247 # mshr miss rate for overall accesses 829system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11822.574462 # average ReadReq mshr miss latency 830system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11822.574462 # average ReadReq mshr miss latency 831system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency 832system.cpu.icache.demand_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency 833system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency 834system.cpu.icache.overall_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency | 823system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082 # number of ReadReq MSHR miss cycles 824system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082 # number of ReadReq MSHR miss cycles 825system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082 # number of demand (read+write) MSHR miss cycles 826system.cpu.icache.demand_mshr_miss_latency::total 290116862082 # number of demand (read+write) MSHR miss cycles 827system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290116862082 # number of overall MSHR miss cycles 828system.cpu.icache.overall_mshr_miss_latency::total 290116862082 # number of overall MSHR miss cycles 829system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4024065500 # number of ReadReq MSHR uncacheable cycles 830system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4024065500 # number of ReadReq MSHR uncacheable cycles --- 6 unchanged lines hidden (view full) --- 837system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for overall accesses 838system.cpu.icache.overall_mshr_miss_rate::total 0.054247 # mshr miss rate for overall accesses 839system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11822.574462 # average ReadReq mshr miss latency 840system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11822.574462 # average ReadReq mshr miss latency 841system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency 842system.cpu.icache.demand_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency 843system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency 844system.cpu.icache.overall_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency |
| 835system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 836system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 837system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 838system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 845system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average ReadReq mshr uncacheable latency 846system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76950.806976 # average ReadReq mshr uncacheable latency 847system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average overall mshr uncacheable latency 848system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76950.806976 # average overall mshr uncacheable latency |
| 839system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 840system.cpu.l2cache.tags.replacements 1594461 # number of replacements 841system.cpu.l2cache.tags.tagsinuse 65370.145273 # Cycle average of tags in use 842system.cpu.l2cache.tags.total_refs 40075906 # Total number of references to valid blocks. 843system.cpu.l2cache.tags.sampled_refs 1658209 # Sample count of references to valid blocks. 844system.cpu.l2cache.tags.avg_refs 24.168187 # Average number of references to valid blocks. 845system.cpu.l2cache.tags.warmup_cycle 6394381000 # Cycle when the warmup percentage was hit. 846system.cpu.l2cache.tags.occ_blocks::writebacks 36356.724167 # Average occupied blocks per requestor --- 196 unchanged lines hidden (view full) --- 1043system.cpu.l2cache.demand_mshr_misses::cpu.inst 107545 # number of demand (read+write) MSHR misses 1044system.cpu.l2cache.demand_mshr_misses::cpu.data 1025546 # number of demand (read+write) MSHR misses 1045system.cpu.l2cache.demand_mshr_misses::total 1144509 # number of demand (read+write) MSHR misses 1046system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6228 # number of overall MSHR misses 1047system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5190 # number of overall MSHR misses 1048system.cpu.l2cache.overall_mshr_misses::cpu.inst 107545 # number of overall MSHR misses 1049system.cpu.l2cache.overall_mshr_misses::cpu.data 1025546 # number of overall MSHR misses 1050system.cpu.l2cache.overall_mshr_misses::total 1144509 # number of overall MSHR misses | 849system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 850system.cpu.l2cache.tags.replacements 1594461 # number of replacements 851system.cpu.l2cache.tags.tagsinuse 65370.145273 # Cycle average of tags in use 852system.cpu.l2cache.tags.total_refs 40075906 # Total number of references to valid blocks. 853system.cpu.l2cache.tags.sampled_refs 1658209 # Sample count of references to valid blocks. 854system.cpu.l2cache.tags.avg_refs 24.168187 # Average number of references to valid blocks. 855system.cpu.l2cache.tags.warmup_cycle 6394381000 # Cycle when the warmup percentage was hit. 856system.cpu.l2cache.tags.occ_blocks::writebacks 36356.724167 # Average occupied blocks per requestor --- 196 unchanged lines hidden (view full) --- 1053system.cpu.l2cache.demand_mshr_misses::cpu.inst 107545 # number of demand (read+write) MSHR misses 1054system.cpu.l2cache.demand_mshr_misses::cpu.data 1025546 # number of demand (read+write) MSHR misses 1055system.cpu.l2cache.demand_mshr_misses::total 1144509 # number of demand (read+write) MSHR misses 1056system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6228 # number of overall MSHR misses 1057system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5190 # number of overall MSHR misses 1058system.cpu.l2cache.overall_mshr_misses::cpu.inst 107545 # number of overall MSHR misses 1059system.cpu.l2cache.overall_mshr_misses::cpu.data 1025546 # number of overall MSHR misses 1060system.cpu.l2cache.overall_mshr_misses::total 1144509 # number of overall MSHR misses |
| 1061system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable 1062system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable 1063system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85990 # number of ReadReq MSHR uncacheable 1064system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable 1065system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable 1066system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses 1067system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses 1068system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119695 # number of overall MSHR uncacheable misses |
|
| 1051system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 460278992 # number of ReadReq MSHR miss cycles 1052system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 386982750 # number of ReadReq MSHR miss cycles 1053system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7477222552 # number of ReadReq MSHR miss cycles 1054system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23476189203 # number of ReadReq MSHR miss cycles 1055system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31800673497 # number of ReadReq MSHR miss cycles 1056system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 18301171671 # number of WriteInvalidateReq MSHR miss cycles 1057system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18301171671 # number of WriteInvalidateReq MSHR miss cycles 1058system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 683876035 # number of UpgradeReq MSHR miss cycles --- 61 unchanged lines hidden (view full) --- 1120system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency 1121system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency 1122system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency 1123system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average overall mshr miss latency 1124system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average overall mshr miss latency 1125system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency 1126system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency 1127system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency | 1069system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 460278992 # number of ReadReq MSHR miss cycles 1070system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 386982750 # number of ReadReq MSHR miss cycles 1071system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7477222552 # number of ReadReq MSHR miss cycles 1072system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23476189203 # number of ReadReq MSHR miss cycles 1073system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31800673497 # number of ReadReq MSHR miss cycles 1074system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 18301171671 # number of WriteInvalidateReq MSHR miss cycles 1075system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18301171671 # number of WriteInvalidateReq MSHR miss cycles 1076system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 683876035 # number of UpgradeReq MSHR miss cycles --- 61 unchanged lines hidden (view full) --- 1138system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency 1139system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency 1140system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency 1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average overall mshr miss latency 1143system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency 1144system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency 1145system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency |
| 1128system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1129system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1130system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1131system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1132system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1133system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1134system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1135system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1146system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average ReadReq mshr uncacheable latency 1147system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156677.253977 # average ReadReq mshr uncacheable latency 1148system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97549.909873 # average ReadReq mshr uncacheable latency 1149system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153464.085447 # average WriteReq mshr uncacheable latency 1150system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153464.085447 # average WriteReq mshr uncacheable latency 1151system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average overall mshr uncacheable latency 1152system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155070.455186 # average overall mshr uncacheable latency 1153system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113294.822257 # average overall mshr uncacheable latency |
| 1136system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1137system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution 1138system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution 1139system.cpu.toL2Bus.trans_dist::WriteReq 33705 # Transaction distribution 1140system.cpu.toL2Bus.trans_dist::WriteResp 33705 # Transaction distribution 1141system.cpu.toL2Bus.trans_dist::Writeback 8509656 # Transaction distribution 1142system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351233 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244454 # Transaction distribution --- 8 unchanged lines hidden (view full) --- 1152system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2262449 # Packet count per connected master and slave (bytes) 1153system.cpu.toL2Bus.pkt_count::total 83069049 # Packet count per connected master and slave (bytes) 1154system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1573857216 # Cumulative packet size per connected master and slave (bytes) 1155system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1254806154 # Cumulative packet size per connected master and slave (bytes) 1156system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2290296 # Cumulative packet size per connected master and slave (bytes) 1157system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes) 1159system.cpu.toL2Bus.snoops 565529 # Total snoops (count) | 1154system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1155system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::WriteReq 33705 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::WriteResp 33705 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::Writeback 8509656 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351233 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244454 # Transaction distribution --- 8 unchanged lines hidden (view full) --- 1170system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2262449 # Packet count per connected master and slave (bytes) 1171system.cpu.toL2Bus.pkt_count::total 83069049 # Packet count per connected master and slave (bytes) 1172system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1573857216 # Cumulative packet size per connected master and slave (bytes) 1173system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1254806154 # Cumulative packet size per connected master and slave (bytes) 1174system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2290296 # Cumulative packet size per connected master and slave (bytes) 1175system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes) 1176system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes) 1177system.cpu.toL2Bus.snoops 565529 # Total snoops (count) |
| 1160system.cpu.toL2Bus.snoop_fanout::samples 46009467 # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::mean 3.002514 # Request fanout histogram 1162system.cpu.toL2Bus.snoop_fanout::stdev 0.050072 # Request fanout histogram | 1178system.cpu.toL2Bus.snoop_fanout::samples 46129162 # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::mean 1.039419 # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::stdev 0.194589 # Request fanout histogram |
| 1163system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1181system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1165system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::3 45893822 99.75% 99.75% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::4 115645 0.25% 100.00% # Request fanout histogram | 1183system.cpu.toL2Bus.snoop_fanout::1 44310813 96.06% 96.06% # Request fanout histogram 1184system.cpu.toL2Bus.snoop_fanout::2 1818349 3.94% 100.00% # Request fanout histogram |
| 1169system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1185system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1170system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::total 46009467 # Request fanout histogram | 1186system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1187system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1188system.cpu.toL2Bus.snoop_fanout::total 46129162 # Request fanout histogram |
| 1173system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks) 1174system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1175system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks) 1176system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1177system.cpu.toL2Bus.respLayer0.occupancy 36924053878 # Layer occupancy (ticks) 1178system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1179system.cpu.toL2Bus.respLayer1.occupancy 15679140875 # Layer occupancy (ticks) 1180system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 254 unchanged lines hidden (view full) --- 1435system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1436system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13824 # Cumulative packet size per connected master and slave (bytes) 1437system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198447468 # Cumulative packet size per connected master and slave (bytes) 1438system.membus.pkt_size_system.cpu.l2cache.mem_side::total 198617866 # Cumulative packet size per connected master and slave (bytes) 1439system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952 # Cumulative packet size per connected master and slave (bytes) 1440system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes) 1441system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes) 1442system.membus.snoops 2980 # Total snoops (count) | 1189system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks) 1190system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1191system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks) 1192system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1193system.cpu.toL2Bus.respLayer0.occupancy 36924053878 # Layer occupancy (ticks) 1194system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1195system.cpu.toL2Bus.respLayer1.occupancy 15679140875 # Layer occupancy (ticks) 1196system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 254 unchanged lines hidden (view full) --- 1451system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1452system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13824 # Cumulative packet size per connected master and slave (bytes) 1453system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198447468 # Cumulative packet size per connected master and slave (bytes) 1454system.membus.pkt_size_system.cpu.l2cache.mem_side::total 198617866 # Cumulative packet size per connected master and slave (bytes) 1455system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952 # Cumulative packet size per connected master and slave (bytes) 1456system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes) 1457system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes) 1458system.membus.snoops 2980 # Total snoops (count) |
| 1443system.membus.snoop_fanout::samples 3310460 # Request fanout histogram | 1459system.membus.snoop_fanout::samples 3430156 # Request fanout histogram |
| 1444system.membus.snoop_fanout::mean 1 # Request fanout histogram 1445system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1446system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1447system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1460system.membus.snoop_fanout::mean 1 # Request fanout histogram 1461system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1462system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1463system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1448system.membus.snoop_fanout::1 3310460 100.00% 100.00% # Request fanout histogram | 1464system.membus.snoop_fanout::1 3430156 100.00% 100.00% # Request fanout histogram |
| 1449system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1450system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1451system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1452system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1465system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1466system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1467system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1468system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1453system.membus.snoop_fanout::total 3310460 # Request fanout histogram | 1469system.membus.snoop_fanout::total 3430156 # Request fanout histogram |
| 1454system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks) 1455system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1456system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1457system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1458system.membus.reqLayer2.occupancy 5637000 # Layer occupancy (ticks) 1459system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1460system.membus.reqLayer5.occupancy 12263986868 # Layer occupancy (ticks) 1461system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) --- 48 unchanged lines hidden --- | 1470system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks) 1471system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1472system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1473system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1474system.membus.reqLayer2.occupancy 5637000 # Layer occupancy (ticks) 1475system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1476system.membus.reqLayer5.occupancy 12263986868 # Layer occupancy (ticks) 1477system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) --- 48 unchanged lines hidden --- |