| stats.txt (10515:bd7c2aa12122) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 51.727209 # Number of seconds simulated 4sim_ticks 51727209160500 # Number of ticks simulated 5final_tick 51727209160500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 51.688410 # Number of seconds simulated 4sim_ticks 51688410348500 # Number of ticks simulated 5final_tick 51688410348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 180889 # Simulator instruction rate (inst/s) 8host_op_rate 212546 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9849373518 # Simulator tick rate (ticks/s) 10host_mem_usage 656984 # Number of bytes of host memory used 11host_seconds 5251.83 # Real time elapsed on the host 12sim_insts 949996153 # Number of instructions simulated 13sim_ops 1116252474 # Number of ops (including micro ops) simulated | 7host_inst_rate 152333 # Simulator instruction rate (inst/s) 8host_op_rate 179011 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8275752383 # Simulator tick rate (ticks/s) 10host_mem_usage 662164 # Number of bytes of host memory used 11host_seconds 6245.77 # Real time elapsed on the host 12sim_insts 951433762 # Number of instructions simulated 13sim_ops 1118058358 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::realview.ide 424768 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 725248 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 1005696 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 91312008 # Number of bytes read from this memory 20system.physmem.bytes_read::total 93467720 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 9575168 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 9575168 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 57345920 # Number of bytes written to this memory 24system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.inst 101255460 # Number of bytes written to this memory 26system.physmem.bytes_written::total 165427876 # Number of bytes written to this memory 27system.physmem.num_reads::realview.ide 6637 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 11332 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 15714 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 1426763 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 1460446 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 896030 # Number of write requests responded to by this memory 33system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.inst 1584368 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 2587062 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.ide 8212 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 14021 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 19442 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 1765261 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 1806935 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu.inst 185109 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::total 185109 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_write::writebacks 1108622 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::realview.ide 131971 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.inst 1957489 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 3198082 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1108622 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.ide 140183 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 14021 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 19442 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 3722750 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 5005018 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 1460446 # Number of read requests accepted 54system.physmem.writeReqs 2587062 # Number of write requests accepted 55system.physmem.readBursts 1460446 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 2587062 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 93277376 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 191168 # Total number of bytes read from write queue 59system.physmem.bytesWritten 160708736 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 93467720 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 165427876 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 2987 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 75973 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 39020 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 90929 # Per bank write bursts 66system.physmem.perBankRdBursts::1 88965 # Per bank write bursts 67system.physmem.perBankRdBursts::2 84770 # Per bank write bursts 68system.physmem.perBankRdBursts::3 81753 # Per bank write bursts 69system.physmem.perBankRdBursts::4 95872 # Per bank write bursts 70system.physmem.perBankRdBursts::5 100020 # Per bank write bursts 71system.physmem.perBankRdBursts::6 87194 # Per bank write bursts 72system.physmem.perBankRdBursts::7 85191 # Per bank write bursts 73system.physmem.perBankRdBursts::8 88300 # Per bank write bursts 74system.physmem.perBankRdBursts::9 142631 # Per bank write bursts 75system.physmem.perBankRdBursts::10 90249 # Per bank write bursts 76system.physmem.perBankRdBursts::11 90988 # Per bank write bursts 77system.physmem.perBankRdBursts::12 86795 # Per bank write bursts 78system.physmem.perBankRdBursts::13 81108 # Per bank write bursts 79system.physmem.perBankRdBursts::14 81197 # Per bank write bursts 80system.physmem.perBankRdBursts::15 81497 # Per bank write bursts 81system.physmem.perBankWrBursts::0 153488 # Per bank write bursts 82system.physmem.perBankWrBursts::1 130402 # Per bank write bursts 83system.physmem.perBankWrBursts::2 156905 # Per bank write bursts 84system.physmem.perBankWrBursts::3 130743 # Per bank write bursts 85system.physmem.perBankWrBursts::4 190154 # Per bank write bursts 86system.physmem.perBankWrBursts::5 164896 # Per bank write bursts 87system.physmem.perBankWrBursts::6 144797 # Per bank write bursts 88system.physmem.perBankWrBursts::7 175639 # Per bank write bursts 89system.physmem.perBankWrBursts::8 162274 # Per bank write bursts 90system.physmem.perBankWrBursts::9 194391 # Per bank write bursts 91system.physmem.perBankWrBursts::10 215398 # Per bank write bursts 92system.physmem.perBankWrBursts::11 156932 # Per bank write bursts 93system.physmem.perBankWrBursts::12 147011 # Per bank write bursts 94system.physmem.perBankWrBursts::13 124629 # Per bank write bursts 95system.physmem.perBankWrBursts::14 132966 # Per bank write bursts 96system.physmem.perBankWrBursts::15 130449 # Per bank write bursts | 16system.physmem.bytes_read::cpu.dtb.walker 411264 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 350272 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 77213320 # Number of bytes read from this memory 19system.physmem.bytes_read::realview.ide 415808 # Number of bytes read from this memory 20system.physmem.bytes_read::total 78390664 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 10284736 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 10284736 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 94966144 # Number of bytes written to this memory 24system.physmem.bytes_written::cpu.inst 20580 # Number of bytes written to this memory 25system.physmem.bytes_written::total 94986724 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 6426 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5473 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 1206471 # Number of read requests responded to by this memory 29system.physmem.num_reads::realview.ide 6497 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 1224867 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 1483846 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.inst 2573 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 1486419 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 7957 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 6777 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.inst 1493823 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::realview.ide 8045 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 1516600 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu.inst 198976 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::total 198976 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_write::writebacks 1837281 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_write::cpu.inst 398 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1837679 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1837281 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 7957 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 6777 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.inst 1494221 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.ide 8045 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::total 3354280 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.readReqs 1224867 # Number of read requests accepted 51system.physmem.writeReqs 2137165 # Number of write requests accepted 52system.physmem.readBursts 1224867 # Number of DRAM read bursts, including those serviced by the write queue 53system.physmem.writeBursts 2137165 # Number of DRAM write bursts, including those merged in the write queue 54system.physmem.bytesReadDRAM 78347456 # Total number of bytes read from DRAM 55system.physmem.bytesReadWrQ 44032 # Total number of bytes read from write queue 56system.physmem.bytesWritten 136289472 # Total number of bytes written to DRAM 57system.physmem.bytesReadSys 78390664 # Total read bytes from the system interface side 58system.physmem.bytesWrittenSys 136634468 # Total written bytes from the system interface side 59system.physmem.servicedByWrQ 688 # Number of DRAM read bursts serviced by the write queue 60system.physmem.mergedWrBursts 7616 # Number of DRAM write bursts merged with an existing one 61system.physmem.neitherReadNorWriteReqs 39979 # Number of requests that are neither read nor write 62system.physmem.perBankRdBursts::0 71039 # Per bank write bursts 63system.physmem.perBankRdBursts::1 73325 # Per bank write bursts 64system.physmem.perBankRdBursts::2 71985 # Per bank write bursts 65system.physmem.perBankRdBursts::3 70214 # Per bank write bursts 66system.physmem.perBankRdBursts::4 72864 # Per bank write bursts 67system.physmem.perBankRdBursts::5 82821 # Per bank write bursts 68system.physmem.perBankRdBursts::6 75004 # Per bank write bursts 69system.physmem.perBankRdBursts::7 73137 # Per bank write bursts 70system.physmem.perBankRdBursts::8 67826 # Per bank write bursts 71system.physmem.perBankRdBursts::9 129786 # Per bank write bursts 72system.physmem.perBankRdBursts::10 72316 # Per bank write bursts 73system.physmem.perBankRdBursts::11 77203 # Per bank write bursts 74system.physmem.perBankRdBursts::12 71594 # Per bank write bursts 75system.physmem.perBankRdBursts::13 74115 # Per bank write bursts 76system.physmem.perBankRdBursts::14 68849 # Per bank write bursts 77system.physmem.perBankRdBursts::15 72101 # Per bank write bursts 78system.physmem.perBankWrBursts::0 128045 # Per bank write bursts 79system.physmem.perBankWrBursts::1 133141 # Per bank write bursts 80system.physmem.perBankWrBursts::2 133329 # Per bank write bursts 81system.physmem.perBankWrBursts::3 132983 # Per bank write bursts 82system.physmem.perBankWrBursts::4 135529 # Per bank write bursts 83system.physmem.perBankWrBursts::5 141007 # Per bank write bursts 84system.physmem.perBankWrBursts::6 130525 # Per bank write bursts 85system.physmem.perBankWrBursts::7 133720 # Per bank write bursts 86system.physmem.perBankWrBursts::8 132879 # Per bank write bursts 87system.physmem.perBankWrBursts::9 138815 # Per bank write bursts 88system.physmem.perBankWrBursts::10 133616 # Per bank write bursts 89system.physmem.perBankWrBursts::11 135999 # Per bank write bursts 90system.physmem.perBankWrBursts::12 129210 # Per bank write bursts 91system.physmem.perBankWrBursts::13 131804 # Per bank write bursts 92system.physmem.perBankWrBursts::14 128438 # Per bank write bursts 93system.physmem.perBankWrBursts::15 130483 # Per bank write bursts |
| 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 94system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 98system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 99system.physmem.totGap 51727207457500 # Total gap between requests | 95system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 96system.physmem.totGap 51688408694500 # Total gap between requests |
| 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 13 # Read request sizes (log2) 104system.physmem.readPktSize::4 2 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) | 97system.physmem.readPktSize::0 0 # Read request sizes (log2) 98system.physmem.readPktSize::1 0 # Read request sizes (log2) 99system.physmem.readPktSize::2 0 # Read request sizes (log2) 100system.physmem.readPktSize::3 13 # Read request sizes (log2) 101system.physmem.readPktSize::4 2 # Read request sizes (log2) 102system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 106system.physmem.readPktSize::6 1460431 # Read request sizes (log2) | 103system.physmem.readPktSize::6 1224852 # Read request sizes (log2) |
| 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 1 # Write request sizes (log2) 110system.physmem.writePktSize::3 2572 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) | 104system.physmem.writePktSize::0 0 # Write request sizes (log2) 105system.physmem.writePktSize::1 0 # Write request sizes (log2) 106system.physmem.writePktSize::2 1 # Write request sizes (log2) 107system.physmem.writePktSize::3 2572 # Write request sizes (log2) 108system.physmem.writePktSize::4 0 # Write request sizes (log2) 109system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 113system.physmem.writePktSize::6 2584489 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 1416507 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 34555 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 2426 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 627 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 762 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 442 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 403 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 309 # What read queue length does an incoming req see | 110system.physmem.writePktSize::6 2134592 # Write request sizes (log2) 111system.physmem.rdQLenPdf::0 1187733 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::1 30120 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::2 2405 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::3 606 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::4 760 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::5 444 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::6 390 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::7 307 # What read queue length does an incoming req see |
| 122system.physmem.rdQLenPdf::8 227 # What read queue length does an incoming req see | 119system.physmem.rdQLenPdf::8 227 # What read queue length does an incoming req see |
| 123system.physmem.rdQLenPdf::9 153 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 129 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 128 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 111 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 70 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see | 120system.physmem.rdQLenPdf::9 158 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::10 142 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::12 121 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::13 113 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::14 110 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see |
| 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 133system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 150system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 161system.physmem.wrQLenPdf::15 72795 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 99197 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 141412 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 149421 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 158127 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 155282 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 155338 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 158469 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 154756 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 163262 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 150399 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 141869 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 140112 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 143384 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 124899 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 123820 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 121368 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 119840 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 5134 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 4523 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 3842 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 3476 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 3047 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 2850 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 2456 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 2169 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 1779 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 1580 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 1367 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 1142 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 843 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 674 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 466 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 216 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 179 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 143 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 125 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 110 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 83 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 780499 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 325.414218 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 182.439490 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 353.699104 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 309228 39.62% 39.62% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 174811 22.40% 62.02% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 65731 8.42% 70.44% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 36715 4.70% 75.14% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 26784 3.43% 78.57% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 18838 2.41% 80.99% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 14160 1.81% 82.80% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 15996 2.05% 84.85% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 118236 15.15% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 780499 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 115810 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 12.584803 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 189.442624 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-2047 115806 100.00% 100.00% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::49152-51199 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 115810 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 115810 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 21.682704 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 20.755419 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 7.614982 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 58231 50.28% 50.28% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 24453 21.11% 71.40% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 18350 15.84% 87.24% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 9042 7.81% 95.05% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 1932 1.67% 96.72% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 855 0.74% 97.46% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 730 0.63% 98.09% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 458 0.40% 98.48% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 355 0.31% 98.79% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 216 0.19% 98.97% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 209 0.18% 99.15% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 191 0.16% 99.32% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 504 0.44% 99.75% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 74 0.06% 99.82% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 53 0.05% 99.86% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 51 0.04% 99.91% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 44 0.04% 99.95% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 3 0.00% 99.95% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 5 0.00% 99.95% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::92-95 2 0.00% 99.96% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::96-99 14 0.01% 99.97% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::100-103 6 0.01% 99.97% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::104-107 5 0.00% 99.98% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::108-111 2 0.00% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::112-115 8 0.01% 99.99% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::116-119 2 0.00% 99.99% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::120-123 1 0.00% 99.99% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::128-131 9 0.01% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::132-135 1 0.00% 100.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::148-151 1 0.00% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::total 115810 # Writes before turning the bus around for reads 270system.physmem.totQLat 16665773749 # Total ticks spent queuing 271system.physmem.totMemAccLat 43993129999 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 7287295000 # Total ticks spent in databus transfers 273system.physmem.avgQLat 11434.81 # Average queueing delay per DRAM burst | 158system.physmem.wrQLenPdf::15 48573 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::16 74403 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::17 119873 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::18 132680 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::19 128553 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::20 131972 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::21 134309 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::22 139176 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::23 138776 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::24 138399 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::25 133829 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::26 121319 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::27 116942 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::28 113077 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::29 105310 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::30 103984 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::31 102748 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::32 101616 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::33 4095 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::34 3572 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::35 3285 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::36 2974 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::37 2761 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::38 2608 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::39 2544 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::40 2490 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::41 2322 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::42 2151 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::43 2024 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::44 2001 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::45 1673 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::46 1597 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::47 1417 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::48 1205 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::49 1076 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::50 961 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::51 816 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::52 680 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::53 540 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::54 407 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::55 282 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::56 204 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::58 85 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::59 42 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 207system.physmem.bytesPerActivate::samples 728572 # Bytes accessed per row activation 208system.physmem.bytesPerActivate::mean 294.598947 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::gmean 169.664587 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::stdev 329.125501 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::0-127 296144 40.65% 40.65% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::128-255 177091 24.31% 64.95% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::256-383 64790 8.89% 73.85% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::384-511 35671 4.90% 78.74% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::512-639 25285 3.47% 82.21% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::640-767 17267 2.37% 84.58% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::768-895 13064 1.79% 86.38% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::896-1023 11522 1.58% 87.96% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1024-1151 87738 12.04% 100.00% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::total 728572 # Bytes accessed per row activation 221system.physmem.rdPerTurnAround::samples 97844 # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::mean 12.511242 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::stdev 125.941708 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::0-1023 97842 100.00% 100.00% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::total 97844 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 97844 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 21.764472 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 20.107027 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 12.533220 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-23 71394 72.97% 72.97% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::24-31 19346 19.77% 92.74% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::32-39 3261 3.33% 96.07% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::40-47 806 0.82% 96.90% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::48-55 888 0.91% 97.80% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::56-63 399 0.41% 98.21% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::64-71 342 0.35% 98.56% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::72-79 242 0.25% 98.81% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::80-87 261 0.27% 99.08% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::88-95 243 0.25% 99.32% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::96-103 222 0.23% 99.55% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::104-111 63 0.06% 99.61% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::112-119 71 0.07% 99.69% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::120-127 48 0.05% 99.74% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::128-135 149 0.15% 99.89% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::136-143 24 0.02% 99.91% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::144-151 24 0.02% 99.94% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::152-159 7 0.01% 99.94% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::160-167 12 0.01% 99.96% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::168-175 6 0.01% 99.96% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::176-183 10 0.01% 99.97% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::184-191 2 0.00% 99.98% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::192-199 4 0.00% 99.98% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::200-207 6 0.01% 99.99% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::208-215 3 0.00% 99.99% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::216-223 3 0.00% 99.99% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::224-231 5 0.01% 100.00% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::232-239 2 0.00% 100.00% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 97844 # Writes before turning the bus around for reads 262system.physmem.totQLat 16127261998 # Total ticks spent queuing 263system.physmem.totMemAccLat 39080618248 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 6120895000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 13173.94 # Average queueing delay per DRAM burst |
| 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 275system.physmem.avgMemAccLat 30184.81 # Average memory access latency per DRAM burst 276system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s 277system.physmem.avgWrBW 3.11 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 1.81 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 3.20 # Average system write bandwidth in MiByte/s | 267system.physmem.avgMemAccLat 31923.94 # Average memory access latency per DRAM burst 268system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s |
| 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 281system.physmem.busUtil 0.04 # Data bus utilization in percentage | 273system.physmem.busUtil 0.03 # Data bus utilization in percentage |
| 282system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 283system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 284system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 274system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 276system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 285system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing 286system.physmem.readRowHits 1137142 # Number of row buffer hits during reads 287system.physmem.writeRowHits 2050889 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 78.02 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 81.67 # Row buffer hit rate for writes 290system.physmem.avgGap 12780013.64 # Average gap between requests 291system.physmem.pageHitRate 80.33 # Row buffer hit rate, read and write combined 292system.physmem.memoryStateTime::IDLE 49431156944750 # Time in different power states 293system.physmem.memoryStateTime::REF 1727285040000 # Time in different power states | 277system.physmem.avgWrQLen 23.82 # Average write queue length when enqueuing 278system.physmem.readRowHits 946951 # Number of row buffer hits during reads 279system.physmem.writeRowHits 1678178 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 77.35 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 78.80 # Row buffer hit rate for writes 282system.physmem.avgGap 15374157.26 # Average gap between requests 283system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined 284system.physmem.memoryStateTime::IDLE 49562808778250 # Time in different power states 285system.physmem.memoryStateTime::REF 1725989460000 # Time in different power states |
| 294system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 286system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 295system.physmem.memoryStateTime::ACT 568765880250 # Time in different power states | 287system.physmem.memoryStateTime::ACT 399611675250 # Time in different power states |
| 296system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 288system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 297system.physmem.actEnergy::0 2969235360 # Energy for activate commands per rank (pJ) 298system.physmem.actEnergy::1 2931337080 # Energy for activate commands per rank (pJ) 299system.physmem.preEnergy::0 1620118500 # Energy for precharge commands per rank (pJ) 300system.physmem.preEnergy::1 1599439875 # Energy for precharge commands per rank (pJ) 301system.physmem.readEnergy::0 5574566400 # Energy for read commands per rank (pJ) 302system.physmem.readEnergy::1 5793535800 # Energy for read commands per rank (pJ) 303system.physmem.writeEnergy::0 8080715520 # Energy for write commands per rank (pJ) 304system.physmem.writeEnergy::1 8191044000 # Energy for write commands per rank (pJ) 305system.physmem.refreshEnergy::0 3378569538240 # Energy for refresh commands per rank (pJ) 306system.physmem.refreshEnergy::1 3378569538240 # Energy for refresh commands per rank (pJ) 307system.physmem.actBackEnergy::0 1383201002250 # Energy for active background per rank (pJ) 308system.physmem.actBackEnergy::1 1386870926445 # Energy for active background per rank (pJ) 309system.physmem.preBackEnergy::0 29822988580500 # Energy for precharge background per rank (pJ) 310system.physmem.preBackEnergy::1 29819769348750 # Energy for precharge background per rank (pJ) 311system.physmem.totalEnergy::0 34603003756770 # Total energy per rank (pJ) 312system.physmem.totalEnergy::1 34603725170190 # Total energy per rank (pJ) 313system.physmem.averagePower::0 668.951744 # Core power per rank (mW) 314system.physmem.averagePower::1 668.965690 # Core power per rank (mW) | 289system.physmem.actEnergy::0 2776243680 # Energy for activate commands per rank (pJ) 290system.physmem.actEnergy::1 2731760640 # Energy for activate commands per rank (pJ) 291system.physmem.preEnergy::0 1514815500 # Energy for precharge commands per rank (pJ) 292system.physmem.preEnergy::1 1490544000 # Energy for precharge commands per rank (pJ) 293system.physmem.readEnergy::0 4604987400 # Energy for read commands per rank (pJ) 294system.physmem.readEnergy::1 4943562000 # Energy for read commands per rank (pJ) 295system.physmem.writeEnergy::0 6922447920 # Energy for write commands per rank (pJ) 296system.physmem.writeEnergy::1 6876861120 # Energy for write commands per rank (pJ) 297system.physmem.refreshEnergy::0 3376035383760 # Energy for refresh commands per rank (pJ) 298system.physmem.refreshEnergy::1 3376035383760 # Energy for refresh commands per rank (pJ) 299system.physmem.actBackEnergy::0 1310091236460 # Energy for active background per rank (pJ) 300system.physmem.actBackEnergy::1 1307916167760 # Energy for active background per rank (pJ) 301system.physmem.preBackEnergy::0 29863840623750 # Energy for precharge background per rank (pJ) 302system.physmem.preBackEnergy::1 29865748578750 # Energy for precharge background per rank (pJ) 303system.physmem.totalEnergy::0 34565785738470 # Total energy per rank (pJ) 304system.physmem.totalEnergy::1 34565742858030 # Total energy per rank (pJ) 305system.physmem.averagePower::0 668.733833 # Core power per rank (mW) 306system.physmem.averagePower::1 668.733004 # Core power per rank (mW) |
| 315system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory 316system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 317system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 318system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 319system.realview.nvmem.num_reads::cpu.inst 16 # Number of read requests responded to by this memory 320system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 321system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 326system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) | 307system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory 308system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 309system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 310system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 311system.realview.nvmem.num_reads::cpu.inst 16 # Number of read requests responded to by this memory 312system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 313system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 314system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 315system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 316system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 317system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 318system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) |
| 327system.membus.trans_dist::ReadReq 594629 # Transaction distribution 328system.membus.trans_dist::ReadResp 594629 # Transaction distribution 329system.membus.trans_dist::WriteReq 33870 # Transaction distribution 330system.membus.trans_dist::WriteResp 33870 # Transaction distribution 331system.membus.trans_dist::Writeback 896030 # Transaction distribution 332system.membus.trans_dist::WriteInvalidateReq 1688459 # Transaction distribution 333system.membus.trans_dist::WriteInvalidateResp 1688459 # Transaction distribution 334system.membus.trans_dist::UpgradeReq 39025 # Transaction distribution 335system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 336system.membus.trans_dist::UpgradeResp 39026 # Transaction distribution 337system.membus.trans_dist::ReadExReq 901834 # Transaction distribution 338system.membus.trans_dist::ReadExResp 901834 # Transaction distribution 339system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) 342system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7050430 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7180576 # Packet count per connected master and slave (bytes) 344system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228843 # Packet count per connected master and slave (bytes) 345system.membus.pkt_count_system.iocache.mem_side::total 228843 # Packet count per connected master and slave (bytes) 346system.membus.pkt_count::total 7409419 # Packet count per connected master and slave (bytes) 347system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) 348system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 349system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) 350system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 251644332 # Cumulative packet size per connected master and slave (bytes) 351system.membus.pkt_size_system.cpu.l2cache.mem_side::total 251815240 # Cumulative packet size per connected master and slave (bytes) 352system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7251264 # Cumulative packet size per connected master and slave (bytes) 353system.membus.pkt_size_system.iocache.mem_side::total 7251264 # Cumulative packet size per connected master and slave (bytes) 354system.membus.pkt_size::total 259066504 # Cumulative packet size per connected master and slave (bytes) 355system.membus.snoops 2247 # Total snoops (count) 356system.membus.snoop_fanout::samples 4033943 # Request fanout histogram 357system.membus.snoop_fanout::mean 1 # Request fanout histogram 358system.membus.snoop_fanout::stdev 0 # Request fanout histogram 359system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 360system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 361system.membus.snoop_fanout::1 4033943 100.00% 100.00% # Request fanout histogram 362system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 363system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 364system.membus.snoop_fanout::min_value 1 # Request fanout histogram 365system.membus.snoop_fanout::max_value 1 # Request fanout histogram 366system.membus.snoop_fanout::total 4033943 # Request fanout histogram 367system.membus.reqLayer0.occupancy 113743500 # Layer occupancy (ticks) 368system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 369system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) 370system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 371system.membus.reqLayer2.occupancy 5505500 # Layer occupancy (ticks) 372system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 373system.membus.reqLayer5.occupancy 25619760742 # Layer occupancy (ticks) 374system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 375system.membus.respLayer2.occupancy 15669502469 # Layer occupancy (ticks) 376system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 377system.membus.respLayer3.occupancy 186602993 # Layer occupancy (ticks) 378system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 379system.realview.ethernet.txBytes 966 # Bytes Transmitted 380system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 381system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 382system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 383system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 384system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 385system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 386system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 387system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 388system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 389system.realview.ethernet.totPackets 3 # Total Packets 390system.realview.ethernet.totBytes 966 # Total Bytes 391system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 392system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 393system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 394system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 395system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 396system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 397system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 398system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 399system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 400system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 401system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 402system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 403system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 404system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 405system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 406system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 407system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 408system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 409system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 410system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 411system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 412system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 413system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 414system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 415system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 416system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 417system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 418system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 419system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 420system.realview.ethernet.droppedPackets 0 # number of packets dropped | |
| 421system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 422system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 423system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 424system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 425system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 426system.cf0.dma_write_txs 1669 # Number of DMA write transactions. | 319system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 320system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 321system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 322system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 323system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 324system.cf0.dma_write_txs 1669 # Number of DMA write transactions. |
| 427system.iobus.trans_dist::ReadReq 40404 # Transaction distribution 428system.iobus.trans_dist::ReadResp 40404 # Transaction distribution 429system.iobus.trans_dist::WriteReq 136687 # Transaction distribution 430system.iobus.trans_dist::WriteResp 136733 # Transaction distribution 431system.iobus.trans_dist::WriteInvalidateReq 46 # Transaction distribution 432system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) 433system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 434system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 435system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 436system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 437system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 438system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 439system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 440system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 441system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 442system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 443system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 444system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 445system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 446system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 447system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) 448system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) 449system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) 450system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 451system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 452system.iobus.pkt_count::total 354274 # Packet count per connected master and slave (bytes) 453system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) 454system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 455system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 456system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 457system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 458system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 459system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 460system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 461system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 462system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 463system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 464system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 465system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 466system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 467system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 468system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) 469system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) 470system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) 471system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 472system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 473system.iobus.pkt_size::total 7492854 # Cumulative packet size per connected master and slave (bytes) 474system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) 475system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 476system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 477system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 478system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 479system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 480system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 481system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 482system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 483system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 484system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 485system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 486system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 487system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 488system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 489system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 490system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 491system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 492system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 493system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 494system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 495system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 496system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 497system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 498system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 499system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 500system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 501system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 502system.iobus.reqLayer27.occupancy 981194482 # Layer occupancy (ticks) 503system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 504system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 505system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 506system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) 507system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 508system.iobus.respLayer3.occupancy 179049007 # Layer occupancy (ticks) 509system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 510system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 511system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 512system.cpu_clk_domain.clock 500 # Clock period in ticks 513system.cpu.branchPred.lookups 259878452 # Number of BP lookups 514system.cpu.branchPred.condPredicted 182434681 # Number of conditional branches predicted 515system.cpu.branchPred.condIncorrect 12106293 # Number of conditional branches incorrect 516system.cpu.branchPred.BTBLookups 193171007 # Number of BTB lookups 517system.cpu.branchPred.BTBHits 136122005 # Number of BTB hits | 325system.cpu.branchPred.lookups 261297703 # Number of BP lookups 326system.cpu.branchPred.condPredicted 183348683 # Number of conditional branches predicted 327system.cpu.branchPred.condIncorrect 12210638 # Number of conditional branches incorrect 328system.cpu.branchPred.BTBLookups 193789546 # Number of BTB lookups 329system.cpu.branchPred.BTBHits 136743179 # Number of BTB hits |
| 518system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 330system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 519system.cpu.branchPred.BTBHitPct 70.467099 # BTB Hit Percentage 520system.cpu.branchPred.usedRAS 31463060 # Number of times the RAS was used to get a target. 521system.cpu.branchPred.RASInCorrect 2055318 # Number of incorrect RAS predictions. | 331system.cpu.branchPred.BTBHitPct 70.562722 # BTB Hit Percentage 332system.cpu.branchPred.usedRAS 31690204 # Number of times the RAS was used to get a target. 333system.cpu.branchPred.RASInCorrect 2146162 # Number of incorrect RAS predictions. 334system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 522system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 523system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 524system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 525system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 526system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 527system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 528system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 529system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 537system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 538system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 539system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 540system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 541system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 542system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 543system.cpu.dtb.inst_hits 0 # ITB inst hits 544system.cpu.dtb.inst_misses 0 # ITB inst misses | 335system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 336system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 337system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 338system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 339system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 340system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 341system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 342system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 350system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 351system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 352system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 353system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 354system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 355system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 356system.cpu.dtb.inst_hits 0 # ITB inst hits 357system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 545system.cpu.dtb.read_hits 183357098 # DTB read hits 546system.cpu.dtb.read_misses 476791 # DTB read misses 547system.cpu.dtb.write_hits 162738381 # DTB write hits 548system.cpu.dtb.write_misses 102414 # DTB write misses | 358system.cpu.dtb.read_hits 183672011 # DTB read hits 359system.cpu.dtb.read_misses 484545 # DTB read misses 360system.cpu.dtb.write_hits 163011983 # DTB write hits 361system.cpu.dtb.write_misses 101734 # DTB write misses |
| 549system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 550system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 362system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 363system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 551system.cpu.dtb.flush_tlb_mva_asid 47228 # Number of times TLB was flushed by MVA & ASID 552system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID 553system.cpu.dtb.flush_entries 80239 # Number of entries that have been flushed from TLB 554system.cpu.dtb.align_faults 828 # Number of TLB faults due to alignment restrictions 555system.cpu.dtb.prefetch_faults 14730 # Number of TLB faults due to prefetch | 364system.cpu.dtb.flush_tlb_mva_asid 47427 # Number of times TLB was flushed by MVA & ASID 365system.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID 366system.cpu.dtb.flush_entries 80165 # Number of entries that have been flushed from TLB 367system.cpu.dtb.align_faults 779 # Number of TLB faults due to alignment restrictions 368system.cpu.dtb.prefetch_faults 14148 # Number of TLB faults due to prefetch |
| 556system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 369system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 557system.cpu.dtb.perms_faults 23395 # Number of TLB faults due to permissions restrictions 558system.cpu.dtb.read_accesses 183833889 # DTB read accesses 559system.cpu.dtb.write_accesses 162840795 # DTB write accesses | 370system.cpu.dtb.perms_faults 23574 # Number of TLB faults due to permissions restrictions 371system.cpu.dtb.read_accesses 184156556 # DTB read accesses 372system.cpu.dtb.write_accesses 163113717 # DTB write accesses |
| 560system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 373system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 561system.cpu.dtb.hits 346095479 # DTB hits 562system.cpu.dtb.misses 579205 # DTB misses 563system.cpu.dtb.accesses 346674684 # DTB accesses | 374system.cpu.dtb.hits 346683994 # DTB hits 375system.cpu.dtb.misses 586279 # DTB misses 376system.cpu.dtb.accesses 347270273 # DTB accesses |
| 564system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 565system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 566system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 567system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 568system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 569system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 570system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 571system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 577system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 578system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 579system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 580system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 581system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 582system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 583system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 584system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 377system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 378system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 379system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 380system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 381system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 382system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 383system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 384system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 390system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 391system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 392system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 393system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 394system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 395system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 396system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 397system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 585system.cpu.itb.inst_hits 453041166 # ITB inst hits 586system.cpu.itb.inst_misses 137089 # ITB inst misses | 398system.cpu.itb.inst_hits 455292001 # ITB inst hits 399system.cpu.itb.inst_misses 136900 # ITB inst misses |
| 587system.cpu.itb.read_hits 0 # DTB read hits 588system.cpu.itb.read_misses 0 # DTB read misses 589system.cpu.itb.write_hits 0 # DTB write hits 590system.cpu.itb.write_misses 0 # DTB write misses 591system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 592system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 400system.cpu.itb.read_hits 0 # DTB read hits 401system.cpu.itb.read_misses 0 # DTB read misses 402system.cpu.itb.write_hits 0 # DTB write hits 403system.cpu.itb.write_misses 0 # DTB write misses 404system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 405system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 593system.cpu.itb.flush_tlb_mva_asid 47228 # Number of times TLB was flushed by MVA & ASID 594system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID 595system.cpu.itb.flush_entries 57684 # Number of entries that have been flushed from TLB | 406system.cpu.itb.flush_tlb_mva_asid 47427 # Number of times TLB was flushed by MVA & ASID 407system.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID 408system.cpu.itb.flush_entries 57667 # Number of entries that have been flushed from TLB |
| 596system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 597system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 598system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 409system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 410system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 411system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 599system.cpu.itb.perms_faults 391598 # Number of TLB faults due to permissions restrictions | 412system.cpu.itb.perms_faults 366615 # Number of TLB faults due to permissions restrictions |
| 600system.cpu.itb.read_accesses 0 # DTB read accesses 601system.cpu.itb.write_accesses 0 # DTB write accesses | 413system.cpu.itb.read_accesses 0 # DTB read accesses 414system.cpu.itb.write_accesses 0 # DTB write accesses |
| 602system.cpu.itb.inst_accesses 453178255 # ITB inst accesses 603system.cpu.itb.hits 453041166 # DTB hits 604system.cpu.itb.misses 137089 # DTB misses 605system.cpu.itb.accesses 453178255 # DTB accesses 606system.cpu.numCycles 2529291390 # number of cpu cycles simulated | 415system.cpu.itb.inst_accesses 455428901 # ITB inst accesses 416system.cpu.itb.hits 455292001 # DTB hits 417system.cpu.itb.misses 136900 # DTB misses 418system.cpu.itb.accesses 455428901 # DTB accesses 419system.cpu.numCycles 2518825477 # number of cpu cycles simulated |
| 607system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 608system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 420system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 421system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 609system.cpu.committedInsts 949996153 # Number of instructions committed 610system.cpu.committedOps 1116252474 # Number of ops (including micro ops) committed 611system.cpu.discardedOps 97459423 # Number of ops (including micro ops) which were discarded before commit 612system.cpu.numFetchSuspends 7746 # Number of times Execute suspended instruction fetching 613system.cpu.quiesceCycles 100926289028 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 614system.cpu.cpi 2.662423 # CPI: cycles per instruction 615system.cpu.ipc 0.375598 # IPC: instructions per cycle | 422system.cpu.committedInsts 951433762 # Number of instructions committed 423system.cpu.committedOps 1118058358 # Number of ops (including micro ops) committed 424system.cpu.discardedOps 97427430 # Number of ops (including micro ops) which were discarded before commit 425system.cpu.numFetchSuspends 7769 # Number of times Execute suspended instruction fetching 426system.cpu.quiesceCycles 100859175256 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 427system.cpu.cpi 2.647400 # CPI: cycles per instruction 428system.cpu.ipc 0.377729 # IPC: instructions per cycle |
| 616system.cpu.kern.inst.arm 0 # number of arm instructions executed | 429system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 617system.cpu.kern.inst.quiesce 16606 # number of quiesce instructions executed 618system.cpu.tickCycles 1758931949 # Number of cycles that the object actually ticked 619system.cpu.idleCycles 770359441 # Total number of cycles that the object has spent stopped 620system.cpu.icache.tags.replacements 24421267 # number of replacements 621system.cpu.icache.tags.tagsinuse 511.933272 # Cycle average of tags in use 622system.cpu.icache.tags.total_refs 428216370 # Total number of references to valid blocks. 623system.cpu.icache.tags.sampled_refs 24421779 # Sample count of references to valid blocks. 624system.cpu.icache.tags.avg_refs 17.534201 # Average number of references to valid blocks. 625system.cpu.icache.tags.warmup_cycle 20287456250 # Cycle when the warmup percentage was hit. 626system.cpu.icache.tags.occ_blocks::cpu.inst 511.933272 # Average occupied blocks per requestor 627system.cpu.icache.tags.occ_percent::cpu.inst 0.999870 # Average percentage of cache occupancy 628system.cpu.icache.tags.occ_percent::total 0.999870 # Average percentage of cache occupancy | 430system.cpu.kern.inst.quiesce 16629 # number of quiesce instructions executed 431system.cpu.tickCycles 1804872231 # Number of cycles that the object actually ticked 432system.cpu.idleCycles 713953246 # Total number of cycles that the object has spent stopped 433system.cpu.dcache.tags.replacements 11184340 # number of replacements 434system.cpu.dcache.tags.tagsinuse 511.959663 # Cycle average of tags in use 435system.cpu.dcache.tags.total_refs 330369377 # Total number of references to valid blocks. 436system.cpu.dcache.tags.sampled_refs 11184852 # Sample count of references to valid blocks. 437system.cpu.dcache.tags.avg_refs 29.537215 # Average number of references to valid blocks. 438system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. 439system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959663 # Average occupied blocks per requestor 440system.cpu.dcache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy 441system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy 442system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id 445system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 446system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 447system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 448system.cpu.dcache.tags.tag_accesses 1387996074 # Number of tag accesses 449system.cpu.dcache.tags.data_accesses 1387996074 # Number of data accesses 450system.cpu.dcache.ReadReq_hits::cpu.inst 169370817 # number of ReadReq hits 451system.cpu.dcache.ReadReq_hits::total 169370817 # number of ReadReq hits 452system.cpu.dcache.WriteReq_hits::cpu.inst 152148495 # number of WriteReq hits 453system.cpu.dcache.WriteReq_hits::total 152148495 # number of WriteReq hits 454system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 336885 # number of WriteInvalidateReq hits 455system.cpu.dcache.WriteInvalidateReq_hits::total 336885 # number of WriteInvalidateReq hits 456system.cpu.dcache.LoadLockedReq_hits::cpu.inst 4109295 # number of LoadLockedReq hits 457system.cpu.dcache.LoadLockedReq_hits::total 4109295 # number of LoadLockedReq hits 458system.cpu.dcache.StoreCondReq_hits::cpu.inst 4353813 # number of StoreCondReq hits 459system.cpu.dcache.StoreCondReq_hits::total 4353813 # number of StoreCondReq hits 460system.cpu.dcache.demand_hits::cpu.inst 321519312 # number of demand (read+write) hits 461system.cpu.dcache.demand_hits::total 321519312 # number of demand (read+write) hits 462system.cpu.dcache.overall_hits::cpu.inst 321519312 # number of overall hits 463system.cpu.dcache.overall_hits::total 321519312 # number of overall hits 464system.cpu.dcache.ReadReq_misses::cpu.inst 8065146 # number of ReadReq misses 465system.cpu.dcache.ReadReq_misses::total 8065146 # number of ReadReq misses 466system.cpu.dcache.WriteReq_misses::cpu.inst 4327048 # number of WriteReq misses 467system.cpu.dcache.WriteReq_misses::total 4327048 # number of WriteReq misses 468system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst 1245044 # number of WriteInvalidateReq misses 469system.cpu.dcache.WriteInvalidateReq_misses::total 1245044 # number of WriteInvalidateReq misses 470system.cpu.dcache.LoadLockedReq_misses::cpu.inst 246250 # number of LoadLockedReq misses 471system.cpu.dcache.LoadLockedReq_misses::total 246250 # number of LoadLockedReq misses 472system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses 473system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 474system.cpu.dcache.demand_misses::cpu.inst 12392194 # number of demand (read+write) misses 475system.cpu.dcache.demand_misses::total 12392194 # number of demand (read+write) misses 476system.cpu.dcache.overall_misses::cpu.inst 12392194 # number of overall misses 477system.cpu.dcache.overall_misses::total 12392194 # number of overall misses 478system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128575099737 # number of ReadReq miss cycles 479system.cpu.dcache.ReadReq_miss_latency::total 128575099737 # number of ReadReq miss cycles 480system.cpu.dcache.WriteReq_miss_latency::cpu.inst 143976164605 # number of WriteReq miss cycles 481system.cpu.dcache.WriteReq_miss_latency::total 143976164605 # number of WriteReq miss cycles 482system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.inst 29659207447 # number of WriteInvalidateReq miss cycles 483system.cpu.dcache.WriteInvalidateReq_miss_latency::total 29659207447 # number of WriteInvalidateReq miss cycles 484system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 3578517253 # number of LoadLockedReq miss cycles 485system.cpu.dcache.LoadLockedReq_miss_latency::total 3578517253 # number of LoadLockedReq miss cycles 486system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 150500 # number of StoreCondReq miss cycles 487system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles 488system.cpu.dcache.demand_miss_latency::cpu.inst 272551264342 # number of demand (read+write) miss cycles 489system.cpu.dcache.demand_miss_latency::total 272551264342 # number of demand (read+write) miss cycles 490system.cpu.dcache.overall_miss_latency::cpu.inst 272551264342 # number of overall miss cycles 491system.cpu.dcache.overall_miss_latency::total 272551264342 # number of overall miss cycles 492system.cpu.dcache.ReadReq_accesses::cpu.inst 177435963 # number of ReadReq accesses(hits+misses) 493system.cpu.dcache.ReadReq_accesses::total 177435963 # number of ReadReq accesses(hits+misses) 494system.cpu.dcache.WriteReq_accesses::cpu.inst 156475543 # number of WriteReq accesses(hits+misses) 495system.cpu.dcache.WriteReq_accesses::total 156475543 # number of WriteReq accesses(hits+misses) 496system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst 1581929 # number of WriteInvalidateReq accesses(hits+misses) 497system.cpu.dcache.WriteInvalidateReq_accesses::total 1581929 # number of WriteInvalidateReq accesses(hits+misses) 498system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 4355545 # number of LoadLockedReq accesses(hits+misses) 499system.cpu.dcache.LoadLockedReq_accesses::total 4355545 # number of LoadLockedReq accesses(hits+misses) 500system.cpu.dcache.StoreCondReq_accesses::cpu.inst 4353815 # number of StoreCondReq accesses(hits+misses) 501system.cpu.dcache.StoreCondReq_accesses::total 4353815 # number of StoreCondReq accesses(hits+misses) 502system.cpu.dcache.demand_accesses::cpu.inst 333911506 # number of demand (read+write) accesses 503system.cpu.dcache.demand_accesses::total 333911506 # number of demand (read+write) accesses 504system.cpu.dcache.overall_accesses::cpu.inst 333911506 # number of overall (read+write) accesses 505system.cpu.dcache.overall_accesses::total 333911506 # number of overall (read+write) accesses 506system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.045454 # miss rate for ReadReq accesses 507system.cpu.dcache.ReadReq_miss_rate::total 0.045454 # miss rate for ReadReq accesses 508system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.027653 # miss rate for WriteReq accesses 509system.cpu.dcache.WriteReq_miss_rate::total 0.027653 # miss rate for WriteReq accesses 510system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.inst 0.787042 # miss rate for WriteInvalidateReq accesses 511system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787042 # miss rate for WriteInvalidateReq accesses 512system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.056537 # miss rate for LoadLockedReq accesses 513system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056537 # miss rate for LoadLockedReq accesses 514system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000000 # miss rate for StoreCondReq accesses 515system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 516system.cpu.dcache.demand_miss_rate::cpu.inst 0.037112 # miss rate for demand accesses 517system.cpu.dcache.demand_miss_rate::total 0.037112 # miss rate for demand accesses 518system.cpu.dcache.overall_miss_rate::cpu.inst 0.037112 # miss rate for overall accesses 519system.cpu.dcache.overall_miss_rate::total 0.037112 # miss rate for overall accesses 520system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15942.067228 # average ReadReq miss latency 521system.cpu.dcache.ReadReq_avg_miss_latency::total 15942.067228 # average ReadReq miss latency 522system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 33273.530732 # average WriteReq miss latency 523system.cpu.dcache.WriteReq_avg_miss_latency::total 33273.530732 # average WriteReq miss latency 524system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.inst 23821.814688 # average WriteInvalidateReq miss latency 525system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23821.814688 # average WriteInvalidateReq miss latency 526system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14532.049758 # average LoadLockedReq miss latency 527system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14532.049758 # average LoadLockedReq miss latency 528system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 75250 # average StoreCondReq miss latency 529system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency 530system.cpu.dcache.demand_avg_miss_latency::cpu.inst 21993.786116 # average overall miss latency 531system.cpu.dcache.demand_avg_miss_latency::total 21993.786116 # average overall miss latency 532system.cpu.dcache.overall_avg_miss_latency::cpu.inst 21993.786116 # average overall miss latency 533system.cpu.dcache.overall_avg_miss_latency::total 21993.786116 # average overall miss latency 534system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 540system.cpu.dcache.fast_writes 0 # number of fast writes performed 541system.cpu.dcache.cache_copies 0 # number of cache copies performed 542system.cpu.dcache.writebacks::writebacks 8574653 # number of writebacks 543system.cpu.dcache.writebacks::total 8574653 # number of writebacks 544system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 754189 # number of ReadReq MSHR hits 545system.cpu.dcache.ReadReq_mshr_hits::total 754189 # number of ReadReq MSHR hits 546system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1894189 # number of WriteReq MSHR hits 547system.cpu.dcache.WriteReq_mshr_hits::total 1894189 # number of WriteReq MSHR hits 548system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.inst 150 # number of WriteInvalidateReq MSHR hits 549system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 150 # number of WriteInvalidateReq MSHR hits 550system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 2 # number of LoadLockedReq MSHR hits 551system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 552system.cpu.dcache.demand_mshr_hits::cpu.inst 2648378 # number of demand (read+write) MSHR hits 553system.cpu.dcache.demand_mshr_hits::total 2648378 # number of demand (read+write) MSHR hits 554system.cpu.dcache.overall_mshr_hits::cpu.inst 2648378 # number of overall MSHR hits 555system.cpu.dcache.overall_mshr_hits::total 2648378 # number of overall MSHR hits 556system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7310957 # number of ReadReq MSHR misses 557system.cpu.dcache.ReadReq_mshr_misses::total 7310957 # number of ReadReq MSHR misses 558system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2432859 # number of WriteReq MSHR misses 559system.cpu.dcache.WriteReq_mshr_misses::total 2432859 # number of WriteReq MSHR misses 560system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.inst 1244894 # number of WriteInvalidateReq MSHR misses 561system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244894 # number of WriteInvalidateReq MSHR misses 562system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 246248 # number of LoadLockedReq MSHR misses 563system.cpu.dcache.LoadLockedReq_mshr_misses::total 246248 # number of LoadLockedReq MSHR misses 564system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses 565system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 566system.cpu.dcache.demand_mshr_misses::cpu.inst 9743816 # number of demand (read+write) MSHR misses 567system.cpu.dcache.demand_mshr_misses::total 9743816 # number of demand (read+write) MSHR misses 568system.cpu.dcache.overall_mshr_misses::cpu.inst 9743816 # number of overall MSHR misses 569system.cpu.dcache.overall_mshr_misses::total 9743816 # number of overall MSHR misses 570system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102346476258 # number of ReadReq MSHR miss cycles 571system.cpu.dcache.ReadReq_mshr_miss_latency::total 102346476258 # number of ReadReq MSHR miss cycles 572system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 73412590018 # number of WriteReq MSHR miss cycles 573system.cpu.dcache.WriteReq_mshr_miss_latency::total 73412590018 # number of WriteReq MSHR miss cycles 574system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 27165305803 # number of WriteInvalidateReq MSHR miss cycles 575system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 27165305803 # number of WriteInvalidateReq MSHR miss cycles 576system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 3084334247 # number of LoadLockedReq MSHR miss cycles 577system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3084334247 # number of LoadLockedReq MSHR miss cycles 578system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 146500 # number of StoreCondReq MSHR miss cycles 579system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles 580system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 175759066276 # number of demand (read+write) MSHR miss cycles 581system.cpu.dcache.demand_mshr_miss_latency::total 175759066276 # number of demand (read+write) MSHR miss cycles 582system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 175759066276 # number of overall MSHR miss cycles 583system.cpu.dcache.overall_mshr_miss_latency::total 175759066276 # number of overall MSHR miss cycles 584system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5728692998 # number of ReadReq MSHR uncacheable cycles 585system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5728692998 # number of ReadReq MSHR uncacheable cycles 586system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 5585086250 # number of WriteReq MSHR uncacheable cycles 587system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5585086250 # number of WriteReq MSHR uncacheable cycles 588system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 11313779248 # number of overall MSHR uncacheable cycles 589system.cpu.dcache.overall_mshr_uncacheable_latency::total 11313779248 # number of overall MSHR uncacheable cycles 590system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.041203 # mshr miss rate for ReadReq accesses 591system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041203 # mshr miss rate for ReadReq accesses 592system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015548 # mshr miss rate for WriteReq accesses 593system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015548 # mshr miss rate for WriteReq accesses 594system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.786947 # mshr miss rate for WriteInvalidateReq accesses 595system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786947 # mshr miss rate for WriteInvalidateReq accesses 596system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.056537 # mshr miss rate for LoadLockedReq accesses 597system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056537 # mshr miss rate for LoadLockedReq accesses 598system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for StoreCondReq accesses 599system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 600system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.029181 # mshr miss rate for demand accesses 601system.cpu.dcache.demand_mshr_miss_rate::total 0.029181 # mshr miss rate for demand accesses 602system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.029181 # mshr miss rate for overall accesses 603system.cpu.dcache.overall_mshr_miss_rate::total 0.029181 # mshr miss rate for overall accesses 604system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 13999.053237 # average ReadReq mshr miss latency 605system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13999.053237 # average ReadReq mshr miss latency 606system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 30175.439686 # average WriteReq mshr miss latency 607system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30175.439686 # average WriteReq mshr miss latency 608system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 21821.380618 # average WriteInvalidateReq mshr miss latency 609system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21821.380618 # average WriteInvalidateReq mshr miss latency 610system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12525.316945 # average LoadLockedReq mshr miss latency 611system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12525.316945 # average LoadLockedReq mshr miss latency 612system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 73250 # average StoreCondReq mshr miss latency 613system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency 614system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18038.011625 # average overall mshr miss latency 615system.cpu.dcache.demand_avg_mshr_miss_latency::total 18038.011625 # average overall mshr miss latency 616system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18038.011625 # average overall mshr miss latency 617system.cpu.dcache.overall_avg_mshr_miss_latency::total 18038.011625 # average overall mshr miss latency 618system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 619system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 620system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 621system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 622system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 623system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 624system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 625system.cpu.icache.tags.replacements 24658250 # number of replacements 626system.cpu.icache.tags.tagsinuse 511.931964 # Cycle average of tags in use 627system.cpu.icache.tags.total_refs 430254710 # Total number of references to valid blocks. 628system.cpu.icache.tags.sampled_refs 24658762 # Sample count of references to valid blocks. 629system.cpu.icache.tags.avg_refs 17.448350 # Average number of references to valid blocks. 630system.cpu.icache.tags.warmup_cycle 21183887000 # Cycle when the warmup percentage was hit. 631system.cpu.icache.tags.occ_blocks::cpu.inst 511.931964 # Average occupied blocks per requestor 632system.cpu.icache.tags.occ_percent::cpu.inst 0.999867 # Average percentage of cache occupancy 633system.cpu.icache.tags.occ_percent::total 0.999867 # Average percentage of cache occupancy |
| 629system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 634system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 630system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 631system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id 632system.cpu.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id | 635system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 636system.cpu.icache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id 637system.cpu.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id |
| 633system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 638system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 634system.cpu.icache.tags.tag_accesses 477059947 # Number of tag accesses 635system.cpu.icache.tags.data_accesses 477059947 # Number of data accesses 636system.cpu.icache.ReadReq_hits::cpu.inst 428216370 # number of ReadReq hits 637system.cpu.icache.ReadReq_hits::total 428216370 # number of ReadReq hits 638system.cpu.icache.demand_hits::cpu.inst 428216370 # number of demand (read+write) hits 639system.cpu.icache.demand_hits::total 428216370 # number of demand (read+write) hits 640system.cpu.icache.overall_hits::cpu.inst 428216370 # number of overall hits 641system.cpu.icache.overall_hits::total 428216370 # number of overall hits 642system.cpu.icache.ReadReq_misses::cpu.inst 24421789 # number of ReadReq misses 643system.cpu.icache.ReadReq_misses::total 24421789 # number of ReadReq misses 644system.cpu.icache.demand_misses::cpu.inst 24421789 # number of demand (read+write) misses 645system.cpu.icache.demand_misses::total 24421789 # number of demand (read+write) misses 646system.cpu.icache.overall_misses::cpu.inst 24421789 # number of overall misses 647system.cpu.icache.overall_misses::total 24421789 # number of overall misses 648system.cpu.icache.ReadReq_miss_latency::cpu.inst 323902842267 # number of ReadReq miss cycles 649system.cpu.icache.ReadReq_miss_latency::total 323902842267 # number of ReadReq miss cycles 650system.cpu.icache.demand_miss_latency::cpu.inst 323902842267 # number of demand (read+write) miss cycles 651system.cpu.icache.demand_miss_latency::total 323902842267 # number of demand (read+write) miss cycles 652system.cpu.icache.overall_miss_latency::cpu.inst 323902842267 # number of overall miss cycles 653system.cpu.icache.overall_miss_latency::total 323902842267 # number of overall miss cycles 654system.cpu.icache.ReadReq_accesses::cpu.inst 452638159 # number of ReadReq accesses(hits+misses) 655system.cpu.icache.ReadReq_accesses::total 452638159 # number of ReadReq accesses(hits+misses) 656system.cpu.icache.demand_accesses::cpu.inst 452638159 # number of demand (read+write) accesses 657system.cpu.icache.demand_accesses::total 452638159 # number of demand (read+write) accesses 658system.cpu.icache.overall_accesses::cpu.inst 452638159 # number of overall (read+write) accesses 659system.cpu.icache.overall_accesses::total 452638159 # number of overall (read+write) accesses 660system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.053954 # miss rate for ReadReq accesses 661system.cpu.icache.ReadReq_miss_rate::total 0.053954 # miss rate for ReadReq accesses 662system.cpu.icache.demand_miss_rate::cpu.inst 0.053954 # miss rate for demand accesses 663system.cpu.icache.demand_miss_rate::total 0.053954 # miss rate for demand accesses 664system.cpu.icache.overall_miss_rate::cpu.inst 0.053954 # miss rate for overall accesses 665system.cpu.icache.overall_miss_rate::total 0.053954 # miss rate for overall accesses 666system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13262.863022 # average ReadReq miss latency 667system.cpu.icache.ReadReq_avg_miss_latency::total 13262.863022 # average ReadReq miss latency 668system.cpu.icache.demand_avg_miss_latency::cpu.inst 13262.863022 # average overall miss latency 669system.cpu.icache.demand_avg_miss_latency::total 13262.863022 # average overall miss latency 670system.cpu.icache.overall_avg_miss_latency::cpu.inst 13262.863022 # average overall miss latency 671system.cpu.icache.overall_avg_miss_latency::total 13262.863022 # average overall miss latency | 639system.cpu.icache.tags.tag_accesses 479572253 # Number of tag accesses 640system.cpu.icache.tags.data_accesses 479572253 # Number of data accesses 641system.cpu.icache.ReadReq_hits::cpu.inst 430254710 # number of ReadReq hits 642system.cpu.icache.ReadReq_hits::total 430254710 # number of ReadReq hits 643system.cpu.icache.demand_hits::cpu.inst 430254710 # number of demand (read+write) hits 644system.cpu.icache.demand_hits::total 430254710 # number of demand (read+write) hits 645system.cpu.icache.overall_hits::cpu.inst 430254710 # number of overall hits 646system.cpu.icache.overall_hits::total 430254710 # number of overall hits 647system.cpu.icache.ReadReq_misses::cpu.inst 24658772 # number of ReadReq misses 648system.cpu.icache.ReadReq_misses::total 24658772 # number of ReadReq misses 649system.cpu.icache.demand_misses::cpu.inst 24658772 # number of demand (read+write) misses 650system.cpu.icache.demand_misses::total 24658772 # number of demand (read+write) misses 651system.cpu.icache.overall_misses::cpu.inst 24658772 # number of overall misses 652system.cpu.icache.overall_misses::total 24658772 # number of overall misses 653system.cpu.icache.ReadReq_miss_latency::cpu.inst 327794821206 # number of ReadReq miss cycles 654system.cpu.icache.ReadReq_miss_latency::total 327794821206 # number of ReadReq miss cycles 655system.cpu.icache.demand_miss_latency::cpu.inst 327794821206 # number of demand (read+write) miss cycles 656system.cpu.icache.demand_miss_latency::total 327794821206 # number of demand (read+write) miss cycles 657system.cpu.icache.overall_miss_latency::cpu.inst 327794821206 # number of overall miss cycles 658system.cpu.icache.overall_miss_latency::total 327794821206 # number of overall miss cycles 659system.cpu.icache.ReadReq_accesses::cpu.inst 454913482 # number of ReadReq accesses(hits+misses) 660system.cpu.icache.ReadReq_accesses::total 454913482 # number of ReadReq accesses(hits+misses) 661system.cpu.icache.demand_accesses::cpu.inst 454913482 # number of demand (read+write) accesses 662system.cpu.icache.demand_accesses::total 454913482 # number of demand (read+write) accesses 663system.cpu.icache.overall_accesses::cpu.inst 454913482 # number of overall (read+write) accesses 664system.cpu.icache.overall_accesses::total 454913482 # number of overall (read+write) accesses 665system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054205 # miss rate for ReadReq accesses 666system.cpu.icache.ReadReq_miss_rate::total 0.054205 # miss rate for ReadReq accesses 667system.cpu.icache.demand_miss_rate::cpu.inst 0.054205 # miss rate for demand accesses 668system.cpu.icache.demand_miss_rate::total 0.054205 # miss rate for demand accesses 669system.cpu.icache.overall_miss_rate::cpu.inst 0.054205 # miss rate for overall accesses 670system.cpu.icache.overall_miss_rate::total 0.054205 # miss rate for overall accesses 671system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13293.233791 # average ReadReq miss latency 672system.cpu.icache.ReadReq_avg_miss_latency::total 13293.233791 # average ReadReq miss latency 673system.cpu.icache.demand_avg_miss_latency::cpu.inst 13293.233791 # average overall miss latency 674system.cpu.icache.demand_avg_miss_latency::total 13293.233791 # average overall miss latency 675system.cpu.icache.overall_avg_miss_latency::cpu.inst 13293.233791 # average overall miss latency 676system.cpu.icache.overall_avg_miss_latency::total 13293.233791 # average overall miss latency |
| 672system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 673system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 674system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 675system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 676system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 677system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 678system.cpu.icache.fast_writes 0 # number of fast writes performed 679system.cpu.icache.cache_copies 0 # number of cache copies performed | 677system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 678system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 679system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 680system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 681system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 682system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 683system.cpu.icache.fast_writes 0 # number of fast writes performed 684system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 680system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24421789 # number of ReadReq MSHR misses 681system.cpu.icache.ReadReq_mshr_misses::total 24421789 # number of ReadReq MSHR misses 682system.cpu.icache.demand_mshr_misses::cpu.inst 24421789 # number of demand (read+write) MSHR misses 683system.cpu.icache.demand_mshr_misses::total 24421789 # number of demand (read+write) MSHR misses 684system.cpu.icache.overall_mshr_misses::cpu.inst 24421789 # number of overall MSHR misses 685system.cpu.icache.overall_mshr_misses::total 24421789 # number of overall MSHR misses 686system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275014410207 # number of ReadReq MSHR miss cycles 687system.cpu.icache.ReadReq_mshr_miss_latency::total 275014410207 # number of ReadReq MSHR miss cycles 688system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275014410207 # number of demand (read+write) MSHR miss cycles 689system.cpu.icache.demand_mshr_miss_latency::total 275014410207 # number of demand (read+write) MSHR miss cycles 690system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275014410207 # number of overall MSHR miss cycles 691system.cpu.icache.overall_mshr_miss_latency::total 275014410207 # number of overall MSHR miss cycles 692system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3812415750 # number of ReadReq MSHR uncacheable cycles 693system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3812415750 # number of ReadReq MSHR uncacheable cycles 694system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3812415750 # number of overall MSHR uncacheable cycles 695system.cpu.icache.overall_mshr_uncacheable_latency::total 3812415750 # number of overall MSHR uncacheable cycles 696system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053954 # mshr miss rate for ReadReq accesses 697system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053954 # mshr miss rate for ReadReq accesses 698system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053954 # mshr miss rate for demand accesses 699system.cpu.icache.demand_mshr_miss_rate::total 0.053954 # mshr miss rate for demand accesses 700system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053954 # mshr miss rate for overall accesses 701system.cpu.icache.overall_mshr_miss_rate::total 0.053954 # mshr miss rate for overall accesses 702system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11261.026381 # average ReadReq mshr miss latency 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11261.026381 # average ReadReq mshr miss latency 704system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11261.026381 # average overall mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::total 11261.026381 # average overall mshr miss latency 706system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11261.026381 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::total 11261.026381 # average overall mshr miss latency | 685system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24658772 # number of ReadReq MSHR misses 686system.cpu.icache.ReadReq_mshr_misses::total 24658772 # number of ReadReq MSHR misses 687system.cpu.icache.demand_mshr_misses::cpu.inst 24658772 # number of demand (read+write) MSHR misses 688system.cpu.icache.demand_mshr_misses::total 24658772 # number of demand (read+write) MSHR misses 689system.cpu.icache.overall_mshr_misses::cpu.inst 24658772 # number of overall MSHR misses 690system.cpu.icache.overall_mshr_misses::total 24658772 # number of overall MSHR misses 691system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 278428644242 # number of ReadReq MSHR miss cycles 692system.cpu.icache.ReadReq_mshr_miss_latency::total 278428644242 # number of ReadReq MSHR miss cycles 693system.cpu.icache.demand_mshr_miss_latency::cpu.inst 278428644242 # number of demand (read+write) MSHR miss cycles 694system.cpu.icache.demand_mshr_miss_latency::total 278428644242 # number of demand (read+write) MSHR miss cycles 695system.cpu.icache.overall_mshr_miss_latency::cpu.inst 278428644242 # number of overall MSHR miss cycles 696system.cpu.icache.overall_mshr_miss_latency::total 278428644242 # number of overall MSHR miss cycles 697system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3812277750 # number of ReadReq MSHR uncacheable cycles 698system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3812277750 # number of ReadReq MSHR uncacheable cycles 699system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3812277750 # number of overall MSHR uncacheable cycles 700system.cpu.icache.overall_mshr_uncacheable_latency::total 3812277750 # number of overall MSHR uncacheable cycles 701system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054205 # mshr miss rate for ReadReq accesses 702system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054205 # mshr miss rate for ReadReq accesses 703system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054205 # mshr miss rate for demand accesses 704system.cpu.icache.demand_mshr_miss_rate::total 0.054205 # mshr miss rate for demand accesses 705system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054205 # mshr miss rate for overall accesses 706system.cpu.icache.overall_mshr_miss_rate::total 0.054205 # mshr miss rate for overall accesses 707system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11291.261554 # average ReadReq mshr miss latency 708system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11291.261554 # average ReadReq mshr miss latency 709system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11291.261554 # average overall mshr miss latency 710system.cpu.icache.demand_avg_mshr_miss_latency::total 11291.261554 # average overall mshr miss latency 711system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11291.261554 # average overall mshr miss latency 712system.cpu.icache.overall_avg_mshr_miss_latency::total 11291.261554 # average overall mshr miss latency |
| 708system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 709system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 710system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 711system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 712system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 713system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 714system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 715system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 716system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 717system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 713system.cpu.toL2Bus.trans_dist::ReadReq 33751616 # Transaction distribution 714system.cpu.toL2Bus.trans_dist::ReadResp 33743319 # Transaction distribution 715system.cpu.toL2Bus.trans_dist::WriteReq 33870 # Transaction distribution 716system.cpu.toL2Bus.trans_dist::WriteResp 33870 # Transaction distribution 717system.cpu.toL2Bus.trans_dist::Writeback 7503603 # Transaction distribution 718system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1688467 # Transaction distribution 719system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1581795 # Transaction distribution 720system.cpu.toL2Bus.trans_dist::UpgradeReq 49741 # Transaction distribution 721system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 722system.cpu.toL2Bus.trans_dist::UpgradeResp 49742 # Transaction distribution 723system.cpu.toL2Bus.trans_dist::ReadExReq 2372919 # Transaction distribution 724system.cpu.toL2Bus.trans_dist::ReadExResp 2372919 # Transaction distribution 725system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48947837 # Packet count per connected master and slave (bytes) 726system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30709223 # Packet count per connected master and slave (bytes) 727system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697396 # Packet count per connected master and slave (bytes) 728system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2259044 # Packet count per connected master and slave (bytes) 729system.cpu.toL2Bus.pkt_count::total 82613500 # Packet count per connected master and slave (bytes) 730system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1566322176 # Cumulative packet size per connected master and slave (bytes) 731system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1215506888 # Cumulative packet size per connected master and slave (bytes) 732system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2302360 # Cumulative packet size per connected master and slave (bytes) 733system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7713224 # Cumulative packet size per connected master and slave (bytes) 734system.cpu.toL2Bus.pkt_size::total 2791844648 # Cumulative packet size per connected master and slave (bytes) 735system.cpu.toL2Bus.snoops 568944 # Total snoops (count) 736system.cpu.toL2Bus.snoop_fanout::samples 45280303 # Request fanout histogram 737system.cpu.toL2Bus.snoop_fanout::mean 5.002552 # Request fanout histogram 738system.cpu.toL2Bus.snoop_fanout::stdev 0.050452 # Request fanout histogram 739system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 740system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 741system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 742system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 743system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 744system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 745system.cpu.toL2Bus.snoop_fanout::5 45164753 99.74% 99.74% # Request fanout histogram 746system.cpu.toL2Bus.snoop_fanout::6 115550 0.26% 100.00% # Request fanout histogram 747system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 748system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 749system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 750system.cpu.toL2Bus.snoop_fanout::total 45280303 # Request fanout histogram 751system.cpu.toL2Bus.reqLayer0.occupancy 31745616637 # Layer occupancy (ticks) 752system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 753system.cpu.toL2Bus.snoopLayer0.occupancy 870000 # Layer occupancy (ticks) 754system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 755system.cpu.toL2Bus.respLayer0.occupancy 36745726780 # Layer occupancy (ticks) 756system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 757system.cpu.toL2Bus.respLayer1.occupancy 15986739626 # Layer occupancy (ticks) 758system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 759system.cpu.toL2Bus.respLayer2.occupancy 411079115 # Layer occupancy (ticks) 760system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 761system.cpu.toL2Bus.respLayer3.occupancy 1295977131 # Layer occupancy (ticks) 762system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 763system.cpu.l2cache.tags.replacements 1126830 # number of replacements 764system.cpu.l2cache.tags.tagsinuse 64583.745426 # Cycle average of tags in use 765system.cpu.l2cache.tags.total_refs 39448197 # Total number of references to valid blocks. 766system.cpu.l2cache.tags.sampled_refs 1188930 # Sample count of references to valid blocks. 767system.cpu.l2cache.tags.avg_refs 33.179579 # Average number of references to valid blocks. 768system.cpu.l2cache.tags.warmup_cycle 13946888021000 # Cycle when the warmup percentage was hit. 769system.cpu.l2cache.tags.occ_blocks::writebacks 34952.581213 # Average occupied blocks per requestor 770system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 365.608431 # Average occupied blocks per requestor 771system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 461.071203 # Average occupied blocks per requestor 772system.cpu.l2cache.tags.occ_blocks::cpu.inst 28804.484579 # Average occupied blocks per requestor 773system.cpu.l2cache.tags.occ_percent::writebacks 0.533334 # Average percentage of cache occupancy 774system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005579 # Average percentage of cache occupancy 775system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007035 # Average percentage of cache occupancy 776system.cpu.l2cache.tags.occ_percent::cpu.inst 0.439522 # Average percentage of cache occupancy 777system.cpu.l2cache.tags.occ_percent::total 0.985470 # Average percentage of cache occupancy 778system.cpu.l2cache.tags.occ_task_id_blocks::1023 475 # Occupied blocks per task id 779system.cpu.l2cache.tags.occ_task_id_blocks::1024 61625 # Occupied blocks per task id 780system.cpu.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 781system.cpu.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id 782system.cpu.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 783system.cpu.l2cache.tags.age_task_id_blocks_1023::4 455 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1805 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5403 # Occupied blocks per task id 788system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54172 # Occupied blocks per task id 789system.cpu.l2cache.tags.occ_task_id_percent::1023 0.007248 # Percentage of cache occupancy per task id 790system.cpu.l2cache.tags.occ_task_id_percent::1024 0.940323 # Percentage of cache occupancy per task id 791system.cpu.l2cache.tags.tag_accesses 361655243 # Number of tag accesses 792system.cpu.l2cache.tags.data_accesses 361655243 # Number of data accesses 793system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 952821 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 272081 # number of ReadReq hits 795system.cpu.l2cache.ReadReq_hits::cpu.inst 31479251 # number of ReadReq hits 796system.cpu.l2cache.ReadReq_hits::total 32704153 # number of ReadReq hits 797system.cpu.l2cache.Writeback_hits::writebacks 7503603 # number of Writeback hits 798system.cpu.l2cache.Writeback_hits::total 7503603 # number of Writeback hits 799system.cpu.l2cache.UpgradeReq_hits::cpu.inst 11325 # number of UpgradeReq hits 800system.cpu.l2cache.UpgradeReq_hits::total 11325 # number of UpgradeReq hits 801system.cpu.l2cache.ReadExReq_hits::cpu.inst 1470476 # number of ReadExReq hits 802system.cpu.l2cache.ReadExReq_hits::total 1470476 # number of ReadExReq hits 803system.cpu.l2cache.demand_hits::cpu.dtb.walker 952821 # number of demand (read+write) hits 804system.cpu.l2cache.demand_hits::cpu.itb.walker 272081 # number of demand (read+write) hits 805system.cpu.l2cache.demand_hits::cpu.inst 32949727 # number of demand (read+write) hits 806system.cpu.l2cache.demand_hits::total 34174629 # number of demand (read+write) hits 807system.cpu.l2cache.overall_hits::cpu.dtb.walker 952821 # number of overall hits 808system.cpu.l2cache.overall_hits::cpu.itb.walker 272081 # number of overall hits 809system.cpu.l2cache.overall_hits::cpu.inst 32949727 # number of overall hits 810system.cpu.l2cache.overall_hits::total 34174629 # number of overall hits 811system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11332 # number of ReadReq misses 812system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 15714 # number of ReadReq misses 813system.cpu.l2cache.ReadReq_misses::cpu.inst 472686 # number of ReadReq misses 814system.cpu.l2cache.ReadReq_misses::total 499732 # number of ReadReq misses 815system.cpu.l2cache.UpgradeReq_misses::cpu.inst 38413 # number of UpgradeReq misses 816system.cpu.l2cache.UpgradeReq_misses::total 38413 # number of UpgradeReq misses 817system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 1 # number of SCUpgradeReq misses 818system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 819system.cpu.l2cache.ReadExReq_misses::cpu.inst 902443 # number of ReadExReq misses 820system.cpu.l2cache.ReadExReq_misses::total 902443 # number of ReadExReq misses 821system.cpu.l2cache.demand_misses::cpu.dtb.walker 11332 # number of demand (read+write) misses 822system.cpu.l2cache.demand_misses::cpu.itb.walker 15714 # number of demand (read+write) misses 823system.cpu.l2cache.demand_misses::cpu.inst 1375129 # number of demand (read+write) misses 824system.cpu.l2cache.demand_misses::total 1402175 # number of demand (read+write) misses 825system.cpu.l2cache.overall_misses::cpu.dtb.walker 11332 # number of overall misses 826system.cpu.l2cache.overall_misses::cpu.itb.walker 15714 # number of overall misses 827system.cpu.l2cache.overall_misses::cpu.inst 1375129 # number of overall misses 828system.cpu.l2cache.overall_misses::total 1402175 # number of overall misses 829system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 888032250 # number of ReadReq miss cycles 830system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1212828000 # number of ReadReq miss cycles 831system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35148842209 # number of ReadReq miss cycles 832system.cpu.l2cache.ReadReq_miss_latency::total 37249702459 # number of ReadReq miss cycles 833system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 434827365 # number of UpgradeReq miss cycles 834system.cpu.l2cache.UpgradeReq_miss_latency::total 434827365 # number of UpgradeReq miss cycles 835system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 23499 # number of SCUpgradeReq miss cycles 836system.cpu.l2cache.SCUpgradeReq_miss_latency::total 23499 # number of SCUpgradeReq miss cycles 837system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 65253641861 # number of ReadExReq miss cycles 838system.cpu.l2cache.ReadExReq_miss_latency::total 65253641861 # number of ReadExReq miss cycles 839system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 888032250 # number of demand (read+write) miss cycles 840system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1212828000 # number of demand (read+write) miss cycles 841system.cpu.l2cache.demand_miss_latency::cpu.inst 100402484070 # number of demand (read+write) miss cycles 842system.cpu.l2cache.demand_miss_latency::total 102503344320 # number of demand (read+write) miss cycles 843system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 888032250 # number of overall miss cycles 844system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1212828000 # number of overall miss cycles 845system.cpu.l2cache.overall_miss_latency::cpu.inst 100402484070 # number of overall miss cycles 846system.cpu.l2cache.overall_miss_latency::total 102503344320 # number of overall miss cycles 847system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 964153 # number of ReadReq accesses(hits+misses) 848system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 287795 # number of ReadReq accesses(hits+misses) 849system.cpu.l2cache.ReadReq_accesses::cpu.inst 31951937 # number of ReadReq accesses(hits+misses) 850system.cpu.l2cache.ReadReq_accesses::total 33203885 # number of ReadReq accesses(hits+misses) 851system.cpu.l2cache.Writeback_accesses::writebacks 7503603 # number of Writeback accesses(hits+misses) 852system.cpu.l2cache.Writeback_accesses::total 7503603 # number of Writeback accesses(hits+misses) 853system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 49738 # number of UpgradeReq accesses(hits+misses) 854system.cpu.l2cache.UpgradeReq_accesses::total 49738 # number of UpgradeReq accesses(hits+misses) 855system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 1 # number of SCUpgradeReq accesses(hits+misses) 856system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 857system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2372919 # number of ReadExReq accesses(hits+misses) 858system.cpu.l2cache.ReadExReq_accesses::total 2372919 # number of ReadExReq accesses(hits+misses) 859system.cpu.l2cache.demand_accesses::cpu.dtb.walker 964153 # number of demand (read+write) accesses 860system.cpu.l2cache.demand_accesses::cpu.itb.walker 287795 # number of demand (read+write) accesses 861system.cpu.l2cache.demand_accesses::cpu.inst 34324856 # number of demand (read+write) accesses 862system.cpu.l2cache.demand_accesses::total 35576804 # number of demand (read+write) accesses 863system.cpu.l2cache.overall_accesses::cpu.dtb.walker 964153 # number of overall (read+write) accesses 864system.cpu.l2cache.overall_accesses::cpu.itb.walker 287795 # number of overall (read+write) accesses 865system.cpu.l2cache.overall_accesses::cpu.inst 34324856 # number of overall (read+write) accesses 866system.cpu.l2cache.overall_accesses::total 35576804 # number of overall (read+write) accesses 867system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011753 # miss rate for ReadReq accesses 868system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.054601 # miss rate for ReadReq accesses 869system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014794 # miss rate for ReadReq accesses 870system.cpu.l2cache.ReadReq_miss_rate::total 0.015050 # miss rate for ReadReq accesses 871system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.772307 # miss rate for UpgradeReq accesses 872system.cpu.l2cache.UpgradeReq_miss_rate::total 0.772307 # miss rate for UpgradeReq accesses | 718system.cpu.l2cache.tags.replacements 1618781 # number of replacements 719system.cpu.l2cache.tags.tagsinuse 65312.211718 # Cycle average of tags in use 720system.cpu.l2cache.tags.total_refs 40301488 # Total number of references to valid blocks. 721system.cpu.l2cache.tags.sampled_refs 1682083 # Sample count of references to valid blocks. 722system.cpu.l2cache.tags.avg_refs 23.959274 # Average number of references to valid blocks. 723system.cpu.l2cache.tags.warmup_cycle 5745484000 # Cycle when the warmup percentage was hit. 724system.cpu.l2cache.tags.occ_blocks::writebacks 36153.667077 # Average occupied blocks per requestor 725system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 338.579375 # Average occupied blocks per requestor 726system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 416.289773 # Average occupied blocks per requestor 727system.cpu.l2cache.tags.occ_blocks::cpu.inst 28403.675493 # Average occupied blocks per requestor 728system.cpu.l2cache.tags.occ_percent::writebacks 0.551661 # Average percentage of cache occupancy 729system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005166 # Average percentage of cache occupancy 730system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006352 # Average percentage of cache occupancy 731system.cpu.l2cache.tags.occ_percent::cpu.inst 0.433406 # Average percentage of cache occupancy 732system.cpu.l2cache.tags.occ_percent::total 0.996585 # Average percentage of cache occupancy 733system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id 734system.cpu.l2cache.tags.occ_task_id_blocks::1024 63024 # Occupied blocks per task id 735system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 736system.cpu.l2cache.tags.age_task_id_blocks_1023::4 277 # Occupied blocks per task id 737system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 738system.cpu.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id 739system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2429 # Occupied blocks per task id 740system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5550 # Occupied blocks per task id 741system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54509 # Occupied blocks per task id 742system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id 743system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961670 # Percentage of cache occupancy per task id 744system.cpu.l2cache.tags.tag_accesses 370683226 # Number of tag accesses 745system.cpu.l2cache.tags.data_accesses 370683226 # Number of data accesses 746system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 969390 # number of ReadReq hits 747system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 282718 # number of ReadReq hits 748system.cpu.l2cache.ReadReq_hits::cpu.inst 31773452 # number of ReadReq hits 749system.cpu.l2cache.ReadReq_hits::total 33025560 # number of ReadReq hits 750system.cpu.l2cache.Writeback_hits::writebacks 8574653 # number of Writeback hits 751system.cpu.l2cache.Writeback_hits::total 8574653 # number of Writeback hits 752system.cpu.l2cache.WriteInvalidateReq_hits::cpu.inst 700619 # number of WriteInvalidateReq hits 753system.cpu.l2cache.WriteInvalidateReq_hits::total 700619 # number of WriteInvalidateReq hits 754system.cpu.l2cache.UpgradeReq_hits::cpu.inst 10899 # number of UpgradeReq hits 755system.cpu.l2cache.UpgradeReq_hits::total 10899 # number of UpgradeReq hits 756system.cpu.l2cache.ReadExReq_hits::cpu.inst 1669806 # number of ReadExReq hits 757system.cpu.l2cache.ReadExReq_hits::total 1669806 # number of ReadExReq hits 758system.cpu.l2cache.demand_hits::cpu.dtb.walker 969390 # number of demand (read+write) hits 759system.cpu.l2cache.demand_hits::cpu.itb.walker 282718 # number of demand (read+write) hits 760system.cpu.l2cache.demand_hits::cpu.inst 33443258 # number of demand (read+write) hits 761system.cpu.l2cache.demand_hits::total 34695366 # number of demand (read+write) hits 762system.cpu.l2cache.overall_hits::cpu.dtb.walker 969390 # number of overall hits 763system.cpu.l2cache.overall_hits::cpu.itb.walker 282718 # number of overall hits 764system.cpu.l2cache.overall_hits::cpu.inst 33443258 # number of overall hits 765system.cpu.l2cache.overall_hits::total 34695366 # number of overall hits 766system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6426 # number of ReadReq misses 767system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5473 # number of ReadReq misses 768system.cpu.l2cache.ReadReq_misses::cpu.inst 442244 # number of ReadReq misses 769system.cpu.l2cache.ReadReq_misses::total 454143 # number of ReadReq misses 770system.cpu.l2cache.WriteInvalidateReq_misses::cpu.inst 544275 # number of WriteInvalidateReq misses 771system.cpu.l2cache.WriteInvalidateReq_misses::total 544275 # number of WriteInvalidateReq misses 772system.cpu.l2cache.UpgradeReq_misses::cpu.inst 39165 # number of UpgradeReq misses 773system.cpu.l2cache.UpgradeReq_misses::total 39165 # number of UpgradeReq misses 774system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses 775system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 776system.cpu.l2cache.ReadExReq_misses::cpu.inst 713266 # number of ReadExReq misses 777system.cpu.l2cache.ReadExReq_misses::total 713266 # number of ReadExReq misses 778system.cpu.l2cache.demand_misses::cpu.dtb.walker 6426 # number of demand (read+write) misses 779system.cpu.l2cache.demand_misses::cpu.itb.walker 5473 # number of demand (read+write) misses 780system.cpu.l2cache.demand_misses::cpu.inst 1155510 # number of demand (read+write) misses 781system.cpu.l2cache.demand_misses::total 1167409 # number of demand (read+write) misses 782system.cpu.l2cache.overall_misses::cpu.dtb.walker 6426 # number of overall misses 783system.cpu.l2cache.overall_misses::cpu.itb.walker 5473 # number of overall misses 784system.cpu.l2cache.overall_misses::cpu.inst 1155510 # number of overall misses 785system.cpu.l2cache.overall_misses::total 1167409 # number of overall misses 786system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 506602500 # number of ReadReq miss cycles 787system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 435256500 # number of ReadReq miss cycles 788system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 33470920971 # number of ReadReq miss cycles 789system.cpu.l2cache.ReadReq_miss_latency::total 34412779971 # number of ReadReq miss cycles 790system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.inst 4488807 # number of WriteInvalidateReq miss cycles 791system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4488807 # number of WriteInvalidateReq miss cycles 792system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 437669201 # number of UpgradeReq miss cycles 793system.cpu.l2cache.UpgradeReq_miss_latency::total 437669201 # number of UpgradeReq miss cycles 794system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 144500 # number of SCUpgradeReq miss cycles 795system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles 796system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 53261752624 # number of ReadExReq miss cycles 797system.cpu.l2cache.ReadExReq_miss_latency::total 53261752624 # number of ReadExReq miss cycles 798system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 506602500 # number of demand (read+write) miss cycles 799system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 435256500 # number of demand (read+write) miss cycles 800system.cpu.l2cache.demand_miss_latency::cpu.inst 86732673595 # number of demand (read+write) miss cycles 801system.cpu.l2cache.demand_miss_latency::total 87674532595 # number of demand (read+write) miss cycles 802system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 506602500 # number of overall miss cycles 803system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 435256500 # number of overall miss cycles 804system.cpu.l2cache.overall_miss_latency::cpu.inst 86732673595 # number of overall miss cycles 805system.cpu.l2cache.overall_miss_latency::total 87674532595 # number of overall miss cycles 806system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 975816 # number of ReadReq accesses(hits+misses) 807system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 288191 # number of ReadReq accesses(hits+misses) 808system.cpu.l2cache.ReadReq_accesses::cpu.inst 32215696 # number of ReadReq accesses(hits+misses) 809system.cpu.l2cache.ReadReq_accesses::total 33479703 # number of ReadReq accesses(hits+misses) 810system.cpu.l2cache.Writeback_accesses::writebacks 8574653 # number of Writeback accesses(hits+misses) 811system.cpu.l2cache.Writeback_accesses::total 8574653 # number of Writeback accesses(hits+misses) 812system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.inst 1244894 # number of WriteInvalidateReq accesses(hits+misses) 813system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244894 # number of WriteInvalidateReq accesses(hits+misses) 814system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 50064 # number of UpgradeReq accesses(hits+misses) 815system.cpu.l2cache.UpgradeReq_accesses::total 50064 # number of UpgradeReq accesses(hits+misses) 816system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) 817system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 818system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2383072 # number of ReadExReq accesses(hits+misses) 819system.cpu.l2cache.ReadExReq_accesses::total 2383072 # number of ReadExReq accesses(hits+misses) 820system.cpu.l2cache.demand_accesses::cpu.dtb.walker 975816 # number of demand (read+write) accesses 821system.cpu.l2cache.demand_accesses::cpu.itb.walker 288191 # number of demand (read+write) accesses 822system.cpu.l2cache.demand_accesses::cpu.inst 34598768 # number of demand (read+write) accesses 823system.cpu.l2cache.demand_accesses::total 35862775 # number of demand (read+write) accesses 824system.cpu.l2cache.overall_accesses::cpu.dtb.walker 975816 # number of overall (read+write) accesses 825system.cpu.l2cache.overall_accesses::cpu.itb.walker 288191 # number of overall (read+write) accesses 826system.cpu.l2cache.overall_accesses::cpu.inst 34598768 # number of overall (read+write) accesses 827system.cpu.l2cache.overall_accesses::total 35862775 # number of overall (read+write) accesses 828system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006585 # miss rate for ReadReq accesses 829system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018991 # miss rate for ReadReq accesses 830system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.013728 # miss rate for ReadReq accesses 831system.cpu.l2cache.ReadReq_miss_rate::total 0.013565 # miss rate for ReadReq accesses 832system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.inst 0.437206 # miss rate for WriteInvalidateReq accesses 833system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.437206 # miss rate for WriteInvalidateReq accesses 834system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.782299 # miss rate for UpgradeReq accesses 835system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782299 # miss rate for UpgradeReq accesses |
| 873system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses 874system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 836system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses 837system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 875system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.380309 # miss rate for ReadExReq accesses 876system.cpu.l2cache.ReadExReq_miss_rate::total 0.380309 # miss rate for ReadExReq accesses 877system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011753 # miss rate for demand accesses 878system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.054601 # miss rate for demand accesses 879system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040062 # miss rate for demand accesses 880system.cpu.l2cache.demand_miss_rate::total 0.039413 # miss rate for demand accesses 881system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011753 # miss rate for overall accesses 882system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.054601 # miss rate for overall accesses 883system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040062 # miss rate for overall accesses 884system.cpu.l2cache.overall_miss_rate::total 0.039413 # miss rate for overall accesses 885system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78365.006177 # average ReadReq miss latency 886system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77181.366934 # average ReadReq miss latency 887system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74359.812241 # average ReadReq miss latency 888system.cpu.l2cache.ReadReq_avg_miss_latency::total 74539.358014 # average ReadReq miss latency 889system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11319.797074 # average UpgradeReq miss latency 890system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11319.797074 # average UpgradeReq miss latency 891system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23499 # average SCUpgradeReq miss latency 892system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency 893system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72307.771085 # average ReadExReq miss latency 894system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72307.771085 # average ReadExReq miss latency 895system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78365.006177 # average overall miss latency 896system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77181.366934 # average overall miss latency 897system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73013.138455 # average overall miss latency 898system.cpu.l2cache.demand_avg_miss_latency::total 73103.103621 # average overall miss latency 899system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78365.006177 # average overall miss latency 900system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77181.366934 # average overall miss latency 901system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73013.138455 # average overall miss latency 902system.cpu.l2cache.overall_avg_miss_latency::total 73103.103621 # average overall miss latency | 838system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.299305 # miss rate for ReadExReq accesses 839system.cpu.l2cache.ReadExReq_miss_rate::total 0.299305 # miss rate for ReadExReq accesses 840system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006585 # miss rate for demand accesses 841system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018991 # miss rate for demand accesses 842system.cpu.l2cache.demand_miss_rate::cpu.inst 0.033397 # miss rate for demand accesses 843system.cpu.l2cache.demand_miss_rate::total 0.032552 # miss rate for demand accesses 844system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006585 # miss rate for overall accesses 845system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018991 # miss rate for overall accesses 846system.cpu.l2cache.overall_miss_rate::cpu.inst 0.033397 # miss rate for overall accesses 847system.cpu.l2cache.overall_miss_rate::total 0.032552 # miss rate for overall accesses 848system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78836.367880 # average ReadReq miss latency 849system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79527.955418 # average ReadReq miss latency 850system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75684.285080 # average ReadReq miss latency 851system.cpu.l2cache.ReadReq_avg_miss_latency::total 75775.207305 # average ReadReq miss latency 852system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.inst 8.247314 # average WriteInvalidateReq miss latency 853system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 8.247314 # average WriteInvalidateReq miss latency 854system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11175.008324 # average UpgradeReq miss latency 855system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11175.008324 # average UpgradeReq miss latency 856system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 72250 # average SCUpgradeReq miss latency 857system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency 858system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74673.056930 # average ReadExReq miss latency 859system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74673.056930 # average ReadExReq miss latency 860system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78836.367880 # average overall miss latency 861system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79527.955418 # average overall miss latency 862system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75060.080480 # average overall miss latency 863system.cpu.l2cache.demand_avg_miss_latency::total 75101.813156 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78836.367880 # average overall miss latency 865system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79527.955418 # average overall miss latency 866system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75060.080480 # average overall miss latency 867system.cpu.l2cache.overall_avg_miss_latency::total 75101.813156 # average overall miss latency |
| 903system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 905system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 906system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 907system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 908system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 909system.cpu.l2cache.fast_writes 0 # number of fast writes performed 910system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 868system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 869system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 870system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 871system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 872system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 873system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 874system.cpu.l2cache.fast_writes 0 # number of fast writes performed 875system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 911system.cpu.l2cache.writebacks::writebacks 896030 # number of writebacks 912system.cpu.l2cache.writebacks::total 896030 # number of writebacks 913system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits 914system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits 915system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits 916system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits 917system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits 918system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits 919system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 11332 # number of ReadReq MSHR misses 920system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 15714 # number of ReadReq MSHR misses 921system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 472664 # number of ReadReq MSHR misses 922system.cpu.l2cache.ReadReq_mshr_misses::total 499710 # number of ReadReq MSHR misses 923system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 38413 # number of UpgradeReq MSHR misses 924system.cpu.l2cache.UpgradeReq_mshr_misses::total 38413 # number of UpgradeReq MSHR misses 925system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 1 # number of SCUpgradeReq MSHR misses 926system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 927system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 902443 # number of ReadExReq MSHR misses 928system.cpu.l2cache.ReadExReq_mshr_misses::total 902443 # number of ReadExReq MSHR misses 929system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 11332 # number of demand (read+write) MSHR misses 930system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 15714 # number of demand (read+write) MSHR misses 931system.cpu.l2cache.demand_mshr_misses::cpu.inst 1375107 # number of demand (read+write) MSHR misses 932system.cpu.l2cache.demand_mshr_misses::total 1402153 # number of demand (read+write) MSHR misses 933system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 11332 # number of overall MSHR misses 934system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 15714 # number of overall MSHR misses 935system.cpu.l2cache.overall_mshr_misses::cpu.inst 1375107 # number of overall MSHR misses 936system.cpu.l2cache.overall_mshr_misses::total 1402153 # number of overall MSHR misses 937system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 747069250 # number of ReadReq MSHR miss cycles 938system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 1017596000 # number of ReadReq MSHR miss cycles 939system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29199771041 # number of ReadReq MSHR miss cycles 940system.cpu.l2cache.ReadReq_mshr_miss_latency::total 30964436291 # number of ReadReq MSHR miss cycles 941system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 31915763266 # number of WriteInvalidateReq MSHR miss cycles 942system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 31915763266 # number of WriteInvalidateReq MSHR miss cycles 943system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 384713359 # number of UpgradeReq MSHR miss cycles 944system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 384713359 # number of UpgradeReq MSHR miss cycles 945system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 10001 # number of SCUpgradeReq MSHR miss cycles 946system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles 947system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53676834083 # number of ReadExReq MSHR miss cycles 948system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53676834083 # number of ReadExReq MSHR miss cycles 949system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 747069250 # number of demand (read+write) MSHR miss cycles 950system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 1017596000 # number of demand (read+write) MSHR miss cycles 951system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 82876605124 # number of demand (read+write) MSHR miss cycles 952system.cpu.l2cache.demand_mshr_miss_latency::total 84641270374 # number of demand (read+write) MSHR miss cycles 953system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 747069250 # number of overall MSHR miss cycles 954system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1017596000 # number of overall MSHR miss cycles 955system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 82876605124 # number of overall MSHR miss cycles 956system.cpu.l2cache.overall_mshr_miss_latency::total 84641270374 # number of overall MSHR miss cycles 957system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007389750 # number of ReadReq MSHR uncacheable cycles 958system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8007389750 # number of ReadReq MSHR uncacheable cycles 959system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 5176574500 # number of WriteReq MSHR uncacheable cycles 960system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176574500 # number of WriteReq MSHR uncacheable cycles 961system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 13183964250 # number of overall MSHR uncacheable cycles 962system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13183964250 # number of overall MSHR uncacheable cycles 963system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011753 # mshr miss rate for ReadReq accesses 964system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.054601 # mshr miss rate for ReadReq accesses 965system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014793 # mshr miss rate for ReadReq accesses 966system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015050 # mshr miss rate for ReadReq accesses 967system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.772307 # mshr miss rate for UpgradeReq accesses 968system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.772307 # mshr miss rate for UpgradeReq accesses | 876system.cpu.l2cache.writebacks::writebacks 1377216 # number of writebacks 877system.cpu.l2cache.writebacks::total 1377216 # number of writebacks 878system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 23 # number of ReadReq MSHR hits 879system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits 880system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits 881system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits 882system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits 883system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits 884system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6426 # number of ReadReq MSHR misses 885system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5473 # number of ReadReq MSHR misses 886system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 442221 # number of ReadReq MSHR misses 887system.cpu.l2cache.ReadReq_mshr_misses::total 454120 # number of ReadReq MSHR misses 888system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.inst 544275 # number of WriteInvalidateReq MSHR misses 889system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 544275 # number of WriteInvalidateReq MSHR misses 890system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 39165 # number of UpgradeReq MSHR misses 891system.cpu.l2cache.UpgradeReq_mshr_misses::total 39165 # number of UpgradeReq MSHR misses 892system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses 893system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 894system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 713266 # number of ReadExReq MSHR misses 895system.cpu.l2cache.ReadExReq_mshr_misses::total 713266 # number of ReadExReq MSHR misses 896system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6426 # number of demand (read+write) MSHR misses 897system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5473 # number of demand (read+write) MSHR misses 898system.cpu.l2cache.demand_mshr_misses::cpu.inst 1155487 # number of demand (read+write) MSHR misses 899system.cpu.l2cache.demand_mshr_misses::total 1167386 # number of demand (read+write) MSHR misses 900system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6426 # number of overall MSHR misses 901system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5473 # number of overall MSHR misses 902system.cpu.l2cache.overall_mshr_misses::cpu.inst 1155487 # number of overall MSHR misses 903system.cpu.l2cache.overall_mshr_misses::total 1167386 # number of overall MSHR misses 904system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 426390000 # number of ReadReq MSHR miss cycles 905system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 366985500 # number of ReadReq MSHR miss cycles 906system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27899659527 # number of ReadReq MSHR miss cycles 907system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28693035027 # number of ReadReq MSHR miss cycles 908system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 12715651197 # number of WriteInvalidateReq MSHR miss cycles 909system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 12715651197 # number of WriteInvalidateReq MSHR miss cycles 910system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 392011653 # number of UpgradeReq MSHR miss cycles 911system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 392011653 # number of UpgradeReq MSHR miss cycles 912system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 120500 # number of SCUpgradeReq MSHR miss cycles 913system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles 914system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 44103603876 # number of ReadExReq MSHR miss cycles 915system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44103603876 # number of ReadExReq MSHR miss cycles 916system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 426390000 # number of demand (read+write) MSHR miss cycles 917system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 366985500 # number of demand (read+write) MSHR miss cycles 918system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72003263403 # number of demand (read+write) MSHR miss cycles 919system.cpu.l2cache.demand_mshr_miss_latency::total 72796638903 # number of demand (read+write) MSHR miss cycles 920system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 426390000 # number of overall MSHR miss cycles 921system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 366985500 # number of overall MSHR miss cycles 922system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72003263403 # number of overall MSHR miss cycles 923system.cpu.l2cache.overall_mshr_miss_latency::total 72796638903 # number of overall MSHR miss cycles 924system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007275752 # number of ReadReq MSHR uncacheable cycles 925system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8007275752 # number of ReadReq MSHR uncacheable cycles 926system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 5177466000 # number of WriteReq MSHR uncacheable cycles 927system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5177466000 # number of WriteReq MSHR uncacheable cycles 928system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 13184741752 # number of overall MSHR uncacheable cycles 929system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13184741752 # number of overall MSHR uncacheable cycles 930system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006585 # mshr miss rate for ReadReq accesses 931system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018991 # mshr miss rate for ReadReq accesses 932system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.013727 # mshr miss rate for ReadReq accesses 933system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013564 # mshr miss rate for ReadReq accesses 934system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.437206 # mshr miss rate for WriteInvalidateReq accesses 935system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.437206 # mshr miss rate for WriteInvalidateReq accesses 936system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.782299 # mshr miss rate for UpgradeReq accesses 937system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782299 # mshr miss rate for UpgradeReq accesses |
| 969system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses 970system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 938system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses 939system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 971system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.380309 # mshr miss rate for ReadExReq accesses 972system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.380309 # mshr miss rate for ReadExReq accesses 973system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011753 # mshr miss rate for demand accesses 974system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.054601 # mshr miss rate for demand accesses 975system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040062 # mshr miss rate for demand accesses 976system.cpu.l2cache.demand_mshr_miss_rate::total 0.039412 # mshr miss rate for demand accesses 977system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011753 # mshr miss rate for overall accesses 978system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.054601 # mshr miss rate for overall accesses 979system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040062 # mshr miss rate for overall accesses 980system.cpu.l2cache.overall_mshr_miss_rate::total 0.039412 # mshr miss rate for overall accesses 981system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957 # average ReadReq mshr miss latency 982system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64757.286496 # average ReadReq mshr miss latency 983system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61777.015049 # average ReadReq mshr miss latency 984system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61964.812173 # average ReadReq mshr miss latency 985system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst inf # average WriteInvalidateReq mshr miss latency 986system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 987system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10015.186499 # average UpgradeReq mshr miss latency 988system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.186499 # average UpgradeReq mshr miss latency 989system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # average SCUpgradeReq mshr miss latency 990system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 991system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59479.473034 # average ReadExReq mshr miss latency 992system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59479.473034 # average ReadExReq mshr miss latency 993system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957 # average overall mshr miss latency 994system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64757.286496 # average overall mshr miss latency 995system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60269.204596 # average overall mshr miss latency 996system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60365.217187 # average overall mshr miss latency 997system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957 # average overall mshr miss latency 998system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64757.286496 # average overall mshr miss latency 999system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60269.204596 # average overall mshr miss latency 1000system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60365.217187 # average overall mshr miss latency | 940system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.299305 # mshr miss rate for ReadExReq accesses 941system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.299305 # mshr miss rate for ReadExReq accesses 942system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006585 # mshr miss rate for demand accesses 943system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018991 # mshr miss rate for demand accesses 944system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033397 # mshr miss rate for demand accesses 945system.cpu.l2cache.demand_mshr_miss_rate::total 0.032551 # mshr miss rate for demand accesses 946system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006585 # mshr miss rate for overall accesses 947system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018991 # mshr miss rate for overall accesses 948system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033397 # mshr miss rate for overall accesses 949system.cpu.l2cache.overall_mshr_miss_rate::total 0.032551 # mshr miss rate for overall accesses 950system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883 # average ReadReq mshr miss latency 951system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67053.809611 # average ReadReq mshr miss latency 952system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63089.856716 # average ReadReq mshr miss latency 953system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63183.817112 # average ReadReq mshr miss latency 954system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 23362.548706 # average WriteInvalidateReq mshr miss latency 955system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23362.548706 # average WriteInvalidateReq mshr miss latency 956system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10009.234087 # average UpgradeReq mshr miss latency 957system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.234087 # average UpgradeReq mshr miss latency 958system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency 959system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency 960system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61833.318672 # average ReadExReq mshr miss latency 961system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61833.318672 # average ReadExReq mshr miss latency 962system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883 # average overall mshr miss latency 963system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67053.809611 # average overall mshr miss latency 964system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62314.213317 # average overall mshr miss latency 965system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62358.670485 # average overall mshr miss latency 966system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883 # average overall mshr miss latency 967system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67053.809611 # average overall mshr miss latency 968system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62314.213317 # average overall mshr miss latency 969system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62358.670485 # average overall mshr miss latency |
| 1001system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1002system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1003system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1004system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1005system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1006system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1007system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 970system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 971system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 972system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 973system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 974system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 975system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 976system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1008system.cpu.dcache.tags.replacements 11147587 # number of replacements 1009system.cpu.dcache.tags.tagsinuse 511.959699 # Cycle average of tags in use 1010system.cpu.dcache.tags.total_refs 329635231 # Total number of references to valid blocks. 1011system.cpu.dcache.tags.sampled_refs 11148099 # Sample count of references to valid blocks. 1012system.cpu.dcache.tags.avg_refs 29.568739 # Average number of references to valid blocks. 1013system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. 1014system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959699 # Average occupied blocks per requestor 1015system.cpu.dcache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy 1016system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy 1017system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1018system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 1019system.cpu.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id 1020system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 1021system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1022system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1023system.cpu.dcache.tags.tag_accesses 1384853655 # Number of tag accesses 1024system.cpu.dcache.tags.data_accesses 1384853655 # Number of data accesses 1025system.cpu.dcache.ReadReq_hits::cpu.inst 168902945 # number of ReadReq hits 1026system.cpu.dcache.ReadReq_hits::total 168902945 # number of ReadReq hits 1027system.cpu.dcache.WriteReq_hits::cpu.inst 151918527 # number of WriteReq hits 1028system.cpu.dcache.WriteReq_hits::total 151918527 # number of WriteReq hits 1029system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 1581795 # number of WriteInvalidateReq hits 1030system.cpu.dcache.WriteInvalidateReq_hits::total 1581795 # number of WriteInvalidateReq hits 1031system.cpu.dcache.LoadLockedReq_hits::cpu.inst 4090248 # number of LoadLockedReq hits 1032system.cpu.dcache.LoadLockedReq_hits::total 4090248 # number of LoadLockedReq hits 1033system.cpu.dcache.StoreCondReq_hits::cpu.inst 4335751 # number of StoreCondReq hits 1034system.cpu.dcache.StoreCondReq_hits::total 4335751 # number of StoreCondReq hits 1035system.cpu.dcache.demand_hits::cpu.inst 320821472 # number of demand (read+write) hits 1036system.cpu.dcache.demand_hits::total 320821472 # number of demand (read+write) hits 1037system.cpu.dcache.overall_hits::cpu.inst 320821472 # number of overall hits 1038system.cpu.dcache.overall_hits::total 320821472 # number of overall hits 1039system.cpu.dcache.ReadReq_misses::cpu.inst 8037897 # number of ReadReq misses 1040system.cpu.dcache.ReadReq_misses::total 8037897 # number of ReadReq misses 1041system.cpu.dcache.WriteReq_misses::cpu.inst 4311983 # number of WriteReq misses 1042system.cpu.dcache.WriteReq_misses::total 4311983 # number of WriteReq misses 1043system.cpu.dcache.LoadLockedReq_misses::cpu.inst 247236 # number of LoadLockedReq misses 1044system.cpu.dcache.LoadLockedReq_misses::total 247236 # number of LoadLockedReq misses 1045system.cpu.dcache.StoreCondReq_misses::cpu.inst 1 # number of StoreCondReq misses 1046system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 1047system.cpu.dcache.demand_misses::cpu.inst 12349880 # number of demand (read+write) misses 1048system.cpu.dcache.demand_misses::total 12349880 # number of demand (read+write) misses 1049system.cpu.dcache.overall_misses::cpu.inst 12349880 # number of overall misses 1050system.cpu.dcache.overall_misses::total 12349880 # number of overall misses 1051system.cpu.dcache.ReadReq_miss_latency::cpu.inst 130169188997 # number of ReadReq miss cycles 1052system.cpu.dcache.ReadReq_miss_latency::total 130169188997 # number of ReadReq miss cycles 1053system.cpu.dcache.WriteReq_miss_latency::cpu.inst 162013771213 # number of WriteReq miss cycles 1054system.cpu.dcache.WriteReq_miss_latency::total 162013771213 # number of WriteReq miss cycles 1055system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 3579343752 # number of LoadLockedReq miss cycles 1056system.cpu.dcache.LoadLockedReq_miss_latency::total 3579343752 # number of LoadLockedReq miss cycles 1057system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 26501 # number of StoreCondReq miss cycles 1058system.cpu.dcache.StoreCondReq_miss_latency::total 26501 # number of StoreCondReq miss cycles 1059system.cpu.dcache.demand_miss_latency::cpu.inst 292182960210 # number of demand (read+write) miss cycles 1060system.cpu.dcache.demand_miss_latency::total 292182960210 # number of demand (read+write) miss cycles 1061system.cpu.dcache.overall_miss_latency::cpu.inst 292182960210 # number of overall miss cycles 1062system.cpu.dcache.overall_miss_latency::total 292182960210 # number of overall miss cycles 1063system.cpu.dcache.ReadReq_accesses::cpu.inst 176940842 # number of ReadReq accesses(hits+misses) 1064system.cpu.dcache.ReadReq_accesses::total 176940842 # number of ReadReq accesses(hits+misses) 1065system.cpu.dcache.WriteReq_accesses::cpu.inst 156230510 # number of WriteReq accesses(hits+misses) 1066system.cpu.dcache.WriteReq_accesses::total 156230510 # number of WriteReq accesses(hits+misses) 1067system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst 1581795 # number of WriteInvalidateReq accesses(hits+misses) 1068system.cpu.dcache.WriteInvalidateReq_accesses::total 1581795 # number of WriteInvalidateReq accesses(hits+misses) 1069system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 4337484 # number of LoadLockedReq accesses(hits+misses) 1070system.cpu.dcache.LoadLockedReq_accesses::total 4337484 # number of LoadLockedReq accesses(hits+misses) 1071system.cpu.dcache.StoreCondReq_accesses::cpu.inst 4335752 # number of StoreCondReq accesses(hits+misses) 1072system.cpu.dcache.StoreCondReq_accesses::total 4335752 # number of StoreCondReq accesses(hits+misses) 1073system.cpu.dcache.demand_accesses::cpu.inst 333171352 # number of demand (read+write) accesses 1074system.cpu.dcache.demand_accesses::total 333171352 # number of demand (read+write) accesses 1075system.cpu.dcache.overall_accesses::cpu.inst 333171352 # number of overall (read+write) accesses 1076system.cpu.dcache.overall_accesses::total 333171352 # number of overall (read+write) accesses 1077system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.045427 # miss rate for ReadReq accesses 1078system.cpu.dcache.ReadReq_miss_rate::total 0.045427 # miss rate for ReadReq accesses 1079system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.027600 # miss rate for WriteReq accesses 1080system.cpu.dcache.WriteReq_miss_rate::total 0.027600 # miss rate for WriteReq accesses 1081system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.057000 # miss rate for LoadLockedReq accesses 1082system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057000 # miss rate for LoadLockedReq accesses 1083system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000000 # miss rate for StoreCondReq accesses 1084system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 1085system.cpu.dcache.demand_miss_rate::cpu.inst 0.037068 # miss rate for demand accesses 1086system.cpu.dcache.demand_miss_rate::total 0.037068 # miss rate for demand accesses 1087system.cpu.dcache.overall_miss_rate::cpu.inst 0.037068 # miss rate for overall accesses 1088system.cpu.dcache.overall_miss_rate::total 0.037068 # miss rate for overall accesses 1089system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16194.433569 # average ReadReq miss latency 1090system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.433569 # average ReadReq miss latency 1091system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 37572.915110 # average WriteReq miss latency 1092system.cpu.dcache.WriteReq_avg_miss_latency::total 37572.915110 # average WriteReq miss latency 1093system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14477.437558 # average LoadLockedReq miss latency 1094system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14477.437558 # average LoadLockedReq miss latency 1095system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26501 # average StoreCondReq miss latency 1096system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency 1097system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23658.769171 # average overall miss latency 1098system.cpu.dcache.demand_avg_miss_latency::total 23658.769171 # average overall miss latency 1099system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23658.769171 # average overall miss latency 1100system.cpu.dcache.overall_avg_miss_latency::total 23658.769171 # average overall miss latency 1101system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1102system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1103system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1104system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1105system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1106system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1107system.cpu.dcache.fast_writes 1581795 # number of fast writes performed 1108system.cpu.dcache.cache_copies 0 # number of cache copies performed 1109system.cpu.dcache.writebacks::writebacks 7503603 # number of writebacks 1110system.cpu.dcache.writebacks::total 7503603 # number of writebacks 1111system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 754441 # number of ReadReq MSHR hits 1112system.cpu.dcache.ReadReq_mshr_hits::total 754441 # number of ReadReq MSHR hits 1113system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1888429 # number of WriteReq MSHR hits 1114system.cpu.dcache.WriteReq_mshr_hits::total 1888429 # number of WriteReq MSHR hits 1115system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits 1116system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 1117system.cpu.dcache.demand_mshr_hits::cpu.inst 2642870 # number of demand (read+write) MSHR hits 1118system.cpu.dcache.demand_mshr_hits::total 2642870 # number of demand (read+write) MSHR hits 1119system.cpu.dcache.overall_mshr_hits::cpu.inst 2642870 # number of overall MSHR hits 1120system.cpu.dcache.overall_mshr_hits::total 2642870 # number of overall MSHR hits 1121system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7283456 # number of ReadReq MSHR misses 1122system.cpu.dcache.ReadReq_mshr_misses::total 7283456 # number of ReadReq MSHR misses 1123system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2422384 # number of WriteReq MSHR misses 1124system.cpu.dcache.WriteReq_mshr_misses::total 2422384 # number of WriteReq MSHR misses 1125system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 247233 # number of LoadLockedReq MSHR misses 1126system.cpu.dcache.LoadLockedReq_mshr_misses::total 247233 # number of LoadLockedReq MSHR misses 1127system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 1 # number of StoreCondReq MSHR misses 1128system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 1129system.cpu.dcache.demand_mshr_misses::cpu.inst 9705840 # number of demand (read+write) MSHR misses 1130system.cpu.dcache.demand_mshr_misses::total 9705840 # number of demand (read+write) MSHR misses 1131system.cpu.dcache.overall_mshr_misses::cpu.inst 9705840 # number of overall MSHR misses 1132system.cpu.dcache.overall_mshr_misses::total 9705840 # number of overall MSHR misses 1133system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 104220169248 # number of ReadReq MSHR miss cycles 1134system.cpu.dcache.ReadReq_mshr_miss_latency::total 104220169248 # number of ReadReq MSHR miss cycles 1135system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 83386178898 # number of WriteReq MSHR miss cycles 1136system.cpu.dcache.WriteReq_mshr_miss_latency::total 83386178898 # number of WriteReq MSHR miss cycles 1137system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 50958353731 # number of WriteInvalidateReq MSHR miss cycles 1138system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 50958353731 # number of WriteInvalidateReq MSHR miss cycles 1139system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 3083220248 # number of LoadLockedReq MSHR miss cycles 1140system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3083220248 # number of LoadLockedReq MSHR miss cycles 1141system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 24499 # number of StoreCondReq MSHR miss cycles 1142system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 24499 # number of StoreCondReq MSHR miss cycles 1143system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 187606348146 # number of demand (read+write) MSHR miss cycles 1144system.cpu.dcache.demand_mshr_miss_latency::total 187606348146 # number of demand (read+write) MSHR miss cycles 1145system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 187606348146 # number of overall MSHR miss cycles 1146system.cpu.dcache.overall_mshr_miss_latency::total 187606348146 # number of overall MSHR miss cycles 1147system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5728567000 # number of ReadReq MSHR uncacheable cycles 1148system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5728567000 # number of ReadReq MSHR uncacheable cycles 1149system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 5584485000 # number of WriteReq MSHR uncacheable cycles 1150system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5584485000 # number of WriteReq MSHR uncacheable cycles 1151system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 11313052000 # number of overall MSHR uncacheable cycles 1152system.cpu.dcache.overall_mshr_uncacheable_latency::total 11313052000 # number of overall MSHR uncacheable cycles 1153system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.041163 # mshr miss rate for ReadReq accesses 1154system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041163 # mshr miss rate for ReadReq accesses 1155system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015505 # mshr miss rate for WriteReq accesses 1156system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015505 # mshr miss rate for WriteReq accesses 1157system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.056999 # mshr miss rate for LoadLockedReq accesses 1158system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056999 # mshr miss rate for LoadLockedReq accesses 1159system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for StoreCondReq accesses 1160system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 1161system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.029132 # mshr miss rate for demand accesses 1162system.cpu.dcache.demand_mshr_miss_rate::total 0.029132 # mshr miss rate for demand accesses 1163system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.029132 # mshr miss rate for overall accesses 1164system.cpu.dcache.overall_mshr_miss_rate::total 0.029132 # mshr miss rate for overall accesses 1165system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14309.164392 # average ReadReq mshr miss latency 1166system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14309.164392 # average ReadReq mshr miss latency 1167system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 34423.187611 # average WriteReq mshr miss latency 1168system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34423.187611 # average WriteReq mshr miss latency 1169system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst inf # average WriteInvalidateReq mshr miss latency 1170system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1171system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12470.909013 # average LoadLockedReq mshr miss latency 1172system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.909013 # average LoadLockedReq mshr miss latency 1173system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24499 # average StoreCondReq mshr miss latency 1174system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency 1175system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 19329.223246 # average overall mshr miss latency 1176system.cpu.dcache.demand_avg_mshr_miss_latency::total 19329.223246 # average overall mshr miss latency 1177system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 19329.223246 # average overall mshr miss latency 1178system.cpu.dcache.overall_avg_mshr_miss_latency::total 19329.223246 # average overall mshr miss latency 1179system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1180system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1181system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1182system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1183system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1184system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1185system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1186system.iocache.tags.replacements 115484 # number of replacements 1187system.iocache.tags.tagsinuse 10.452726 # Cycle average of tags in use | 977system.cpu.toL2Bus.trans_dist::ReadReq 34021842 # Transaction distribution 978system.cpu.toL2Bus.trans_dist::ReadResp 34013749 # Transaction distribution 979system.cpu.toL2Bus.trans_dist::WriteReq 33869 # Transaction distribution 980system.cpu.toL2Bus.trans_dist::WriteResp 33869 # Transaction distribution 981system.cpu.toL2Bus.trans_dist::Writeback 8574653 # Transaction distribution 982system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351558 # Transaction distribution 983system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244894 # Transaction distribution 984system.cpu.toL2Bus.trans_dist::UpgradeReq 50067 # Transaction distribution 985system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 986system.cpu.toL2Bus.trans_dist::UpgradeResp 50069 # Transaction distribution 987system.cpu.toL2Bus.trans_dist::ReadExReq 2383072 # Transaction distribution 988system.cpu.toL2Bus.trans_dist::ReadExResp 2383072 # Transaction distribution 989system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49422067 # Packet count per connected master and slave (bytes) 990system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31180667 # Packet count per connected master and slave (bytes) 991system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697225 # Packet count per connected master and slave (bytes) 992system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2277994 # Packet count per connected master and slave (bytes) 993system.cpu.toL2Bus.pkt_count::total 83577953 # Packet count per connected master and slave (bytes) 994system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581505984 # Cumulative packet size per connected master and slave (bytes) 995system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1264852800 # Cumulative packet size per connected master and slave (bytes) 996system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2305528 # Cumulative packet size per connected master and slave (bytes) 997system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7806528 # Cumulative packet size per connected master and slave (bytes) 998system.cpu.toL2Bus.pkt_size::total 2856470840 # Cumulative packet size per connected master and slave (bytes) 999system.cpu.toL2Bus.snoops 563561 # Total snoops (count) 1000system.cpu.toL2Bus.snoop_fanout::samples 46295151 # Request fanout histogram 1001system.cpu.toL2Bus.snoop_fanout::mean 5.002496 # Request fanout histogram 1002system.cpu.toL2Bus.snoop_fanout::stdev 0.049898 # Request fanout histogram 1003system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1004system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1005system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1006system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1007system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1008system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1009system.cpu.toL2Bus.snoop_fanout::5 46179597 99.75% 99.75% # Request fanout histogram 1010system.cpu.toL2Bus.snoop_fanout::6 115554 0.25% 100.00% # Request fanout histogram 1011system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1012system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1013system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1014system.cpu.toL2Bus.snoop_fanout::total 46295151 # Request fanout histogram 1015system.cpu.toL2Bus.reqLayer0.occupancy 32987192886 # Layer occupancy (ticks) 1016system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1017system.cpu.toL2Bus.snoopLayer0.occupancy 1194000 # Layer occupancy (ticks) 1018system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1019system.cpu.toL2Bus.respLayer0.occupancy 37103090732 # Layer occupancy (ticks) 1020system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1021system.cpu.toL2Bus.respLayer1.occupancy 15825165926 # Layer occupancy (ticks) 1022system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1023system.cpu.toL2Bus.respLayer2.occupancy 409755911 # Layer occupancy (ticks) 1024system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1025system.cpu.toL2Bus.respLayer3.occupancy 1302956232 # Layer occupancy (ticks) 1026system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1027system.iobus.trans_dist::ReadReq 40416 # Transaction distribution 1028system.iobus.trans_dist::ReadResp 40416 # Transaction distribution 1029system.iobus.trans_dist::WriteReq 136733 # Transaction distribution 1030system.iobus.trans_dist::WriteResp 30069 # Transaction distribution 1031system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution 1032system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) 1033system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1034system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1035system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1036system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1037system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1038system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1039system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1040system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1041system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1042system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1043system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1044system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1045system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1046system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1047system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) 1048system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231028 # Packet count per connected master and slave (bytes) 1049system.iobus.pkt_count_system.realview.ide.dma::total 231028 # Packet count per connected master and slave (bytes) 1050system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1051system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1052system.iobus.pkt_count::total 354298 # Packet count per connected master and slave (bytes) 1053system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) 1054system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1055system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1056system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1057system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1058system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1059system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1060system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1061system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1062system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1063system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1064system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1065system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1066system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1067system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1068system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) 1069system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334544 # Cumulative packet size per connected master and slave (bytes) 1070system.iobus.pkt_size_system.realview.ide.dma::total 7334544 # Cumulative packet size per connected master and slave (bytes) 1071system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1072system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1073system.iobus.pkt_size::total 7492950 # Cumulative packet size per connected master and slave (bytes) 1074system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) 1075system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1076system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1077system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1078system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 1079system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1080system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 1081system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1082system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1083system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1084system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1085system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1086system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1087system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1088system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1089system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1090system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 1091system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1092system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1093system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1094system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 1095system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1096system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 1097system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1098system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 1099system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1100system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 1101system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1102system.iobus.reqLayer27.occupancy 1042369212 # Layer occupancy (ticks) 1103system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1104system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1105system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1106system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) 1107system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1108system.iobus.respLayer3.occupancy 179072505 # Layer occupancy (ticks) 1109system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1110system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 1111system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1112system.iocache.tags.replacements 115495 # number of replacements 1113system.iocache.tags.tagsinuse 10.448328 # Cycle average of tags in use |
| 1188system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 1114system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 1189system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. | 1115system.iocache.tags.sampled_refs 115511 # Sample count of references to valid blocks. |
| 1190system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 1116system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
| 1191system.iocache.tags.warmup_cycle 13140359698000 # Cycle when the warmup percentage was hit. 1192system.iocache.tags.occ_blocks::realview.ethernet 3.516791 # Average occupied blocks per requestor 1193system.iocache.tags.occ_blocks::realview.ide 6.935936 # Average occupied blocks per requestor 1194system.iocache.tags.occ_percent::realview.ethernet 0.219799 # Average percentage of cache occupancy 1195system.iocache.tags.occ_percent::realview.ide 0.433496 # Average percentage of cache occupancy 1196system.iocache.tags.occ_percent::total 0.653295 # Average percentage of cache occupancy | 1117system.iocache.tags.warmup_cycle 13141221301000 # Cycle when the warmup percentage was hit. 1118system.iocache.tags.occ_blocks::realview.ethernet 3.519405 # Average occupied blocks per requestor 1119system.iocache.tags.occ_blocks::realview.ide 6.928922 # Average occupied blocks per requestor 1120system.iocache.tags.occ_percent::realview.ethernet 0.219963 # Average percentage of cache occupancy 1121system.iocache.tags.occ_percent::realview.ide 0.433058 # Average percentage of cache occupancy 1122system.iocache.tags.occ_percent::total 0.653020 # Average percentage of cache occupancy |
| 1197system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1198system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1199system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1123system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1124system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1125system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1200system.iocache.tags.tag_accesses 1040243 # Number of tag accesses 1201system.iocache.tags.data_accesses 1040243 # Number of data accesses 1202system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits 1203system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits | 1126system.iocache.tags.tag_accesses 1039983 # Number of tag accesses 1127system.iocache.tags.data_accesses 1039983 # Number of data accesses |
| 1204system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 1128system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
| 1205system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses 1206system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses | 1129system.iocache.ReadReq_misses::realview.ide 8850 # number of ReadReq misses 1130system.iocache.ReadReq_misses::total 8887 # number of ReadReq misses |
| 1207system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1208system.iocache.WriteReq_misses::total 3 # number of WriteReq misses | 1131system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1132system.iocache.WriteReq_misses::total 3 # number of WriteReq misses |
| 1209system.iocache.WriteInvalidateReq_misses::realview.ide 46 # number of WriteInvalidateReq misses 1210system.iocache.WriteInvalidateReq_misses::total 46 # number of WriteInvalidateReq misses | 1133system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses 1134system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses |
| 1211system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 1135system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 1212system.iocache.demand_misses::realview.ide 8838 # number of demand (read+write) misses 1213system.iocache.demand_misses::total 8878 # number of demand (read+write) misses | 1136system.iocache.demand_misses::realview.ide 8850 # number of demand (read+write) misses 1137system.iocache.demand_misses::total 8890 # number of demand (read+write) misses |
| 1214system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 1138system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 1215system.iocache.overall_misses::realview.ide 8838 # number of overall misses 1216system.iocache.overall_misses::total 8878 # number of overall misses | 1139system.iocache.overall_misses::realview.ide 8850 # number of overall misses 1140system.iocache.overall_misses::total 8890 # number of overall misses |
| 1217system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles | 1141system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles |
| 1218system.iocache.ReadReq_miss_latency::realview.ide 1936499108 # number of ReadReq miss cycles 1219system.iocache.ReadReq_miss_latency::total 1941984108 # number of ReadReq miss cycles | 1142system.iocache.ReadReq_miss_latency::realview.ide 1921500610 # number of ReadReq miss cycles 1143system.iocache.ReadReq_miss_latency::total 1926985610 # number of ReadReq miss cycles |
| 1220system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles 1221system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles | 1144system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles 1145system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles |
| 1146system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28836803097 # number of WriteInvalidateReq miss cycles 1147system.iocache.WriteInvalidateReq_miss_latency::total 28836803097 # number of WriteInvalidateReq miss cycles |
|
| 1222system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles | 1148system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles |
| 1223system.iocache.demand_miss_latency::realview.ide 1936499108 # number of demand (read+write) miss cycles 1224system.iocache.demand_miss_latency::total 1942323108 # number of demand (read+write) miss cycles | 1149system.iocache.demand_miss_latency::realview.ide 1921500610 # number of demand (read+write) miss cycles 1150system.iocache.demand_miss_latency::total 1927324610 # number of demand (read+write) miss cycles |
| 1225system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles | 1151system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles |
| 1226system.iocache.overall_miss_latency::realview.ide 1936499108 # number of overall miss cycles 1227system.iocache.overall_miss_latency::total 1942323108 # number of overall miss cycles | 1152system.iocache.overall_miss_latency::realview.ide 1921500610 # number of overall miss cycles 1153system.iocache.overall_miss_latency::total 1927324610 # number of overall miss cycles |
| 1228system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 1154system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
| 1229system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) 1230system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) | 1155system.iocache.ReadReq_accesses::realview.ide 8850 # number of ReadReq accesses(hits+misses) 1156system.iocache.ReadReq_accesses::total 8887 # number of ReadReq accesses(hits+misses) |
| 1231system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1232system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) | 1157system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1158system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) |
| 1233system.iocache.WriteInvalidateReq_accesses::realview.ide 106710 # number of WriteInvalidateReq accesses(hits+misses) 1234system.iocache.WriteInvalidateReq_accesses::total 106710 # number of WriteInvalidateReq accesses(hits+misses) | 1159system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) 1160system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) |
| 1235system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 1161system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 1236system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses 1237system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses | 1162system.iocache.demand_accesses::realview.ide 8850 # number of demand (read+write) accesses 1163system.iocache.demand_accesses::total 8890 # number of demand (read+write) accesses |
| 1238system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 1164system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 1239system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses 1240system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses | 1165system.iocache.overall_accesses::realview.ide 8850 # number of overall (read+write) accesses 1166system.iocache.overall_accesses::total 8890 # number of overall (read+write) accesses |
| 1241system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1242system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1243system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1244system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1245system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses | 1167system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1168system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1169system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1170system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1171system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses |
| 1246system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000431 # miss rate for WriteInvalidateReq accesses 1247system.iocache.WriteInvalidateReq_miss_rate::total 0.000431 # miss rate for WriteInvalidateReq accesses | 1172system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1173system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses |
| 1248system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1249system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1250system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1251system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1252system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1253system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1254system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency | 1174system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1175system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1176system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1177system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1178system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1179system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1180system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency |
| 1255system.iocache.ReadReq_avg_miss_latency::realview.ide 219110.557592 # average ReadReq miss latency 1256system.iocache.ReadReq_avg_miss_latency::total 218815.110761 # average ReadReq miss latency | 1181system.iocache.ReadReq_avg_miss_latency::realview.ide 217118.712994 # average ReadReq miss latency 1182system.iocache.ReadReq_avg_miss_latency::total 216831.957916 # average ReadReq miss latency |
| 1257system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency 1258system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency | 1183system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency 1184system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency |
| 1185system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270351.787829 # average WriteInvalidateReq miss latency 1186system.iocache.WriteInvalidateReq_avg_miss_latency::total 270351.787829 # average WriteInvalidateReq miss latency |
|
| 1259system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency | 1187system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency |
| 1260system.iocache.demand_avg_miss_latency::realview.ide 219110.557592 # average overall miss latency 1261system.iocache.demand_avg_miss_latency::total 218779.354359 # average overall miss latency | 1188system.iocache.demand_avg_miss_latency::realview.ide 217118.712994 # average overall miss latency 1189system.iocache.demand_avg_miss_latency::total 216796.919010 # average overall miss latency |
| 1262system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency | 1190system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency |
| 1263system.iocache.overall_avg_miss_latency::realview.ide 219110.557592 # average overall miss latency 1264system.iocache.overall_avg_miss_latency::total 218779.354359 # average overall miss latency 1265system.iocache.blocked_cycles::no_mshrs 53642 # number of cycles access was blocked | 1191system.iocache.overall_avg_miss_latency::realview.ide 217118.712994 # average overall miss latency 1192system.iocache.overall_avg_miss_latency::total 216796.919010 # average overall miss latency 1193system.iocache.blocked_cycles::no_mshrs 224459 # number of cycles access was blocked |
| 1266system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1194system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1267system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked | 1195system.iocache.blocked::no_mshrs 27520 # number of cycles access was blocked |
| 1268system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1196system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1269system.iocache.avg_blocked_cycles::no_mshrs 9.770856 # average number of cycles each access was blocked | 1197system.iocache.avg_blocked_cycles::no_mshrs 8.156214 # average number of cycles each access was blocked |
| 1270system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1198system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1271system.iocache.fast_writes 106664 # number of fast writes performed | 1199system.iocache.fast_writes 0 # number of fast writes performed |
| 1272system.iocache.cache_copies 0 # number of cache copies performed | 1200system.iocache.cache_copies 0 # number of cache copies performed |
| 1201system.iocache.writebacks::writebacks 106630 # number of writebacks 1202system.iocache.writebacks::total 106630 # number of writebacks |
|
| 1273system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses | 1203system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses |
| 1274system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses 1275system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses | 1204system.iocache.ReadReq_mshr_misses::realview.ide 8850 # number of ReadReq MSHR misses 1205system.iocache.ReadReq_mshr_misses::total 8887 # number of ReadReq MSHR misses |
| 1276system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1277system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses | 1206system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1207system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses |
| 1208system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses 1209system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses |
|
| 1278system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 1210system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 1279system.iocache.demand_mshr_misses::realview.ide 8838 # number of demand (read+write) MSHR misses 1280system.iocache.demand_mshr_misses::total 8878 # number of demand (read+write) MSHR misses | 1211system.iocache.demand_mshr_misses::realview.ide 8850 # number of demand (read+write) MSHR misses 1212system.iocache.demand_mshr_misses::total 8890 # number of demand (read+write) MSHR misses |
| 1281system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 1213system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 1282system.iocache.overall_mshr_misses::realview.ide 8838 # number of overall MSHR misses 1283system.iocache.overall_mshr_misses::total 8878 # number of overall MSHR misses | 1214system.iocache.overall_mshr_misses::realview.ide 8850 # number of overall MSHR misses 1215system.iocache.overall_mshr_misses::total 8890 # number of overall MSHR misses |
| 1284system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles | 1216system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles |
| 1285system.iocache.ReadReq_mshr_miss_latency::realview.ide 1476815114 # number of ReadReq MSHR miss cycles 1286system.iocache.ReadReq_mshr_miss_latency::total 1480376114 # number of ReadReq MSHR miss cycles | 1217system.iocache.ReadReq_mshr_miss_latency::realview.ide 1461199612 # number of ReadReq MSHR miss cycles 1218system.iocache.ReadReq_mshr_miss_latency::total 1464760612 # number of ReadReq MSHR miss cycles |
| 1287system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles 1288system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles | 1219system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles 1220system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles |
| 1289system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6530998375 # number of WriteInvalidateReq MSHR miss cycles 1290system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6530998375 # number of WriteInvalidateReq MSHR miss cycles | 1221system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23290267105 # number of WriteInvalidateReq MSHR miss cycles 1222system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23290267105 # number of WriteInvalidateReq MSHR miss cycles |
| 1291system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles | 1223system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles |
| 1292system.iocache.demand_mshr_miss_latency::realview.ide 1476815114 # number of demand (read+write) MSHR miss cycles 1293system.iocache.demand_mshr_miss_latency::total 1480559114 # number of demand (read+write) MSHR miss cycles | 1224system.iocache.demand_mshr_miss_latency::realview.ide 1461199612 # number of demand (read+write) MSHR miss cycles 1225system.iocache.demand_mshr_miss_latency::total 1464943612 # number of demand (read+write) MSHR miss cycles |
| 1294system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles | 1226system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles |
| 1295system.iocache.overall_mshr_miss_latency::realview.ide 1476815114 # number of overall MSHR miss cycles 1296system.iocache.overall_mshr_miss_latency::total 1480559114 # number of overall MSHR miss cycles | 1227system.iocache.overall_mshr_miss_latency::realview.ide 1461199612 # number of overall MSHR miss cycles 1228system.iocache.overall_mshr_miss_latency::total 1464943612 # number of overall MSHR miss cycles |
| 1297system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1298system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1299system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1300system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1301system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses | 1229system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1230system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1231system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1232system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1233system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses |
| 1234system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1235system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses |
|
| 1302system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1303system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1304system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1305system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1306system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1307system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1308system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency | 1236system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1237system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1238system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1239system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1240system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1241system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1242system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency |
| 1309system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167098.338312 # average ReadReq mshr miss latency 1310system.iocache.ReadReq_avg_mshr_miss_latency::total 166802.942423 # average ReadReq mshr miss latency | 1243system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165107.300791 # average ReadReq mshr miss latency 1244system.iocache.ReadReq_avg_mshr_miss_latency::total 164820.593226 # average ReadReq mshr miss latency |
| 1311system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency 1312system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency | 1245system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency 1246system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency |
| 1313system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1314system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency | 1247system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218351.712902 # average WriteInvalidateReq mshr miss latency 1248system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218351.712902 # average WriteInvalidateReq mshr miss latency |
| 1315system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency | 1249system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency |
| 1316system.iocache.demand_avg_mshr_miss_latency::realview.ide 167098.338312 # average overall mshr miss latency 1317system.iocache.demand_avg_mshr_miss_latency::total 166767.190133 # average overall mshr miss latency | 1250system.iocache.demand_avg_mshr_miss_latency::realview.ide 165107.300791 # average overall mshr miss latency 1251system.iocache.demand_avg_mshr_miss_latency::total 164785.558155 # average overall mshr miss latency |
| 1318system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency | 1252system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency |
| 1319system.iocache.overall_avg_mshr_miss_latency::realview.ide 167098.338312 # average overall mshr miss latency 1320system.iocache.overall_avg_mshr_miss_latency::total 166767.190133 # average overall mshr miss latency | 1253system.iocache.overall_avg_mshr_miss_latency::realview.ide 165107.300791 # average overall mshr miss latency 1254system.iocache.overall_avg_mshr_miss_latency::total 164785.558155 # average overall mshr miss latency |
| 1321system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1255system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1256system.membus.trans_dist::ReadReq 549050 # Transaction distribution 1257system.membus.trans_dist::ReadResp 549050 # Transaction distribution 1258system.membus.trans_dist::WriteReq 33869 # Transaction distribution 1259system.membus.trans_dist::WriteResp 33869 # Transaction distribution 1260system.membus.trans_dist::Writeback 1483846 # Transaction distribution 1261system.membus.trans_dist::WriteInvalidateReq 650746 # Transaction distribution 1262system.membus.trans_dist::WriteInvalidateResp 650746 # Transaction distribution 1263system.membus.trans_dist::UpgradeReq 39985 # Transaction distribution 1264system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1265system.membus.trans_dist::UpgradeResp 39987 # Transaction distribution 1266system.membus.trans_dist::ReadExReq 712642 # Transaction distribution 1267system.membus.trans_dist::ReadExResp 712642 # Transaction distribution 1268system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) 1269system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1270system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6920 # Packet count per connected master and slave (bytes) 1271system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4987889 # Packet count per connected master and slave (bytes) 1272system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5118031 # Packet count per connected master and slave (bytes) 1273system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335345 # Packet count per connected master and slave (bytes) 1274system.membus.pkt_count_system.iocache.mem_side::total 335345 # Packet count per connected master and slave (bytes) 1275system.membus.pkt_count::total 5453376 # Packet count per connected master and slave (bytes) 1276system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) 1277system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1278system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13840 # Cumulative packet size per connected master and slave (bytes) 1279system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 200958508 # Cumulative packet size per connected master and slave (bytes) 1280system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201129408 # Cumulative packet size per connected master and slave (bytes) 1281system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066624 # Cumulative packet size per connected master and slave (bytes) 1282system.membus.pkt_size_system.iocache.mem_side::total 14066624 # Cumulative packet size per connected master and slave (bytes) 1283system.membus.pkt_size::total 215196032 # Cumulative packet size per connected master and slave (bytes) 1284system.membus.snoops 3058 # Total snoops (count) 1285system.membus.snoop_fanout::samples 3350229 # Request fanout histogram 1286system.membus.snoop_fanout::mean 1 # Request fanout histogram 1287system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1288system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1289system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1290system.membus.snoop_fanout::1 3350229 100.00% 100.00% # Request fanout histogram 1291system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1292system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1293system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1294system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1295system.membus.snoop_fanout::total 3350229 # Request fanout histogram 1296system.membus.reqLayer0.occupancy 113834500 # Layer occupancy (ticks) 1297system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1298system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) 1299system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1300system.membus.reqLayer2.occupancy 5697498 # Layer occupancy (ticks) 1301system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1302system.membus.reqLayer5.occupancy 21359860992 # Layer occupancy (ticks) 1303system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1304system.membus.respLayer2.occupancy 12431404244 # Layer occupancy (ticks) 1305system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1306system.membus.respLayer3.occupancy 186704495 # Layer occupancy (ticks) 1307system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1308system.realview.ethernet.txBytes 966 # Bytes Transmitted 1309system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1310system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1311system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1312system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1313system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1314system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1315system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1316system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1317system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 1318system.realview.ethernet.totPackets 3 # Total Packets 1319system.realview.ethernet.totBytes 966 # Total Bytes 1320system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1321system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 1322system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1323system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1324system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1325system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1326system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1327system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1328system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1329system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1330system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1331system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1332system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1333system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1334system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1335system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1336system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1337system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1338system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1339system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1340system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1341system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1342system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1343system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1344system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1345system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1346system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1347system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1348system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1349system.realview.ethernet.droppedPackets 0 # number of packets dropped |
|
| 1322 1323---------- End Simulation Statistics ---------- | 1350 1351---------- End Simulation Statistics ---------- |