Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

Deleted Added

sdiff udiff text old ( 11687:b3d5f0e9e258 ) new ( 11754:c209cb86278a )

full compact

3,5c3,5
< sim_seconds 51.688775 # Number of seconds simulated
< sim_ticks 51688774990000 # Number of ticks simulated
< final_tick 51688774990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 51.688741 # Number of seconds simulated
> sim_ticks 51688741391000 # Number of ticks simulated
> final_tick 51688741391000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 278192 # Simulator instruction rate (inst/s)
< host_op_rate 326870 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 15185295340 # Simulator tick rate (ticks/s)
< host_mem_usage 686764 # Number of bytes of host memory used
< host_seconds 3403.87 # Real time elapsed on the host
< sim_insts 946928269 # Number of instructions simulated
< sim_ops 1112623169 # Number of ops (including micro ops) simulated
---
> host_inst_rate 269524 # Simulator instruction rate (inst/s)
> host_op_rate 316717 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 14692427127 # Simulator tick rate (ticks/s)
> host_mem_usage 686428 # Number of bytes of host memory used
> host_seconds 3518.05 # Real time elapsed on the host
> sim_insts 948199503 # Number of instructions simulated
> sim_ops 1114227092 # Number of ops (including micro ops) simulated
16,25c16,25
< system.physmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.dtb.walker 401472 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 331520 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 10196544 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 65400968 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 425152 # Number of bytes read from this memory
< system.physmem.bytes_read::total 76755656 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 10196544 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 10196544 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 93615936 # Number of bytes written to this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.dtb.walker 396416 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 330752 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 10254464 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 65885128 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 402816 # Number of bytes read from this memory
> system.physmem.bytes_read::total 77269576 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 10254464 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 10254464 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 94159808 # Number of bytes written to this memory
27,34c27,34
< system.physmem.bytes_written::total 93636516 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 6273 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 5180 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 159321 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1021903 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6643 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1199320 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1462749 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 94180388 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 6194 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 5168 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 160226 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1029468 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6294 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1207350 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1471247 # Number of write requests responded to by this memory
36,45c36,45
< system.physmem.num_writes::total 1465322 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 7767 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 6414 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 197268 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1265284 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 8225 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1484958 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 197268 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 197268 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1811146 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1473820 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 7669 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 6399 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 198389 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1274651 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 7793 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1494901 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 198389 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 198389 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1821670 # Write bandwidth from this memory (bytes/s)
47,64c47,64
< system.physmem.bw_write::total 1811544 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1811146 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 7767 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 6414 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 197268 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1265682 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 8225 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3296502 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1199320 # Number of read requests accepted
< system.physmem.writeReqs 1465322 # Number of write requests accepted
< system.physmem.readBursts 1199320 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1465322 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 76712512 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 43968 # Total number of bytes read from write queue
< system.physmem.bytesWritten 93634496 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 76755656 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 93636516 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 687 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_write::total 1822068 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1821670 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 7669 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 6399 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 198389 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1275050 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 7793 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3316969 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1207350 # Number of read requests accepted
> system.physmem.writeReqs 1473820 # Number of write requests accepted
> system.physmem.readBursts 1207350 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1473820 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 77222592 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 47808 # Total number of bytes read from write queue
> system.physmem.bytesWritten 94178368 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 77269576 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 94180388 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 747 # Number of DRAM read bursts serviced by the write queue
67,98c67,98
< system.physmem.perBankRdBursts::0 70144 # Per bank write bursts
< system.physmem.perBankRdBursts::1 74650 # Per bank write bursts
< system.physmem.perBankRdBursts::2 68418 # Per bank write bursts
< system.physmem.perBankRdBursts::3 68145 # Per bank write bursts
< system.physmem.perBankRdBursts::4 72367 # Per bank write bursts
< system.physmem.perBankRdBursts::5 76479 # Per bank write bursts
< system.physmem.perBankRdBursts::6 68140 # Per bank write bursts
< system.physmem.perBankRdBursts::7 71247 # Per bank write bursts
< system.physmem.perBankRdBursts::8 66581 # Per bank write bursts
< system.physmem.perBankRdBursts::9 125666 # Per bank write bursts
< system.physmem.perBankRdBursts::10 74635 # Per bank write bursts
< system.physmem.perBankRdBursts::11 76739 # Per bank write bursts
< system.physmem.perBankRdBursts::12 72169 # Per bank write bursts
< system.physmem.perBankRdBursts::13 75530 # Per bank write bursts
< system.physmem.perBankRdBursts::14 66172 # Per bank write bursts
< system.physmem.perBankRdBursts::15 71551 # Per bank write bursts
< system.physmem.perBankWrBursts::0 89120 # Per bank write bursts
< system.physmem.perBankWrBursts::1 91694 # Per bank write bursts
< system.physmem.perBankWrBursts::2 88427 # Per bank write bursts
< system.physmem.perBankWrBursts::3 87889 # Per bank write bursts
< system.physmem.perBankWrBursts::4 92386 # Per bank write bursts
< system.physmem.perBankWrBursts::5 94711 # Per bank write bursts
< system.physmem.perBankWrBursts::6 88472 # Per bank write bursts
< system.physmem.perBankWrBursts::7 91239 # Per bank write bursts
< system.physmem.perBankWrBursts::8 88274 # Per bank write bursts
< system.physmem.perBankWrBursts::9 94990 # Per bank write bursts
< system.physmem.perBankWrBursts::10 92874 # Per bank write bursts
< system.physmem.perBankWrBursts::11 94799 # Per bank write bursts
< system.physmem.perBankWrBursts::12 93039 # Per bank write bursts
< system.physmem.perBankWrBursts::13 95949 # Per bank write bursts
< system.physmem.perBankWrBursts::14 87664 # Per bank write bursts
< system.physmem.perBankWrBursts::15 91512 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 73856 # Per bank write bursts
> system.physmem.perBankRdBursts::1 76732 # Per bank write bursts
> system.physmem.perBankRdBursts::2 71137 # Per bank write bursts
> system.physmem.perBankRdBursts::3 69219 # Per bank write bursts
> system.physmem.perBankRdBursts::4 73839 # Per bank write bursts
> system.physmem.perBankRdBursts::5 75948 # Per bank write bursts
> system.physmem.perBankRdBursts::6 69505 # Per bank write bursts
> system.physmem.perBankRdBursts::7 70913 # Per bank write bursts
> system.physmem.perBankRdBursts::8 66486 # Per bank write bursts
> system.physmem.perBankRdBursts::9 126372 # Per bank write bursts
> system.physmem.perBankRdBursts::10 74130 # Per bank write bursts
> system.physmem.perBankRdBursts::11 75275 # Per bank write bursts
> system.physmem.perBankRdBursts::12 69111 # Per bank write bursts
> system.physmem.perBankRdBursts::13 75650 # Per bank write bursts
> system.physmem.perBankRdBursts::14 65166 # Per bank write bursts
> system.physmem.perBankRdBursts::15 73264 # Per bank write bursts
> system.physmem.perBankWrBursts::0 92929 # Per bank write bursts
> system.physmem.perBankWrBursts::1 92717 # Per bank write bursts
> system.physmem.perBankWrBursts::2 91280 # Per bank write bursts
> system.physmem.perBankWrBursts::3 89601 # Per bank write bursts
> system.physmem.perBankWrBursts::4 92792 # Per bank write bursts
> system.physmem.perBankWrBursts::5 94531 # Per bank write bursts
> system.physmem.perBankWrBursts::6 90574 # Per bank write bursts
> system.physmem.perBankWrBursts::7 91937 # Per bank write bursts
> system.physmem.perBankWrBursts::8 87601 # Per bank write bursts
> system.physmem.perBankWrBursts::9 94297 # Per bank write bursts
> system.physmem.perBankWrBursts::10 91232 # Per bank write bursts
> system.physmem.perBankWrBursts::11 93669 # Per bank write bursts
> system.physmem.perBankWrBursts::12 91213 # Per bank write bursts
> system.physmem.perBankWrBursts::13 96164 # Per bank write bursts
> system.physmem.perBankWrBursts::14 87189 # Per bank write bursts
> system.physmem.perBankWrBursts::15 93811 # Per bank write bursts
100,101c100,101
< system.physmem.numWrRetry 468 # Number of times write queue was full causing retry
< system.physmem.totGap 51688773130000 # Total gap between requests
---
> system.physmem.numWrRetry 476 # Number of times write queue was full causing retry
> system.physmem.totGap 51688739531000 # Total gap between requests
108c108
< system.physmem.readPktSize::6 1199305 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1207335 # Read request sizes (log2)
115,136c115,136
< system.physmem.writePktSize::6 1462749 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1127245 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 64919 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 779 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 491 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 476 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 609 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 509 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1056 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 628 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 296 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 301 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 207 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 165 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1471247 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1136082 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 64384 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 825 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 489 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 447 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 571 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 478 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 974 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 532 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 276 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 271 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 74 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
163,230c163,229
< system.physmem.wrQLenPdf::15 29655 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 37473 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 78822 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 84952 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 87044 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 83743 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 88388 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 87662 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 88784 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 85626 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 88571 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 89853 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 87229 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 84323 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 82904 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 81964 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 79861 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 79771 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 2782 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 2400 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 2080 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 1918 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 1552 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1400 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1354 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 1254 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1171 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1114 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 996 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 968 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 849 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 803 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 723 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 703 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 853 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 763 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 689 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 985 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 920 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 1056 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 910 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 634 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 1027 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 1982 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 1362 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 537 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 1066 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 662940 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 256.956322 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 154.084684 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 293.850288 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 284383 42.90% 42.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 170705 25.75% 68.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 61081 9.21% 77.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 33561 5.06% 82.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 23575 3.56% 86.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 15515 2.34% 88.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 11286 1.70% 90.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 9362 1.41% 91.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 53472 8.07% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 662940 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 77129 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 15.540445 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 141.912078 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 77126 100.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 29717 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 37973 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 79220 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 85555 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 88116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 84810 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 88690 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 87321 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 89133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 85642 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 88726 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 90107 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 87724 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 84525 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 83639 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 82667 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 80351 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 80396 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 2860 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 2434 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 2158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 1987 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 1580 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 1469 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1363 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 1367 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1224 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1052 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1108 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 913 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 831 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 764 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 795 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 922 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 870 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 856 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 796 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 769 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 1121 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 874 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 726 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 1082 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 1526 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 1562 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 596 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 1031 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 665465 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 257.565125 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 154.597276 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 293.769616 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 284377 42.73% 42.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 171033 25.70% 68.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 61820 9.29% 77.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 34355 5.16% 82.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 24207 3.64% 86.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 15228 2.29% 88.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 11511 1.73% 90.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 9122 1.37% 91.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 53812 8.09% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 665465 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 77525 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 15.563805 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 141.518145 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 77523 100.00% 100.00% # Reads before turning the bus around for writes
233,271c232,270
< system.physmem.rdPerTurnAround::total 77129 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 77129 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 18.968728 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.139558 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 8.416384 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 64621 83.78% 83.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 3761 4.88% 88.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 3195 4.14% 92.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 2420 3.14% 95.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 1145 1.48% 97.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 346 0.45% 97.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 199 0.26% 98.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 173 0.22% 98.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 112 0.15% 98.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 62 0.08% 98.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 79 0.10% 98.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 69 0.09% 98.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 561 0.73% 99.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 77 0.10% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 111 0.14% 99.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 54 0.07% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 32 0.04% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 4 0.01% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 3 0.00% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 3 0.00% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 2 0.00% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.00% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 3 0.00% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 13 0.02% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 7 0.01% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 2 0.00% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 3 0.00% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 17 0.02% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 5 0.01% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 4 0.01% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 12 0.02% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 5 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 77525 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 77525 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 18.981451 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.132244 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 8.585951 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 65037 83.89% 83.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 3875 5.00% 88.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 3091 3.99% 92.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 2418 3.12% 96.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 1125 1.45% 97.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 202 0.26% 97.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 259 0.33% 98.04% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 156 0.20% 98.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 148 0.19% 98.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 64 0.08% 98.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 86 0.11% 98.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 78 0.10% 98.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 560 0.72% 99.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 82 0.11% 99.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 101 0.13% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 77 0.10% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 43 0.06% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 5 0.01% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 4 0.01% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 3 0.00% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 3 0.00% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 2 0.00% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 4 0.01% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 18 0.02% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 5 0.01% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 1 0.00% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 7 0.01% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 20 0.03% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 6 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 10 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 6 0.01% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads
272a272
> system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads
274,283c274,285
< system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 3 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-195 12 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 77129 # Writes before turning the bus around for reads
< system.physmem.totQLat 38956691672 # Total ticks spent queuing
< system.physmem.totMemAccLat 61431060422 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 5993165000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 32500.93 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::172-175 3 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 3 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 8 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::212-215 2 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 77525 # Writes before turning the bus around for reads
> system.physmem.totQLat 38963077638 # Total ticks spent queuing
> system.physmem.totMemAccLat 61586883888 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 6033015000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 32291.55 # Average queueing delay per DRAM burst
285,289c287,291
< system.physmem.avgMemAccLat 51250.93 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 51041.55 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s
295,340c297,342
< system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing
< system.physmem.readRowHits 929087 # Number of row buffer hits during reads
< system.physmem.writeRowHits 1069644 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 73.11 # Row buffer hit rate for writes
< system.physmem.avgGap 19398017.87 # Average gap between requests
< system.physmem.pageHitRate 75.09 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 2341677240 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1244627175 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 4066872600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3778956360 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 50725624560.000008 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 43528474080 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 3238135680 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 96319832910 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 74142648000 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 12293580495315 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 12572988857670 # Total energy per rank (pJ)
< system.physmem_0.averagePower 243.244086 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 51584838283234 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 6009063000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 21570724000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 51180529926500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 193079953190 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 76356875016 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 211228448294 # Time in different power states
< system.physmem_1.actEnergy 2391721500 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1271230125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 4491367020 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3858107220 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 51763751520.000015 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 44789626440 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 3183541920 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 99591324540 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 75005755680 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 12290774240265 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 12577142748300 # Total energy per rank (pJ)
< system.physmem_1.averagePower 243.324450 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 51582206485554 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 5783812250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 22010710000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 51168482999000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 195327455894 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 78768252696 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 218401760160 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgWrQLen 27.17 # Average write queue length when enqueuing
> system.physmem.readRowHits 937085 # Number of row buffer hits during reads
> system.physmem.writeRowHits 1075589 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 77.66 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 73.09 # Row buffer hit rate for writes
> system.physmem.avgGap 19278426.78 # Average gap between requests
> system.physmem.pageHitRate 75.15 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 2387508900 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1268991075 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 4149403860 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 3843804420 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 50777254320.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 43920274980 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 3215166720 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 97172465130 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 73954032000 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 12292934061825 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 12573646841220 # Total energy per rank (pJ)
> system.physmem_0.averagePower 243.256974 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 51583978414040 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 5941628250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 21591460000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 51178312983500 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 192588592528 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 77208837210 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 213097889512 # Time in different power states
> system.physmem_1.actEnergy 2363918340 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1256448600 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 4465741560 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3837618720 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 51996700080.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 45282427920 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 3208431840 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 99358559340 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 75199350240 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 12290630942340 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 12577622785650 # Total energy per rank (pJ)
> system.physmem_1.averagePower 243.333895 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 51581032449783 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 5840657750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 22110720000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 51167308964000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 195831815407 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 79757518717 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 217891715126 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
357,359c359,361
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
366,370c368,372
< system.cpu.branchPred.lookups 261505306 # Number of BP lookups
< system.cpu.branchPred.condPredicted 182498706 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 12291836 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 192874347 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 130159045 # Number of BTB hits
---
> system.cpu.branchPred.lookups 261998834 # Number of BP lookups
> system.cpu.branchPred.condPredicted 182856277 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 12304668 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 193336179 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 130354436 # Number of BTB hits
372,378c374,380
< system.cpu.branchPred.BTBHitPct 67.483855 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 31722667 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 2144910 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 7175659 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 5109497 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 2066162 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 844099 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 67.423716 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 31812925 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 2139415 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 7174940 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 5106056 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 2068884 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 846506 # Number of mispredicted indirect branches.
380c382
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
410,433c412,435
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.walks 574319 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 574319 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21733 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksLongTerminationLevel::Level3 190269 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 574319 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 574319 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 574319 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 212002 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 25745.962302 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 21834.815515 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 18121.324193 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-65535 209468 98.80% 98.80% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-131071 2131 1.01% 99.81% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-196607 103 0.05% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::196608-262143 132 0.06% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::262144-327679 91 0.04% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-458751 12 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::589824-655359 29 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 212002 # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.walks 578626 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 578626 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22326 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksLongTerminationLevel::Level3 190823 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 578626 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 578626 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 578626 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 213149 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 25594.731854 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 21754.484647 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 18075.189624 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-65535 210684 98.84% 98.84% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-131071 2067 0.97% 99.81% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-196607 93 0.04% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::196608-262143 125 0.06% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-327679 100 0.05% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.02% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::589824-655359 34 0.02% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 213149 # Table walker service (enqueue to completion) latency
437,440c439,442
< system.cpu.dtb.walker.walkPageSizes::4K 190270 89.75% 89.75% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::2M 21733 10.25% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 212003 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 574319 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkPageSizes::4K 190824 89.53% 89.53% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::2M 22326 10.47% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 213150 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 578626 # Table walker requests started/completed, data/inst
442,443c444,445
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 574319 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 212003 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 578626 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213150 # Table walker requests started/completed, data/inst
445,446c447,448
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 212003 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 786322 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213150 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 791776 # Table walker requests started/completed, data/inst
449,452c451,454
< system.cpu.dtb.read_hits 182769858 # DTB read hits
< system.cpu.dtb.read_misses 473161 # DTB read misses
< system.cpu.dtb.write_hits 162201881 # DTB write hits
< system.cpu.dtb.write_misses 101158 # DTB write misses
---
> system.cpu.dtb.read_hits 182986827 # DTB read hits
> system.cpu.dtb.read_misses 476580 # DTB read misses
> system.cpu.dtb.write_hits 162437421 # DTB write hits
> system.cpu.dtb.write_misses 102046 # DTB write misses
455,459c457,461
< system.cpu.dtb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID
< system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID
< system.cpu.dtb.flush_entries 79796 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 1477 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 15505 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_tlb_mva_asid 47208 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID
> system.cpu.dtb.flush_entries 80100 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 1397 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 15136 # Number of TLB faults due to prefetch
461,463c463,465
< system.cpu.dtb.perms_faults 23270 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 183243019 # DTB read accesses
< system.cpu.dtb.write_accesses 162303039 # DTB write accesses
---
> system.cpu.dtb.perms_faults 23302 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 183463407 # DTB read accesses
> system.cpu.dtb.write_accesses 162539467 # DTB write accesses
465,468c467,470
< system.cpu.dtb.hits 344971739 # DTB hits
< system.cpu.dtb.misses 574319 # DTB misses
< system.cpu.dtb.accesses 345546058 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.hits 345424248 # DTB hits
> system.cpu.dtb.misses 578626 # DTB misses
> system.cpu.dtb.accesses 346002874 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
498,521c500,523
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.walks 135751 # Table walker walks requested
< system.cpu.itb.walker.walksLong 135751 # Table walker walks initiated with long descriptors
< system.cpu.itb.walker.walksLongTerminationLevel::Level2 1056 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksLongTerminationLevel::Level3 117755 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walkWaitTime::samples 135751 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 135751 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 135751 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 118811 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 28810.606762 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 24143.293111 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 28291.561253 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-65535 115975 97.61% 97.61% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::65536-131071 2399 2.02% 99.63% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::131072-196607 123 0.10% 99.74% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::262144-327679 44 0.04% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::589824-655359 141 0.12% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 118811 # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.walks 136092 # Table walker walks requested
> system.cpu.itb.walker.walksLong 136092 # Table walker walks initiated with long descriptors
> system.cpu.itb.walker.walksLongTerminationLevel::Level2 1064 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksLongTerminationLevel::Level3 118204 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walkWaitTime::samples 136092 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 136092 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 136092 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 119268 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 28638.176208 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 24049.001367 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 28797.920728 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-65535 116455 97.64% 97.64% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::65536-131071 2388 2.00% 99.64% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-196607 112 0.09% 99.74% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::196608-262143 99 0.08% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.84% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::327680-393215 23 0.02% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::393216-458751 4 0.00% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::589824-655359 153 0.13% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 119268 # Table walker service (enqueue to completion) latency
525,527c527,529
< system.cpu.itb.walker.walkPageSizes::4K 117755 99.11% 99.11% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::2M 1056 0.89% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 118811 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkPageSizes::4K 118204 99.11% 99.11% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::2M 1064 0.89% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 119268 # Table walker page sizes translated
529,530c531,532
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135751 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 135751 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136092 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 136092 # Table walker requests started/completed, data/inst
532,536c534,538
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118811 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 118811 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 254562 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 452655900 # ITB inst hits
< system.cpu.itb.inst_misses 135751 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119268 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 119268 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 255360 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 453450761 # ITB inst hits
> system.cpu.itb.inst_misses 136092 # ITB inst misses
543,545c545,547
< system.cpu.itb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID
< system.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID
< system.cpu.itb.flush_entries 57242 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_tlb_mva_asid 47208 # Number of times TLB was flushed by MVA & ASID
> system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID
> system.cpu.itb.flush_entries 57496 # Number of entries that have been flushed from TLB
549c551
< system.cpu.itb.perms_faults 322846 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 333218 # Number of TLB faults due to permissions restrictions
552,561c554,563
< system.cpu.itb.inst_accesses 452791651 # ITB inst accesses
< system.cpu.itb.hits 452655900 # DTB hits
< system.cpu.itb.misses 135751 # DTB misses
< system.cpu.itb.accesses 452791651 # DTB accesses
< system.cpu.numPwrStateTransitions 33180 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 16590 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 3039388324.246233 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 59640903157.908096 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::underflows 7293 43.96% 43.96% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1000-5e+10 9262 55.83% 99.79% # Distribution of time spent in the clock gated state
---
> system.cpu.itb.inst_accesses 453586853 # ITB inst accesses
> system.cpu.itb.hits 453450761 # DTB hits
> system.cpu.itb.misses 136092 # DTB misses
> system.cpu.itb.accesses 453586853 # DTB accesses
> system.cpu.numPwrStateTransitions 33202 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 16601 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 3037201042.152340 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 59610606886.622597 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::underflows 7303 43.99% 43.99% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1000-5e+10 9263 55.80% 99.79% # Distribution of time spent in the clock gated state
573,577c575,579
< system.cpu.pwrStateClkGateDist::max_value 1988777698120 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::total 16590 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 1265322690755 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 50423452299245 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 2530699433 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::max_value 1988777738856 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::total 16601 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 1268166890229 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 50420574500771 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 2536387791 # number of cpu cycles simulated
580,586c582,588
< system.cpu.committedInsts 946928269 # Number of instructions committed
< system.cpu.committedOps 1112623169 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 97851669 # Number of ops (including micro ops) which were discarded before commit
< system.cpu.numFetchSuspends 7730 # Number of times Execute suspended instruction fetching
< system.cpu.quiesceCycles 100847957157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.672536 # CPI: cycles per instruction
< system.cpu.ipc 0.374177 # IPC: instructions per cycle
---
> system.cpu.committedInsts 948199503 # Number of instructions committed
> system.cpu.committedOps 1114227092 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 98303819 # Number of ops (including micro ops) which were discarded before commit
> system.cpu.numFetchSuspends 7741 # Number of times Execute suspended instruction fetching
> system.cpu.quiesceCycles 100842203450 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.674952 # CPI: cycles per instruction
> system.cpu.ipc 0.373839 # IPC: instructions per cycle
588,590c590,592
< system.cpu.op_class_0::IntAlu 771151081 69.31% 69.31% # Class of committed instruction
< system.cpu.op_class_0::IntMult 2302642 0.21% 69.52% # Class of committed instruction
< system.cpu.op_class_0::IntDiv 99189 0.01% 69.53% # Class of committed instruction
---
> system.cpu.op_class_0::IntAlu 772296777 69.31% 69.31% # Class of committed instruction
> system.cpu.op_class_0::IntMult 2306158 0.21% 69.52% # Class of committed instruction
> system.cpu.op_class_0::IntDiv 98958 0.01% 69.53% # Class of committed instruction
597,622c599,624
< system.cpu.op_class_0::FloatMisc 108989 0.01% 69.53% # Class of committed instruction
< system.cpu.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatAdd 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatCmp 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatCvt 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMisc 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction
< system.cpu.op_class_0::MemRead 177200146 15.93% 85.46% # Class of committed instruction
< system.cpu.op_class_0::MemWrite 160983743 14.47% 99.93% # Class of committed instruction
< system.cpu.op_class_0::FloatMemRead 112460 0.01% 99.94% # Class of committed instruction
< system.cpu.op_class_0::FloatMemWrite 664876 0.06% 100.00% # Class of committed instruction
---
> system.cpu.op_class_0::FloatMisc 108924 0.01% 69.54% # Class of committed instruction
> system.cpu.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAdd 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCmp 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCvt 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMisc 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction
> system.cpu.op_class_0::MemRead 177418599 15.92% 85.46% # Class of committed instruction
> system.cpu.op_class_0::MemWrite 161212850 14.47% 99.93% # Class of committed instruction
> system.cpu.op_class_0::FloatMemRead 115060 0.01% 99.94% # Class of committed instruction
> system.cpu.op_class_0::FloatMemWrite 669723 0.06% 100.00% # Class of committed instruction
625c627
< system.cpu.op_class_0::total 1112623169 # Class of committed instruction
---
> system.cpu.op_class_0::total 1114227092 # Class of committed instruction
627,635c629,637
< system.cpu.kern.inst.quiesce 16590 # number of quiesce instructions executed
< system.cpu.tickCycles 1791525295 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 739174138 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 11091024 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.954083 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 329234475 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 11091536 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 29.683398 # Average number of references to valid blocks.
---
> system.cpu.kern.inst.quiesce 16601 # number of quiesce instructions executed
> system.cpu.tickCycles 1794953387 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 741434404 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 11118153 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.954086 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 329643971 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 11118665 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 29.647801 # Average number of references to valid blocks.
637c639
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.954083 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.954086 # Average occupied blocks per requestor
641,643c643,646
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
645,673c648,676
< system.cpu.dcache.tags.tag_accesses 1381544711 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1381544711 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 168600534 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 168600534 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 151416750 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 151416750 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 521238 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 521238 # number of SoftPFReq hits
< system.cpu.dcache.WriteLineReq_hits::cpu.data 337307 # number of WriteLineReq hits
< system.cpu.dcache.WriteLineReq_hits::total 337307 # number of WriteLineReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 4005998 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 4005998 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 4318996 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 4318996 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 320354591 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 320354591 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 320875829 # number of overall hits
< system.cpu.dcache.overall_hits::total 320875829 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 6093036 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 6093036 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 4287792 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 4287792 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 1473735 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 1473735 # number of SoftPFReq misses
< system.cpu.dcache.WriteLineReq_misses::cpu.data 1243168 # number of WriteLineReq misses
< system.cpu.dcache.WriteLineReq_misses::total 1243168 # number of WriteLineReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 314729 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 314729 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 1383364255 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1383364255 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 168779255 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 168779255 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 151620030 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 151620030 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 521599 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 521599 # number of SoftPFReq hits
> system.cpu.dcache.WriteLineReq_hits::cpu.data 337919 # number of WriteLineReq hits
> system.cpu.dcache.WriteLineReq_hits::total 337919 # number of WriteLineReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 4018497 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 4018497 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 4332994 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 4332994 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 320737204 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 320737204 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 321258803 # number of overall hits
> system.cpu.dcache.overall_hits::total 321258803 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 6105244 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 6105244 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 4304073 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 4304073 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 1482683 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 1482683 # number of SoftPFReq misses
> system.cpu.dcache.WriteLineReq_misses::cpu.data 1242865 # number of WriteLineReq misses
> system.cpu.dcache.WriteLineReq_misses::total 1242865 # number of WriteLineReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 316228 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 316228 # number of LoadLockedReq misses
676,687c679,690
< system.cpu.dcache.demand_misses::cpu.data 11623996 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 11623996 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 13097731 # number of overall misses
< system.cpu.dcache.overall_misses::total 13097731 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 107249746000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 107249746000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 169106972500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 169106972500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27289591000 # number of WriteLineReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::total 27289591000 # number of WriteLineReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5063641000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 5063641000 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 11652182 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 11652182 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 13134865 # number of overall misses
> system.cpu.dcache.overall_misses::total 13134865 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 107444842500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 107444842500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 170230992500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 170230992500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27308613500 # number of WriteLineReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::total 27308613500 # number of WriteLineReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5074922000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 5074922000 # number of LoadLockedReq miss cycles
690,719c693,722
< system.cpu.dcache.demand_miss_latency::cpu.data 303646309500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 303646309500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 303646309500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 303646309500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 174693570 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 174693570 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 155704542 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 155704542 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 1994973 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 1994973 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::cpu.data 1580475 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::total 1580475 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4320727 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 4320727 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 4318997 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 4318997 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 331978587 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 331978587 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 333973560 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 333973560 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034878 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.034878 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027538 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.027538 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738724 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.738724 # miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786579 # miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::total 0.786579 # miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072842 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.072842 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_miss_latency::cpu.data 304984448500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 304984448500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 304984448500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 304984448500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 174884499 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 174884499 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 155924103 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 155924103 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2004282 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2004282 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::cpu.data 1580784 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::total 1580784 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4334725 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 4334725 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 4332995 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 4332995 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 332389386 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 332389386 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 334393668 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 334393668 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034910 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.034910 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027604 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.027604 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.739758 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.739758 # miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786233 # miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::total 0.786233 # miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072952 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.072952 # miss rate for LoadLockedReq accesses
722,733c725,736
< system.cpu.dcache.demand_miss_rate::cpu.data 0.035014 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.035014 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.039218 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.039218 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17602.020733 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 17602.020733 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39439.173472 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 39439.173472 # average WriteReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21951.651748 # average WriteLineReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21951.651748 # average WriteLineReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16088.892349 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16088.892349 # average LoadLockedReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.035056 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.035056 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.039280 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.039280 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.779426 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.779426 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39551.139700 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 39551.139700 # average WriteReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21972.308738 # average WriteLineReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21972.308738 # average WriteLineReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16048.300593 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16048.300593 # average LoadLockedReq miss latency
736,740c739,743
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.368719 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 26122.368719 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 23183.123054 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 23183.123054 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 26174.020325 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 26174.020325 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 23219.458175 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 23219.458175 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked
744c747
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 19 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked
746,769c749,772
< system.cpu.dcache.writebacks::writebacks 8512101 # number of writebacks
< system.cpu.dcache.writebacks::total 8512101 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 311042 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 311042 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1897692 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1897692 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::total 152 # number of WriteLineReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70889 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 70889 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2208886 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2208886 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2208886 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2208886 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5781994 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 5781994 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2390100 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2390100 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1466271 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 1466271 # number of SoftPFReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1243016 # number of WriteLineReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::total 1243016 # number of WriteLineReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 243840 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 243840 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 8530547 # number of writebacks
> system.cpu.dcache.writebacks::total 8530547 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 315482 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 315482 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1904891 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1904891 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 158 # number of WriteLineReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::total 158 # number of WriteLineReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70720 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 70720 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2220531 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2220531 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2220531 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2220531 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5789762 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 5789762 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2399182 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2399182 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1475215 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 1475215 # number of SoftPFReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1242707 # number of WriteLineReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::total 1242707 # number of WriteLineReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 245508 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 245508 # number of LoadLockedReq MSHR misses
772,775c775,778
< system.cpu.dcache.demand_mshr_misses::cpu.data 9415110 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 9415110 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 10881381 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 10881381 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 9431651 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 9431651 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 10906866 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 10906866 # number of overall MSHR misses
782,791c785,794
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 94763834000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 94763834000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88482137000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 88482137000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 25605238500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 25605238500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26041674000 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26041674000 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3459340500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3459340500 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 94938379000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 94938379000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89047691000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 89047691000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 25686251500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 25686251500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26061179000 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26061179000 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3474287500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3474287500 # number of LoadLockedReq MSHR miss cycles
794,811c797,814
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 209287645000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 209287645000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 234892883500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 234892883500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231136500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231136500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231136500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 6231136500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033098 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033098 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015350 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015350 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734983 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734983 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786483 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786483 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056435 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056435 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 210047249000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 210047249000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 235733500500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 235733500500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6230847500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6230847500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6230847500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6230847500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033106 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033106 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015387 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015387 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.736032 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.736032 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786133 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786133 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056638 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056638 # mshr miss rate for LoadLockedReq accesses
814,827c817,830
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028361 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.028361 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032582 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.032582 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16389.472905 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16389.472905 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37020.265679 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37020.265679 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17462.828154 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17462.828154 # average SoftPFReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20950.393237 # average WriteLineReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20950.393237 # average WriteLineReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14186.927904 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14186.927904 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028375 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.028375 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032617 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.032617 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16397.630680 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16397.630680 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37115.854904 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37115.854904 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17411.869795 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17411.869795 # average SoftPFReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20971.298142 # average WriteLineReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20971.298142 # average WriteLineReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14151.422764 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14151.422764 # average LoadLockedReq mshr miss latency
830,839c833,842
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22228.911293 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22228.911293 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21586.679439 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21586.679439 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184922.142094 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184922.142094 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92445.981633 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92445.981633 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 24547500 # number of replacements
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.464524 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.464524 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21613.312248 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 21613.312248 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184913.565408 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184913.565408 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92441.693990 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92441.693990 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 24600209 # number of replacements
841,844c844,847
< system.cpu.icache.tags.total_refs 427774095 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 24548012 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 17.426018 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 21430762500 # Cycle when the warmup percentage was hit.
---
> system.cpu.icache.tags.total_refs 428505873 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 24600721 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 17.418427 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 21430954500 # Cycle when the warmup percentage was hit.
849,851c852,854
< system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id
853,891c856,894
< system.cpu.icache.tags.tag_accesses 476870138 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 476870138 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 427774095 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 427774095 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 427774095 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 427774095 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 427774095 # number of overall hits
< system.cpu.icache.overall_hits::total 427774095 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 24548022 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 24548022 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 24548022 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 24548022 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 24548022 # number of overall misses
< system.cpu.icache.overall_misses::total 24548022 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 329750158000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 329750158000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 329750158000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 329750158000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 329750158000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 329750158000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 452322117 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 452322117 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 452322117 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 452322117 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 452322117 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 452322117 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054271 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.054271 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.054271 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.054271 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.054271 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.054271 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13432.860619 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13432.860619 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13432.860619 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13432.860619 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 477707334 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 477707334 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 428505873 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 428505873 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 428505873 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 428505873 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 428505873 # number of overall hits
> system.cpu.icache.overall_hits::total 428505873 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 24600731 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 24600731 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 24600731 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 24600731 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 24600731 # number of overall misses
> system.cpu.icache.overall_misses::total 24600731 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 330486746500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 330486746500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 330486746500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 330486746500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 330486746500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 330486746500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 453106604 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 453106604 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 453106604 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 453106604 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 453106604 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 453106604 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054293 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.054293 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.054293 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.054293 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.054293 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.054293 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13434.021391 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13434.021391 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13434.021391 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13434.021391 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13434.021391 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13434.021391 # average overall miss latency
898,905c901,908
< system.cpu.icache.writebacks::writebacks 24547500 # number of writebacks
< system.cpu.icache.writebacks::total 24547500 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24548022 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 24548022 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 24548022 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 24548022 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 24548022 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 24548022 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 24600209 # number of writebacks
> system.cpu.icache.writebacks::total 24600209 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24600731 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 24600731 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 24600731 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 24600731 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 24600731 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 24600731 # number of overall MSHR misses
910,915c913,918
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305202137000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 305202137000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305202137000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 305202137000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305202137000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 305202137000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305886016500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 305886016500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305886016500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 305886016500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305886016500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 305886016500 # number of overall MSHR miss cycles
920,931c923,934
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054271 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.054271 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.054271 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12432.860660 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12432.860660 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12432.860660 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12432.860660 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12432.860660 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12432.860660 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054293 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.054293 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.054293 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12434.021432 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12434.021432 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12434.021432 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12434.021432 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12434.021432 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12434.021432 # average overall mshr miss latency
936,941c939,944
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 1591901 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65408.549959 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 69520908 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1655396 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 41.996542 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 1601564 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65405.294347 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 69675530 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1664947 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 41.848497 # Average number of references to valid blocks.
943,998c946,1001
< system.cpu.l2cache.tags.occ_blocks::writebacks 9036.958133 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 433.683776 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 402.305370 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 7871.756997 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 47663.845683 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.137893 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006617 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006139 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120113 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.727293 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.998055 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 271 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 63224 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 271 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 790 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5976 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56108 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004135 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.964722 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 582399864 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 582399864 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 921588 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 261482 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1183070 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 8512101 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 8512101 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 24543775 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 24543775 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 29573 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 29573 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1660508 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1660508 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24440962 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 24440962 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7164937 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 7164937 # number of ReadSharedReq hits
< system.cpu.l2cache.InvalidateReq_hits::cpu.data 700668 # number of InvalidateReq hits
< system.cpu.l2cache.InvalidateReq_hits::total 700668 # number of InvalidateReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 921588 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 261482 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 24440962 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 8825445 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 34449477 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 921588 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 261482 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 24440962 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 8825445 # number of overall hits
< system.cpu.l2cache.overall_hits::total 34449477 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6273 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5180 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 11453 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 4073 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 4073 # number of UpgradeReq misses
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 9201.337762 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 431.981496 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 403.879639 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 8049.770162 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 47318.325288 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.140401 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006592 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006163 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122830 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.722020 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.998006 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 257 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 63126 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 257 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 803 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5965 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56053 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963226 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 583673795 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 583673795 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 921476 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 260236 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1181712 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 8530547 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 8530547 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 24596465 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 24596465 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 29651 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 29651 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1663600 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1663600 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24492767 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 24492767 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7181719 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 7181719 # number of ReadSharedReq hits
> system.cpu.l2cache.InvalidateReq_hits::cpu.data 699060 # number of InvalidateReq hits
> system.cpu.l2cache.InvalidateReq_hits::total 699060 # number of InvalidateReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 921476 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 260236 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 24492767 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 8845319 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 34519798 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 921476 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 260236 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 24492767 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 8845319 # number of overall hits
> system.cpu.l2cache.overall_hits::total 34519798 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6194 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5168 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 11362 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 4020 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 4020 # number of UpgradeReq misses
1001,1023c1004,1026
< system.cpu.l2cache.ReadExReq_misses::cpu.data 696158 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 696158 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107059 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 107059 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 326956 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 326956 # number of ReadSharedReq misses
< system.cpu.l2cache.InvalidateReq_misses::cpu.data 542348 # number of InvalidateReq misses
< system.cpu.l2cache.InvalidateReq_misses::total 542348 # number of InvalidateReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 6273 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 5180 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 107059 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1023114 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1141626 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 6273 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 5180 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 107059 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1023114 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1141626 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 939749000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 683365000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1623114000 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72777000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 72777000 # number of UpgradeReq miss cycles
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 702193 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 702193 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107963 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 107963 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 328484 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 328484 # number of ReadSharedReq misses
> system.cpu.l2cache.InvalidateReq_misses::cpu.data 543647 # number of InvalidateReq misses
> system.cpu.l2cache.InvalidateReq_misses::total 543647 # number of InvalidateReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 6194 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 5168 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 107963 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1030677 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1150002 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 6194 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 5168 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 107963 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1030677 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1150002 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 927255500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 692143500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1619399000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72892500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 72892500 # number of UpgradeReq miss cycles
1026,1052c1029,1053
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66999821500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 66999821500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11524194500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 11524194500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37120013000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 37120013000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 2135500 # number of InvalidateReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::total 2135500 # number of InvalidateReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 939749000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 683365000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 11524194500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 104119834500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 117267143000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 939749000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 683365000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 11524194500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 104119834500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 117267143000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 927861 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 266662 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1194523 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 8512101 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 8512101 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 24543775 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 24543775 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33646 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 33646 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67521066500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 67521066500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11586638500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 11586638500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37187085000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 37187085000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 927255500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 692143500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 11586638500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 104708151500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 117914189000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 927255500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 692143500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 11586638500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 104708151500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 117914189000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 927670 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 265404 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1193074 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 8530547 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 8530547 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 24596465 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 24596465 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33671 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 33671 # number of UpgradeReq accesses(hits+misses)
1055,1077c1056,1078
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2356666 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2356666 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24548021 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 24548021 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7491893 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 7491893 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1243016 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::total 1243016 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 927861 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 266662 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 24548021 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 9848559 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 35591103 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 927861 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 266662 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 24548021 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 9848559 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 35591103 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006761 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.019425 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.009588 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.121055 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.121055 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 2365793 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 2365793 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24600730 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 24600730 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7510203 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 7510203 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1242707 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::total 1242707 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 927670 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 265404 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 24600730 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 9875996 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 35669800 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 927670 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 265404 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 24600730 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 9875996 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 35669800 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006677 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.019472 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.009523 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.119391 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.119391 # miss rate for UpgradeReq accesses
1080,1102c1081,1103
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.295400 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.295400 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004361 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004361 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043641 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043641 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.436316 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::total 0.436316 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006761 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.019425 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004361 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.103885 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.032076 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006761 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.019425 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004361 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.103885 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.032076 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 149808.544556 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 131923.745174 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 141719.549463 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17868.156150 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17868.156150 # average UpgradeReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.296811 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.296811 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004389 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004389 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043738 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043738 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.437470 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::total 0.437470 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006677 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.019472 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004389 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.104362 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.032240 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006677 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.019472 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004389 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.104362 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.032240 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 149702.211818 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133928.695820 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 142527.635980 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18132.462687 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18132.462687 # average UpgradeReq miss latency
1105,1122c1106,1121
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96242.263251 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96242.263251 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107643.397566 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107643.397566 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 113532.135823 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 113532.135823 # average ReadSharedReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 3.937509 # average InvalidateReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 3.937509 # average InvalidateReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 149808.544556 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 131923.745174 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107643.397566 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101767.578686 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 102719.404604 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 149808.544556 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 131923.745174 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107643.397566 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101767.578686 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 102719.404604 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96157.418972 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96157.418972 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107320.457008 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107320.457008 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 113208.208010 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 113208.208010 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 149702.211818 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133928.695820 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107320.457008 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101591.625213 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 102533.899071 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 149702.211818 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133928.695820 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107320.457008 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101591.625213 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 102533.899071 # average overall miss latency
1129,1132c1128,1131
< system.cpu.l2cache.writebacks::writebacks 1356118 # number of writebacks
< system.cpu.l2cache.writebacks::total 1356118 # number of writebacks
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 1364616 # number of writebacks
> system.cpu.l2cache.writebacks::total 1364616 # number of writebacks
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
1135c1134
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1137,1138c1136,1137
< system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1140,1143c1139,1142
< system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6273 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5180 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 11453 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6194 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5168 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 11362 # number of ReadReq MSHR misses
1146,1147c1145,1146
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4073 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 4073 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4020 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 4020 # number of UpgradeReq MSHR misses
1150,1167c1149,1166
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 696158 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 696158 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107056 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107056 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 326935 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 326935 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 542348 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::total 542348 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6273 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5180 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 107056 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1023093 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1141602 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6273 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5180 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 107056 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1023093 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1141602 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 702193 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 702193 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107961 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107961 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 328463 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 328463 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 543647 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::total 543647 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6194 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5168 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 107961 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1030656 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1149979 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6194 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5168 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 107961 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1030656 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1149979 # number of overall MSHR misses
1176,1180c1175,1179
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 877019000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 631565000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1508584000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77761500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77761500 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 865315500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 640463500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1505779000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76760000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76760000 # number of UpgradeReq MSHR miss cycles
1183,1200c1182,1199
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60038241001 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60038241001 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10453433004 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10453433004 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33849413548 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33849413548 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11199554001 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11199554001 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 877019000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 631565000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10453433004 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93887654549 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 105849671553 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 877019000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 631565000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10453433004 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93887654549 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 105849671553 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60499136001 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60499136001 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10506850003 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10506850003 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33899524045 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33899524045 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11224464501 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11224464501 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 865315500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 640463500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10506850003 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 94398660046 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 106411289049 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 865315500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 640463500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10506850003 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 94398660046 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 106411289049 # number of overall MSHR miss cycles
1202,1203c1201,1202
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809783000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9420792000 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809544500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9420553500 # number of ReadReq MSHR uncacheable cycles
1205,1209c1204,1208
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809783000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9420792000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009588 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809544500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9420553500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009523 # mshr miss rate for ReadReq accesses
1212,1213c1211,1212
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.121055 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.121055 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119391 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119391 # mshr miss rate for UpgradeReq accesses
1216,1238c1215,1237
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.295400 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.295400 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004361 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043639 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043639 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.436316 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.436316 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.032075 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.032075 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131719.549463 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19091.946968 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19091.946968 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296811 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296811 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004389 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043736 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043736 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.437470 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.437470 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104360 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.032240 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104360 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.032240 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132527.635980 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19094.527363 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19094.527363 # average UpgradeReq mshr miss latency
1241,1258c1240,1257
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86242.262534 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86242.262534 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97644.531871 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97644.531871 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103535.606613 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103535.606613 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20650.125014 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20650.125014 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86157.418261 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86157.418261 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97320.791795 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97320.791795 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103206.522637 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103206.522637 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20646.604324 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20646.604324 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97320.791795 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91590.850920 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92533.245432 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97320.791795 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91590.850920 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92533.245432 # average overall mshr miss latency
1260,1261c1259,1260
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172417.586657 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109560.654518 # average ReadReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172410.508666 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109557.880842 # average ReadReq mshr uncacheable latency
1263,1269c1262,1268
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.724270 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78707.303624 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 72021080 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 36381496 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4425 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 1940 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1940 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86191.185852 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78705.311043 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 72189026 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 36469595 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4452 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1946 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1946 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1271,1273c1270,1272
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadReq 1770978 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 33811680 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadReq 1780354 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 33892071 # Transaction distribution
1276,1279c1275,1278
< system.cpu.toL2Bus.trans_dist::WritebackDirty 9868219 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 24547500 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 2814706 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 33649 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 9895163 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 24600209 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 2824554 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 33674 # Transaction distribution
1281,1302c1280,1301
< system.cpu.toL2Bus.trans_dist::UpgradeResp 33650 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2356666 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2356666 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 24548022 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 7494335 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 1271849 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateResp 1243016 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73748124 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33477065 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 672528 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2206986 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 110104703 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3145459904 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1175323090 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2133296 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7422888 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 4330339178 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 2114439 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 90765792 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 39101108 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.018304 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.134047 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 33675 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 2365793 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 2365793 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 24600731 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 7513010 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 1271678 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateResp 1242738 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73906251 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33558527 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 672286 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2215155 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 110352219 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3152206656 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1178259346 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2123232 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7421360 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 4340010594 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 2135457 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 91396008 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 39200512 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.018468 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.134637 # Request fanout histogram
1304,1305c1303,1304
< system.cpu.toL2Bus.snoop_fanout::0 38385418 98.17% 98.17% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 715690 1.83% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 38476553 98.15% 98.15% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 723959 1.85% 100.00% # Request fanout histogram
1310,1311c1309,1310
< system.cpu.toL2Bus.snoop_fanout::total 39101108 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 69634684493 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 39200512 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 69790374998 # Layer occupancy (ticks)
1313c1312
< system.cpu.toL2Bus.snoopLayer0.occupancy 1487890 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 1501881 # Layer occupancy (ticks)
1315c1314
< system.cpu.toL2Bus.respLayer0.occupancy 36904751913 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 36983722099 # Layer occupancy (ticks)
1317c1316
< system.cpu.toL2Bus.respLayer1.occupancy 15462672587 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 15503705051 # Layer occupancy (ticks)
1319c1318
< system.cpu.toL2Bus.respLayer2.occupancy 405908415 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 406910942 # Layer occupancy (ticks)
1321c1320
< system.cpu.toL2Bus.respLayer3.occupancy 1279140469 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 1287502964 # Layer occupancy (ticks)
1323,1325c1322,1324
< system.iobus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.iobus.trans_dist::ReadReq 40325 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40325 # Transaction distribution
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.iobus.trans_dist::ReadReq 40334 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40334 # Transaction distribution
1342,1343c1341,1342
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231026 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231026 # Packet count per connected master and slave (bytes)
1346c1345
< system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353810 # Packet count per connected master and slave (bytes)
1361,1362c1360,1361
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334536 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7334536 # Cumulative packet size per connected master and slave (bytes)
1365,1366c1364,1365
< system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 37691500 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7492456 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 37695500 # Layer occupancy (ticks)
1370c1369
< system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 339500 # Layer occupancy (ticks)
1388c1387
< system.iobus.reqLayer23.occupancy 25239000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 25148500 # Layer occupancy (ticks)
1390c1389
< system.iobus.reqLayer24.occupancy 36441500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 36444000 # Layer occupancy (ticks)
1392c1391
< system.iobus.reqLayer25.occupancy 569511366 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 569308376 # Layer occupancy (ticks)
1396c1395
< system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147786000 # Layer occupancy (ticks)
1400,1402c1399,1401
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.iocache.tags.replacements 115486 # number of replacements
< system.iocache.tags.tagsinuse 10.448155 # Cycle average of tags in use
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.iocache.tags.replacements 115495 # number of replacements
> system.iocache.tags.tagsinuse 10.448162 # Cycle average of tags in use
1404c1403
< system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115511 # Sample count of references to valid blocks.
1406,1407c1405,1406
< system.iocache.tags.warmup_cycle 13141696144000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.519387 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 13141692173000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.519394 # Average occupied blocks per requestor
1415,1417c1414,1416
< system.iocache.tags.tag_accesses 1039893 # Number of tag accesses
< system.iocache.tags.data_accesses 1039893 # Number of data accesses
< system.iocache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.tag_accesses 1039974 # Number of tag accesses
> system.iocache.tags.data_accesses 1039974 # Number of data accesses
> system.iocache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
1419,1420c1418,1419
< system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8849 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8886 # number of ReadReq misses
1426,1427c1425,1426
< system.iocache.demand_misses::realview.ide 115504 # number of demand (read+write) misses
< system.iocache.demand_misses::total 115544 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115513 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115553 # number of demand (read+write) misses
1429,1430c1428,1429
< system.iocache.overall_misses::realview.ide 115504 # number of overall misses
< system.iocache.overall_misses::total 115544 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115513 # number of overall misses
> system.iocache.overall_misses::total 115553 # number of overall misses
1432,1433c1431,1432
< system.iocache.ReadReq_miss_latency::realview.ide 2067712004 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 2072797504 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 2011459152 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 2016544652 # number of ReadReq miss cycles
1436,1437c1435,1436
< system.iocache.WriteLineReq_miss_latency::realview.ide 13276938862 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 13276938862 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13390572724 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13390572724 # number of WriteLineReq miss cycles
1439,1440c1438,1439
< system.iocache.demand_miss_latency::realview.ide 15344650866 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 15350087366 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15402031876 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15407468376 # number of demand (read+write) miss cycles
1442,1443c1441,1442
< system.iocache.overall_miss_latency::realview.ide 15344650866 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 15350087366 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15402031876 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15407468376 # number of overall miss cycles
1445,1446c1444,1445
< system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8849 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8886 # number of ReadReq accesses(hits+misses)
1452,1453c1451,1452
< system.iocache.demand_accesses::realview.ide 115504 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 115544 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115513 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115553 # number of demand (read+write) accesses
1455,1456c1454,1455
< system.iocache.overall_accesses::realview.ide 115504 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 115544 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115513 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115553 # number of overall (read+write) accesses
1471,1472c1470,1471
< system.iocache.ReadReq_avg_miss_latency::realview.ide 233904.072851 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 233502.028163 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 227309.204656 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 226935.027234 # average ReadReq miss latency
1475,1476c1474,1475
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124474.413692 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 124474.413692 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125539.757781 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 125539.757781 # average WriteLineReq miss latency
1478,1479c1477,1478
< system.iocache.demand_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 132850.579571 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 133335.917827 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 133336.809741 # average overall miss latency
1481,1483c1480,1482
< system.iocache.overall_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 132850.579571 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 54006 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 133335.917827 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 133336.809741 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 51202 # number of cycles access was blocked
1485c1484
< system.iocache.blocked::no_mshrs 3503 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3365 # number of cycles access was blocked
1487c1486
< system.iocache.avg_blocked_cycles::no_mshrs 15.417071 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 15.216048 # average number of cycles each access was blocked
1492,1493c1491,1492
< system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8849 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8886 # number of ReadReq MSHR misses
1499,1500c1498,1499
< system.iocache.demand_mshr_misses::realview.ide 115504 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 115544 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115513 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115553 # number of demand (read+write) MSHR misses
1502,1503c1501,1502
< system.iocache.overall_mshr_misses::realview.ide 115504 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 115544 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115513 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115553 # number of overall MSHR misses
1505,1506c1504,1505
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1625712004 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1628947504 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1569009152 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1572244652 # number of ReadReq MSHR miss cycles
1509,1510c1508,1509
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7936726922 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7936726922 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8051866391 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8051866391 # number of WriteLineReq MSHR miss cycles
1512,1513c1511,1512
< system.iocache.demand_mshr_miss_latency::realview.ide 9562438926 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 9565875426 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9620875543 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9624312043 # number of demand (read+write) MSHR miss cycles
1515,1516c1514,1515
< system.iocache.overall_mshr_miss_latency::realview.ide 9562438926 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 9565875426 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9620875543 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9624312043 # number of overall MSHR miss cycles
1531,1532c1530,1531
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 183904.072851 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 183502.028163 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177309.204656 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 176935.027234 # average ReadReq mshr miss latency
1535,1536c1534,1535
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74408.675111 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74408.675111 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75488.134619 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75488.134619 # average WriteLineReq mshr miss latency
1538,1539c1537,1538
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 83288.249314 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 83289.157728 # average overall mshr miss latency
1541,1545c1540,1544
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 3510315 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 1740308 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 83288.249314 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 83289.157728 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 3529625 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 1749962 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 3622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1549c1548
< system.membus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
1551c1550
< system.membus.trans_dist::ReadResp 540308 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 542659 # Transaction distribution
1554,1556c1553,1555
< system.membus.trans_dist::WritebackDirty 1462749 # Transaction distribution
< system.membus.trans_dist::CleanEvict 243530 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4703 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 1471247 # Transaction distribution
> system.membus.trans_dist::CleanEvict 244702 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4583 # Transaction distribution
1559,1562c1558,1562
< system.membus.trans_dist::ReadExReq 695596 # Transaction distribution
< system.membus.trans_dist::ReadExResp 695596 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 454321 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 648947 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 701633 # Transaction distribution
> system.membus.trans_dist::ReadExResp 701633 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 456672 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 650311 # Transaction distribution
> system.membus.trans_dist::InvalidateResp 28814 # Transaction distribution
1566,1570c1566,1570
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4528935 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4658587 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237673 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 237673 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 4896260 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4556598 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4686250 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237342 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 237342 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 4923592 # Packet count per connected master and slave (bytes)
1574,1583c1574,1583
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163142636 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163313042 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7249536 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7249536 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 170562578 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 2899 # Total snoops (count)
< system.membus.snoopTraffic 185088 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 1923263 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.016618 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.127834 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164222764 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164393170 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7227200 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7227200 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 171620370 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 32071 # Total snoops (count)
> system.membus.snoopTraffic 208000 # Total snoop traffic (bytes)
> system.membus.snoop_fanout::samples 1932895 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.016796 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.128505 # Request fanout histogram
1585,1586c1585,1586
< system.membus.snoop_fanout::0 1891303 98.34% 98.34% # Request fanout histogram
< system.membus.snoop_fanout::1 31960 1.66% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 1900431 98.32% 98.32% # Request fanout histogram
> system.membus.snoop_fanout::1 32464 1.68% 100.00% # Request fanout histogram
1591,1592c1591,1592
< system.membus.snoop_fanout::total 1923263 # Request fanout histogram
< system.membus.reqLayer0.occupancy 99811000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 1932895 # Request fanout histogram
> system.membus.reqLayer0.occupancy 99728500 # Layer occupancy (ticks)
1596c1596
< system.membus.reqLayer2.occupancy 5612500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5568000 # Layer occupancy (ticks)
1598c1598
< system.membus.reqLayer5.occupancy 9664854495 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 9720767792 # Layer occupancy (ticks)
1600c1600
< system.membus.respLayer2.occupancy 6432615655 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 6477610584 # Layer occupancy (ticks)
1602c1602
< system.membus.respLayer3.occupancy 44921497 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 75150025 # Layer occupancy (ticks)
1604,1610c1604,1610
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
1617,1618c1617,1618
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
1661,1667c1661,1667
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
1672,1683c1672,1683
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states