7,11c7,11
< host_inst_rate 204210 # Simulator instruction rate (inst/s)
< host_op_rate 239956 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 11350998190 # Simulator tick rate (ticks/s)
< host_mem_usage 682908 # Number of bytes of host memory used
< host_seconds 4551.20 # Real time elapsed on the host
---
> host_inst_rate 286668 # Simulator instruction rate (inst/s)
> host_op_rate 336848 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 15934426663 # Simulator tick rate (ticks/s)
> host_mem_usage 682904 # Number of bytes of host memory used
> host_seconds 3242.08 # Real time elapsed on the host
607,610c607,610
< system.cpu.dcache.demand_hits::cpu.data 313786004 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 313786004 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 314301494 # number of overall hits
< system.cpu.dcache.overall_hits::total 314301494 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 314122591 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 314122591 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 314638081 # number of overall hits
> system.cpu.dcache.overall_hits::total 314638081 # number of overall hits
623,626c623,626
< system.cpu.dcache.demand_misses::cpu.data 10601209 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 10601209 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 12022090 # number of overall misses
< system.cpu.dcache.overall_misses::total 12022090 # number of overall misses
---
> system.cpu.dcache.demand_misses::cpu.data 11841309 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 11841309 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 13262190 # number of overall misses
> system.cpu.dcache.overall_misses::total 13262190 # number of overall misses
637,640c637,640
< system.cpu.dcache.demand_miss_latency::cpu.data 325526040000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 325526040000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 325526040000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 325526040000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 378997815500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 378997815500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 378997815500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 378997815500 # number of overall miss cycles
653,656c653,656
< system.cpu.dcache.demand_accesses::cpu.data 324387213 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 324387213 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 326323584 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 326323584 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 325963900 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 325963900 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 327900271 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 327900271 # number of overall (read+write) accesses
669,672c669,672
< system.cpu.dcache.demand_miss_rate::cpu.data 0.032681 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.032681 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.036841 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.036841 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.036327 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.036327 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.040446 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.040446 # miss rate for overall accesses
683,686c683,686
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 30706.501494 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 30706.501494 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.325157 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 27077.325157 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 32006.412087 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 32006.412087 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 28577.317585 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 28577.317585 # average overall miss latency
693,694d692
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
705,708c703,706
< system.cpu.dcache.demand_mshr_hits::cpu.data 2620111 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2620111 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2620111 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2620111 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 2620277 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2620277 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2620277 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2620277 # number of overall MSHR hits
721,724c719,722
< system.cpu.dcache.demand_mshr_misses::cpu.data 7981098 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 7981098 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 9394451 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9394451 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 9221032 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 9221032 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 10634385 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 10634385 # number of overall MSHR misses
743,746c741,744
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206893714000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 206893714000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233795004500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 233795004500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 259115478000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 259115478000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286016768500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 286016768500 # number of overall MSHR miss cycles
749,752c747,748
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6191865500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6191865500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12389494000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 12389494000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197628500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197628500 # number of overall MSHR uncacheable cycles
765,768c761,764
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024604 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.024604 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028789 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.028789 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028289 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.028289 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032432 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses
781,784c777,780
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25922.963733 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 25922.963733 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24886.499967 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 24886.499967 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661 # average overall mshr miss latency
787,791c783,784
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183702.174687 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183702.174687 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 183812.204205 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 183812.204205 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency
850,851d842
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
890d880
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1083,1084d1072
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1160,1161d1147
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5803513500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5803513500 # number of WriteReq MSHR uncacheable cycles
1163,1164c1149,1150
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11579839500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17515913500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5776326000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11712400000 # number of overall MSHR uncacheable cycles
1220,1221d1205
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172180.427817 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172180.427817 # average WriteReq mshr uncacheable latency
1223,1225c1207,1208
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 171800.060828 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146317.106890 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85698.351705 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97838.144881 # average overall mshr uncacheable latency
1382,1383c1365,1366
< system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8879 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115503 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115543 # number of demand (read+write) misses
1385,1386c1368,1369
< system.iocache.overall_misses::realview.ide 8839 # number of overall misses
< system.iocache.overall_misses::total 8879 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115503 # number of overall misses
> system.iocache.overall_misses::total 115543 # number of overall misses
1395,1396c1378,1379
< system.iocache.demand_miss_latency::realview.ide 1644126101 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1649547101 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15056019107 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15061440107 # number of demand (read+write) miss cycles
1398,1399c1381,1382
< system.iocache.overall_miss_latency::realview.ide 1644126101 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1649547101 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15056019107 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15061440107 # number of overall miss cycles
1408,1409c1391,1392
< system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115503 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115543 # number of demand (read+write) accesses
1411,1412c1394,1395
< system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115503 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115543 # number of overall (read+write) accesses
1434,1435c1417,1418
< system.iocache.demand_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 185780.729925 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 130353.548956 # average overall miss latency
1437,1438c1420,1421
< system.iocache.overall_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 185780.729925 # average overall miss latency
---
> system.iocache.overall_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 130353.548956 # average overall miss latency
1445,1446d1427
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1457,1458c1438,1439
< system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115503 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115543 # number of demand (read+write) MSHR misses
1460,1461c1441,1442
< system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115503 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115543 # number of overall MSHR misses
1470,1471c1451,1452
< system.iocache.demand_mshr_miss_latency::realview.ide 1202176101 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1205597101 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9275723962 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9279144962 # number of demand (read+write) MSHR miss cycles
1473,1474c1454,1455
< system.iocache.overall_mshr_miss_latency::realview.ide 1202176101 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1205597101 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9275723962 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9279144962 # number of overall MSHR miss cycles
1496,1497c1477,1478
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency
1499,1501c1480,1481
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency
< host_inst_rate 204210 # Simulator instruction rate (inst/s)
< host_op_rate 239956 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 11350998190 # Simulator tick rate (ticks/s)
< host_mem_usage 682908 # Number of bytes of host memory used
< host_seconds 4551.20 # Real time elapsed on the host
---
> host_inst_rate 286668 # Simulator instruction rate (inst/s)
> host_op_rate 336848 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 15934426663 # Simulator tick rate (ticks/s)
> host_mem_usage 682904 # Number of bytes of host memory used
> host_seconds 3242.08 # Real time elapsed on the host
607,610c607,610
< system.cpu.dcache.demand_hits::cpu.data 313786004 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 313786004 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 314301494 # number of overall hits
< system.cpu.dcache.overall_hits::total 314301494 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 314122591 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 314122591 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 314638081 # number of overall hits
> system.cpu.dcache.overall_hits::total 314638081 # number of overall hits
623,626c623,626
< system.cpu.dcache.demand_misses::cpu.data 10601209 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 10601209 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 12022090 # number of overall misses
< system.cpu.dcache.overall_misses::total 12022090 # number of overall misses
---
> system.cpu.dcache.demand_misses::cpu.data 11841309 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 11841309 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 13262190 # number of overall misses
> system.cpu.dcache.overall_misses::total 13262190 # number of overall misses
637,640c637,640
< system.cpu.dcache.demand_miss_latency::cpu.data 325526040000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 325526040000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 325526040000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 325526040000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 378997815500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 378997815500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 378997815500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 378997815500 # number of overall miss cycles
653,656c653,656
< system.cpu.dcache.demand_accesses::cpu.data 324387213 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 324387213 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 326323584 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 326323584 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 325963900 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 325963900 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 327900271 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 327900271 # number of overall (read+write) accesses
669,672c669,672
< system.cpu.dcache.demand_miss_rate::cpu.data 0.032681 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.032681 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.036841 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.036841 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.036327 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.036327 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.040446 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.040446 # miss rate for overall accesses
683,686c683,686
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 30706.501494 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 30706.501494 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.325157 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 27077.325157 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 32006.412087 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 32006.412087 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 28577.317585 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 28577.317585 # average overall miss latency
693,694d692
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
705,708c703,706
< system.cpu.dcache.demand_mshr_hits::cpu.data 2620111 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2620111 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2620111 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2620111 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 2620277 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2620277 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2620277 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2620277 # number of overall MSHR hits
721,724c719,722
< system.cpu.dcache.demand_mshr_misses::cpu.data 7981098 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 7981098 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 9394451 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9394451 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 9221032 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 9221032 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 10634385 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 10634385 # number of overall MSHR misses
743,746c741,744
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206893714000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 206893714000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233795004500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 233795004500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 259115478000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 259115478000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286016768500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 286016768500 # number of overall MSHR miss cycles
749,752c747,748
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6191865500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6191865500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12389494000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 12389494000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197628500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197628500 # number of overall MSHR uncacheable cycles
765,768c761,764
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024604 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.024604 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028789 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.028789 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028289 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.028289 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032432 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses
781,784c777,780
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25922.963733 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 25922.963733 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24886.499967 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 24886.499967 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661 # average overall mshr miss latency
787,791c783,784
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183702.174687 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183702.174687 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 183812.204205 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 183812.204205 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency
850,851d842
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
890d880
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1083,1084d1072
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1160,1161d1147
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5803513500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5803513500 # number of WriteReq MSHR uncacheable cycles
1163,1164c1149,1150
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11579839500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17515913500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5776326000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11712400000 # number of overall MSHR uncacheable cycles
1220,1221d1205
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172180.427817 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172180.427817 # average WriteReq mshr uncacheable latency
1223,1225c1207,1208
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 171800.060828 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146317.106890 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85698.351705 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97838.144881 # average overall mshr uncacheable latency
1382,1383c1365,1366
< system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8879 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115503 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115543 # number of demand (read+write) misses
1385,1386c1368,1369
< system.iocache.overall_misses::realview.ide 8839 # number of overall misses
< system.iocache.overall_misses::total 8879 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115503 # number of overall misses
> system.iocache.overall_misses::total 115543 # number of overall misses
1395,1396c1378,1379
< system.iocache.demand_miss_latency::realview.ide 1644126101 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1649547101 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15056019107 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15061440107 # number of demand (read+write) miss cycles
1398,1399c1381,1382
< system.iocache.overall_miss_latency::realview.ide 1644126101 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1649547101 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15056019107 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15061440107 # number of overall miss cycles
1408,1409c1391,1392
< system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115503 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115543 # number of demand (read+write) accesses
1411,1412c1394,1395
< system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115503 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115543 # number of overall (read+write) accesses
1434,1435c1417,1418
< system.iocache.demand_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 185780.729925 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 130353.548956 # average overall miss latency
1437,1438c1420,1421
< system.iocache.overall_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 185780.729925 # average overall miss latency
---
> system.iocache.overall_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 130353.548956 # average overall miss latency
1445,1446d1427
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1457,1458c1438,1439
< system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115503 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115543 # number of demand (read+write) MSHR misses
1460,1461c1441,1442
< system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115503 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115543 # number of overall MSHR misses
1470,1471c1451,1452
< system.iocache.demand_mshr_miss_latency::realview.ide 1202176101 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1205597101 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9275723962 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9279144962 # number of demand (read+write) MSHR miss cycles
1473,1474c1454,1455
< system.iocache.overall_mshr_miss_latency::realview.ide 1202176101 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1205597101 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9275723962 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9279144962 # number of overall MSHR miss cycles
1496,1497c1477,1478
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency
1499,1501c1480,1481
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency