3,5c3,5
< sim_seconds 51.667476 # Number of seconds simulated
< sim_ticks 51667476471000 # Number of ticks simulated
< final_tick 51667476471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 51.660643 # Number of seconds simulated
> sim_ticks 51660642512000 # Number of ticks simulated
> final_tick 51660642512000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 274767 # Simulator instruction rate (inst/s)
< host_op_rate 322852 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 15389929524 # Simulator tick rate (ticks/s)
< host_mem_usage 683068 # Number of bytes of host memory used
< host_seconds 3357.23 # Real time elapsed on the host
< sim_insts 922453344 # Number of instructions simulated
< sim_ops 1083887959 # Number of ops (including micro ops) simulated
---
> host_inst_rate 304990 # Simulator instruction rate (inst/s)
> host_op_rate 358371 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 16937149026 # Simulator tick rate (ticks/s)
> host_mem_usage 683404 # Number of bytes of host memory used
> host_seconds 3050.14 # Real time elapsed on the host
> sim_insts 930261902 # Number of instructions simulated
> sim_ops 1093080704 # Number of ops (including micro ops) simulated
16,24c16,24
< system.physmem.bytes_read::cpu.dtb.walker 349632 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 295488 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 10205120 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 93689288 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 408000 # Number of bytes read from this memory
< system.physmem.bytes_read::total 104947528 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 10205120 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 10205120 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 87402048 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 377280 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 320000 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 10274880 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 61682056 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 384384 # Number of bytes read from this memory
> system.physmem.bytes_read::total 73038600 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 10274880 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 10274880 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 89590976 # Number of bytes written to this memory
26,33c26,33
< system.physmem.bytes_written::total 87422628 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 5463 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 4617 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 159455 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1463908 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6375 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1639818 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1365657 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 89611556 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 5895 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 5000 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 160545 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 963795 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6006 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1141241 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1399859 # Number of write requests responded to by this memory
35,44c35,44
< system.physmem.num_writes::total 1368230 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 6767 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 5719 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 197515 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1813313 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 7897 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2031211 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 197515 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 197515 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1691626 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1402432 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 7303 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 6194 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 198892 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1193985 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 7441 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1413815 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 198892 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 198892 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1734221 # Write bandwidth from this memory (bytes/s)
46,64c46,64
< system.physmem.bw_write::total 1692024 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1691626 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 6767 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 5719 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 197515 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1813711 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 7897 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3723235 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1639818 # Number of read requests accepted
< system.physmem.writeReqs 1368230 # Number of write requests accepted
< system.physmem.readBursts 1639818 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1368230 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 104895040 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 53312 # Total number of bytes read from write queue
< system.physmem.bytesWritten 87421376 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 104947528 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 87422628 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 833 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_write::total 1734619 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1734221 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 7303 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 6194 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 198892 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1194384 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 7441 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3148435 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1141241 # Number of read requests accepted
> system.physmem.writeReqs 1402432 # Number of write requests accepted
> system.physmem.readBursts 1141241 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1402432 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 72981760 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 57664 # Total number of bytes read from write queue
> system.physmem.bytesWritten 89610624 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 73038600 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 89611556 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 901 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
66,97c66,97
< system.physmem.perBankRdBursts::0 99403 # Per bank write bursts
< system.physmem.perBankRdBursts::1 105228 # Per bank write bursts
< system.physmem.perBankRdBursts::2 100047 # Per bank write bursts
< system.physmem.perBankRdBursts::3 95494 # Per bank write bursts
< system.physmem.perBankRdBursts::4 102929 # Per bank write bursts
< system.physmem.perBankRdBursts::5 111535 # Per bank write bursts
< system.physmem.perBankRdBursts::6 97078 # Per bank write bursts
< system.physmem.perBankRdBursts::7 98055 # Per bank write bursts
< system.physmem.perBankRdBursts::8 92724 # Per bank write bursts
< system.physmem.perBankRdBursts::9 154002 # Per bank write bursts
< system.physmem.perBankRdBursts::10 99475 # Per bank write bursts
< system.physmem.perBankRdBursts::11 105000 # Per bank write bursts
< system.physmem.perBankRdBursts::12 94287 # Per bank write bursts
< system.physmem.perBankRdBursts::13 95690 # Per bank write bursts
< system.physmem.perBankRdBursts::14 90913 # Per bank write bursts
< system.physmem.perBankRdBursts::15 97125 # Per bank write bursts
< system.physmem.perBankWrBursts::0 83951 # Per bank write bursts
< system.physmem.perBankWrBursts::1 87043 # Per bank write bursts
< system.physmem.perBankWrBursts::2 85245 # Per bank write bursts
< system.physmem.perBankWrBursts::3 83208 # Per bank write bursts
< system.physmem.perBankWrBursts::4 88814 # Per bank write bursts
< system.physmem.perBankWrBursts::5 93904 # Per bank write bursts
< system.physmem.perBankWrBursts::6 83820 # Per bank write bursts
< system.physmem.perBankWrBursts::7 85248 # Per bank write bursts
< system.physmem.perBankWrBursts::8 81467 # Per bank write bursts
< system.physmem.perBankWrBursts::9 88240 # Per bank write bursts
< system.physmem.perBankWrBursts::10 85354 # Per bank write bursts
< system.physmem.perBankWrBursts::11 89463 # Per bank write bursts
< system.physmem.perBankWrBursts::12 82403 # Per bank write bursts
< system.physmem.perBankWrBursts::13 83577 # Per bank write bursts
< system.physmem.perBankWrBursts::14 80367 # Per bank write bursts
< system.physmem.perBankWrBursts::15 83855 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 67748 # Per bank write bursts
> system.physmem.perBankRdBursts::1 75024 # Per bank write bursts
> system.physmem.perBankRdBursts::2 69908 # Per bank write bursts
> system.physmem.perBankRdBursts::3 64252 # Per bank write bursts
> system.physmem.perBankRdBursts::4 67104 # Per bank write bursts
> system.physmem.perBankRdBursts::5 72834 # Per bank write bursts
> system.physmem.perBankRdBursts::6 66007 # Per bank write bursts
> system.physmem.perBankRdBursts::7 65201 # Per bank write bursts
> system.physmem.perBankRdBursts::8 62658 # Per bank write bursts
> system.physmem.perBankRdBursts::9 122060 # Per bank write bursts
> system.physmem.perBankRdBursts::10 69885 # Per bank write bursts
> system.physmem.perBankRdBursts::11 74467 # Per bank write bursts
> system.physmem.perBankRdBursts::12 66975 # Per bank write bursts
> system.physmem.perBankRdBursts::13 66087 # Per bank write bursts
> system.physmem.perBankRdBursts::14 62026 # Per bank write bursts
> system.physmem.perBankRdBursts::15 68104 # Per bank write bursts
> system.physmem.perBankWrBursts::0 85430 # Per bank write bursts
> system.physmem.perBankWrBursts::1 89554 # Per bank write bursts
> system.physmem.perBankWrBursts::2 89147 # Per bank write bursts
> system.physmem.perBankWrBursts::3 85797 # Per bank write bursts
> system.physmem.perBankWrBursts::4 87375 # Per bank write bursts
> system.physmem.perBankWrBursts::5 90488 # Per bank write bursts
> system.physmem.perBankWrBursts::6 83025 # Per bank write bursts
> system.physmem.perBankWrBursts::7 85134 # Per bank write bursts
> system.physmem.perBankWrBursts::8 84926 # Per bank write bursts
> system.physmem.perBankWrBursts::9 90963 # Per bank write bursts
> system.physmem.perBankWrBursts::10 87836 # Per bank write bursts
> system.physmem.perBankWrBursts::11 92829 # Per bank write bursts
> system.physmem.perBankWrBursts::12 87557 # Per bank write bursts
> system.physmem.perBankWrBursts::13 87424 # Per bank write bursts
> system.physmem.perBankWrBursts::14 84847 # Per bank write bursts
> system.physmem.perBankWrBursts::15 87834 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 37 # Number of times write queue was full causing retry
< system.physmem.totGap 51667474307000 # Total gap between requests
---
> system.physmem.numWrRetry 50 # Number of times write queue was full causing retry
> system.physmem.totGap 51660640624000 # Total gap between requests
107c107
< system.physmem.readPktSize::6 1639803 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1141226 # Read request sizes (log2)
114,117c114,117
< system.physmem.writePktSize::6 1365657 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1314237 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 318417 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1399859 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1072907 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 61649 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 723 # What read queue length does an incoming req see
119,135c119,135
< system.physmem.rdQLenPdf::4 465 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 530 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 537 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 676 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 362 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 180 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 67 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::4 449 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1108 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 583 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 279 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 324 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 155 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 155 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 117 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 120 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
162,266c162,263
< system.physmem.wrQLenPdf::15 14698 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 18189 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 67736 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 80790 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 82454 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 81257 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 81296 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 82033 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 83039 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 82637 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 83634 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 86681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 83517 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 83880 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 94578 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 83323 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 84131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 81331 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 2502 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 677 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 616 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 411 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 474 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 481 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 385 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 283 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 418 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 298 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 289 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 282 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 267 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 263 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 296 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 241 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 222 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 242 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 129 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 160 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 646147 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 297.635603 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 173.901229 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 324.036577 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 253673 39.26% 39.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 155474 24.06% 63.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 60360 9.34% 72.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 34960 5.41% 78.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 25496 3.95% 82.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 18768 2.90% 84.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 14047 2.17% 87.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 13088 2.03% 89.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 70281 10.88% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 646147 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 79019 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 20.741467 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 283.796699 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 79016 100.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 79019 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 79019 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.286463 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.794878 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 6.949851 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 76956 97.39% 97.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 330 0.42% 97.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 47 0.06% 97.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 101 0.13% 97.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 35 0.04% 98.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 85 0.11% 98.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 245 0.31% 98.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 21 0.03% 98.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 324 0.41% 98.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 69 0.09% 98.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 26 0.03% 99.01% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 53 0.07% 99.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 312 0.39% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 39 0.05% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 28 0.04% 99.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 118 0.15% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 171 0.22% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
---
> system.physmem.wrQLenPdf::15 34167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 39504 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 78543 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 80306 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 82649 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 80800 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 81768 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 85658 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 85076 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 81194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 82459 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 85799 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 82823 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 82988 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 84778 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 80804 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 79640 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 79007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 2607 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 824 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 673 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 570 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 578 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 411 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 395 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 375 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 293 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 273 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 254 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 229 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 261 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 276 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 253 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 195 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 176 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 144 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 169 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 180 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 84 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 132 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 648089 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 250.879123 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 152.008733 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 285.888919 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 280289 43.25% 43.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 166837 25.74% 68.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 60882 9.39% 78.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 33521 5.17% 83.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 23050 3.56% 87.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 16307 2.52% 89.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 11522 1.78% 91.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 9570 1.48% 92.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 46111 7.11% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 648089 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 76765 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 14.854530 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 142.199486 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 76763 100.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 76765 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 76765 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 18.239640 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.683114 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 7.179019 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 64873 84.51% 84.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 9480 12.35% 96.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 455 0.59% 97.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 326 0.42% 97.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 60 0.08% 97.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 114 0.15% 98.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 230 0.30% 98.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 35 0.05% 98.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 294 0.38% 98.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 75 0.10% 98.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 27 0.04% 98.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 50 0.07% 99.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 318 0.41% 99.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 35 0.05% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 31 0.04% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 111 0.14% 99.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 179 0.23% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 5 0.01% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 5 0.01% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 2 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 6 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 16 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads
269,270c266,267
< system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 6 0.01% 100.00% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::176-179 7 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads
273,277c270,274
< system.physmem.wrPerTurnAround::total 79019 # Writes before turning the bus around for reads
< system.physmem.totQLat 26490910104 # Total ticks spent queuing
< system.physmem.totMemAccLat 57221878854 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 8194925000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 16163.00 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 76765 # Writes before turning the bus around for reads
> system.physmem.totQLat 16541565713 # Total ticks spent queuing
> system.physmem.totMemAccLat 37922940713 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 5701700000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 14505.82 # Average queueing delay per DRAM burst
279,283c276,280
< system.physmem.avgMemAccLat 34913.00 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.69 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 33255.82 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.73 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.41 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.73 # Average system write bandwidth in MiByte/s
285,286c282,283
< system.physmem.busUtil 0.03 # Data bus utilization in percentage
< system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 0.02 # Data bus utilization in percentage
> system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
289,306c286,303
< system.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing
< system.physmem.readRowHits 1332864 # Number of row buffer hits during reads
< system.physmem.writeRowHits 1025932 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes
< system.physmem.avgGap 17176412.85 # Average gap between requests
< system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 2496243960 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1362037875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 6316198200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 4479189840 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1323055672425 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 29839910639250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 34552288356030 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.743489 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 49640417958020 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1725290580000 # Time in different power states
---
> system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing
> system.physmem.readRowHits 872320 # Number of row buffer hits during reads
> system.physmem.writeRowHits 1020096 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 76.50 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 72.85 # Row buffer hit rate for writes
> system.physmem.avgGap 20309466.12 # Average gap between requests
> system.physmem.pageHitRate 74.49 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 2456674920 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1340447625 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 4274961600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 4509756000 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3374221858800 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1317434781870 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 29840739448500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 34544977929315 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.690476 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 49641970693393 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1725062300000 # Time in different power states
308c305
< system.physmem_0.memoryStateTime::ACT 301767793230 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 293608746107 # Time in different power states
310,320c307,317
< system.physmem_1.actEnergy 2388627360 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1303318500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 6467877000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 4372224480 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1316624734350 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 29845551821250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 34551376977420 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.725849 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 49649780004526 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1725290580000 # Time in different power states
---
> system.physmem_1.actEnergy 2442877920 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1332919500 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 4619643600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 4563319680 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3374221858800 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1319027164650 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 29839342629750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 34545550413900 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.701557 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 49639611346782 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1725062300000 # Time in different power states
322c319
< system.physmem_1.memoryStateTime::ACT 292405760474 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 295966370718 # Time in different power states
346,350c343,347
< system.cpu.branchPred.lookups 252598760 # Number of BP lookups
< system.cpu.branchPred.condPredicted 176508431 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 11957032 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 185598793 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 131565493 # Number of BTB hits
---
> system.cpu.branchPred.lookups 254908438 # Number of BP lookups
> system.cpu.branchPred.condPredicted 178242351 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 12005241 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 187385958 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 132827814 # Number of BTB hits
352,354c349,351
< system.cpu.branchPred.BTBHitPct 70.887041 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 30959293 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 2131771 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 70.884615 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 31213174 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 2144347 # Number of incorrect RAS predictions.
385,405c382,402
< system.cpu.dtb.walker.walks 560635 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 560635 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20884 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178593 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 560635 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 560635 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 560635 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 199477 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 26985.070961 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 22842.355807 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 20873.513445 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-65535 197251 98.88% 98.88% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.89% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-196607 1888 0.95% 99.83% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::196608-262143 57 0.03% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::262144-327679 109 0.05% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::327680-393215 46 0.02% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-458751 97 0.05% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walks 567320 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 567320 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20723 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksLongTerminationLevel::Level3 182198 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 567320 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 567320 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 567320 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 202921 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 27429.733739 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 23186.871186 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 21494.309968 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-65535 200464 98.79% 98.79% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-131071 14 0.01% 98.80% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-196607 2073 1.02% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::196608-262143 61 0.03% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-327679 133 0.07% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::327680-393215 52 0.03% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::393216-458751 92 0.05% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::458752-524287 15 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
407c404,405
< system.cpu.dtb.walker.walkCompletionTime::total 199477 # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 202921 # Table walker service (enqueue to completion) latency
411,414c409,412
< system.cpu.dtb.walker.walkPageSizes::4K 178594 89.53% 89.53% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::2M 20884 10.47% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 199478 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560635 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkPageSizes::4K 182199 89.79% 89.79% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::2M 20723 10.21% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 202922 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 567320 # Table walker requests started/completed, data/inst
416,417c414,415
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560635 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199478 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 567320 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202922 # Table walker requests started/completed, data/inst
419,420c417,418
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199478 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 760113 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202922 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 770242 # Table walker requests started/completed, data/inst
423,426c421,424
< system.cpu.dtb.read_hits 178339564 # DTB read hits
< system.cpu.dtb.read_misses 462901 # DTB read misses
< system.cpu.dtb.write_hits 158016400 # DTB write hits
< system.cpu.dtb.write_misses 97734 # DTB write misses
---
> system.cpu.dtb.read_hits 179769202 # DTB read hits
> system.cpu.dtb.read_misses 468572 # DTB read misses
> system.cpu.dtb.write_hits 159383411 # DTB write hits
> system.cpu.dtb.write_misses 98748 # DTB write misses
429,433c427,431
< system.cpu.dtb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID
< system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID
< system.cpu.dtb.flush_entries 78401 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 1394 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 14946 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_tlb_mva_asid 45817 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID
> system.cpu.dtb.flush_entries 78846 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 15815 # Number of TLB faults due to prefetch
435,437c433,435
< system.cpu.dtb.perms_faults 23063 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 178802465 # DTB read accesses
< system.cpu.dtb.write_accesses 158114134 # DTB write accesses
---
> system.cpu.dtb.perms_faults 23199 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 180237774 # DTB read accesses
> system.cpu.dtb.write_accesses 159482159 # DTB write accesses
439,441c437,439
< system.cpu.dtb.hits 336355964 # DTB hits
< system.cpu.dtb.misses 560635 # DTB misses
< system.cpu.dtb.accesses 336916599 # DTB accesses
---
> system.cpu.dtb.hits 339152613 # DTB hits
> system.cpu.dtb.misses 567320 # DTB misses
> system.cpu.dtb.accesses 339719933 # DTB accesses
471,496c469,489
< system.cpu.itb.walker.walks 134932 # Table walker walks requested
< system.cpu.itb.walker.walksLong 134932 # Table walker walks initiated with long descriptors
< system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksLongTerminationLevel::Level3 117658 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walkWaitTime::samples 134932 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 134932 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 134932 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 118737 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 30245.892182 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 25862.614601 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 23195.505917 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-32767 58684 49.42% 49.42% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::32768-65535 57510 48.43% 97.86% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::65536-98303 2 0.00% 97.86% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::98304-131071 7 0.01% 97.87% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::131072-163839 1905 1.60% 99.47% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::163840-196607 424 0.36% 99.83% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::196608-229375 23 0.02% 99.85% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::229376-262143 17 0.01% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::262144-294911 94 0.08% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::294912-327679 21 0.02% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::327680-360447 17 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::393216-425983 17 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::425984-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 118737 # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walks 135719 # Table walker walks requested
> system.cpu.itb.walker.walksLong 135719 # Table walker walks initiated with long descriptors
> system.cpu.itb.walker.walksLongTerminationLevel::Level2 1067 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksLongTerminationLevel::Level3 118398 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walkWaitTime::samples 135719 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 135719 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 135719 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 119465 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 30823.412715 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 26220.565528 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 24055.511247 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-65535 116639 97.63% 97.63% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::65536-131071 7 0.01% 97.64% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-196607 2565 2.15% 99.79% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::196608-262143 80 0.07% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::262144-327679 132 0.11% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::327680-393215 26 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::393216-458751 13 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 119465 # Table walker service (enqueue to completion) latency
500,502c493,495
< system.cpu.itb.walker.walkPageSizes::4K 117658 99.09% 99.09% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::2M 1079 0.91% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 118737 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkPageSizes::4K 118398 99.11% 99.11% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::2M 1067 0.89% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 119465 # Table walker page sizes translated
504,505c497,498
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134932 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 134932 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135719 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 135719 # Table walker requests started/completed, data/inst
507,511c500,504
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118737 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 118737 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 253669 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 439091546 # ITB inst hits
< system.cpu.itb.inst_misses 134932 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119465 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 119465 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 255184 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 443155891 # ITB inst hits
> system.cpu.itb.inst_misses 135719 # ITB inst misses
518,520c511,513
< system.cpu.itb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID
< system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID
< system.cpu.itb.flush_entries 56478 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_tlb_mva_asid 45817 # Number of times TLB was flushed by MVA & ASID
> system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID
> system.cpu.itb.flush_entries 56716 # Number of entries that have been flushed from TLB
524c517
< system.cpu.itb.perms_faults 354973 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 363456 # Number of TLB faults due to permissions restrictions
527,531c520,524
< system.cpu.itb.inst_accesses 439226478 # ITB inst accesses
< system.cpu.itb.hits 439091546 # DTB hits
< system.cpu.itb.misses 134932 # DTB misses
< system.cpu.itb.accesses 439226478 # DTB accesses
< system.cpu.numCycles 2564620605 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 443291610 # ITB inst accesses
> system.cpu.itb.hits 443155891 # DTB hits
> system.cpu.itb.misses 135719 # DTB misses
> system.cpu.itb.accesses 443291610 # DTB accesses
> system.cpu.numCycles 2560430377 # number of cpu cycles simulated
534,540c527,533
< system.cpu.committedInsts 922453344 # Number of instructions committed
< system.cpu.committedOps 1083887959 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 92875630 # Number of ops (including micro ops) which were discarded before commit
< system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching
< system.cpu.quiesceCycles 100771468164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.780217 # CPI: cycles per instruction
< system.cpu.ipc 0.359684 # IPC: instructions per cycle
---
> system.cpu.committedInsts 930261902 # Number of instructions committed
> system.cpu.committedOps 1093080704 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 94082781 # Number of ops (including micro ops) which were discarded before commit
> system.cpu.numFetchSuspends 7654 # Number of times Execute suspended instruction fetching
> system.cpu.quiesceCycles 100762000477 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.752376 # CPI: cycles per instruction
> system.cpu.ipc 0.363322 # IPC: instructions per cycle
542,549c535,542
< system.cpu.kern.inst.quiesce 16482 # number of quiesce instructions executed
< system.cpu.tickCycles 1741581813 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 823038792 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 10731841 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.930081 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 320513038 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 10732353 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 29.864191 # Average number of references to valid blocks.
---
> system.cpu.kern.inst.quiesce 16514 # number of quiesce instructions executed
> system.cpu.tickCycles 1756892100 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 803538277 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 10835760 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.930073 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 323161698 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 10836272 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 29.822221 # Average number of references to valid blocks.
551c544
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.930081 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.930073 # Average occupied blocks per requestor
555,557c548,550
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
560,653c553,646
< system.cpu.dcache.tags.tag_accesses 1346389769 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1346389769 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 164045150 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 164045150 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 147553918 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 147553918 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 512343 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 512343 # number of SoftPFReq hits
< system.cpu.dcache.WriteLineReq_hits::cpu.data 335860 # number of WriteLineReq hits
< system.cpu.dcache.WriteLineReq_hits::total 335860 # number of WriteLineReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 3854660 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 3854660 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 4163151 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 4163151 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 311599068 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 311599068 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 312111411 # number of overall hits
< system.cpu.dcache.overall_hits::total 312111411 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 6370722 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 6370722 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 4130704 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 4130704 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 1398816 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 1398816 # number of SoftPFReq misses
< system.cpu.dcache.WriteLineReq_misses::cpu.data 1238819 # number of WriteLineReq misses
< system.cpu.dcache.WriteLineReq_misses::total 1238819 # number of WriteLineReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 310200 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 310200 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 10501426 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 10501426 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 11900242 # number of overall misses
< system.cpu.dcache.overall_misses::total 11900242 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 117402431000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 117402431000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 199951337000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 199951337000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 84556806000 # number of WriteLineReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::total 84556806000 # number of WriteLineReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5139718000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 5139718000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 317353768000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 317353768000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 317353768000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 317353768000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 170415872 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 170415872 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 151684622 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 151684622 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 1911159 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 1911159 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::cpu.data 1574679 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::total 1574679 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4164860 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 4164860 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 4163152 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 4163152 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 322100494 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 322100494 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 324011653 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 324011653 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037383 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.037383 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027232 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.027232 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.731920 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.731920 # miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786712 # miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::total 0.786712 # miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074480 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074480 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.032603 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.032603 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.036728 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.036728 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18428.434171 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 18428.434171 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48406.116003 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 48406.116003 # average WriteReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68255.980898 # average WriteLineReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68255.980898 # average WriteLineReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.045777 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.045777 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 30220.064208 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 30220.064208 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 26667.841545 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 26667.841545 # average overall miss latency
---
> system.cpu.dcache.tags.tag_accesses 1357625936 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1357625936 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 165326360 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 165326360 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 148822242 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 148822242 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 515783 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 515783 # number of SoftPFReq hits
> system.cpu.dcache.WriteLineReq_hits::cpu.data 336254 # number of WriteLineReq hits
> system.cpu.dcache.WriteLineReq_hits::total 336254 # number of WriteLineReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 3901835 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 3901835 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 4210707 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 4210707 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 314148602 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 314148602 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 314664385 # number of overall hits
> system.cpu.dcache.overall_hits::total 314664385 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 6435963 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 6435963 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 4178110 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 4178110 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 1419320 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 1419320 # number of SoftPFReq misses
> system.cpu.dcache.WriteLineReq_misses::cpu.data 1240241 # number of WriteLineReq misses
> system.cpu.dcache.WriteLineReq_misses::total 1240241 # number of WriteLineReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 310588 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 310588 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 10614073 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 10614073 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 12033393 # number of overall misses
> system.cpu.dcache.overall_misses::total 12033393 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 119289543000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 119289543000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 206542043000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 206542043000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53400604000 # number of WriteLineReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::total 53400604000 # number of WriteLineReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5170357500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 5170357500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245500 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 245500 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 325831586000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 325831586000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 325831586000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 325831586000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 171762323 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 171762323 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 153000352 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 153000352 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 1935103 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 1935103 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576495 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::total 1576495 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4212423 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 4212423 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 4210710 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 4210710 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 324762675 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 324762675 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 326697778 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 326697778 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037470 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.037470 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027308 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.027308 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733460 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.733460 # miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786708 # miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::total 0.786708 # miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073731 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073731 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.032683 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.032683 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.036833 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.036833 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18534.839775 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 18534.839775 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49434.323893 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 49434.323893 # average WriteReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43056.634960 # average WriteLineReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43056.634960 # average WriteLineReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16646.996986 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16646.996986 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 81833.333333 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 81833.333333 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 30698.072832 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 30698.072832 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.282858 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 27077.282858 # average overall miss latency
662,691c655,684
< system.cpu.dcache.writebacks::writebacks 8243774 # number of writebacks
< system.cpu.dcache.writebacks::total 8243774 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 770626 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 770626 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821654 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1821654 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 153 # number of WriteLineReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::total 153 # number of WriteLineReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68982 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 68982 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2592280 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2592280 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2592280 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2592280 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5600096 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 5600096 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2309050 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2309050 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1391260 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 1391260 # number of SoftPFReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238666 # number of WriteLineReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::total 1238666 # number of WriteLineReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241218 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 241218 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 7909146 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 7909146 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 9300406 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9300406 # number of overall MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 8326510 # number of writebacks
> system.cpu.dcache.writebacks::total 8326510 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 781266 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 781266 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841490 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1841490 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 148 # number of WriteLineReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::total 148 # number of WriteLineReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69021 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 69021 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2622756 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2622756 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2622756 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2622756 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5654697 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 5654697 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2336620 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2336620 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1411789 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 1411789 # number of SoftPFReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1240093 # number of WriteLineReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::total 1240093 # number of WriteLineReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241567 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 241567 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 7991317 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 7991317 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9403106 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9403106 # number of overall MSHR misses
698,757c691,750
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96067975500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 96067975500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106000226500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 106000226500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26589323500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26589323500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83310681500 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83310681500 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3491728500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3491728500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202068202000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 202068202000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228657525500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 228657525500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197287500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197287500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207449000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207449000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404736500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404736500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032861 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032861 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015223 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015223 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.727967 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.727967 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786615 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786615 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057917 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057917 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024555 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.024555 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028704 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.028704 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17154.701544 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17154.701544 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45906.423204 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45906.423204 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19111.685451 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19111.685451 # average SoftPFReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67258.390478 # average WriteLineReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67258.390478 # average WriteLineReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14475.406064 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14475.406064 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25548.675167 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 25548.675167 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24585.757385 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 24585.757385 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183912.143514 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183912.143514 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184164.510770 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184164.510770 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184038.343991 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184038.343991 # average overall mshr uncacheable latency
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97635804500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 97635804500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109449194500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 109449194500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26743318000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26743318000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52153246000 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52153246000 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3514198000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3514198000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 242500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 242500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207084999000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 207084999000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233828317000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 233828317000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197367000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197367000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207571500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207571500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404938500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404938500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032922 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032922 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015272 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015272 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729568 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729568 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786614 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786614 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057346 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057346 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024607 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.024607 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028782 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.028782 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17266.319398 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17266.319398 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46840.819004 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46840.819004 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18942.857608 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18942.857608 # average SoftPFReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42055.915161 # average WriteLineReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42055.915161 # average WriteLineReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14547.508559 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14547.508559 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80833.333333 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80833.333333 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25913.751013 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 25913.751013 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24867.136136 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24867.136136 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183914.502775 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183914.502775 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.145137 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.145137 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184041.340890 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184041.340890 # average overall mshr uncacheable latency
759,767c752,760
< system.cpu.icache.tags.replacements 24176986 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 414546703 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 24177498 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 17.145972 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 24282731 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.885324 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 418496927 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 24283243 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 17.233980 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 32778398500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.885324 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy
769,771c762,764
< system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id
773,810c766,803
< system.cpu.icache.tags.tag_accesses 462901718 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 462901718 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 414546703 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 414546703 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 414546703 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 414546703 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 414546703 # number of overall hits
< system.cpu.icache.overall_hits::total 414546703 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 24177508 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 24177508 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 24177508 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 24177508 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 24177508 # number of overall misses
< system.cpu.icache.overall_misses::total 24177508 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 327600086000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 327600086000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 327600086000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 327600086000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 327600086000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 327600086000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 438724211 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 438724211 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 438724211 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 438724211 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 438724211 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 438724211 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055109 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.055109 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.055109 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.055109 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.055109 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.055109 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13549.787100 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13549.787100 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13549.787100 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13549.787100 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13549.787100 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13549.787100 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 467063432 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 467063432 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 418496927 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 418496927 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 418496927 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 418496927 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 418496927 # number of overall hits
> system.cpu.icache.overall_hits::total 418496927 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 24283253 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 24283253 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 24283253 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 24283253 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 24283253 # number of overall misses
> system.cpu.icache.overall_misses::total 24283253 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 329126236000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 329126236000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 329126236000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 329126236000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 329126236000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 329126236000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 442780180 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 442780180 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 442780180 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 442780180 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 442780180 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 442780180 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054843 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.054843 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.054843 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.054843 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.054843 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.054843 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13553.630397 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13553.630397 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13553.630397 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13553.630397 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13553.630397 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13553.630397 # average overall miss latency
819,826c812,819
< system.cpu.icache.writebacks::writebacks 24176986 # number of writebacks
< system.cpu.icache.writebacks::total 24176986 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24177508 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 24177508 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 24177508 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 24177508 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 24177508 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 24177508 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 24282731 # number of writebacks
> system.cpu.icache.writebacks::total 24282731 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24283253 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 24283253 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 24283253 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 24283253 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 24283253 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 24283253 # number of overall MSHR misses
831,836c824,829
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303422579000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 303422579000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303422579000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 303422579000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303422579000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 303422579000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304842984000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 304842984000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304842984000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 304842984000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304842984000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 304842984000 # number of overall MSHR miss cycles
841,852c834,845
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055109 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055109 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055109 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.055109 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055109 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.055109 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12549.787141 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12549.787141 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12549.787141 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12549.787141 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12549.787141 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12549.787141 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054843 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054843 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054843 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.054843 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054843 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.054843 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12553.630438 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12553.630438 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12553.630438 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12553.630438 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12553.630438 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12553.630438 # average overall mshr miss latency
858,998c851,990
< system.cpu.l2cache.tags.replacements 1490234 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65213.875092 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 65897094 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1553867 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 42.408452 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 36600562500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 37061.912307 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 323.258711 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 399.460797 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 7867.228358 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 19562.014919 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.565520 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004933 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006095 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120044 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.298493 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.995085 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 63396 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5534 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54861 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.967346 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 573646968 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 573646968 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 914477 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 280144 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1194621 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 8243774 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 8243774 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 24173277 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 24173277 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 10400 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 10400 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1641430 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1641430 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24070330 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 24070330 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6918127 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 6918127 # number of ReadSharedReq hits
< system.cpu.l2cache.InvalidateReq_hits::cpu.data 707471 # number of InvalidateReq hits
< system.cpu.l2cache.InvalidateReq_hits::total 707471 # number of InvalidateReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 914477 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 280144 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 24070330 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 8559557 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 33824508 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 914477 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 280144 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 24070330 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 8559557 # number of overall hits
< system.cpu.l2cache.overall_hits::total 33824508 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5463 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4617 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 10080 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 37497 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 37497 # number of UpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 619977 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 619977 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107175 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 107175 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 314193 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 314193 # number of ReadSharedReq misses
< system.cpu.l2cache.InvalidateReq_misses::cpu.data 531195 # number of InvalidateReq misses
< system.cpu.l2cache.InvalidateReq_misses::total 531195 # number of InvalidateReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 5463 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 4617 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 107175 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 934170 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1051425 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 5463 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 4617 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 107175 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 934170 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1051425 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 750857500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 630554000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1381411500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1438781000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 1438781000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82239355500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 82239355500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14186388500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 14186388500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 42349642500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 42349642500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 73756780500 # number of InvalidateReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::total 73756780500 # number of InvalidateReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 750857500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 630554000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 14186388500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 124588998000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 140156798000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 750857500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 630554000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 14186388500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 124588998000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 140156798000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 919940 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 284761 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1204701 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 8243774 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 8243774 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 24173277 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 24173277 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 47897 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 47897 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2261407 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2261407 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24177505 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 24177505 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7232320 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 7232320 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1238666 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::total 1238666 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 919940 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 284761 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 24177505 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 9493727 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 34875933 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 919940 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 284761 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 24177505 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 9493727 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 34875933 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.005938 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.016214 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.008367 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782867 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782867 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.tags.replacements 1528241 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65327.330583 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 66279197 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1591645 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 41.641947 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 36821.900434 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 322.022869 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 395.139834 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 8029.956207 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 19758.311238 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.561858 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004914 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006029 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122527 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.301488 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996816 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 229 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 63175 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2412 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5471 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54751 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003494 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963974 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 576746891 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 576746891 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 934890 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 285217 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1220107 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 8326510 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 8326510 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 24279004 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 24279004 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 10570 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 10570 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1643650 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1643650 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24174985 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 24174985 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6987496 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 6987496 # number of ReadSharedReq hits
> system.cpu.l2cache.InvalidateReq_hits::cpu.data 703999 # number of InvalidateReq hits
> system.cpu.l2cache.InvalidateReq_hits::total 703999 # number of InvalidateReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 934890 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 285217 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 24174985 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 8631146 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 34026238 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 934890 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 285217 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 24174985 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 8631146 # number of overall hits
> system.cpu.l2cache.overall_hits::total 34026238 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5895 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5000 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 10895 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 37884 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 37884 # number of UpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 644745 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 644745 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 108265 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 108265 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320328 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 320328 # number of ReadSharedReq misses
> system.cpu.l2cache.InvalidateReq_misses::cpu.data 536094 # number of InvalidateReq misses
> system.cpu.l2cache.InvalidateReq_misses::total 536094 # number of InvalidateReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 5895 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 5000 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 108265 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 965073 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1084233 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 5895 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 5000 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 108265 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 965073 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1084233 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 809439000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 684634500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1494073500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1447800500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 1447800500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 238000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 238000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85591105500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 85591105500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14347099000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 14347099000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43249450500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 43249450500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 14977000 # number of InvalidateReq miss cycles
> system.cpu.l2cache.InvalidateReq_miss_latency::total 14977000 # number of InvalidateReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 809439000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 684634500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 14347099000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 128840556000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 144681728500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 809439000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 684634500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 14347099000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 128840556000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 144681728500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 940785 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 290217 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1231002 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 8326510 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 8326510 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 24279004 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 24279004 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 48454 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 48454 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 2288395 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 2288395 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24283250 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 24283250 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7307824 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 7307824 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1240093 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::total 1240093 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 940785 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 290217 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 24283250 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 9596219 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 35110471 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 940785 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 290217 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 24283250 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 9596219 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 35110471 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006266 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.017228 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.008851 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.781855 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.781855 # miss rate for UpgradeReq accesses
1001,1043c993,1035
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.274155 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.274155 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004433 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004433 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043443 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043443 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.428844 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::total 0.428844 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.005938 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.016214 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004433 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.098399 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.030148 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.005938 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.016214 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004433 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.098399 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.030148 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137444.169870 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136572.233052 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 137044.791667 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38370.562978 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38370.562978 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132649.042626 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132649.042626 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132366.582692 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132366.582692 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134788.625144 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134788.625144 # average ReadSharedReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138850.667834 # average InvalidateReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138850.667834 # average InvalidateReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137444.169870 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136572.233052 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132366.582692 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133368.656668 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 133301.755237 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137444.169870 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136572.233052 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132366.582692 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133368.656668 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 133301.755237 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.281746 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.281746 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004458 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004458 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043834 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043834 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.432301 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::total 0.432301 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006266 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017228 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004458 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.100568 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.030881 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006266 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017228 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004458 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.100568 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.030881 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137309.414758 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136926.900000 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 137133.868747 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38216.674586 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38216.674586 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79333.333333 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79333.333333 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132751.871670 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132751.871670 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132518.348497 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132518.348497 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135016.141268 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135016.141268 # average ReadSharedReq miss latency
> system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 27.937265 # average InvalidateReq miss latency
> system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 27.937265 # average InvalidateReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137309.414758 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136926.900000 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132518.348497 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133503.430310 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 133441.546697 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137309.414758 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136926.900000 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132518.348497 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133503.430310 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 133441.546697 # average overall miss latency
1052,1053c1044,1045
< system.cpu.l2cache.writebacks::writebacks 1259026 # number of writebacks
< system.cpu.l2cache.writebacks::total 1259026 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 1293229 # number of writebacks
> system.cpu.l2cache.writebacks::total 1293229 # number of writebacks
1064,1066c1056,1058
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5463 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4617 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 10080 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5895 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5000 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 10895 # number of ReadReq MSHR misses
1069,1090c1061,1082
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37497 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 37497 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 619977 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 619977 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107172 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107172 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 314172 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 314172 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 531195 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::total 531195 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5463 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4617 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 107172 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 934149 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1051401 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5463 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4617 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 107172 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 934149 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1051401 # number of overall MSHR misses
---
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37884 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 37884 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 644745 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 644745 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 108262 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 108262 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320307 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320307 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 536094 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::total 536094 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5895 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5000 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 108262 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 965052 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1084209 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5895 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5000 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 108262 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 965052 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1084209 # number of overall MSHR misses
1099,1123c1091,1115
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 696227500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 584384000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1280611500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2550264500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2550264500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 76039573524 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 76039573524 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13114406000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13114406000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 39205480000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 39205480000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 68444830500 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 68444830500 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 696227500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 584384000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13114406000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115245053524 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 129640071024 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 696227500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 584384000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13114406000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115245053524 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 129640071024 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 750489000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 634634500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1385123500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2576694000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2576694000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 208000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 208000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79143640031 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79143640031 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13264181071 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13264181071 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40044031927 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40044031927 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 37345893500 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 37345893500 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 750489000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 634634500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13264181071 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119187671958 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 133836976529 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 750489000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 634634500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13264181071 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119187671958 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 133836976529 # number of overall MSHR miss cycles
1125,1128c1117,1120
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776017500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712091500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5819225500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5819225500 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776092000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712166000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5819357000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5819357000 # number of WriteReq MSHR uncacheable cycles
1130,1134c1122,1126
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11595243000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17531317000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008367 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11595449000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17531523000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008851 # mshr miss rate for ReadReq accesses
1137,1138c1129,1130
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782867 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782867 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781855 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781855 # mshr miss rate for UpgradeReq accesses
1141,1183c1133,1175
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.274155 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.274155 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004433 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043440 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043440 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.428844 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.428844 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.098396 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.030147 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.098396 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.030147 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127044.791667 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.494333 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.494333 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122649.023309 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122649.023309 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122367.838615 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122367.838615 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124789.860331 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124789.860331 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128850.667834 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128850.667834 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.281746 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.281746 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004458 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043831 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043831 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.432301 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.432301 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.100566 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.030880 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.100566 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.030880 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127133.868747 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68015.362686 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68015.362686 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69333.333333 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69333.333333 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122751.847678 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122751.847678 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122519.268728 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122519.268728 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125017.660953 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125017.660953 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.957429 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.957429 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122519.268728 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.885757 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123442.045334 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122519.268728 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.885757 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123442.045334 # average overall mshr miss latency
1185,1188c1177,1180
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171410.437131 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136177.609702 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172646.576277 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172646.576277 # average WriteReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171412.648010 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136178.475920 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.477660 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.477660 # average WriteReq mshr uncacheable latency
1190,1191c1182,1183
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172028.589232 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146445.778201 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.645476 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.498998 # average overall mshr uncacheable latency
1193,1197c1185,1189
< system.cpu.toL2Bus.snoop_filter.tot_requests 70561172 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 35651281 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4392 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2272 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2272 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 70987580 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 35868028 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4400 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2259 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2259 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1199,1200c1191,1192
< system.cpu.toL2Bus.trans_dist::ReadReq 1729330 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 33139930 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 1747427 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 33339280 # Transaction distribution
1203,1228c1195,1220
< system.cpu.toL2Bus.trans_dist::WritebackDirty 9609467 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 24176986 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 2728127 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 47900 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 47901 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2261407 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2261407 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 24177508 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 7241194 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 1345330 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateResp 1238666 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72636616 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32428005 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 687897 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2160128 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 107912646 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3098035136 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135439954 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2278088 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7359520 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 4243112698 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 2160696 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 38442129 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.018241 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.133822 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 9726418 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 24282731 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 2753122 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 48457 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 48460 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 2288395 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 2288395 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 24283253 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 7316706 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 1346757 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateResp 1240093 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72953851 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32740884 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695726 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2196697 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 108587158 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3111570496 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1147294802 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2321736 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7526280 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 4268713314 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 2190531 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 38708484 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.018284 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.133976 # Request fanout histogram
1230,1231c1222,1223
< system.cpu.toL2Bus.snoop_fanout::0 37740909 98.18% 98.18% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 701220 1.82% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 38000745 98.17% 98.17% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 707739 1.83% 100.00% # Request fanout histogram
1236,1237c1228,1229
< system.cpu.toL2Bus.snoop_fanout::total 38442129 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 68252447493 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 38708484 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 68659919994 # Layer occupancy (ticks)
1239c1231
< system.cpu.toL2Bus.snoopLayer0.occupancy 1464392 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 1469394 # Layer occupancy (ticks)
1241c1233
< system.cpu.toL2Bus.respLayer0.occupancy 36351871671 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 36510728693 # Layer occupancy (ticks)
1243c1235
< system.cpu.toL2Bus.respLayer1.occupancy 14935181922 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 15090009225 # Layer occupancy (ticks)
1245c1237
< system.cpu.toL2Bus.respLayer2.occupancy 403175920 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 405546924 # Layer occupancy (ticks)
1247c1239
< system.cpu.toL2Bus.respLayer3.occupancy 1240232910 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 1255965393 # Layer occupancy (ticks)
1249,1250c1241,1242
< system.iobus.trans_dist::ReadReq 40322 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40322 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 40330 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40330 # Transaction distribution
1267,1268c1259,1260
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231018 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231018 # Packet count per connected master and slave (bytes)
1271c1263
< system.iobus.pkt_count::total 353786 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353802 # Packet count per connected master and slave (bytes)
1286,1287c1278,1279
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334504 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7334504 # Cumulative packet size per connected master and slave (bytes)
1290,1291c1282,1283
< system.iobus.pkt_size::total 7492360 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 42165000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7492424 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 42214500 # Layer occupancy (ticks)
1295c1287
< system.iobus.reqLayer2.occupancy 332500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 333500 # Layer occupancy (ticks)
1309c1301
< system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks)
1313c1305
< system.iobus.reqLayer23.occupancy 25683500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 25698500 # Layer occupancy (ticks)
1315c1307
< system.iobus.reqLayer24.occupancy 34144500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 34147500 # Layer occupancy (ticks)
1317c1309
< system.iobus.reqLayer25.occupancy 567247076 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 566993946 # Layer occupancy (ticks)
1321c1313
< system.iobus.respLayer3.occupancy 147762000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147778000 # Layer occupancy (ticks)
1325,1326c1317,1318
< system.iocache.tags.replacements 115483 # number of replacements
< system.iocache.tags.tagsinuse 10.440004 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115490 # number of replacements
> system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use
1328c1320
< system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115506 # Sample count of references to valid blocks.
1330,1335c1322,1327
< system.iocache.tags.warmup_cycle 13160148727000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.520843 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 6.919161 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.432448 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.652500 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 13153331095000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.521304 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 6.919950 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.220081 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.432497 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.652578 # Average percentage of cache occupancy
1339,1340c1331,1332
< system.iocache.tags.tag_accesses 1039866 # Number of tag accesses
< system.iocache.tags.data_accesses 1039866 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1039938 # Number of tag accesses
> system.iocache.tags.data_accesses 1039938 # Number of data accesses
1342,1343c1334,1335
< system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8845 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8882 # number of ReadReq misses
1349,1350c1341,1342
< system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8877 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8845 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8885 # number of demand (read+write) misses
1352,1356c1344,1348
< system.iocache.overall_misses::realview.ide 8837 # number of overall misses
< system.iocache.overall_misses::total 8877 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::realview.ide 1647976559 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1653046059 # number of ReadReq miss cycles
---
> system.iocache.overall_misses::realview.ide 8845 # number of overall misses
> system.iocache.overall_misses::total 8885 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::realview.ide 1624796190 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1629882190 # number of ReadReq miss cycles
1359,1366c1351,1358
< system.iocache.WriteLineReq_miss_latency::realview.ide 13408898017 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 13408898017 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::realview.ide 1647976559 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1653397059 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles
< system.iocache.overall_miss_latency::realview.ide 1647976559 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1653397059 # number of overall miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13412464756 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13412464756 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::realview.ide 1624796190 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1630233190 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles
> system.iocache.overall_miss_latency::realview.ide 1624796190 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1630233190 # number of overall miss cycles
1368,1369c1360,1361
< system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8845 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8882 # number of ReadReq accesses(hits+misses)
1375,1376c1367,1368
< system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8845 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8885 # number of demand (read+write) accesses
1378,1379c1370,1371
< system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8845 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8885 # number of overall (read+write) accesses
1393,1395c1385,1387
< system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::realview.ide 186485.974765 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 186279.700135 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::realview.ide 183696.573205 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 183503.961946 # average ReadReq miss latency
1398,1406c1390,1398
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125711.561698 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 125711.561698 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 186256.286921 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 186256.286921 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 33362 # number of cycles access was blocked
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125745.000713 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 125745.000713 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 183696.573205 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 183481.507034 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 183696.573205 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 183481.507034 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 31904 # number of cycles access was blocked
1408c1400
< system.iocache.blocked::no_mshrs 3432 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3290 # number of cycles access was blocked
1410c1402
< system.iocache.avg_blocked_cycles::no_mshrs 9.720862 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 9.697264 # average number of cycles each access was blocked
1414,1415c1406,1407
< system.iocache.writebacks::writebacks 106631 # number of writebacks
< system.iocache.writebacks::total 106631 # number of writebacks
---
> system.iocache.writebacks::writebacks 106630 # number of writebacks
> system.iocache.writebacks::total 106630 # number of writebacks
1417,1418c1409,1410
< system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8845 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8882 # number of ReadReq MSHR misses
1424,1425c1416,1417
< system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8845 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8885 # number of demand (read+write) MSHR misses
1427,1431c1419,1423
< system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206126559 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1209346059 # number of ReadReq MSHR miss cycles
---
> system.iocache.overall_mshr_misses::realview.ide 8845 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8885 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1182546190 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1185782190 # number of ReadReq MSHR miss cycles
1434,1441c1426,1433
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8070540171 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 8070540171 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 1206126559 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1209547059 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 1206126559 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1209547059 # number of overall MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8074127324 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8074127324 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 1182546190 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1185983190 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 1182546190 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1185983190 # number of overall MSHR miss cycles
1455,1457c1447,1449
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136485.974765 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 136279.700135 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133696.573205 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 133503.961946 # average ReadReq mshr miss latency
1460,1467c1452,1459
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75663.205683 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75663.205683 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75696.836083 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75696.836083 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 133696.573205 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 133481.507034 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 133696.573205 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 133481.507034 # average overall mshr miss latency
1470c1462
< system.membus.trans_dist::ReadResp 526304 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 534352 # Transaction distribution
1473,1481c1465,1473
< system.membus.trans_dist::WritebackDirty 1365657 # Transaction distribution
< system.membus.trans_dist::CleanEvict 238956 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 38308 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 7 # Transaction distribution
< system.membus.trans_dist::ReadExReq 1150364 # Transaction distribution
< system.membus.trans_dist::ReadExResp 1150364 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 440298 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 1399859 # Transaction distribution
> system.membus.trans_dist::CleanEvict 242769 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 38707 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
> system.membus.trans_dist::ReadExReq 644117 # Transaction distribution
> system.membus.trans_dist::ReadExResp 644117 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 448346 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 642566 # Transaction distribution
1485,1489c1477,1481
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4800126 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4929778 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237399 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 237399 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5167177 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4378022 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4507674 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237045 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 237045 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 4744719 # Packet count per connected master and slave (bytes)
1493,1499c1485,1491
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185137772 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185308178 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232384 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7232384 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 192540562 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 3164 # Total snoops (count)
< system.membus.snoop_fanout::samples 3459998 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155441452 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 155611858 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7208704 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7208704 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 162820562 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 3543 # Total snoops (count)
> system.membus.snoop_fanout::samples 3536130 # Request fanout histogram
1504c1496
< system.membus.snoop_fanout::1 3459998 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 3536130 100.00% 100.00% # Request fanout histogram
1509,1510c1501,1502
< system.membus.snoop_fanout::total 3459998 # Request fanout histogram
< system.membus.reqLayer0.occupancy 102421000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3536130 # Request fanout histogram
> system.membus.reqLayer0.occupancy 102490000 # Layer occupancy (ticks)
1514c1506
< system.membus.reqLayer2.occupancy 5498500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5501500 # Layer occupancy (ticks)
1516c1508
< system.membus.reqLayer5.occupancy 9252697708 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 9311720798 # Layer occupancy (ticks)
1518c1510
< system.membus.respLayer2.occupancy 8691723530 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 6129482304 # Layer occupancy (ticks)
1520c1512
< system.membus.respLayer3.occupancy 44915426 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 44955070 # Layer occupancy (ticks)