3,5c3,5
< sim_seconds 51.694125 # Number of seconds simulated
< sim_ticks 51694125219000 # Number of ticks simulated
< final_tick 51694125219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 51.667585 # Number of seconds simulated
> sim_ticks 51667585479000 # Number of ticks simulated
> final_tick 51667585479000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 131034 # Simulator instruction rate (inst/s)
< host_op_rate 153967 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 7136466436 # Simulator tick rate (ticks/s)
< host_mem_usage 718208 # Number of bytes of host memory used
< host_seconds 7243.66 # Real time elapsed on the host
< sim_insts 949163000 # Number of instructions simulated
< sim_ops 1115282140 # Number of ops (including micro ops) simulated
---
> host_inst_rate 173260 # Simulator instruction rate (inst/s)
> host_op_rate 203581 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9711995066 # Simulator tick rate (ticks/s)
> host_mem_usage 728604 # Number of bytes of host memory used
> host_seconds 5319.98 # Real time elapsed on the host
> sim_insts 921741550 # Number of instructions simulated
> sim_ops 1083047600 # Number of ops (including micro ops) simulated
16,24c16,24
< system.physmem.bytes_read::cpu.dtb.walker 407680 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 346624 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 10124864 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 101217736 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 409088 # Number of bytes read from this memory
< system.physmem.bytes_read::total 112505992 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 10124864 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 10124864 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 94737216 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 358592 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 308608 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 10084224 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 94130760 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 400576 # Number of bytes read from this memory
> system.physmem.bytes_read::total 105282760 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 10084224 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 10084224 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 87776448 # Number of bytes written to this memory
26,33c26,33
< system.physmem.bytes_written::total 94757796 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 6370 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 5416 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 158201 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1581540 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6392 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1757919 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1480269 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 87797028 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 5603 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 4822 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 157566 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1470806 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6259 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1645056 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1371507 # Number of write requests responded to by this memory
35,44c35,44
< system.physmem.num_writes::total 1482842 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 7886 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 6705 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 195861 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1958012 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 7914 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2176379 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 195861 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 195861 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1832650 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1374080 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 6940 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 5973 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 195175 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1821853 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 7753 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2037695 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 195175 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 195175 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1698869 # Write bandwidth from this memory (bytes/s)
46,97c46,97
< system.physmem.bw_write::total 1833048 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1832650 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 7886 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 6705 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 195861 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1958410 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 7914 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4009426 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1757919 # Number of read requests accepted
< system.physmem.writeReqs 1482842 # Number of write requests accepted
< system.physmem.readBursts 1757919 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1482842 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 112457536 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 49280 # Total number of bytes read from write queue
< system.physmem.bytesWritten 94756288 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 112505992 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 94757796 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 770 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 146200 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 105973 # Per bank write bursts
< system.physmem.perBankRdBursts::1 111407 # Per bank write bursts
< system.physmem.perBankRdBursts::2 105002 # Per bank write bursts
< system.physmem.perBankRdBursts::3 101812 # Per bank write bursts
< system.physmem.perBankRdBursts::4 108332 # Per bank write bursts
< system.physmem.perBankRdBursts::5 117578 # Per bank write bursts
< system.physmem.perBankRdBursts::6 104534 # Per bank write bursts
< system.physmem.perBankRdBursts::7 108687 # Per bank write bursts
< system.physmem.perBankRdBursts::8 103848 # Per bank write bursts
< system.physmem.perBankRdBursts::9 161007 # Per bank write bursts
< system.physmem.perBankRdBursts::10 107405 # Per bank write bursts
< system.physmem.perBankRdBursts::11 110838 # Per bank write bursts
< system.physmem.perBankRdBursts::12 104563 # Per bank write bursts
< system.physmem.perBankRdBursts::13 103815 # Per bank write bursts
< system.physmem.perBankRdBursts::14 100822 # Per bank write bursts
< system.physmem.perBankRdBursts::15 101526 # Per bank write bursts
< system.physmem.perBankWrBursts::0 90430 # Per bank write bursts
< system.physmem.perBankWrBursts::1 94995 # Per bank write bursts
< system.physmem.perBankWrBursts::2 91678 # Per bank write bursts
< system.physmem.perBankWrBursts::3 90022 # Per bank write bursts
< system.physmem.perBankWrBursts::4 94229 # Per bank write bursts
< system.physmem.perBankWrBursts::5 99888 # Per bank write bursts
< system.physmem.perBankWrBursts::6 89385 # Per bank write bursts
< system.physmem.perBankWrBursts::7 93994 # Per bank write bursts
< system.physmem.perBankWrBursts::8 90076 # Per bank write bursts
< system.physmem.perBankWrBursts::9 95745 # Per bank write bursts
< system.physmem.perBankWrBursts::10 91874 # Per bank write bursts
< system.physmem.perBankWrBursts::11 95898 # Per bank write bursts
< system.physmem.perBankWrBursts::12 91438 # Per bank write bursts
< system.physmem.perBankWrBursts::13 92023 # Per bank write bursts
< system.physmem.perBankWrBursts::14 89075 # Per bank write bursts
< system.physmem.perBankWrBursts::15 89817 # Per bank write bursts
---
> system.physmem.bw_write::total 1699267 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1698869 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 6940 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 5973 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 195175 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1822252 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 7753 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3736962 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1645056 # Number of read requests accepted
> system.physmem.writeReqs 1374080 # Number of write requests accepted
> system.physmem.readBursts 1645056 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1374080 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 105226304 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 57280 # Total number of bytes read from write queue
> system.physmem.bytesWritten 87795840 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 105282760 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 87797028 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 895 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 144878 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 98762 # Per bank write bursts
> system.physmem.perBankRdBursts::1 104908 # Per bank write bursts
> system.physmem.perBankRdBursts::2 100268 # Per bank write bursts
> system.physmem.perBankRdBursts::3 95741 # Per bank write bursts
> system.physmem.perBankRdBursts::4 100817 # Per bank write bursts
> system.physmem.perBankRdBursts::5 109226 # Per bank write bursts
> system.physmem.perBankRdBursts::6 96584 # Per bank write bursts
> system.physmem.perBankRdBursts::7 96517 # Per bank write bursts
> system.physmem.perBankRdBursts::8 93312 # Per bank write bursts
> system.physmem.perBankRdBursts::9 154793 # Per bank write bursts
> system.physmem.perBankRdBursts::10 99831 # Per bank write bursts
> system.physmem.perBankRdBursts::11 102735 # Per bank write bursts
> system.physmem.perBankRdBursts::12 98206 # Per bank write bursts
> system.physmem.perBankRdBursts::13 101977 # Per bank write bursts
> system.physmem.perBankRdBursts::14 93251 # Per bank write bursts
> system.physmem.perBankRdBursts::15 97233 # Per bank write bursts
> system.physmem.perBankWrBursts::0 83938 # Per bank write bursts
> system.physmem.perBankWrBursts::1 86643 # Per bank write bursts
> system.physmem.perBankWrBursts::2 85449 # Per bank write bursts
> system.physmem.perBankWrBursts::3 83391 # Per bank write bursts
> system.physmem.perBankWrBursts::4 87884 # Per bank write bursts
> system.physmem.perBankWrBursts::5 92979 # Per bank write bursts
> system.physmem.perBankWrBursts::6 83797 # Per bank write bursts
> system.physmem.perBankWrBursts::7 84591 # Per bank write bursts
> system.physmem.perBankWrBursts::8 82134 # Per bank write bursts
> system.physmem.perBankWrBursts::9 88444 # Per bank write bursts
> system.physmem.perBankWrBursts::10 84764 # Per bank write bursts
> system.physmem.perBankWrBursts::11 87315 # Per bank write bursts
> system.physmem.perBankWrBursts::12 85408 # Per bank write bursts
> system.physmem.perBankWrBursts::13 87944 # Per bank write bursts
> system.physmem.perBankWrBursts::14 81647 # Per bank write bursts
> system.physmem.perBankWrBursts::15 85482 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 27 # Number of times write queue was full causing retry
< system.physmem.totGap 51694123514000 # Total gap between requests
---
> system.physmem.numWrRetry 15 # Number of times write queue was full causing retry
> system.physmem.totGap 51667583532000 # Total gap between requests
107c107
< system.physmem.readPktSize::6 1757904 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1645041 # Read request sizes (log2)
114,134c114,134
< system.physmem.writePktSize::6 1480269 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1422025 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 328688 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 1048 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 351 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 481 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 469 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 522 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 773 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 906 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 358 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 190 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 77 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1371507 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1321455 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 316451 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 938 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 316 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 463 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 518 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1146 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 697 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 315 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 350 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 161 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 101 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 50 # What read queue length does an incoming req see
136c136
< system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
162,228c162,228
< system.physmem.wrQLenPdf::15 15568 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 18151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 71947 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 88213 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 88480 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 88386 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 88377 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 91264 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 92065 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 94405 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 93246 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 93724 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 90170 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 90391 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 100271 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 88772 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 90332 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 87233 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 738 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 612 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 700 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 613 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 492 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 421 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 484 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 399 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 400 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 281 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 261 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 263 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 253 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 271 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 253 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 244 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 219 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 182 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 159 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 129 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 83 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 690739 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 299.988042 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 174.369601 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 327.443819 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 271817 39.35% 39.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 165800 24.00% 63.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 63380 9.18% 72.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 36796 5.33% 77.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 26984 3.91% 81.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 18833 2.73% 84.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 14857 2.15% 86.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 13605 1.97% 88.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 78667 11.39% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 690739 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 86593 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 20.291686 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 270.345126 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 86590 100.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 15056 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 17226 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 66293 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 80848 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 82840 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 82796 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 83570 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 83932 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 85472 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 84523 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 85247 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 89567 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 84372 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 83217 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 92227 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 82440 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 83507 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 80252 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1030 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 604 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 418 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 449 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 392 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 379 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 396 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 370 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 331 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 325 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 325 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 366 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 288 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 288 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 310 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 334 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 190 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 212 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 178 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 156 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 54 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 46 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 646368 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 298.625675 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 174.464471 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 324.594716 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 252807 39.11% 39.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 155954 24.13% 63.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 60049 9.29% 72.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 34895 5.40% 77.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 25863 4.00% 81.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 18951 2.93% 84.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 14056 2.17% 87.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 13035 2.02% 89.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 70758 10.95% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 646368 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 79614 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 20.651179 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 282.749901 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-4095 79611 100.00% 100.00% # Reads before turning the bus around for writes
232,263c232,263
< system.physmem.rdPerTurnAround::total 86593 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 86593 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.097999 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.728630 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 5.809360 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 84121 97.15% 97.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 149 0.17% 97.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 413 0.48% 97.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 198 0.23% 98.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 310 0.36% 98.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 507 0.59% 98.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 123 0.14% 99.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 35 0.04% 99.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 41 0.05% 99.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 24 0.03% 99.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 40 0.05% 99.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 29 0.03% 99.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 413 0.48% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 31 0.04% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 42 0.05% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 40 0.05% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 8 0.01% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 4 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 4 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 4 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 31 0.04% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 2 0.00% 99.98% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 79614 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 79614 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.230763 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.794029 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 6.276538 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 77327 97.13% 97.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 304 0.38% 97.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 53 0.07% 97.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 307 0.39% 97.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 57 0.07% 98.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 338 0.42% 98.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 219 0.28% 98.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 23 0.03% 98.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 64 0.08% 98.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 131 0.16% 99.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 34 0.04% 99.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 35 0.04% 99.09% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 493 0.62% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 27 0.03% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 21 0.03% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 122 0.15% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 7 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.00% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.00% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 2 0.00% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 4 0.01% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 27 0.03% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads
265,275c265,272
< system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 2 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 4 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 86593 # Writes before turning the bus around for reads
< system.physmem.totQLat 26847024830 # Total ticks spent queuing
< system.physmem.totMemAccLat 59793568580 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 8785745000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 15278.74 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 3 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 79614 # Writes before turning the bus around for reads
> system.physmem.totQLat 26413369588 # Total ticks spent queuing
> system.physmem.totMemAccLat 57241388338 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 8220805000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 16064.95 # Average queueing delay per DRAM burst
277,281c274,278
< system.physmem.avgMemAccLat 34028.74 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.18 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 34814.95 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2.04 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.70 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 2.04 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.70 # Average system write bandwidth in MiByte/s
287,304c284,301
< system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing
< system.physmem.readRowHits 1436721 # Number of row buffer hits during reads
< system.physmem.writeRowHits 1110255 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 81.76 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.99 # Row buffer hit rate for writes
< system.physmem.avgGap 15951229.82 # Average gap between requests
< system.physmem.pageHitRate 78.67 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 2651919480 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1446979875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 6733888200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 4825144080 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3376408666800 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1308234674070 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 29868898243500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 34569199516005 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.725939 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 49688706621634 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1726180300000 # Time in different power states
---
> system.physmem.avgWrQLen 21.46 # Average write queue length when enqueuing
> system.physmem.readRowHits 1338705 # Number of row buffer hits during reads
> system.physmem.writeRowHits 1030897 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 75.15 # Row buffer hit rate for writes
> system.physmem.avgGap 17113367.38 # Average gap between requests
> system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 2462533920 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1343644500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 6262011600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 4462594560 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3374675494320 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1320469447905 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 29842244670000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 34551920396805 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.734956 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 49644314314893 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1725294220000 # Time in different power states
306c303
< system.physmem_0.memoryStateTime::ACT 279237825366 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 297976817607 # Time in different power states
308,318c305,315
< system.physmem_1.actEnergy 2570067360 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1402318500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 6971827200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 4768930080 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3376408666800 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1306063695690 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 29870802610500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 34568988116130 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.721850 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 49691848230640 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1726180300000 # Time in different power states
---
> system.physmem_1.actEnergy 2424008160 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1322623500 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 6562436400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 4426734240 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3374675494320 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1320896835045 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 29841869760750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 34552177892415 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.739940 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 49643648149046 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1725294220000 # Time in different power states
320c317
< system.physmem_1.memoryStateTime::ACT 276092348110 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 298642969704 # Time in different power states
344,348c341,345
< system.cpu.branchPred.lookups 260286663 # Number of BP lookups
< system.cpu.branchPred.condPredicted 182589592 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 12077009 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 191806323 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 136128585 # Number of BTB hits
---
> system.cpu.branchPred.lookups 252423071 # Number of BP lookups
> system.cpu.branchPred.condPredicted 176427079 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 11938474 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 185221577 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 131501265 # Number of BTB hits
350,352c347,349
< system.cpu.branchPred.BTBHitPct 70.971896 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 31602025 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 2167880 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 70.996731 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 30906734 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 2133609 # Number of incorrect RAS predictions.
383,410c380,409
< system.cpu.dtb.walker.walks 582770 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 582770 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22376 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191329 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 582770 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 582770 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 582770 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 213705 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 26351.678716 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 22931.447770 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 15578.711548 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-65535 211142 98.80% 98.80% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-131071 2168 1.01% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-196607 149 0.07% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::196608-262143 124 0.06% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::262144-327679 84 0.04% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 213705 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples -58656296 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0 -58656296 100.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total -58656296 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 191330 89.53% 89.53% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::2M 22376 10.47% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 213706 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 582770 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walks 560833 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 560833 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21083 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178899 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 560833 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 560833 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 560833 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 199982 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 27029.240132 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 22851.547546 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 20760.636291 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-65535 197624 98.82% 98.82% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 98.82% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-196607 2039 1.02% 99.84% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::196608-262143 52 0.03% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-327679 109 0.05% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::327680-393215 52 0.03% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::393216-458751 79 0.04% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 199982 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples -1571833592 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0 -1571833592 100.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total -1571833592 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 178900 89.46% 89.46% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::2M 21083 10.54% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 199983 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560833 # Table walker requests started/completed, data/inst
412,413c411,412
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 582770 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213706 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560833 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199983 # Table walker requests started/completed, data/inst
415,416c414,415
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213706 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 796476 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199983 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 760816 # Table walker requests started/completed, data/inst
419,422c418,421
< system.cpu.dtb.read_hits 183257458 # DTB read hits
< system.cpu.dtb.read_misses 481031 # DTB read misses
< system.cpu.dtb.write_hits 162586595 # DTB write hits
< system.cpu.dtb.write_misses 101739 # DTB write misses
---
> system.cpu.dtb.read_hits 178232351 # DTB read hits
> system.cpu.dtb.read_misses 463077 # DTB read misses
> system.cpu.dtb.write_hits 157845440 # DTB write hits
> system.cpu.dtb.write_misses 97756 # DTB write misses
425,429c424,428
< system.cpu.dtb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID
< system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID
< system.cpu.dtb.flush_entries 80339 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 1450 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 15121 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID
> system.cpu.dtb.flush_entries 77809 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 1378 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 14628 # Number of TLB faults due to prefetch
431,433c430,432
< system.cpu.dtb.perms_faults 23575 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 183738489 # DTB read accesses
< system.cpu.dtb.write_accesses 162688334 # DTB write accesses
---
> system.cpu.dtb.perms_faults 23069 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 178695428 # DTB read accesses
> system.cpu.dtb.write_accesses 157943196 # DTB write accesses
435,437c434,436
< system.cpu.dtb.hits 345844053 # DTB hits
< system.cpu.dtb.misses 582770 # DTB misses
< system.cpu.dtb.accesses 346426823 # DTB accesses
---
> system.cpu.dtb.hits 336077791 # DTB hits
> system.cpu.dtb.misses 560833 # DTB misses
> system.cpu.dtb.accesses 336638624 # DTB accesses
467,493c466,492
< system.cpu.itb.walker.walks 136614 # Table walker walks requested
< system.cpu.itb.walker.walksLong 136614 # Table walker walks initiated with long descriptors
< system.cpu.itb.walker.walksLongTerminationLevel::Level2 1073 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksLongTerminationLevel::Level3 118911 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walkWaitTime::samples 136614 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 136614 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 136614 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 119984 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 28837.324143 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 25253.165818 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 17670.490053 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-65535 116985 97.50% 97.50% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::65536-131071 2707 2.26% 99.76% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::131072-196607 180 0.15% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::196608-262143 56 0.05% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::262144-327679 24 0.02% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::327680-393215 27 0.02% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 119984 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples -59528796 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 -59528796 100.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total -59528796 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 118911 99.11% 99.11% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::2M 1073 0.89% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 119984 # Table walker page sizes translated
---
> system.cpu.itb.walker.walks 134950 # Table walker walks requested
> system.cpu.itb.walker.walksLong 134950 # Table walker walks initiated with long descriptors
> system.cpu.itb.walker.walksLongTerminationLevel::Level2 1074 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksLongTerminationLevel::Level3 117621 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walkWaitTime::samples 134950 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 134950 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 134950 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 118695 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 30170.011374 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 25640.228509 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 23413.242871 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-65535 115997 97.73% 97.73% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 97.73% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-196607 2500 2.11% 99.84% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::196608-262143 50 0.04% 99.88% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::262144-327679 104 0.09% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::327680-393215 27 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 118695 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples -1572850092 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 -1572850092 100.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total -1572850092 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 117621 99.10% 99.10% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::2M 1074 0.90% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 118695 # Table walker page sizes translated
495,496c494,495
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136614 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 136614 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134950 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 134950 # Table walker requests started/completed, data/inst
498,502c497,501
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119984 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 119984 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 256598 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 452975639 # ITB inst hits
< system.cpu.itb.inst_misses 136614 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118695 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 118695 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 253645 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 438786222 # ITB inst hits
> system.cpu.itb.inst_misses 134950 # ITB inst misses
509,511c508,510
< system.cpu.itb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID
< system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID
< system.cpu.itb.flush_entries 57698 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID
> system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID
> system.cpu.itb.flush_entries 55568 # Number of entries that have been flushed from TLB
515c514
< system.cpu.itb.perms_faults 370160 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 357024 # Number of TLB faults due to permissions restrictions
518,522c517,521
< system.cpu.itb.inst_accesses 453112253 # ITB inst accesses
< system.cpu.itb.hits 452975639 # DTB hits
< system.cpu.itb.misses 136614 # DTB misses
< system.cpu.itb.accesses 453112253 # DTB accesses
< system.cpu.numCycles 2511767999 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 438921172 # ITB inst accesses
> system.cpu.itb.hits 438786222 # DTB hits
> system.cpu.itb.misses 134950 # DTB misses
> system.cpu.itb.accesses 438921172 # DTB accesses
> system.cpu.numCycles 2561969113 # number of cpu cycles simulated
525,531c524,530
< system.cpu.committedInsts 949163000 # Number of instructions committed
< system.cpu.committedOps 1115282140 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 97160712 # Number of ops (including micro ops) which were discarded before commit
< system.cpu.numFetchSuspends 7743 # Number of times Execute suspended instruction fetching
< system.cpu.quiesceCycles 100877722288 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.646298 # CPI: cycles per instruction
< system.cpu.ipc 0.377886 # IPC: instructions per cycle
---
> system.cpu.committedInsts 921741550 # Number of instructions committed
> system.cpu.committedOps 1083047600 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 92851518 # Number of ops (including micro ops) which were discarded before commit
> system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching
> system.cpu.quiesceCycles 100774422273 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.779487 # CPI: cycles per instruction
> system.cpu.ipc 0.359779 # IPC: instructions per cycle
533,544c532,543
< system.cpu.kern.inst.quiesce 19481 # number of quiesce instructions executed
< system.cpu.tickCycles 1790897935 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 720870064 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 11142195 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.957822 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 329410408 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 11142707 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 29.562871 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 4277412500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.957822 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999918 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999918 # Average percentage of cache occupancy
---
> system.cpu.kern.inst.quiesce 19360 # number of quiesce instructions executed
> system.cpu.tickCycles 1740348403 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 821620710 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 10715341 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.930095 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 320246754 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 10715853 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 29.885325 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 7085883500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.930095 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy
546c545
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
548a548
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
550,577c550,577
< system.cpu.dcache.tags.tag_accesses 1384553632 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1384553632 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 168394927 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 168394927 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 151754199 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 151754199 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 523439 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 523439 # number of SoftPFReq hits
< system.cpu.dcache.WriteLineReq_hits::cpu.data 336679 # number of WriteLineReq hits
< system.cpu.dcache.WriteLineReq_hits::total 336679 # number of WriteLineReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 4017108 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 4017108 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 4334477 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 4334477 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 320149126 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 320149126 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 320672565 # number of overall hits
< system.cpu.dcache.overall_hits::total 320672565 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 6628843 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 6628843 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 4317749 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 4317749 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 1481094 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 1481094 # number of SoftPFReq misses
< system.cpu.dcache.WriteLineReq_misses::cpu.data 1245106 # number of WriteLineReq misses
< system.cpu.dcache.WriteLineReq_misses::total 1245106 # number of WriteLineReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 319103 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 319103 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 1345291071 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1345291071 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 163948346 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 163948346 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 147386054 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 147386054 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 512627 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 512627 # number of SoftPFReq hits
> system.cpu.dcache.WriteLineReq_hits::cpu.data 336269 # number of WriteLineReq hits
> system.cpu.dcache.WriteLineReq_hits::total 336269 # number of WriteLineReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 3854490 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 3854490 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 4160967 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 4160967 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 311334400 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 311334400 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 311847027 # number of overall hits
> system.cpu.dcache.overall_hits::total 311847027 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 6367020 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 6367020 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 4130399 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 4130399 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 1400627 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 1400627 # number of SoftPFReq misses
> system.cpu.dcache.WriteLineReq_misses::cpu.data 1238807 # number of WriteLineReq misses
> system.cpu.dcache.WriteLineReq_misses::total 1238807 # number of WriteLineReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 308186 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 308186 # number of LoadLockedReq misses
580,623c580,623
< system.cpu.dcache.demand_misses::cpu.data 10946592 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 10946592 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 12427686 # number of overall misses
< system.cpu.dcache.overall_misses::total 12427686 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 107264639000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 107264639000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 153170066000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 153170066000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 58641269000 # number of WriteLineReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::total 58641269000 # number of WriteLineReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4837420500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 4837420500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 115500 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 115500 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 260434705000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 260434705000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 260434705000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 260434705000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 175023770 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 175023770 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 156071948 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 156071948 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 2004533 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 2004533 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::cpu.data 1581785 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::total 1581785 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4336211 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 4336211 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 4334479 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 4334479 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 331095718 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 331095718 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 333100251 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 333100251 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037874 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.037874 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027665 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.027665 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738872 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.738872 # miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787152 # miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::total 0.787152 # miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073590 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073590 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_misses::cpu.data 10497419 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 10497419 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 11898046 # number of overall misses
> system.cpu.dcache.overall_misses::total 11898046 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 117617695000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 117617695000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 201217455000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 201217455000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 84065023500 # number of WriteLineReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::total 84065023500 # number of WriteLineReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5131918500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 5131918500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 318835150000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 318835150000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 318835150000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 318835150000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 170315366 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 170315366 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 151516453 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 151516453 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 1913254 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 1913254 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::cpu.data 1575076 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::total 1575076 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4162676 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 4162676 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 4160969 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 4160969 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 321831819 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 321831819 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 323745073 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 323745073 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037384 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.037384 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027260 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.027260 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.732065 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.732065 # miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786506 # miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::total 0.786506 # miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074036 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074036 # miss rate for LoadLockedReq accesses
626,643c626,643
< system.cpu.dcache.demand_miss_rate::cpu.data 0.033062 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.033062 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.037309 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.037309 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16181.502413 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16181.502413 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35474.518320 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 35474.518320 # average WriteReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 47097.410983 # average WriteLineReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::total 47097.410983 # average WriteLineReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15159.432848 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15159.432848 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 57750 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 57750 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 23791.395989 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 23791.395989 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 20956.009429 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 20956.009429 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.032618 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.032618 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.036751 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.036751 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18472.958307 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 18472.958307 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48716.226931 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 48716.226931 # average WriteReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 67859.661352 # average WriteLineReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::total 67859.661352 # average WriteLineReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16652.016964 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16652.016964 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 30372.718284 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 30372.718284 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 26797.269905 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 26797.269905 # average overall miss latency
652,675c652,675
< system.cpu.dcache.writebacks::writebacks 8554549 # number of writebacks
< system.cpu.dcache.writebacks::total 8554549 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 817761 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 817761 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1903794 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1903794 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 151 # number of WriteLineReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::total 151 # number of WriteLineReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70489 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 70489 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2721555 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2721555 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2721555 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2721555 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5811082 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 5811082 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2413955 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2413955 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1473693 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 1473693 # number of SoftPFReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1244955 # number of WriteLineReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::total 1244955 # number of WriteLineReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 248614 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 248614 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 8224375 # number of writebacks
> system.cpu.dcache.writebacks::total 8224375 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 782628 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 782628 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821080 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1821080 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 142 # number of WriteLineReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::total 142 # number of WriteLineReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69834 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 69834 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2603708 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2603708 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2603708 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2603708 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5584392 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 5584392 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2309319 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2309319 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1393093 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 1393093 # number of SoftPFReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238665 # number of WriteLineReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::total 1238665 # number of WriteLineReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 238352 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 238352 # number of LoadLockedReq MSHR misses
678,719c678,719
< system.cpu.dcache.demand_mshr_misses::cpu.data 8225037 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 8225037 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 9698730 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9698730 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33699 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.ReadReq_mshr_uncacheable::total 33699 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67406 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 67406 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87944699500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 87944699500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80337194000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 80337194000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23656791000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23656791000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 57392051500 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 57392051500 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3386354500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3386354500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 113500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 113500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168281893500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 168281893500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191938684500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 191938684500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5830552000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5830552000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5692063000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5692063000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11522615000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11522615000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033202 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033202 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015467 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015467 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.735180 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.735180 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787057 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787057 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057334 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057334 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 7893711 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 7893711 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9286804 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9286804 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96186724500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 96186724500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106755322500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 106755322500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26816989500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26816989500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 82819161500 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 82819161500 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3465009000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3465009000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202942047000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 202942047000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229759036500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 229759036500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5830985000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5830985000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5820481500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5820481500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11651466500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 11651466500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032789 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032789 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015241 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015241 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728128 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728128 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786416 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786416 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057259 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057259 # mshr miss rate for LoadLockedReq accesses
722,747c722,747
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024842 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.024842 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029117 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.029117 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15133.962918 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15133.962918 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33280.319641 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33280.319641 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16052.726721 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.726721 # average SoftPFReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 46099.699588 # average WriteLineReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 46099.699588 # average WriteLineReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13620.932450 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13620.932450 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 56750 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 56750 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20459.712643 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 20459.712643 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19790.084320 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 19790.084320 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173018.546544 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173018.546544 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168868.869968 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168868.869968 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170943.462006 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170943.462006 # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024527 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.024527 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028686 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.028686 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17224.207129 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17224.207129 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46228.053595 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46228.053595 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19249.963570 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19249.963570 # average SoftPFReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 66861.630465 # average WriteLineReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 66861.630465 # average WriteLineReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14537.360710 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14537.360710 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25709.333291 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 25709.333291 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24740.377475 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24740.377475 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173041.665430 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173041.665430 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172683.839672 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172683.839672 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172862.728662 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172862.728662 # average overall mshr uncacheable latency
749,757c749,757
< system.cpu.icache.tags.replacements 24575522 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.918698 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 428017274 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 24576034 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 17.416043 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 26893274500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.918698 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999841 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999841 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 24143027 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.872432 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 414273354 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 24143539 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 17.158767 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 39477111500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.872432 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy
759,761c759,761
< system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 115 # Occupied blocks per task id
763,800c763,800
< system.cpu.icache.tags.tag_accesses 477169361 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 477169361 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 428017274 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 428017274 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 428017274 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 428017274 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 428017274 # number of overall hits
< system.cpu.icache.overall_hits::total 428017274 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 24576044 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 24576044 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 24576044 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 24576044 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 24576044 # number of overall misses
< system.cpu.icache.overall_misses::total 24576044 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 327136040500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 327136040500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 327136040500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 327136040500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 327136040500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 327136040500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 452593318 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 452593318 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 452593318 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 452593318 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 452593318 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 452593318 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054301 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.054301 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.054301 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.054301 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.054301 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.054301 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13311.175733 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13311.175733 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13311.175733 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13311.175733 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13311.175733 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13311.175733 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 462560451 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 462560451 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 414273354 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 414273354 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 414273354 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 414273354 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 414273354 # number of overall hits
> system.cpu.icache.overall_hits::total 414273354 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 24143549 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 24143549 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 24143549 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 24143549 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 24143549 # number of overall misses
> system.cpu.icache.overall_misses::total 24143549 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 326781938000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 326781938000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 326781938000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 326781938000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 326781938000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 326781938000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 438416903 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 438416903 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 438416903 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 438416903 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 438416903 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 438416903 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055070 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.055070 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.055070 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.055070 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.055070 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.055070 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13534.958676 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13534.958676 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13534.958676 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13534.958676 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13534.958676 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13534.958676 # average overall miss latency
809,844c809,844
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24576044 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 24576044 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 24576044 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 24576044 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 24576044 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 24576044 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52295 # number of ReadReq MSHR uncacheable
< system.cpu.icache.ReadReq_mshr_uncacheable::total 52295 # number of ReadReq MSHR uncacheable
< system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52295 # number of overall MSHR uncacheable misses
< system.cpu.icache.overall_mshr_uncacheable_misses::total 52295 # number of overall MSHR uncacheable misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302559997500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 302559997500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302559997500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 302559997500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302559997500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 302559997500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4042938500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4042938500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4042938500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 4042938500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054301 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.054301 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.054301 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12311.175773 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12311.175773 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12311.175773 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12311.175773 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12311.175773 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12311.175773 # average overall mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77310.230424 # average ReadReq mshr uncacheable latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77310.230424 # average ReadReq mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77310.230424 # average overall mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77310.230424 # average overall mshr uncacheable latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24143549 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 24143549 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 24143549 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 24143549 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 24143549 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 24143549 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable
> system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable
> system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses
> system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302638390000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 302638390000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302638390000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 302638390000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302638390000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 302638390000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746821500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746821500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746821500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 6746821500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055070 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055070 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055070 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.055070 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055070 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.055070 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12534.958717 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12534.958717 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12534.958717 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12534.958717 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12534.958717 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12534.958717 # average overall mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.127703 # average ReadReq mshr uncacheable latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.127703 # average ReadReq mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.127703 # average overall mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.127703 # average overall mshr uncacheable latency
846,905c846,905
< system.cpu.l2cache.tags.replacements 1607082 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65318.726670 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 67354503 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1670310 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 40.324552 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 24502286000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 36002.307210 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 335.180696 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 433.791675 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 8203.980766 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 20343.466323 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.549352 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005114 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006619 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125183 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.310417 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996685 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 219 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 63009 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 524 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2413 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5473 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54554 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003342 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961441 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 587356710 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 587356710 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 972528 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 286301 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1258829 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 8554549 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 8554549 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 10855 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 10855 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1654669 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1654669 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24470106 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 24470106 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7204785 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 7204785 # number of ReadSharedReq hits
< system.cpu.l2cache.InvalidateReq_hits::cpu.data 700263 # number of InvalidateReq hits
< system.cpu.l2cache.InvalidateReq_hits::total 700263 # number of InvalidateReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 972528 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 286301 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 24470106 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 8859454 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 34588389 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 972528 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 286301 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 24470106 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 8859454 # number of overall hits
< system.cpu.l2cache.overall_hits::total 34588389 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6370 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5416 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 11786 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 38716 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 38716 # number of UpgradeReq misses
---
> system.cpu.l2cache.tags.replacements 1493610 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65243.274249 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 65796130 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1556709 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 42.266172 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 36608904000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 36783.005624 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 344.357153 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 401.095680 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 8076.862900 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 19637.952892 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.561264 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005254 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006120 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123243 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.299651 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.995533 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 261 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 62838 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 440 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2477 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5563 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54301 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003983 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958832 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 572879965 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 572879965 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 917645 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 281080 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1198725 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 8224375 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 8224375 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 10494 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 10494 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1636293 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1636293 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24038260 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 24038260 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6896602 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 6896602 # number of ReadSharedReq hits
> system.cpu.l2cache.InvalidateReq_hits::cpu.data 710760 # number of InvalidateReq hits
> system.cpu.l2cache.InvalidateReq_hits::total 710760 # number of InvalidateReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 917645 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 281080 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 24038260 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 8532895 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 33769880 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 917645 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 281080 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 24038260 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 8532895 # number of overall hits
> system.cpu.l2cache.overall_hits::total 33769880 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5603 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4822 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 10425 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 37432 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 37432 # number of UpgradeReq misses
908,957c908,957
< system.cpu.l2cache.ReadExReq_misses::cpu.data 709953 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 709953 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 105935 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 105935 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 328366 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 328366 # number of ReadSharedReq misses
< system.cpu.l2cache.InvalidateReq_misses::cpu.data 544692 # number of InvalidateReq misses
< system.cpu.l2cache.InvalidateReq_misses::total 544692 # number of InvalidateReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 6370 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 5416 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 105935 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1038319 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1156040 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 6370 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 5416 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 105935 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1038319 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1156040 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 553122500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 470413000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1023535500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 578007500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 578007500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 110500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 110500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58013412000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 58013412000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8652629500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 8652629500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 27752985500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 27752985500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 47906162000 # number of InvalidateReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::total 47906162000 # number of InvalidateReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 553122500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 470413000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 8652629500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 85766397500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 95442562500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 553122500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 470413000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 8652629500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 85766397500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 95442562500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 978898 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 291717 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1270615 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 8554549 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 8554549 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49571 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 49571 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 625331 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 625331 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 105286 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 105286 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 319004 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 319004 # number of ReadSharedReq misses
> system.cpu.l2cache.InvalidateReq_misses::cpu.data 527905 # number of InvalidateReq misses
> system.cpu.l2cache.InvalidateReq_misses::total 527905 # number of InvalidateReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 5603 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 4822 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 105286 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 944335 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1060046 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 5603 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 4822 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 105286 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 944335 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1060046 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 765667000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 656318500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1421985500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1480581000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 1480581000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82954858000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 82954858000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13909310000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 13909310000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 42957675000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 42957675000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 73230952500 # number of InvalidateReq miss cycles
> system.cpu.l2cache.InvalidateReq_miss_latency::total 73230952500 # number of InvalidateReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 765667000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 656318500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 13909310000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 125912533000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 141243828500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 765667000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 656318500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 13909310000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 125912533000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 141243828500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 923248 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 285902 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1209150 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 8224375 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 8224375 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 47926 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 47926 # number of UpgradeReq accesses(hits+misses)
960,982c960,982
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2364622 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2364622 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24576041 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 24576041 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7533151 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 7533151 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1244955 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::total 1244955 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 978898 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 291717 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 24576041 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 9897773 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 35744429 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 978898 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 291717 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 24576041 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 9897773 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 35744429 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006507 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018566 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.781021 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.781021 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 2261624 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 2261624 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24143546 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 24143546 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7215606 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 7215606 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1238665 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::total 1238665 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 923248 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 285902 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 24143546 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 9477230 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 34829926 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 923248 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 285902 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 24143546 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 9477230 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 34829926 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006069 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.016866 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.008622 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.781037 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.781037 # miss rate for UpgradeReq accesses
985,1027c985,1027
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.300240 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.300240 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004310 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004310 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043589 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043589 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.437519 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::total 0.437519 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006507 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018566 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004310 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.104904 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.032342 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006507 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018566 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004310 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.104904 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.032342 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86832.417582 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86856.166913 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 86843.331071 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14929.421944 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14929.421944 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 55250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 55250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81714.440252 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81714.440252 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81678.666163 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81678.666163 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84518.450449 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84518.450449 # average ReadSharedReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 87950.919052 # average InvalidateReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 87950.919052 # average InvalidateReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86832.417582 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86856.166913 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81678.666163 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82601.202039 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 82559.913584 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86832.417582 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86856.166913 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81678.666163 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82601.202039 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 82559.913584 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.276496 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.276496 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004361 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004361 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044210 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044210 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.426189 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::total 0.426189 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006069 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.016866 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004361 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.099643 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.030435 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006069 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.016866 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004361 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.099643 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.030435 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136653.043013 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136109.187059 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 136401.486811 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39553.884377 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39553.884377 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.517379 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.517379 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132109.777178 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132109.777178 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134661.869444 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134661.869444 # average ReadSharedReq miss latency
> system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138719.944876 # average InvalidateReq miss latency
> system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138719.944876 # average InvalidateReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136653.043013 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136109.187059 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132109.777178 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133334.603716 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 133243.112563 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136653.043013 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136109.187059 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132109.777178 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133334.603716 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 133243.112563 # average overall miss latency
1036,1037c1036,1037
< system.cpu.l2cache.writebacks::writebacks 1373638 # number of writebacks
< system.cpu.l2cache.writebacks::total 1373638 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 1264876 # number of writebacks
> system.cpu.l2cache.writebacks::total 1264876 # number of writebacks
1040,1041c1040,1041
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits
---
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits
1043,1044c1043,1044
< system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits
1046,1054c1046,1054
< system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6370 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5416 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 11786 # number of ReadReq MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1102 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 1102 # number of CleanEvict MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38716 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 38716 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5603 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4822 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 10425 # number of ReadReq MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1101 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 1101 # number of CleanEvict MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37432 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 37432 # number of UpgradeReq MSHR misses
1057,1118c1057,1118
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 709953 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 709953 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 105932 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 105932 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 328345 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 328345 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 544692 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::total 544692 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6370 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5416 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 105932 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1038298 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1156016 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6370 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5416 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 105932 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1038298 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1156016 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52295 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33699 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85994 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52295 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67406 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119701 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 489422500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 416253000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 905675500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 803927500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 803927500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 90500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 90500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50913882000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50913882000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7593134000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7593134000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24468048000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24468048000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 42459242000 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 42459242000 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 489422500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 416253000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7593134000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75381930000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 83880739500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 489422500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 416253000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7593134000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75381930000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 83880739500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3232365500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5409250000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8641615500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5303815500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5303815500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3232365500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10713065500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13945431000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 625331 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 625331 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 105283 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 105283 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 318982 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 318982 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 527905 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::total 527905 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5603 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4822 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 105283 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 944313 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1060021 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5603 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4822 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 105283 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 944313 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1060021 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 86006 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119712 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 709637000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 608098500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1317735500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2648590000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2648590000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 76701548000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 76701548000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12856217500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12856217500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 39765420000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 39765420000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 67951902500 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 67951902500 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 709637000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 608098500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12856217500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116466968000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 130640921000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 709637000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 608098500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12856217500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116466968000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 130640921000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936031500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5409709500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11345741000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5432237500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5432237500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936031500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10841947000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16777978500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006069 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.016866 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008622 # mshr miss rate for ReadReq accesses
1121,1122c1121,1122
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781021 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781021 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781037 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781037 # mshr miss rate for UpgradeReq accesses
1125,1175c1125,1175
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.300240 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.300240 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004310 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043587 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.437519 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.437519 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104902 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.032341 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104902 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.032341 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76843.331071 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.735510 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.735510 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45250 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71714.440252 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71714.440252 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71679.322584 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71679.322584 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74519.325709 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74519.325709 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77950.919052 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77950.919052 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71679.322584 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72601.440049 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72560.189046 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71679.322584 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72601.440049 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72560.189046 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 61810.220862 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160516.632541 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.912157 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157350.565165 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157350.565165 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 61810.220862 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158933.410972 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116502.209672 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.276496 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.276496 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004361 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044207 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044207 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.426189 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.426189 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006069 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016866 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099640 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.030434 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006069 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016866 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099640 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.030434 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126653.043013 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126109.187059 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126401.486811 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70757.373370 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70757.373370 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122657.517379 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122657.517379 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122111.048317 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122111.048317 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124663.523334 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124663.523334 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128719.944876 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128719.944876 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126653.043013 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126109.187059 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122111.048317 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123335.131466 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123243.710266 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126653.043013 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126109.187059 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122111.048317 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123335.131466 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123243.710266 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160539.795828 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 131918.017348 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161165.296980 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161165.296980 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160852.588164 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 140152.854350 # average overall mshr uncacheable latency
1177,1183c1177,1189
< system.cpu.toL2Bus.trans_dist::ReadReq 1789463 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 33899423 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 10034845 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 27401014 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 49574 # Transaction distribution
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 70464557 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 35605124 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4387 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2275 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2275 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.trans_dist::ReadReq 1730195 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 33090138 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 9595897 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 26867205 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 47929 # Transaction distribution
1185,1205c1191,1211
< system.cpu.toL2Bus.trans_dist::UpgradeResp 49576 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2364622 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2364622 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 24576044 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 7542009 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 1351619 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateResp 1244955 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73828388 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33661752 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 699908 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2274176 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 110464224 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576213440 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1181188062 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2333736 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7831184 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 2767566422 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 2271727 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 75147333 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.047128 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.211913 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 47931 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 2261624 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 2261624 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 24143549 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 7224490 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 1345329 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateResp 1238665 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72531044 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32377896 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 689100 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2164239 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 107762279 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548534656 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1133143634 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2287216 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7385984 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 2691351490 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 2160503 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 73254310 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.009691 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.097963 # Request fanout histogram
1207,1209c1213,1215
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 71605763 95.29% 95.29% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 3541570 4.71% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 72544433 99.03% 99.03% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 709877 0.97% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1211,1214c1217,1220
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 75147333 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 45226020496 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 73254310 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 44006051993 # Layer occupancy (ticks)
1216c1222
< system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 1484899 # Layer occupancy (ticks)
1218c1224
< system.cpu.toL2Bus.respLayer0.occupancy 36946016966 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 36299896753 # Layer occupancy (ticks)
1220c1226
< system.cpu.toL2Bus.respLayer1.occupancy 15544978992 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 14910158065 # Layer occupancy (ticks)
1222c1228
< system.cpu.toL2Bus.respLayer2.occupancy 408213455 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 403245904 # Layer occupancy (ticks)
1224c1230
< system.cpu.toL2Bus.respLayer3.occupancy 1295285984 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 1241004972 # Layer occupancy (ticks)
1226,1227c1232,1233
< system.iobus.trans_dist::ReadReq 40306 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40306 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 40332 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40332 # Transaction distribution
1246,1247c1252,1253
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231022 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231022 # Packet count per connected master and slave (bytes)
1250c1256
< system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353806 # Packet count per connected master and slave (bytes)
1267,1268c1273,1274
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334520 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7334520 # Cumulative packet size per connected master and slave (bytes)
1271c1277
< system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size::total 7492440 # Cumulative packet size per connected master and slave (bytes)
1300c1306
< system.iobus.reqLayer27.occupancy 568890575 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 565934074 # Layer occupancy (ticks)
1306c1312
< system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147782000 # Layer occupancy (ticks)
1310,1311c1316,1317
< system.iocache.tags.replacements 115467 # number of replacements
< system.iocache.tags.tagsinuse 10.447125 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115493 # number of replacements
> system.iocache.tags.tagsinuse 10.440039 # Cycle average of tags in use
1313c1319
< system.iocache.tags.sampled_refs 115483 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks.
1315,1320c1321,1326
< system.iocache.tags.warmup_cycle 13147039080000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.519011 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 6.928115 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.219938 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.433007 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.652945 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 13160095445000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.520833 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 6.919206 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.220052 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.432450 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.652502 # Average percentage of cache occupancy
1324,1325c1330,1331
< system.iocache.tags.tag_accesses 1039722 # Number of tag accesses
< system.iocache.tags.data_accesses 1039722 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1039956 # Number of tag accesses
> system.iocache.tags.data_accesses 1039956 # Number of data accesses
1327,1328c1333,1334
< system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8847 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8884 # number of ReadReq misses
1334,1335c1340,1341
< system.iocache.demand_misses::realview.ide 8821 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8861 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8847 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8887 # number of demand (read+write) misses
1337,1338c1343,1344
< system.iocache.overall_misses::realview.ide 8821 # number of overall misses
< system.iocache.overall_misses::total 8861 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 8847 # number of overall misses
> system.iocache.overall_misses::total 8887 # number of overall misses
1340,1341c1346,1347
< system.iocache.ReadReq_miss_latency::realview.ide 1605437158 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1610506158 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1639357105 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1644426105 # number of ReadReq miss cycles
1344,1345c1350,1351
< system.iocache.WriteLineReq_miss_latency::realview.ide 12610481417 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 12610481417 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13823164969 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13823164969 # number of WriteLineReq miss cycles
1347,1348c1353,1354
< system.iocache.demand_miss_latency::realview.ide 1605437158 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1610857158 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 1639357105 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1644777105 # number of demand (read+write) miss cycles
1350,1351c1356,1357
< system.iocache.overall_miss_latency::realview.ide 1605437158 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1610857158 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 1639357105 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1644777105 # number of overall miss cycles
1353,1354c1359,1360
< system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8847 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8884 # number of ReadReq accesses(hits+misses)
1360,1361c1366,1367
< system.iocache.demand_accesses::realview.ide 8821 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8861 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8847 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8887 # number of demand (read+write) accesses
1363,1364c1369,1370
< system.iocache.overall_accesses::realview.ide 8821 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8861 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8847 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8887 # number of overall (read+write) accesses
1379,1380c1385,1386
< system.iocache.ReadReq_avg_miss_latency::realview.ide 182001.718399 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 181813.745541 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 185300.904826 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 185099.741670 # average ReadReq miss latency
1383,1384c1389,1390
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.218940 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118226.218940 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129595.411470 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 129595.411470 # average WriteLineReq miss latency
1386,1387c1392,1393
< system.iocache.demand_avg_miss_latency::realview.ide 182001.718399 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 181791.802054 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 185300.904826 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 185076.753123 # average overall miss latency
1389,1391c1395,1397
< system.iocache.overall_avg_miss_latency::realview.ide 182001.718399 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 181791.802054 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 31114 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 185300.904826 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 185076.753123 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 32638 # number of cycles access was blocked
1393c1399
< system.iocache.blocked::no_mshrs 3332 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3399 # number of cycles access was blocked
1395c1401
< system.iocache.avg_blocked_cycles::no_mshrs 9.337935 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 9.602236 # average number of cycles each access was blocked
1402,1403c1408,1409
< system.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8847 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8884 # number of ReadReq MSHR misses
1409,1410c1415,1416
< system.iocache.demand_mshr_misses::realview.ide 8821 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8861 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8847 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8887 # number of demand (read+write) MSHR misses
1412,1413c1418,1419
< system.iocache.overall_mshr_misses::realview.ide 8821 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8861 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 8847 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8887 # number of overall MSHR misses
1415,1416c1421,1422
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1164387158 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1167606158 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1197007105 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1200226105 # number of ReadReq MSHR miss cycles
1419,1420c1425,1426
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277281417 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7277281417 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8489964969 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8489964969 # number of WriteLineReq MSHR miss cycles
1422,1423c1428,1429
< system.iocache.demand_mshr_miss_latency::realview.ide 1164387158 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1167807158 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 1197007105 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1200427105 # number of demand (read+write) MSHR miss cycles
1425,1426c1431,1432
< system.iocache.overall_mshr_miss_latency::realview.ide 1164387158 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1167807158 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 1197007105 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1200427105 # number of overall MSHR miss cycles
1441,1442c1447,1448
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132001.718399 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 131813.745541 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135300.904826 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 135099.741670 # average ReadReq mshr miss latency
1445,1446c1451,1452
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.218940 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.218940 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79595.411470 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79595.411470 # average WriteLineReq mshr miss latency
1448,1449c1454,1455
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 132001.718399 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 131791.802054 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 135300.904826 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 135076.753123 # average overall mshr miss latency
1451,1452c1457,1458
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 132001.718399 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 131791.802054 # average overall mshr miss latency
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 135300.904826 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 135076.753123 # average overall mshr miss latency
1454,1460c1460,1466
< system.membus.trans_dist::ReadReq 85994 # Transaction distribution
< system.membus.trans_dist::ReadResp 540915 # Transaction distribution
< system.membus.trans_dist::WriteReq 33707 # Transaction distribution
< system.membus.trans_dist::WriteResp 33707 # Transaction distribution
< system.membus.trans_dist::Writeback 1480269 # Transaction distribution
< system.membus.trans_dist::CleanEvict 239619 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 39541 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 86006 # Transaction distribution
> system.membus.trans_dist::ReadResp 529580 # Transaction distribution
> system.membus.trans_dist::WriteReq 33706 # Transaction distribution
> system.membus.trans_dist::WriteResp 33706 # Transaction distribution
> system.membus.trans_dist::Writeback 1371507 # Transaction distribution
> system.membus.trans_dist::CleanEvict 234789 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 38219 # Transaction distribution
1462,1465c1468,1471
< system.membus.trans_dist::UpgradeResp 39543 # Transaction distribution
< system.membus.trans_dist::ReadExReq 1253823 # Transaction distribution
< system.membus.trans_dist::ReadExResp 1253823 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 454921 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 38221 # Transaction distribution
> system.membus.trans_dist::ReadExReq 1152452 # Transaction distribution
> system.membus.trans_dist::ReadExResp 1152452 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 443574 # Transaction distribution
1470,1475c1476,1481
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6922 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5195008 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5324666 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341395 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 341395 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5666061 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4853436 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4983088 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341164 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 341164 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5324252 # Packet count per connected master and slave (bytes)
1478,1485c1484,1491
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13844 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 200030316 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 200200734 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233472 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7233472 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 207434206 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 3131 # Total snoops (count)
< system.membus.snoop_fanout::samples 3697223 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185854828 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186025234 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7224960 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7224960 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 193250194 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 3290 # Total snoops (count)
> system.membus.snoop_fanout::samples 3469738 # Request fanout histogram
1490c1496
< system.membus.snoop_fanout::1 3697223 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 3469738 100.00% 100.00% # Request fanout histogram
1495,1496c1501,1502
< system.membus.snoop_fanout::total 3697223 # Request fanout histogram
< system.membus.reqLayer0.occupancy 102366500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3469738 # Request fanout histogram
> system.membus.reqLayer0.occupancy 102307500 # Layer occupancy (ticks)
1500c1506
< system.membus.reqLayer2.occupancy 5756000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5483000 # Layer occupancy (ticks)
1502c1508
< system.membus.reqLayer5.occupancy 9961724084 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 9286465077 # Layer occupancy (ticks)
1504c1510
< system.membus.respLayer2.occupancy 9396279986 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 8797329089 # Layer occupancy (ticks)
1506c1512
< system.membus.respLayer3.occupancy 228925719 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 228468079 # Layer occupancy (ticks)
1517c1523
< system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
---
> system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
1521c1527
< system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
---
> system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)