3,5c3,5
< sim_seconds 51.609999 # Number of seconds simulated
< sim_ticks 51609998980000 # Number of ticks simulated
< final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 51.610037 # Number of seconds simulated
> sim_ticks 51610036853000 # Number of ticks simulated
> final_tick 51610036853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 182485 # Simulator instruction rate (inst/s)
< host_op_rate 214421 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 9938249935 # Simulator tick rate (ticks/s)
< host_mem_usage 720032 # Number of bytes of host memory used
< host_seconds 5193.07 # Real time elapsed on the host
< sim_insts 947659008 # Number of instructions simulated
< sim_ops 1113505098 # Number of ops (including micro ops) simulated
---
> host_inst_rate 188716 # Simulator instruction rate (inst/s)
> host_op_rate 221745 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 10246213919 # Simulator tick rate (ticks/s)
> host_mem_usage 724572 # Number of bytes of host memory used
> host_seconds 5036.99 # Real time elapsed on the host
> sim_insts 950561948 # Number of instructions simulated
> sim_ops 1116924449 # Number of ops (including micro ops) simulated
16,24c16,24
< system.physmem.bytes_read::cpu.dtb.walker 398592 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 332160 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 10228032 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 65553800 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 419072 # Number of bytes read from this memory
< system.physmem.bytes_read::total 76931656 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 10228032 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 10228032 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 93992704 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 410048 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 340288 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 10352448 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 67122824 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 411200 # Number of bytes read from this memory
> system.physmem.bytes_read::total 78636808 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 10352448 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 10352448 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 95202624 # Number of bytes written to this memory
26,33c26,33
< system.physmem.bytes_written::total 94013284 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 6228 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 5190 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 159813 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1024291 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6548 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1202070 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1468636 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 95223204 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 6407 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 5317 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 161757 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1048807 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6425 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1228713 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1487541 # Number of write requests responded to by this memory
35,44c35,44
< system.physmem.num_writes::total 1471209 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 7723 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 6436 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 198179 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1270176 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 8120 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1490635 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 198179 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 198179 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1821211 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1490114 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 7945 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 6593 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 200590 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1300577 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 7967 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1523673 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 200590 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 200590 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1844653 # Write bandwidth from this memory (bytes/s)
46,97c46,97
< system.physmem.bw_write::total 1821610 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1821211 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 7723 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 6436 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 198179 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1270575 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 8120 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3312245 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1202070 # Number of read requests accepted
< system.physmem.writeReqs 2120779 # Number of write requests accepted
< system.physmem.readBursts 1202070 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 2120779 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 76896960 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue
< system.physmem.bytesWritten 132496640 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 76931656 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 135585764 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 50494 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 39336 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 72977 # Per bank write bursts
< system.physmem.perBankRdBursts::1 77412 # Per bank write bursts
< system.physmem.perBankRdBursts::2 73227 # Per bank write bursts
< system.physmem.perBankRdBursts::3 70716 # Per bank write bursts
< system.physmem.perBankRdBursts::4 69716 # Per bank write bursts
< system.physmem.perBankRdBursts::5 78531 # Per bank write bursts
< system.physmem.perBankRdBursts::6 70002 # Per bank write bursts
< system.physmem.perBankRdBursts::7 72888 # Per bank write bursts
< system.physmem.perBankRdBursts::8 66687 # Per bank write bursts
< system.physmem.perBankRdBursts::9 126636 # Per bank write bursts
< system.physmem.perBankRdBursts::10 72169 # Per bank write bursts
< system.physmem.perBankRdBursts::11 76842 # Per bank write bursts
< system.physmem.perBankRdBursts::12 69750 # Per bank write bursts
< system.physmem.perBankRdBursts::13 69617 # Per bank write bursts
< system.physmem.perBankRdBursts::14 66498 # Per bank write bursts
< system.physmem.perBankRdBursts::15 67847 # Per bank write bursts
< system.physmem.perBankWrBursts::0 128572 # Per bank write bursts
< system.physmem.perBankWrBursts::1 129591 # Per bank write bursts
< system.physmem.perBankWrBursts::2 133621 # Per bank write bursts
< system.physmem.perBankWrBursts::3 133794 # Per bank write bursts
< system.physmem.perBankWrBursts::4 127990 # Per bank write bursts
< system.physmem.perBankWrBursts::5 135547 # Per bank write bursts
< system.physmem.perBankWrBursts::6 129190 # Per bank write bursts
< system.physmem.perBankWrBursts::7 132517 # Per bank write bursts
< system.physmem.perBankWrBursts::8 125103 # Per bank write bursts
< system.physmem.perBankWrBursts::9 133352 # Per bank write bursts
< system.physmem.perBankWrBursts::10 128272 # Per bank write bursts
< system.physmem.perBankWrBursts::11 129497 # Per bank write bursts
< system.physmem.perBankWrBursts::12 125797 # Per bank write bursts
< system.physmem.perBankWrBursts::13 127747 # Per bank write bursts
< system.physmem.perBankWrBursts::14 124476 # Per bank write bursts
< system.physmem.perBankWrBursts::15 125194 # Per bank write bursts
---
> system.physmem.bw_write::total 1845052 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1844653 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 7945 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 6593 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 200590 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1300976 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 7967 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3368725 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1228713 # Number of read requests accepted
> system.physmem.writeReqs 2143008 # Number of write requests accepted
> system.physmem.readBursts 1228713 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 2143008 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 78600192 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 37440 # Total number of bytes read from write queue
> system.physmem.bytesWritten 133928256 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 78636808 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 137008420 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 585 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 50360 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 39728 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 75722 # Per bank write bursts
> system.physmem.perBankRdBursts::1 79954 # Per bank write bursts
> system.physmem.perBankRdBursts::2 72878 # Per bank write bursts
> system.physmem.perBankRdBursts::3 71278 # Per bank write bursts
> system.physmem.perBankRdBursts::4 72651 # Per bank write bursts
> system.physmem.perBankRdBursts::5 79829 # Per bank write bursts
> system.physmem.perBankRdBursts::6 73600 # Per bank write bursts
> system.physmem.perBankRdBursts::7 73320 # Per bank write bursts
> system.physmem.perBankRdBursts::8 65239 # Per bank write bursts
> system.physmem.perBankRdBursts::9 127420 # Per bank write bursts
> system.physmem.perBankRdBursts::10 73665 # Per bank write bursts
> system.physmem.perBankRdBursts::11 77478 # Per bank write bursts
> system.physmem.perBankRdBursts::12 72459 # Per bank write bursts
> system.physmem.perBankRdBursts::13 72712 # Per bank write bursts
> system.physmem.perBankRdBursts::14 69098 # Per bank write bursts
> system.physmem.perBankRdBursts::15 70825 # Per bank write bursts
> system.physmem.perBankWrBursts::0 130775 # Per bank write bursts
> system.physmem.perBankWrBursts::1 132563 # Per bank write bursts
> system.physmem.perBankWrBursts::2 131683 # Per bank write bursts
> system.physmem.perBankWrBursts::3 133448 # Per bank write bursts
> system.physmem.perBankWrBursts::4 132375 # Per bank write bursts
> system.physmem.perBankWrBursts::5 136941 # Per bank write bursts
> system.physmem.perBankWrBursts::6 129100 # Per bank write bursts
> system.physmem.perBankWrBursts::7 132855 # Per bank write bursts
> system.physmem.perBankWrBursts::8 124239 # Per bank write bursts
> system.physmem.perBankWrBursts::9 131924 # Per bank write bursts
> system.physmem.perBankWrBursts::10 130753 # Per bank write bursts
> system.physmem.perBankWrBursts::11 132768 # Per bank write bursts
> system.physmem.perBankWrBursts::12 128150 # Per bank write bursts
> system.physmem.perBankWrBursts::13 130180 # Per bank write bursts
> system.physmem.perBankWrBursts::14 126529 # Per bank write bursts
> system.physmem.perBankWrBursts::15 128346 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 166 # Number of times write queue was full causing retry
< system.physmem.totGap 51609997338500 # Total gap between requests
---
> system.physmem.numWrRetry 140 # Number of times write queue was full causing retry
> system.physmem.totGap 51610035211500 # Total gap between requests
107c107
< system.physmem.readPktSize::6 1202055 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1228698 # Read request sizes (log2)
114,125c114,125
< system.physmem.writePktSize::6 2118206 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1132428 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 62352 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 724 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 310 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 460 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 547 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 490 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 762 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 454 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1875 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 234 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 2140435 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1157126 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 64351 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 755 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 308 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 447 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 546 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 482 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 776 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 503 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1798 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 175 # What read queue length does an incoming req see
128,129c128,129
< system.physmem.rdQLenPdf::13 114 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 110 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::13 110 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 104 # What read queue length does an incoming req see
131,135c131,135
< system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 70 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see
162,228c162,228
< system.physmem.wrQLenPdf::15 51481 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 61019 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 101890 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 106045 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 113976 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 152332 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 126167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 115190 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 114656 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 107766 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 107346 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 140408 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 114567 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 109101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 121792 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 109844 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 105744 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 103641 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 5730 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 5398 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 6493 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 7698 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 7852 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 7029 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 7221 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 7920 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 6653 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 6549 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 5561 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 5785 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 4638 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 4213 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 3839 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 3050 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 2469 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1608 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 1325 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 953 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 771 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 631 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 600 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 605 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 519 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 469 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 428 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 385 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 337 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 232 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 344 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 720627 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 290.570872 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 167.798815 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 325.942314 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 295355 40.99% 40.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 175877 24.41% 65.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 63976 8.88% 74.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 35683 4.95% 79.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 24604 3.41% 82.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 16955 2.35% 84.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 13020 1.81% 86.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 11401 1.58% 88.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 83756 11.62% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 720627 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 99482 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 12.077512 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 124.901364 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 99480 100.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 52200 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 61876 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 103140 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 107216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 115340 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 154284 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 127380 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 116704 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 115742 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 109222 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 108713 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 142144 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 115995 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 110189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 122630 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 110947 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 107019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 104847 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 5989 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 5575 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 6143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 7595 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 8109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 7187 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 6881 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 8026 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 6843 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 6405 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 5844 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 5760 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 4978 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 3912 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 3857 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 3012 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 2330 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1631 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 1213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 768 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 1002 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 546 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 484 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 447 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 404 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 434 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 345 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 339 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 312 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 733749 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 289.646732 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 167.469062 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 324.982397 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 301017 41.02% 41.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 179214 24.42% 65.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 65174 8.88% 74.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 36623 4.99% 79.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 25257 3.44% 82.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 17346 2.36% 85.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 13099 1.79% 86.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 11628 1.58% 88.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 84391 11.50% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 733749 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 100720 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 12.193388 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 124.138953 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 100718 100.00% 100.00% # Reads before turning the bus around for writes
231,247c231,247
< system.physmem.rdPerTurnAround::total 99482 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 99482 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.810398 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.292150 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 17.172998 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-31 95801 96.30% 96.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-47 1933 1.94% 98.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-63 403 0.41% 98.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-79 315 0.32% 98.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-95 148 0.15% 99.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-111 160 0.16% 99.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-127 333 0.33% 99.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-143 129 0.13% 99.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-159 31 0.03% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-175 15 0.02% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-191 63 0.06% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-207 32 0.03% 99.88% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 100720 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 100720 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.776698 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 19.274786 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 17.101890 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 96977 96.28% 96.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 2012 2.00% 98.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 404 0.40% 98.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 303 0.30% 98.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 157 0.16% 99.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 153 0.15% 99.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 320 0.32% 99.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 134 0.13% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 20 0.02% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 11 0.01% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 66 0.07% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 35 0.03% 99.87% # Writes before turning the bus around for reads
249,252c249,252
< system.physmem.wrPerTurnAround::224-239 6 0.01% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-255 1 0.00% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-271 2 0.00% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::272-287 4 0.00% 99.91% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::224-239 5 0.00% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-255 1 0.00% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 7 0.01% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 6 0.01% 99.91% # Writes before turning the bus around for reads
254,263c254,262
< system.physmem.wrPerTurnAround::304-319 7 0.01% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::320-335 9 0.01% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::352-367 20 0.02% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::368-383 6 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::384-399 4 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::400-415 5 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::416-431 1 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::448-463 1 0.00% 99.98% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 8 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 12 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 21 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 5 0.00% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 5 0.00% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::400-415 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::432-447 1 0.00% 99.98% # Writes before turning the bus around for reads
265,270c264,269
< system.physmem.wrPerTurnAround::480-495 2 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::512-527 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::528-543 8 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::544-559 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::496-511 2 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 5 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 5 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-559 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::560-575 1 0.00% 100.00% # Writes before turning the bus around for reads
272,273c271
< system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads
275,279c273,278
< system.physmem.wrPerTurnAround::total 99482 # Writes before turning the bus around for reads
< system.physmem.totQLat 16741886044 # Total ticks spent queuing
< system.physmem.totMemAccLat 39270292294 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 6007575000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 13933.98 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::912-927 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 100720 # Writes before turning the bus around for reads
> system.physmem.totQLat 16983547454 # Total ticks spent queuing
> system.physmem.totMemAccLat 40010947454 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 6140640000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 13828.81 # Average queueing delay per DRAM burst
281,285c280,284
< system.physmem.avgMemAccLat 32683.98 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 32578.81 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.65 # Average system write bandwidth in MiByte/s
291,308c290,307
< system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing
< system.physmem.readRowHits 927538 # Number of row buffer hits during reads
< system.physmem.writeRowHits 1623609 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.42 # Row buffer hit rate for writes
< system.physmem.avgGap 15531851.53 # Average gap between requests
< system.physmem.pageHitRate 77.97 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 2802990960 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1529409750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 4566611400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 6809326560 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1308588544890 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 29818114243500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 34513325311620 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.733317 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 49604286854347 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1723371260000 # Time in different power states
---
> system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing
> system.physmem.readRowHits 948457 # Number of row buffer hits during reads
> system.physmem.writeRowHits 1638549 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 77.23 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 78.30 # Row buffer hit rate for writes
> system.physmem.avgGap 15306733.63 # Average gap between requests
> system.physmem.pageHitRate 77.90 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 2845387440 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1552542750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 4674001800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 6867115200 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3370916218800 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1311782988195 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 29815330787250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 34513969041435 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.745387 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 49599639397461 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1723372300000 # Time in different power states
310c309
< system.physmem_0.memoryStateTime::ACT 282340388153 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 287019858539 # Time in different power states
312,322c311,321
< system.physmem_1.actEnergy 2644949160 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1443176625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 4805158800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 6605958240 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1300507873200 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 29825202552000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 34512123852585 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.710038 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 49616091454429 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1723371260000 # Time in different power states
---
> system.physmem_1.actEnergy 2701755000 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1474171875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 4905342000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 6693120720 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3370916218800 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1303897064130 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 29822248264500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 34512835937025 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.723432 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 49611170347429 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1723372300000 # Time in different power states
324c323
< system.physmem_1.memoryStateTime::ACT 270535519321 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 275493728071 # Time in different power states
348,352c347,351
< system.cpu.branchPred.lookups 260066829 # Number of BP lookups
< system.cpu.branchPred.condPredicted 182351604 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 12179122 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 192997810 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 135975989 # Number of BTB hits
---
> system.cpu.branchPred.lookups 260902420 # Number of BP lookups
> system.cpu.branchPred.condPredicted 182959992 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 12222887 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 194114900 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 136429435 # Number of BTB hits
354,356c353,355
< system.cpu.branchPred.BTBHitPct 70.454680 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 31593975 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 2147293 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 70.282825 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 31730781 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 2172348 # Number of incorrect RAS predictions.
387,407c386,406
< system.cpu.dtb.walker.walks 583127 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 583127 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22581 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191165 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 583127 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 583127 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 583127 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 213746 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 24576.454072 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 20707.683114 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 15710.461946 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-65535 211230 98.82% 98.82% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-131071 2148 1.00% 99.83% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-196607 131 0.06% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::196608-262143 118 0.06% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::262144-327679 73 0.03% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 213746 # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walks 588227 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 588227 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22315 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191623 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 588227 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 588227 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 588227 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 213938 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 24858.035959 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 21008.300307 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 15796.225820 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-65535 211313 98.77% 98.77% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-131071 2233 1.04% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-196607 146 0.07% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::196608-262143 117 0.05% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-327679 91 0.04% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::393216-458751 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 213938 # Table walker service (enqueue to completion) latency
411,414c410,413
< system.cpu.dtb.walker.walkPageSizes::4K 191166 89.44% 89.44% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::2M 22581 10.56% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 213747 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 583127 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkPageSizes::4K 191624 89.57% 89.57% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::2M 22315 10.43% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 213939 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 588227 # Table walker requests started/completed, data/inst
416,417c415,416
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 583127 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213747 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 588227 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213939 # Table walker requests started/completed, data/inst
419,420c418,419
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213747 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 796874 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213939 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 802166 # Table walker requests started/completed, data/inst
423,426c422,425
< system.cpu.dtb.read_hits 182952995 # DTB read hits
< system.cpu.dtb.read_misses 481784 # DTB read misses
< system.cpu.dtb.write_hits 162354187 # DTB write hits
< system.cpu.dtb.write_misses 101343 # DTB write misses
---
> system.cpu.dtb.read_hits 183548892 # DTB read hits
> system.cpu.dtb.read_misses 485969 # DTB read misses
> system.cpu.dtb.write_hits 162881584 # DTB write hits
> system.cpu.dtb.write_misses 102258 # DTB write misses
429,433c428,432
< system.cpu.dtb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID
< system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID
< system.cpu.dtb.flush_entries 80213 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 854 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 14789 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_tlb_mva_asid 47246 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID
> system.cpu.dtb.flush_entries 79791 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 811 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 15585 # Number of TLB faults due to prefetch
435,437c434,436
< system.cpu.dtb.perms_faults 23472 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 183434779 # DTB read accesses
< system.cpu.dtb.write_accesses 162455530 # DTB write accesses
---
> system.cpu.dtb.perms_faults 23526 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 184034861 # DTB read accesses
> system.cpu.dtb.write_accesses 162983842 # DTB write accesses
439,441c438,440
< system.cpu.dtb.hits 345307182 # DTB hits
< system.cpu.dtb.misses 583127 # DTB misses
< system.cpu.dtb.accesses 345890309 # DTB accesses
---
> system.cpu.dtb.hits 346430476 # DTB hits
> system.cpu.dtb.misses 588227 # DTB misses
> system.cpu.dtb.accesses 347018703 # DTB accesses
471,491c470,491
< system.cpu.itb.walker.walks 136411 # Table walker walks requested
< system.cpu.itb.walker.walksLong 136411 # Table walker walks initiated with long descriptors
< system.cpu.itb.walker.walksLongTerminationLevel::Level2 1074 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksLongTerminationLevel::Level3 118764 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walkWaitTime::samples 136411 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 136411 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 136411 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 119838 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 26864.678099 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 23079.638443 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 17315.603436 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-65535 117018 97.65% 97.65% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::65536-131071 2553 2.13% 99.78% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::131072-196607 159 0.13% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::196608-262143 57 0.05% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::262144-327679 28 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.02% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 119838 # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walks 136538 # Table walker walks requested
> system.cpu.itb.walker.walksLong 136538 # Table walker walks initiated with long descriptors
> system.cpu.itb.walker.walksLongTerminationLevel::Level2 1085 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksLongTerminationLevel::Level3 118818 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walkWaitTime::samples 136538 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 136538 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 136538 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 119903 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 27208.529278 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 23313.702861 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 17744.151968 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-65535 116996 97.58% 97.58% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::65536-131071 2625 2.19% 99.76% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-196607 168 0.14% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::196608-262143 53 0.04% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::262144-327679 37 0.03% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 119903 # Table walker service (enqueue to completion) latency
495,497c495,497
< system.cpu.itb.walker.walkPageSizes::4K 118764 99.10% 99.10% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::2M 1074 0.90% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 119838 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkPageSizes::4K 118818 99.10% 99.10% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::2M 1085 0.90% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 119903 # Table walker page sizes translated
499,500c499,500
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136411 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 136411 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136538 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 136538 # Table walker requests started/completed, data/inst
502,506c502,506
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119838 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 119838 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 256249 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 452746266 # ITB inst hits
< system.cpu.itb.inst_misses 136411 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119903 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 119903 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 256441 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 454119408 # ITB inst hits
> system.cpu.itb.inst_misses 136538 # ITB inst misses
513,515c513,515
< system.cpu.itb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID
< system.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID
< system.cpu.itb.flush_entries 57592 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_tlb_mva_asid 47246 # Number of times TLB was flushed by MVA & ASID
> system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID
> system.cpu.itb.flush_entries 57195 # Number of entries that have been flushed from TLB
519c519
< system.cpu.itb.perms_faults 369764 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 369083 # Number of TLB faults due to permissions restrictions
522,526c522,526
< system.cpu.itb.inst_accesses 452882677 # ITB inst accesses
< system.cpu.itb.hits 452746266 # DTB hits
< system.cpu.itb.misses 136411 # DTB misses
< system.cpu.itb.accesses 452882677 # DTB accesses
< system.cpu.numCycles 2486475408 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 454255946 # ITB inst accesses
> system.cpu.itb.hits 454119408 # DTB hits
> system.cpu.itb.misses 136538 # DTB misses
> system.cpu.itb.accesses 454255946 # DTB accesses
> system.cpu.numCycles 2495798541 # number of cpu cycles simulated
529,535c529,535
< system.cpu.committedInsts 947659008 # Number of instructions committed
< system.cpu.committedOps 1113505098 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 96546934 # Number of ops (including micro ops) which were discarded before commit
< system.cpu.numFetchSuspends 7735 # Number of times Execute suspended instruction fetching
< system.cpu.quiesceCycles 100734690731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.623808 # CPI: cycles per instruction
< system.cpu.ipc 0.381125 # IPC: instructions per cycle
---
> system.cpu.committedInsts 950561948 # Number of instructions committed
> system.cpu.committedOps 1116924449 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 97483728 # Number of ops (including micro ops) which were discarded before commit
> system.cpu.numFetchSuspends 7747 # Number of times Execute suspended instruction fetching
> system.cpu.quiesceCycles 100725440428 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.625603 # CPI: cycles per instruction
> system.cpu.ipc 0.380865 # IPC: instructions per cycle
537,540c537,540
< system.cpu.kern.inst.quiesce 16595 # number of quiesce instructions executed
< system.cpu.tickCycles 1791502894 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 694972514 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 11092406 # number of replacements
---
> system.cpu.kern.inst.quiesce 16607 # number of quiesce instructions executed
> system.cpu.tickCycles 1794634441 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 701164100 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 11128908 # number of replacements
542,544c542,544
< system.cpu.dcache.tags.total_refs 328965151 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 11092918 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 29.655421 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 330012577 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 11129420 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 29.652271 # Average number of references to valid blocks.
550,552c550,552
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
554,581c554,581
< system.cpu.dcache.tags.tag_accesses 1382417296 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1382417296 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 168207875 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 168207875 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 151549113 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 151549113 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 490930 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 490930 # number of SoftPFReq hits
< system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 335942 # number of WriteInvalidateReq hits
< system.cpu.dcache.WriteInvalidateReq_hits::total 335942 # number of WriteInvalidateReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 4008865 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 4008865 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 4323127 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 4323127 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 319756988 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 319756988 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 320247918 # number of overall hits
< system.cpu.dcache.overall_hits::total 320247918 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 6578537 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 6578537 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 4302299 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 4302299 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 1473808 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 1473808 # number of SoftPFReq misses
< system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1244599 # number of WriteInvalidateReq misses
< system.cpu.dcache.WriteInvalidateReq_misses::total 1244599 # number of WriteInvalidateReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 315993 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 315993 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 1386837426 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1386837426 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 168701491 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 168701491 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 152033429 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 152033429 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 523995 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 523995 # number of SoftPFReq hits
> system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits
> system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 4025252 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 4025252 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 4342024 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 4342024 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 320734920 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 320734920 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 321258915 # number of overall hits
> system.cpu.dcache.overall_hits::total 321258915 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 6599201 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 6599201 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 4320372 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 4320372 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 1481368 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 1481368 # number of SoftPFReq misses
> system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1244671 # number of WriteInvalidateReq misses
> system.cpu.dcache.WriteInvalidateReq_misses::total 1244671 # number of WriteInvalidateReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 318506 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 318506 # number of LoadLockedReq misses
584,595c584,595
< system.cpu.dcache.demand_misses::cpu.data 10880836 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 10880836 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 12354644 # number of overall misses
< system.cpu.dcache.overall_misses::total 12354644 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 106697920457 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 106697920457 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 153242376598 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 153242376598 # number of WriteReq miss cycles
< system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35461255171 # number of WriteInvalidateReq miss cycles
< system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35461255171 # number of WriteInvalidateReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4805977234 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 4805977234 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 10919573 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 10919573 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 12400941 # number of overall misses
> system.cpu.dcache.overall_misses::total 12400941 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 107641538217 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 107641538217 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 155110738831 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 155110738831 # number of WriteReq miss cycles
> system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35571203201 # number of WriteInvalidateReq miss cycles
> system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35571203201 # number of WriteInvalidateReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4850646421 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 4850646421 # number of LoadLockedReq miss cycles
598,627c598,627
< system.cpu.dcache.demand_miss_latency::cpu.data 259940297055 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 259940297055 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 259940297055 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 259940297055 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 174786412 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 174786412 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 155851412 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 155851412 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 1964738 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 1964738 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1580541 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu.dcache.WriteInvalidateReq_accesses::total 1580541 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4324858 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 4324858 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 4323128 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 4323128 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 330637824 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 330637824 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 332602562 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 332602562 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037638 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.037638 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027605 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.027605 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.750130 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.750130 # miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787451 # miss rate for WriteInvalidateReq accesses
< system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787451 # miss rate for WriteInvalidateReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073064 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073064 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_miss_latency::cpu.data 262752277048 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 262752277048 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 262752277048 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 262752277048 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 175300692 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 175300692 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 156353801 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 156353801 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2005363 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2005363 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1581358 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu.dcache.WriteInvalidateReq_accesses::total 1581358 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4343758 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 4343758 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 4342025 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 4342025 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 331654493 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 331654493 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 333659856 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 333659856 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037645 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.037645 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027632 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.027632 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738703 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.738703 # miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787090 # miss rate for WriteInvalidateReq accesses
> system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787090 # miss rate for WriteInvalidateReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073325 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073325 # miss rate for LoadLockedReq accesses
630,641c630,641
< system.cpu.dcache.demand_miss_rate::cpu.data 0.032909 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.032909 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.037145 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.037145 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.095592 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.095592 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35618.718410 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 35618.718410 # average WriteReq miss latency
< system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28492.112858 # average WriteInvalidateReq miss latency
< system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28492.112858 # average WriteInvalidateReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15209.125626 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15209.125626 # average LoadLockedReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.032925 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.032925 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.037166 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.037166 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16311.298628 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16311.298628 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35902.172042 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35902.172042 # average WriteReq miss latency
> system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28578.799700 # average WriteInvalidateReq miss latency
> system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28578.799700 # average WriteInvalidateReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15229.372197 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15229.372197 # average LoadLockedReq miss latency
644,648c644,648
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 23889.735775 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 23889.735775 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 21039.885654 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 21039.885654 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 24062.504738 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 24062.504738 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21188.091859 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21188.091859 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
650c650
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
652c652
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
656,679c656,679
< system.cpu.dcache.writebacks::writebacks 8509656 # number of writebacks
< system.cpu.dcache.writebacks::total 8509656 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 799615 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 799615 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1895946 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1895946 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 144 # number of WriteInvalidateReq MSHR hits
< system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 144 # number of WriteInvalidateReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69791 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 69791 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2695561 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2695561 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2695561 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2695561 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5778922 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 5778922 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2406353 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2406353 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1466300 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 1466300 # number of SoftPFReq MSHR misses
< system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244455 # number of WriteInvalidateReq MSHR misses
< system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244455 # number of WriteInvalidateReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246202 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 246202 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 8539693 # number of writebacks
> system.cpu.dcache.writebacks::total 8539693 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803144 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 803144 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1904565 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1904565 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 147 # number of WriteInvalidateReq MSHR hits
> system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 147 # number of WriteInvalidateReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69655 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 69655 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2707709 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2707709 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2707709 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2707709 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5796057 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 5796057 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2415807 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2415807 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1473891 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 1473891 # number of SoftPFReq MSHR misses
> system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244524 # number of WriteInvalidateReq MSHR misses
> system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244524 # number of WriteInvalidateReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 248851 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 248851 # number of LoadLockedReq MSHR misses
682,685c682,685
< system.cpu.dcache.demand_mshr_misses::cpu.data 8185275 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 8211864 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 8211864 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9685755 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9685755 # number of overall MSHR misses
692,701c692,701
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 78901247228 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22730570766 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22730570766 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33591268829 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33591268829 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3240983258 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3240983258 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 85294782786 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 85294782786 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79878018296 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 79878018296 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23078167080 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23078167080 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33700697799 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33700697799 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3279664007 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3279664007 # number of LoadLockedReq MSHR miss cycles
704,723c704,723
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163468245028 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 163468245028 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186198815794 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 186198815794 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751743992 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751743992 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611366250 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611366250 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363110242 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363110242 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033063 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033063 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015440 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015440 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746308 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746308 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787360 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787360 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056927 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056927 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165172801082 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 165172801082 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188250968162 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 188250968162 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5750649000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5750649000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5615353750 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5615353750 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11366002750 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 11366002750 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033064 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033064 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015451 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015451 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734975 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734975 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786997 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786997 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057289 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057289 # mshr miss rate for LoadLockedReq accesses
726,739c726,739
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024756 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.024756 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029018 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.029018 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14633.697738 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14633.697738 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32788.725190 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32788.725190 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15501.991929 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15501.991929 # average SoftPFReq mshr miss latency
< system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 26992.754924 # average WriteInvalidateReq mshr miss latency
< system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26992.754924 # average WriteInvalidateReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13163.919294 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13163.919294 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024760 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.024760 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029029 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.029029 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14716.001376 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14716.001376 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33064.735012 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33064.735012 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15657.987653 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15657.987653 # average SoftPFReq mshr miss latency
> system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27079.186740 # average WriteInvalidateReq mshr miss latency
> system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.186740 # average WriteInvalidateReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13179.227759 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13179.227759 # average LoadLockedReq mshr miss latency
742,751c742,751
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170695.156458 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170695.156458 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166484.683281 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166484.683281 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168589.638759 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168589.638759 # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20113.923110 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 20113.923110 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19435.858966 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 19435.858966 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170662.660256 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170662.660256 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166602.989171 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166602.989171 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168632.553671 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168632.553671 # average overall mshr uncacheable latency
753,759c753,759
< system.cpu.icache.tags.replacements 24538707 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 427825373 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 24539219 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 17.434352 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 22330853250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.926996 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.replacements 24596775 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.926998 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 429140951 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 24597287 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 17.446678 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 22329177250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.926998 # Average occupied blocks per requestor
763,765c763,765
< system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id
767,804c767,804
< system.cpu.icache.tags.tag_accesses 476903830 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 476903830 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 427825373 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 427825373 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 427825373 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 427825373 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 427825373 # number of overall hits
< system.cpu.icache.overall_hits::total 427825373 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 24539229 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 24539229 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 24539229 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 24539229 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 24539229 # number of overall misses
< system.cpu.icache.overall_misses::total 24539229 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 326974610838 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 326974610838 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 326974610838 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 326974610838 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 326974610838 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 326974610838 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 452364602 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 452364602 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 452364602 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 452364602 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 452364602 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 452364602 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054247 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.054247 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.054247 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.054247 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.054247 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.054247 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13324.567403 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13324.567403 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13324.567403 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13324.567403 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13324.567403 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13324.567403 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 478335544 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 478335544 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 429140951 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 429140951 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 429140951 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 429140951 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 429140951 # number of overall hits
> system.cpu.icache.overall_hits::total 429140951 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 24597297 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 24597297 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 24597297 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 24597297 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 24597297 # number of overall misses
> system.cpu.icache.overall_misses::total 24597297 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 327843901768 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 327843901768 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 327843901768 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 327843901768 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 327843901768 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 327843901768 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 453738248 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 453738248 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 453738248 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 453738248 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 453738248 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 453738248 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054210 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.054210 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.054210 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.054210 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.054210 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.054210 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13328.452381 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13328.452381 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13328.452381 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13328.452381 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13328.452381 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13328.452381 # average overall miss latency
813,818c813,818
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24539229 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 24539229 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 24539229 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 24539229 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 24539229 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 24539229 # number of overall MSHR misses
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24597297 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 24597297 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 24597297 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 24597297 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 24597297 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 24597297 # number of overall MSHR misses
823,828c823,828
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 290116862082 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290116862082 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 290116862082 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290898201664 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 290898201664 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290898201664 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 290898201664 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290898201664 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 290898201664 # number of overall MSHR miss cycles
833,844c833,844
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054247 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.054247 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.054247 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11822.574462 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11822.574462 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054210 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054210 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054210 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.054210 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054210 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.054210 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11826.429614 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11826.429614 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11826.429614 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11826.429614 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11826.429614 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11826.429614 # average overall mshr miss latency
850,910c850,910
< system.cpu.l2cache.tags.replacements 1594461 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65370.145273 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 40075906 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1658209 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 24.168187 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 6394381000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 36356.724167 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 340.112458 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 426.747711 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.252666 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 20073.308271 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.554760 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005190 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006512 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124714 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.306294 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.997469 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 294 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 63454 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 294 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 492 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2445 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5512 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54953 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.968231 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 368332557 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 368332557 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 961086 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 281097 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 24431679 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 7167695 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 32841557 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 8509656 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 8509656 # number of Writeback hits
< system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 701377 # number of WriteInvalidateReq hits
< system.cpu.l2cache.WriteInvalidateReq_hits::total 701377 # number of WriteInvalidateReq hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 10751 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 10751 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1655224 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1655224 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 961086 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 281097 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 24431679 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 8822919 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 34496781 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 961086 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 281097 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 24431679 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 8822919 # number of overall hits
< system.cpu.l2cache.overall_hits::total 34496781 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6228 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5190 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.inst 107547 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 323472 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 442437 # number of ReadReq misses
< system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 543077 # number of WriteInvalidateReq misses
< system.cpu.l2cache.WriteInvalidateReq_misses::total 543077 # number of WriteInvalidateReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 38541 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 38541 # number of UpgradeReq misses
---
> system.cpu.l2cache.tags.replacements 1624472 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65307.335302 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 40176051 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1687699 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 23.805223 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 6393601000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 36145.263997 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 333.648075 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 422.733439 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 8142.717924 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 20262.971868 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.551533 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005091 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006450 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124248 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.309188 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996511 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 253 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 62974 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 253 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 498 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5584 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54389 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003860 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960907 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 369553553 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 369553553 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 980236 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 284775 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 24487803 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 7183333 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 32936147 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 8539693 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 8539693 # number of Writeback hits
> system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 698094 # number of WriteInvalidateReq hits
> system.cpu.l2cache.WriteInvalidateReq_hits::total 698094 # number of WriteInvalidateReq hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 10791 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 10791 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1651497 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1651497 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 980236 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 284775 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 24487803 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 8834830 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 34587644 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 980236 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 284775 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 24487803 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 8834830 # number of overall hits
> system.cpu.l2cache.overall_hits::total 34587644 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6407 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5317 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.inst 109491 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 335212 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 456427 # number of ReadReq misses
> system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 546430 # number of WriteInvalidateReq misses
> system.cpu.l2cache.WriteInvalidateReq_misses::total 546430 # number of WriteInvalidateReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 38901 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 38901 # number of UpgradeReq misses
913,933c913,933
< system.cpu.l2cache.ReadExReq_misses::cpu.data 702095 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 702095 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 6228 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 5190 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 107547 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1025567 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1144532 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 6228 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 5190 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 107547 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1025567 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1144532 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 538586008 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 452279750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8825389448 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 27527866547 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 37344121753 # number of ReadReq miss cycles
< system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 5340829 # number of WriteInvalidateReq miss cycles
< system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 5340829 # number of WriteInvalidateReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 585352278 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 585352278 # number of UpgradeReq miss cycles
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 714872 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 714872 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 6407 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 5317 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 109491 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1050084 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1171299 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 6407 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 5317 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 109491 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1050084 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1171299 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 560042000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 465198251 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8958985804 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28447834598 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 38432060653 # number of ReadReq miss cycles
> system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 6247800 # number of WriteInvalidateReq miss cycles
> system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 6247800 # number of WriteInvalidateReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 584783300 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 584783300 # number of UpgradeReq miss cycles
936,958c936,958
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57779848170 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 57779848170 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 538586008 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 452279750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 8825389448 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 85307714717 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 95123969923 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 538586008 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 452279750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 8825389448 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 85307714717 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 95123969923 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 967314 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 286287 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 24539226 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 7491167 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 33283994 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 8509656 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 8509656 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1244454 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244454 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49292 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 49292 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58773696620 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 58773696620 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 560042000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 465198251 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 8958985804 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 87221531218 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 97205757273 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 560042000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 465198251 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 8958985804 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 87221531218 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 97205757273 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 986643 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 290092 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 24597294 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 7518545 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 33392574 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 8539693 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 8539693 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1244524 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244524 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49692 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 49692 # number of UpgradeReq accesses(hits+misses)
961,981c961,981
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2357319 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2357319 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 967314 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 286287 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 24539226 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 9848486 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 35641313 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 967314 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 286287 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 24539226 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 9848486 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 35641313 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006438 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018129 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004383 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043180 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.013293 # miss rate for ReadReq accesses
< system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.436398 # miss rate for WriteInvalidateReq accesses
< system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.436398 # miss rate for WriteInvalidateReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.781892 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.781892 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 2366369 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 2366369 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 986643 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 290092 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 24597294 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 9884914 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 35758943 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 986643 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 290092 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 24597294 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 9884914 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 35758943 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006494 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018329 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004451 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.044585 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.013669 # miss rate for ReadReq accesses
> system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.439067 # miss rate for WriteInvalidateReq accesses
> system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.439067 # miss rate for WriteInvalidateReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782842 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782842 # miss rate for UpgradeReq accesses
984,1004c984,1004
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.297836 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.297836 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006438 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018129 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004383 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.104134 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.032113 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006438 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018129 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004383 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.104134 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.032113 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86478.164419 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87144.460501 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82060.768297 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85101.234564 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 84405.512543 # average ReadReq miss latency
< system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 9.834386 # average WriteInvalidateReq miss latency
< system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 9.834386 # average WriteInvalidateReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15187.781272 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15187.781272 # average UpgradeReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.302097 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.302097 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006494 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018329 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004451 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.106231 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.032755 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006494 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018329 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004451 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.106231 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.032755 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87410.956766 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87492.618206 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81823.947210 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84865.203507 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 84201.987729 # average ReadReq miss latency
> system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 11.433852 # average WriteInvalidateReq miss latency
> system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 11.433852 # average WriteInvalidateReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15032.603275 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15032.603275 # average UpgradeReq miss latency
1007,1018c1007,1018
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82296.339057 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82296.339057 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86478.164419 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87144.460501 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82060.768297 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.025440 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 83111.673525 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86478.164419 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87144.460501 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82060.768297 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.025440 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 83111.673525 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82215.692627 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82215.692627 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87410.956766 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87492.618206 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81823.947210 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83061.480051 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 82989.703972 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87410.956766 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87492.618206 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81823.947210 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83061.480051 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 82989.703972 # average overall miss latency
1027,1028c1027,1028
< system.cpu.l2cache.writebacks::writebacks 1362005 # number of writebacks
< system.cpu.l2cache.writebacks::total 1362005 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 1380910 # number of writebacks
> system.cpu.l2cache.writebacks::total 1380910 # number of writebacks
1038,1046c1038,1046
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6228 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5190 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 107545 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 323451 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 442414 # number of ReadReq MSHR misses
< system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 543077 # number of WriteInvalidateReq MSHR misses
< system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 543077 # number of WriteInvalidateReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38541 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 38541 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6407 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5317 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 109489 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 335191 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 456404 # number of ReadReq MSHR misses
> system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 546430 # number of WriteInvalidateReq MSHR misses
> system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 546430 # number of WriteInvalidateReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38901 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 38901 # number of UpgradeReq MSHR misses
1049,1060c1049,1060
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 702095 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 702095 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6228 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5190 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 107545 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1025546 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1144509 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6228 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5190 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 107545 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1025546 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1144509 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 714872 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 714872 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6407 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5317 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 109489 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1050063 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1171276 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6407 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5317 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 109489 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1050063 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1171276 # number of overall MSHR misses
1069,1077c1069,1077
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 460278992 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 386982750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7477222552 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23476189203 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31800673497 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 18301171671 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18301171671 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 683876035 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 683876035 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 479479000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 398285251 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7586646696 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24249187152 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32713598099 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 18411194701 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18411194701 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 691147894 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 691147894 # number of UpgradeReq MSHR miss cycles
1080,1091c1080,1091
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49002604830 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49002604830 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 460278992 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 386982750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7477222552 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 72478794033 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 80803278327 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 460278992 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 386982750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7477222552 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 72478794033 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 80803278327 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49837354880 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49837354880 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 479479000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 398285251 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7586646696 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 74086542032 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 82550952979 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 479479000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 398285251 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7586646696 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 74086542032 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 82550952979 # number of overall MSHR miss cycles
1093,1096c1093,1096
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279396750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8388316750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5172507000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5172507000 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5278320250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8387240250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176274500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176274500 # number of WriteReq MSHR uncacheable cycles
1098,1108c1098,1108
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10451903750 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13560823750 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006438 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.043178 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013292 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.436398 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.436398 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781892 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781892 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10454594750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13563514750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006494 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018329 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004451 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044582 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013668 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.439067 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.439067 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782842 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782842 # mshr miss rate for UpgradeReq accesses
1111,1131c1111,1131
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.297836 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.297836 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006438 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104132 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.032112 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006438 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104132 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.032112 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69526.454526 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72580.357467 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71879.898685 # average ReadReq mshr miss latency
< system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33699.036547 # average WriteInvalidateReq mshr miss latency
< system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33699.036547 # average WriteInvalidateReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17744.117563 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17744.117563 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.302097 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.302097 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006494 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018329 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004451 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.106229 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.032755 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006494 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018329 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004451 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.106229 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.032755 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69291.405493 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72344.386192 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71676.843540 # average ReadReq mshr miss latency
> system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33693.601561 # average WriteInvalidateReq mshr miss latency
> system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33693.601561 # average WriteInvalidateReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17766.841315 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17766.841315 # average UpgradeReq mshr miss latency
1134,1145c1134,1145
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.835215 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.835215 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69715.074699 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69715.074699 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69291.405493 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70554.378196 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70479.505240 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69291.405493 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70554.378196 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70479.505240 # average overall mshr miss latency
1147,1150c1147,1150
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156677.253977 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97549.909873 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153464.085447 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153464.085447 # average WriteReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156645.306565 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97537.390976 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153575.864115 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153575.864115 # average WriteReq mshr uncacheable latency
1152,1153c1152,1153
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155070.455186 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113294.822257 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155110.380410 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113317.304399 # average overall mshr uncacheable latency
1155,1156c1155,1156
< system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 33924038 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 33915953 # Transaction distribution
1159,1162c1159,1162
< system.cpu.toL2Bus.trans_dist::Writeback 8509656 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351233 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244454 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 49295 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 8539693 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351286 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244524 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 49695 # Transaction distribution
1164,1180c1164,1180
< system.cpu.toL2Bus.trans_dist::UpgradeResp 49296 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2357319 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2357319 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49183042 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30929702 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 693856 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2262449 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 83069049 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1573857216 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1254806154 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2290296 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 565529 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 46129162 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.039419 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.194589 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 49696 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 2366369 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 2366369 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49299178 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31033537 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 698041 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2292039 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 83322795 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1577573568 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1259064522 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2320736 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7893144 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 2846851970 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 553019 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 46264787 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.039533 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.194859 # Request fanout histogram
1183,1184c1183,1184
< system.cpu.toL2Bus.snoop_fanout::1 44310813 96.06% 96.06% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 1818349 3.94% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 44435816 96.05% 96.05% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 1828971 3.95% 100.00% # Request fanout histogram
1188,1189c1188,1189
< system.cpu.toL2Bus.snoop_fanout::total 46129162 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 46264787 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 32875768488 # Layer occupancy (ticks)
1191c1191
< system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 1167000 # Layer occupancy (ticks)
1193c1193
< system.cpu.toL2Bus.respLayer0.occupancy 36924053878 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 37011580552 # Layer occupancy (ticks)
1195c1195
< system.cpu.toL2Bus.respLayer1.occupancy 15679140875 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 15738706286 # Layer occupancy (ticks)
1197c1197
< system.cpu.toL2Bus.respLayer2.occupancy 408249695 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 408640707 # Layer occupancy (ticks)
1199c1199
< system.cpu.toL2Bus.respLayer3.occupancy 1295905979 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 1306185489 # Layer occupancy (ticks)
1201,1202c1201,1202
< system.iobus.trans_dist::ReadReq 40311 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40311 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 40309 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40309 # Transaction distribution
1222,1223c1222,1223
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes)
1226c1226
< system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes)
1243,1244c1243,1244
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes)
1247c1247
< system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes)
1276c1276
< system.iobus.reqLayer27.occupancy 607011706 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 606954435 # Layer occupancy (ticks)
1282c1282
< system.iobus.respLayer3.occupancy 148422470 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 148397760 # Layer occupancy (ticks)
1286,1287c1286,1287
< system.iocache.tags.replacements 115472 # number of replacements
< system.iocache.tags.tagsinuse 10.439528 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115470 # number of replacements
> system.iocache.tags.tagsinuse 10.439534 # Cycle average of tags in use
1289c1289
< system.iocache.tags.sampled_refs 115488 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks.
1291,1293c1291,1293
< system.iocache.tags.warmup_cycle 13142428728000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.524738 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 6.914790 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 13142420796000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.524742 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 6.914791 # Average occupied blocks per requestor
1300,1301c1300,1301
< system.iocache.tags.tag_accesses 1039767 # Number of tag accesses
< system.iocache.tags.data_accesses 1039767 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1039749 # Number of tag accesses
> system.iocache.tags.data_accesses 1039749 # Number of data accesses
1303,1304c1303,1304
< system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses
1310,1311c1310,1311
< system.iocache.demand_misses::realview.ide 8826 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8866 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8824 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8864 # number of demand (read+write) misses
1313,1314c1313,1314
< system.iocache.overall_misses::realview.ide 8826 # number of overall misses
< system.iocache.overall_misses::total 8866 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 8824 # number of overall misses
> system.iocache.overall_misses::total 8864 # number of overall misses
1316,1317c1316,1317
< system.iocache.ReadReq_miss_latency::realview.ide 1599431674 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1604503674 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1602204582 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1607276582 # number of ReadReq miss cycles
1320,1321c1320,1321
< system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19839532562 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 19839532562 # number of WriteInvalidateReq miss cycles
---
> system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19806517093 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 19806517093 # number of WriteInvalidateReq miss cycles
1323,1324c1323,1324
< system.iocache.demand_miss_latency::realview.ide 1599431674 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1604856174 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 1602204582 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1607629082 # number of demand (read+write) miss cycles
1326,1327c1326,1327
< system.iocache.overall_miss_latency::realview.ide 1599431674 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1604856174 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 1602204582 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1607629082 # number of overall miss cycles
1329,1330c1329,1330
< system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses)
1336,1337c1336,1337
< system.iocache.demand_accesses::realview.ide 8826 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8866 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8824 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8864 # number of demand (read+write) accesses
1339,1340c1339,1340
< system.iocache.overall_accesses::realview.ide 8826 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8866 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8824 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8864 # number of overall (read+write) accesses
1355,1356c1355,1356
< system.iocache.ReadReq_avg_miss_latency::realview.ide 181218.181962 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 181033.924630 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 181573.502040 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 181387.719445 # average ReadReq miss latency
1359,1360c1359,1360
< system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186000.267775 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 186000.267775 # average WriteInvalidateReq miss latency
---
> system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185690.740015 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 185690.740015 # average WriteInvalidateReq miss latency
1362,1363c1362,1363
< system.iocache.demand_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 181012.426573 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 181573.502040 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 181366.096796 # average overall miss latency
1365,1367c1365,1367
< system.iocache.overall_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 181012.426573 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 109629 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 181573.502040 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 181366.096796 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 109809 # number of cycles access was blocked
1369c1369
< system.iocache.blocked::no_mshrs 16167 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked
1371c1371
< system.iocache.avg_blocked_cycles::no_mshrs 6.781035 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6.797635 # average number of cycles each access was blocked
1378,1379c1378,1379
< system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses
1385,1386c1385,1386
< system.iocache.demand_mshr_misses::realview.ide 8826 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8866 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8824 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8864 # number of demand (read+write) MSHR misses
1388,1389c1388,1389
< system.iocache.overall_mshr_misses::realview.ide 8826 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8866 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 8824 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8864 # number of overall MSHR misses
1391,1392c1391,1392
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1139388578 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1142530578 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1142260060 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1145402060 # number of ReadReq MSHR miss cycles
1395,1396c1395,1396
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14292968598 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14292968598 # number of WriteInvalidateReq MSHR miss cycles
---
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14259947135 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14259947135 # number of WriteInvalidateReq MSHR miss cycles
1398,1399c1398,1399
< system.iocache.demand_mshr_miss_latency::realview.ide 1139388578 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1142724078 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 1142260060 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1145595560 # number of demand (read+write) MSHR miss cycles
1401,1402c1401,1402
< system.iocache.overall_mshr_miss_latency::realview.ide 1139388578 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1142724078 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 1142260060 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1145595560 # number of overall MSHR miss cycles
1417,1418c1417,1418
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129094.559030 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 128910.140810 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129449.236174 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 129263.295339 # average ReadReq mshr miss latency
1421,1422c1421,1422
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133999.930605 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133999.930605 # average WriteInvalidateReq mshr miss latency
---
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133690.346649 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133690.346649 # average WriteInvalidateReq mshr miss latency
1424,1425c1424,1425
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 129449.236174 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 129241.376354 # average overall mshr miss latency
1427,1428c1427,1428
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 129449.236174 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 129241.376354 # average overall mshr miss latency
1430,1431c1430,1431
< system.membus.trans_dist::ReadReq 537267 # Transaction distribution
< system.membus.trans_dist::ReadResp 537267 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 551255 # Transaction distribution
> system.membus.trans_dist::ReadResp 551255 # Transaction distribution
1434,1437c1434,1437
< system.membus.trans_dist::Writeback 1468636 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 649570 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 649570 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 39342 # Transaction distribution
---
> system.membus.trans_dist::Writeback 1487541 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 652894 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 652894 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 39734 # Transaction distribution
1439,1441c1439,1441
< system.membus.trans_dist::UpgradeResp 39343 # Transaction distribution
< system.membus.trans_dist::ReadExReq 701468 # Transaction distribution
< system.membus.trans_dist::ReadExResp 701468 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 39735 # Transaction distribution
> system.membus.trans_dist::ReadExReq 714242 # Transaction distribution
> system.membus.trans_dist::ReadExResp 714242 # Transaction distribution
1445,1449c1445,1449
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4923341 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5052989 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335373 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 335373 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5388362 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5003208 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5132856 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335248 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 335248 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5468104 # Packet count per connected master and slave (bytes)
1453,1459c1453,1459
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198447468 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 198617866 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 2980 # Total snoops (count)
< system.membus.snoop_fanout::samples 3430156 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 201583148 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201753546 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14062080 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 14062080 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 215815626 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 3099 # Total snoops (count)
> system.membus.snoop_fanout::samples 3479513 # Request fanout histogram
1464c1464
< system.membus.snoop_fanout::1 3430156 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 3479513 100.00% 100.00% # Request fanout histogram
1469,1470c1469,1470
< system.membus.snoop_fanout::total 3430156 # Request fanout histogram
< system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3479513 # Request fanout histogram
> system.membus.reqLayer0.occupancy 102597500 # Layer occupancy (ticks)
1474c1474
< system.membus.reqLayer2.occupancy 5637000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5574500 # Layer occupancy (ticks)
1476c1476
< system.membus.reqLayer5.occupancy 12263986868 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 12409067173 # Layer occupancy (ticks)
1478c1478
< system.membus.respLayer2.occupancy 7071367467 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 7217145927 # Layer occupancy (ticks)
1480c1480
< system.membus.respLayer3.occupancy 151550030 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 151545740 # Layer occupancy (ticks)