Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

Deleted Added

sdiff udiff text old ( 11530:6e143fd2cabf ) new ( 11547:dd6dfd38b6c2 )

full compact

stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660653 # Number of seconds simulated 4sim_ticks 51660652947000 # Number of ticks simulated 5final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660653 # Number of seconds simulated 4sim_ticks 51660652947000 # Number of ticks simulated 5final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 288085 # Simulator instruction rate (inst/s) 8host_op_rate 338513 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16013200726 # Simulator tick rate (ticks/s) 10host_mem_usage 724944 # Number of bytes of host memory used 11host_seconds 3226.13 # Real time elapsed on the host	7host_inst_rate 170651 # Simulator instruction rate (inst/s) 8host_op_rate 200523 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9485631865 # Simulator tick rate (ticks/s) 10host_mem_usage 683504 # Number of bytes of host memory used 11host_seconds 5446.20 # Real time elapsed on the host
12sim_insts 929398934 # Number of instructions simulated 13sim_ops 1092086880 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 394752 # Number of bytes read from this memory 22system.physmem.bytes_read::total 73038088 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 10229888 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 10229888 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 89631104 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 27system.physmem.bytes_written::total 89651684 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 5915 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 4899 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 159842 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 964409 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6168 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 1141233 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1400486 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 1403059 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 7328 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 6069 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 198021 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1194746 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 7641 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 1413805 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 198021 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 198021 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1734998 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 1735396 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1734998 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 7328 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 6069 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 198021 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1195144 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 7641 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 3149201 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 1141233 # Number of read requests accepted 56system.physmem.writeReqs 1403059 # Number of write requests accepted 57system.physmem.readBursts 1141233 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 1403059 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 72990656 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 48256 # Total number of bytes read from write queue 61system.physmem.bytesWritten 89651072 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 73038088 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 89651684 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 754 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 69460 # Per bank write bursts 68system.physmem.perBankRdBursts::1 75077 # Per bank write bursts 69system.physmem.perBankRdBursts::2 69733 # Per bank write bursts 70system.physmem.perBankRdBursts::3 63631 # Per bank write bursts 71system.physmem.perBankRdBursts::4 66485 # Per bank write bursts 72system.physmem.perBankRdBursts::5 73840 # Per bank write bursts 73system.physmem.perBankRdBursts::6 65699 # Per bank write bursts 74system.physmem.perBankRdBursts::7 65290 # Per bank write bursts 75system.physmem.perBankRdBursts::8 63012 # Per bank write bursts 76system.physmem.perBankRdBursts::9 121917 # Per bank write bursts 77system.physmem.perBankRdBursts::10 71008 # Per bank write bursts 78system.physmem.perBankRdBursts::11 72120 # Per bank write bursts 79system.physmem.perBankRdBursts::12 67529 # Per bank write bursts 80system.physmem.perBankRdBursts::13 67730 # Per bank write bursts 81system.physmem.perBankRdBursts::14 61491 # Per bank write bursts 82system.physmem.perBankRdBursts::15 66457 # Per bank write bursts 83system.physmem.perBankWrBursts::0 88448 # Per bank write bursts 84system.physmem.perBankWrBursts::1 89667 # Per bank write bursts 85system.physmem.perBankWrBursts::2 88153 # Per bank write bursts 86system.physmem.perBankWrBursts::3 85223 # Per bank write bursts 87system.physmem.perBankWrBursts::4 87614 # Per bank write bursts 88system.physmem.perBankWrBursts::5 91670 # Per bank write bursts 89system.physmem.perBankWrBursts::6 83331 # Per bank write bursts 90system.physmem.perBankWrBursts::7 85393 # Per bank write bursts 91system.physmem.perBankWrBursts::8 84672 # Per bank write bursts 92system.physmem.perBankWrBursts::9 89835 # Per bank write bursts 93system.physmem.perBankWrBursts::10 89185 # Per bank write bursts 94system.physmem.perBankWrBursts::11 91387 # Per bank write bursts 95system.physmem.perBankWrBursts::12 86991 # Per bank write bursts 96system.physmem.perBankWrBursts::13 87934 # Per bank write bursts 97system.physmem.perBankWrBursts::14 84251 # Per bank write bursts 98system.physmem.perBankWrBursts::15 87044 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 34 # Number of times write queue was full causing retry 101system.physmem.totGap 51660651059000 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 0 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 1141218 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 1400486 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 1073017 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 61473 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 751 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 541 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1073 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 679 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 307 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 335 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 34323 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 39840 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 78472 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 80418 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 82705 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 81025 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 81933 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 85813 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 85053 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 81235 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 82570 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 85921 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 82664 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 82805 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 85182 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 80817 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 79743 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 79137 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 1073 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 741 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 625 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 472 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 563 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 387 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 330 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 327 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 265 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 275 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 294 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 263 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 272 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 180 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 209 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 233 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 155 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 122 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 119 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 164 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 648791 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 250.683724 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 151.960276 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 285.693480 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 280366 43.21% 43.21% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 167406 25.80% 69.02% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 61019 9.41% 78.42% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 33573 5.17% 83.60% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 23084 3.56% 87.15% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 16255 2.51% 89.66% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 11383 1.75% 91.41% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 9506 1.47% 92.88% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 46199 7.12% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 648791 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 76825 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 14.845063 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 142.168306 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-1023 76822 100.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::total 76825 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 76825 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 18.233622 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 17.685886 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 7.065993 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16-19 64901 84.48% 84.48% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20-23 9488 12.35% 96.83% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::24-27 481 0.63% 97.46% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::28-31 307 0.40% 97.85% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::32-35 57 0.07% 97.93% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::36-39 121 0.16% 98.09% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::40-43 251 0.33% 98.41% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::44-47 28 0.04% 98.45% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::48-51 303 0.39% 98.84% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::52-55 81 0.11% 98.95% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::56-59 29 0.04% 98.99% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::60-63 51 0.07% 99.05% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::64-67 317 0.41% 99.47% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::68-71 31 0.04% 99.51% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::76-79 113 0.15% 99.69% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::80-83 181 0.24% 99.92% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::88-91 5 0.01% 99.93% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::92-95 1 0.00% 99.93% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::128-131 10 0.01% 99.96% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::total 76825 # Writes before turning the bus around for reads 274system.physmem.totQLat 16555348236 # Total ticks spent queuing 275system.physmem.totMemAccLat 37939329486 # Total ticks spent from burst creation until serviced by the DRAM 276system.physmem.totBusLat 5702395000 # Total ticks spent in databus transfers 277system.physmem.avgQLat 14516.14 # Average queueing delay per DRAM burst 278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 279system.physmem.avgMemAccLat 33266.14 # Average memory access latency per DRAM burst 280system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s 281system.physmem.avgWrBW 1.74 # Average achieved write bandwidth in MiByte/s 282system.physmem.avgRdBWSys 1.41 # Average system read bandwidth in MiByte/s 283system.physmem.avgWrBWSys 1.74 # Average system write bandwidth in MiByte/s 284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 285system.physmem.busUtil 0.02 # Data bus utilization in percentage 286system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 287system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 288system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 289system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing 290system.physmem.readRowHits 872195 # Number of row buffer hits during reads 291system.physmem.writeRowHits 1020290 # Number of row buffer hits during writes 292system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads 293system.physmem.writeRowHitRate 72.84 # Row buffer hit rate for writes 294system.physmem.avgGap 20304529.14 # Average gap between requests 295system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined 296system.physmem_0.actEnergy 2468362680 # Energy for activate commands per rank (pJ) 297system.physmem_0.preEnergy 1346824875 # Energy for precharge commands per rank (pJ) 298system.physmem_0.readEnergy 4283830200 # Energy for read commands per rank (pJ) 299system.physmem_0.writeEnergy 4532753520 # Energy for write commands per rank (pJ) 300system.physmem_0.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) 301system.physmem_0.actBackEnergy 1318333461255 # Energy for active background per rank (pJ) 302system.physmem_0.preBackEnergy 29839955813250 # Energy for precharge background per rank (pJ) 303system.physmem_0.totalEnergy 34545143413140 # Total energy per rank (pJ) 304system.physmem_0.averagePower 668.693578 # Core power per rank (mW) 305system.physmem_0.memoryStateTime::IDLE 49640663734133 # Time in different power states 306system.physmem_0.memoryStateTime::REF 1725062560000 # Time in different power states 307system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 308system.physmem_0.memoryStateTime::ACT 294925880867 # Time in different power states 309system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 310system.physmem_1.actEnergy 2436497280 # Energy for activate commands per rank (pJ) 311system.physmem_1.preEnergy 1329438000 # Energy for precharge commands per rank (pJ) 312system.physmem_1.readEnergy 4611859200 # Energy for read commands per rank (pJ) 313system.physmem_1.writeEnergy 4544417520 # Energy for write commands per rank (pJ) 314system.physmem_1.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) 315system.physmem_1.actBackEnergy 1316960739945 # Energy for active background per rank (pJ) 316system.physmem_1.preBackEnergy 29841159946500 # Energy for precharge background per rank (pJ) 317system.physmem_1.totalEnergy 34545265265805 # Total energy per rank (pJ) 318system.physmem_1.averagePower 668.695937 # Core power per rank (mW) 319system.physmem_1.memoryStateTime::IDLE 49642646529009 # Time in different power states 320system.physmem_1.memoryStateTime::REF 1725062560000 # Time in different power states 321system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 322system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states 323system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 324system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 325system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 330system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 332system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 333system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 340system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 341system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 342system.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 343system.bridge.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 344system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 345system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 346system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 347system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 348system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 349system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 350system.cpu.branchPred.lookups 256209592 # Number of BP lookups 351system.cpu.branchPred.condPredicted 178352168 # Number of conditional branches predicted 352system.cpu.branchPred.condIncorrect 12215343 # Number of conditional branches incorrect 353system.cpu.branchPred.BTBLookups 188533609 # Number of BTB lookups 354system.cpu.branchPred.BTBHits 127068742 # Number of BTB hits 355system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 356system.cpu.branchPred.BTBHitPct 67.398456 # BTB Hit Percentage 357system.cpu.branchPred.usedRAS 31319231 # Number of times the RAS was used to get a target. 358system.cpu.branchPred.RASInCorrect 2132154 # Number of incorrect RAS predictions. 359system.cpu.branchPred.indirectLookups 7072039 # Number of indirect predictor lookups. 360system.cpu.branchPred.indirectHits 5016643 # Number of indirect target hits. 361system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses. 362system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches. 363system.cpu_clk_domain.clock 500 # Clock period in ticks 364system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 365system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 366system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 369system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 373system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 374system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 375system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 376system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 377system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 378system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 379system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 380system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 381system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 382system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 383system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 384system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 385system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 386system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 387system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 388system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 389system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 390system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 391system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 392system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 393system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 394system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 395system.cpu.dtb.walker.walks 561578 # Table walker walks requested 396system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors 397system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate 398system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181761 # Level at which table walker walks with long descriptors terminate 399system.cpu.dtb.walker.walkWaitTime::samples 561578 # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::0 561578 100.00% 100.00% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::total 561578 # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkCompletionTime::samples 202628 # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::mean 27245.592909 # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::gmean 23033.802603 # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::stdev 21444.921579 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::0-65535 200160 98.78% 98.78% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.78% # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::131072-196607 2084 1.03% 99.81% # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::196608-262143 75 0.04% 99.85% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::262144-327679 137 0.07% 99.92% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::327680-393215 55 0.03% 99.94% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::393216-458751 85 0.04% 99.99% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 99.99% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::589824-655359 10 0.00% 100.00% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::total 202628 # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution 420system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution 421system.cpu.dtb.walker.walkPageSizes::4K 181762 89.70% 89.70% # Table walker page sizes translated 422system.cpu.dtb.walker.walkPageSizes::2M 20867 10.30% 100.00% # Table walker page sizes translated 423system.cpu.dtb.walker.walkPageSizes::total 202629 # Table walker page sizes translated 424system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561578 # Table walker requests started/completed, data/inst 425system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 426system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561578 # Table walker requests started/completed, data/inst 427system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202629 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202629 # Table walker requests started/completed, data/inst 430system.cpu.dtb.walker.walkRequestOrigin::total 764207 # Table walker requests started/completed, data/inst 431system.cpu.dtb.inst_hits 0 # ITB inst hits 432system.cpu.dtb.inst_misses 0 # ITB inst misses 433system.cpu.dtb.read_hits 179568747 # DTB read hits 434system.cpu.dtb.read_misses 462708 # DTB read misses 435system.cpu.dtb.write_hits 159223685 # DTB write hits 436system.cpu.dtb.write_misses 98870 # DTB write misses 437system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 438system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 439system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 440system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID	12sim_insts 929398934 # Number of instructions simulated 13sim_ops 1092086880 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 394752 # Number of bytes read from this memory 22system.physmem.bytes_read::total 73038088 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 10229888 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 10229888 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 89631104 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 27system.physmem.bytes_written::total 89651684 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 5915 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 4899 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 159842 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 964409 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6168 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 1141233 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1400486 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 1403059 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 7328 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 6069 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 198021 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1194746 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 7641 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 1413805 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 198021 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 198021 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1734998 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 1735396 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1734998 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 7328 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 6069 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 198021 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1195144 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 7641 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 3149201 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 1141233 # Number of read requests accepted 56system.physmem.writeReqs 1403059 # Number of write requests accepted 57system.physmem.readBursts 1141233 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 1403059 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 72990656 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 48256 # Total number of bytes read from write queue 61system.physmem.bytesWritten 89651072 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 73038088 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 89651684 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 754 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 69460 # Per bank write bursts 68system.physmem.perBankRdBursts::1 75077 # Per bank write bursts 69system.physmem.perBankRdBursts::2 69733 # Per bank write bursts 70system.physmem.perBankRdBursts::3 63631 # Per bank write bursts 71system.physmem.perBankRdBursts::4 66485 # Per bank write bursts 72system.physmem.perBankRdBursts::5 73840 # Per bank write bursts 73system.physmem.perBankRdBursts::6 65699 # Per bank write bursts 74system.physmem.perBankRdBursts::7 65290 # Per bank write bursts 75system.physmem.perBankRdBursts::8 63012 # Per bank write bursts 76system.physmem.perBankRdBursts::9 121917 # Per bank write bursts 77system.physmem.perBankRdBursts::10 71008 # Per bank write bursts 78system.physmem.perBankRdBursts::11 72120 # Per bank write bursts 79system.physmem.perBankRdBursts::12 67529 # Per bank write bursts 80system.physmem.perBankRdBursts::13 67730 # Per bank write bursts 81system.physmem.perBankRdBursts::14 61491 # Per bank write bursts 82system.physmem.perBankRdBursts::15 66457 # Per bank write bursts 83system.physmem.perBankWrBursts::0 88448 # Per bank write bursts 84system.physmem.perBankWrBursts::1 89667 # Per bank write bursts 85system.physmem.perBankWrBursts::2 88153 # Per bank write bursts 86system.physmem.perBankWrBursts::3 85223 # Per bank write bursts 87system.physmem.perBankWrBursts::4 87614 # Per bank write bursts 88system.physmem.perBankWrBursts::5 91670 # Per bank write bursts 89system.physmem.perBankWrBursts::6 83331 # Per bank write bursts 90system.physmem.perBankWrBursts::7 85393 # Per bank write bursts 91system.physmem.perBankWrBursts::8 84672 # Per bank write bursts 92system.physmem.perBankWrBursts::9 89835 # Per bank write bursts 93system.physmem.perBankWrBursts::10 89185 # Per bank write bursts 94system.physmem.perBankWrBursts::11 91387 # Per bank write bursts 95system.physmem.perBankWrBursts::12 86991 # Per bank write bursts 96system.physmem.perBankWrBursts::13 87934 # Per bank write bursts 97system.physmem.perBankWrBursts::14 84251 # Per bank write bursts 98system.physmem.perBankWrBursts::15 87044 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 34 # Number of times write queue was full causing retry 101system.physmem.totGap 51660651059000 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 0 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 1141218 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 1400486 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 1073017 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 61473 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 751 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 541 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1073 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 679 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 307 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 335 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 34323 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 39840 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 78472 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 80418 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 82705 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 81025 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 81933 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 85813 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 85053 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 81235 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 82570 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 85921 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 82664 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 82805 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 85182 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 80817 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 79743 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 79137 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 1073 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 741 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 625 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 472 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 563 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 387 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 330 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 327 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 265 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 275 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 294 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 263 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 272 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 180 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 209 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 233 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 155 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 122 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 119 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 164 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 648791 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 250.683724 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 151.960276 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 285.693480 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 280366 43.21% 43.21% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 167406 25.80% 69.02% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 61019 9.41% 78.42% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 33573 5.17% 83.60% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 23084 3.56% 87.15% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 16255 2.51% 89.66% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 11383 1.75% 91.41% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 9506 1.47% 92.88% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 46199 7.12% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 648791 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 76825 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 14.845063 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 142.168306 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-1023 76822 100.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::total 76825 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 76825 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 18.233622 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 17.685886 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 7.065993 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16-19 64901 84.48% 84.48% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20-23 9488 12.35% 96.83% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::24-27 481 0.63% 97.46% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::28-31 307 0.40% 97.85% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::32-35 57 0.07% 97.93% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::36-39 121 0.16% 98.09% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::40-43 251 0.33% 98.41% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::44-47 28 0.04% 98.45% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::48-51 303 0.39% 98.84% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::52-55 81 0.11% 98.95% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::56-59 29 0.04% 98.99% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::60-63 51 0.07% 99.05% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::64-67 317 0.41% 99.47% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::68-71 31 0.04% 99.51% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::76-79 113 0.15% 99.69% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::80-83 181 0.24% 99.92% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::88-91 5 0.01% 99.93% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::92-95 1 0.00% 99.93% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::128-131 10 0.01% 99.96% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::total 76825 # Writes before turning the bus around for reads 274system.physmem.totQLat 16555348236 # Total ticks spent queuing 275system.physmem.totMemAccLat 37939329486 # Total ticks spent from burst creation until serviced by the DRAM 276system.physmem.totBusLat 5702395000 # Total ticks spent in databus transfers 277system.physmem.avgQLat 14516.14 # Average queueing delay per DRAM burst 278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 279system.physmem.avgMemAccLat 33266.14 # Average memory access latency per DRAM burst 280system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s 281system.physmem.avgWrBW 1.74 # Average achieved write bandwidth in MiByte/s 282system.physmem.avgRdBWSys 1.41 # Average system read bandwidth in MiByte/s 283system.physmem.avgWrBWSys 1.74 # Average system write bandwidth in MiByte/s 284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 285system.physmem.busUtil 0.02 # Data bus utilization in percentage 286system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 287system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 288system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 289system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing 290system.physmem.readRowHits 872195 # Number of row buffer hits during reads 291system.physmem.writeRowHits 1020290 # Number of row buffer hits during writes 292system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads 293system.physmem.writeRowHitRate 72.84 # Row buffer hit rate for writes 294system.physmem.avgGap 20304529.14 # Average gap between requests 295system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined 296system.physmem_0.actEnergy 2468362680 # Energy for activate commands per rank (pJ) 297system.physmem_0.preEnergy 1346824875 # Energy for precharge commands per rank (pJ) 298system.physmem_0.readEnergy 4283830200 # Energy for read commands per rank (pJ) 299system.physmem_0.writeEnergy 4532753520 # Energy for write commands per rank (pJ) 300system.physmem_0.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) 301system.physmem_0.actBackEnergy 1318333461255 # Energy for active background per rank (pJ) 302system.physmem_0.preBackEnergy 29839955813250 # Energy for precharge background per rank (pJ) 303system.physmem_0.totalEnergy 34545143413140 # Total energy per rank (pJ) 304system.physmem_0.averagePower 668.693578 # Core power per rank (mW) 305system.physmem_0.memoryStateTime::IDLE 49640663734133 # Time in different power states 306system.physmem_0.memoryStateTime::REF 1725062560000 # Time in different power states 307system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 308system.physmem_0.memoryStateTime::ACT 294925880867 # Time in different power states 309system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 310system.physmem_1.actEnergy 2436497280 # Energy for activate commands per rank (pJ) 311system.physmem_1.preEnergy 1329438000 # Energy for precharge commands per rank (pJ) 312system.physmem_1.readEnergy 4611859200 # Energy for read commands per rank (pJ) 313system.physmem_1.writeEnergy 4544417520 # Energy for write commands per rank (pJ) 314system.physmem_1.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) 315system.physmem_1.actBackEnergy 1316960739945 # Energy for active background per rank (pJ) 316system.physmem_1.preBackEnergy 29841159946500 # Energy for precharge background per rank (pJ) 317system.physmem_1.totalEnergy 34545265265805 # Total energy per rank (pJ) 318system.physmem_1.averagePower 668.695937 # Core power per rank (mW) 319system.physmem_1.memoryStateTime::IDLE 49642646529009 # Time in different power states 320system.physmem_1.memoryStateTime::REF 1725062560000 # Time in different power states 321system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 322system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states 323system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 324system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 325system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 330system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 332system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 333system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 340system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 341system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 342system.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 343system.bridge.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 344system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 345system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 346system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 347system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 348system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 349system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 350system.cpu.branchPred.lookups 256209592 # Number of BP lookups 351system.cpu.branchPred.condPredicted 178352168 # Number of conditional branches predicted 352system.cpu.branchPred.condIncorrect 12215343 # Number of conditional branches incorrect 353system.cpu.branchPred.BTBLookups 188533609 # Number of BTB lookups 354system.cpu.branchPred.BTBHits 127068742 # Number of BTB hits 355system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 356system.cpu.branchPred.BTBHitPct 67.398456 # BTB Hit Percentage 357system.cpu.branchPred.usedRAS 31319231 # Number of times the RAS was used to get a target. 358system.cpu.branchPred.RASInCorrect 2132154 # Number of incorrect RAS predictions. 359system.cpu.branchPred.indirectLookups 7072039 # Number of indirect predictor lookups. 360system.cpu.branchPred.indirectHits 5016643 # Number of indirect target hits. 361system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses. 362system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches. 363system.cpu_clk_domain.clock 500 # Clock period in ticks 364system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 365system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 366system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 369system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 373system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 374system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 375system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 376system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 377system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 378system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 379system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 380system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 381system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 382system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 383system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 384system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 385system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 386system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 387system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 388system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 389system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 390system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 391system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 392system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 393system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 394system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 395system.cpu.dtb.walker.walks 561578 # Table walker walks requested 396system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors 397system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate 398system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181761 # Level at which table walker walks with long descriptors terminate 399system.cpu.dtb.walker.walkWaitTime::samples 561578 # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::0 561578 100.00% 100.00% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::total 561578 # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkCompletionTime::samples 202628 # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::mean 27245.592909 # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::gmean 23033.802603 # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::stdev 21444.921579 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::0-65535 200160 98.78% 98.78% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.78% # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::131072-196607 2084 1.03% 99.81% # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::196608-262143 75 0.04% 99.85% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::262144-327679 137 0.07% 99.92% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::327680-393215 55 0.03% 99.94% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::393216-458751 85 0.04% 99.99% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 99.99% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::589824-655359 10 0.00% 100.00% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::total 202628 # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution 420system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution 421system.cpu.dtb.walker.walkPageSizes::4K 181762 89.70% 89.70% # Table walker page sizes translated 422system.cpu.dtb.walker.walkPageSizes::2M 20867 10.30% 100.00% # Table walker page sizes translated 423system.cpu.dtb.walker.walkPageSizes::total 202629 # Table walker page sizes translated 424system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561578 # Table walker requests started/completed, data/inst 425system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 426system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561578 # Table walker requests started/completed, data/inst 427system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202629 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202629 # Table walker requests started/completed, data/inst 430system.cpu.dtb.walker.walkRequestOrigin::total 764207 # Table walker requests started/completed, data/inst 431system.cpu.dtb.inst_hits 0 # ITB inst hits 432system.cpu.dtb.inst_misses 0 # ITB inst misses 433system.cpu.dtb.read_hits 179568747 # DTB read hits 434system.cpu.dtb.read_misses 462708 # DTB read misses 435system.cpu.dtb.write_hits 159223685 # DTB write hits 436system.cpu.dtb.write_misses 98870 # DTB write misses 437system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 438system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 439system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 440system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID
441system.cpu.dtb.flush_entries 78994 # Number of entries that have been flushed from TLB	441system.cpu.dtb.flush_entries 78930 # Number of entries that have been flushed from TLB
442system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions 443system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch 444system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 445system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions 446system.cpu.dtb.read_accesses 180031455 # DTB read accesses 447system.cpu.dtb.write_accesses 159322555 # DTB write accesses 448system.cpu.dtb.inst_accesses 0 # ITB inst accesses 449system.cpu.dtb.hits 338792432 # DTB hits 450system.cpu.dtb.misses 561578 # DTB misses 451system.cpu.dtb.accesses 339354010 # DTB accesses 452system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 453system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 461system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 462system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 463system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 464system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 465system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 466system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 467system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 468system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 469system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 470system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 471system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 472system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 473system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 474system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 475system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 476system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 477system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 478system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 479system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 480system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 481system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 482system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 483system.cpu.itb.walker.walks 133823 # Table walker walks requested 484system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors 485system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate 486system.cpu.itb.walker.walksLongTerminationLevel::Level3 116932 # Level at which table walker walks with long descriptors terminate 487system.cpu.itb.walker.walkWaitTime::samples 133823 # Table walker wait (enqueue to first request) latency 488system.cpu.itb.walker.walkWaitTime::0 133823 100.00% 100.00% # Table walker wait (enqueue to first request) latency 489system.cpu.itb.walker.walkWaitTime::total 133823 # Table walker wait (enqueue to first request) latency 490system.cpu.itb.walker.walkCompletionTime::samples 117989 # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::mean 30581.308427 # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::gmean 25983.502451 # Table walker service (enqueue to completion) latency 493system.cpu.itb.walker.walkCompletionTime::stdev 24251.357512 # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::0-65535 115208 97.64% 97.64% # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 97.65% # Table walker service (enqueue to completion) latency 496system.cpu.itb.walker.walkCompletionTime::131072-196607 2538 2.15% 99.80% # Table walker service (enqueue to completion) latency 497system.cpu.itb.walker.walkCompletionTime::196608-262143 65 0.06% 99.85% # Table walker service (enqueue to completion) latency 498system.cpu.itb.walker.walkCompletionTime::262144-327679 122 0.10% 99.96% # Table walker service (enqueue to completion) latency 499system.cpu.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.98% # Table walker service (enqueue to completion) latency 500system.cpu.itb.walker.walkCompletionTime::393216-458751 18 0.02% 100.00% # Table walker service (enqueue to completion) latency 501system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 502system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 503system.cpu.itb.walker.walkCompletionTime::total 117989 # Table walker service (enqueue to completion) latency 504system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution 505system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution 506system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution 507system.cpu.itb.walker.walkPageSizes::4K 116932 99.10% 99.10% # Table walker page sizes translated 508system.cpu.itb.walker.walkPageSizes::2M 1057 0.90% 100.00% # Table walker page sizes translated 509system.cpu.itb.walker.walkPageSizes::total 117989 # Table walker page sizes translated 510system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 511system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 133823 # Table walker requests started/completed, data/inst 512system.cpu.itb.walker.walkRequestOrigin_Requested::total 133823 # Table walker requests started/completed, data/inst 513system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 514system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 117989 # Table walker requests started/completed, data/inst 515system.cpu.itb.walker.walkRequestOrigin_Completed::total 117989 # Table walker requests started/completed, data/inst 516system.cpu.itb.walker.walkRequestOrigin::total 251812 # Table walker requests started/completed, data/inst 517system.cpu.itb.inst_hits 442793055 # ITB inst hits 518system.cpu.itb.inst_misses 133823 # ITB inst misses 519system.cpu.itb.read_hits 0 # DTB read hits 520system.cpu.itb.read_misses 0 # DTB read misses 521system.cpu.itb.write_hits 0 # DTB write hits 522system.cpu.itb.write_misses 0 # DTB write misses 523system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 524system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 525system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 526system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID	442system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions 443system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch 444system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 445system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions 446system.cpu.dtb.read_accesses 180031455 # DTB read accesses 447system.cpu.dtb.write_accesses 159322555 # DTB write accesses 448system.cpu.dtb.inst_accesses 0 # ITB inst accesses 449system.cpu.dtb.hits 338792432 # DTB hits 450system.cpu.dtb.misses 561578 # DTB misses 451system.cpu.dtb.accesses 339354010 # DTB accesses 452system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 453system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 461system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 462system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 463system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 464system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 465system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 466system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 467system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 468system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 469system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 470system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 471system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 472system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 473system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 474system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 475system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 476system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 477system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 478system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 479system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 480system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 481system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 482system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 483system.cpu.itb.walker.walks 133823 # Table walker walks requested 484system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors 485system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate 486system.cpu.itb.walker.walksLongTerminationLevel::Level3 116932 # Level at which table walker walks with long descriptors terminate 487system.cpu.itb.walker.walkWaitTime::samples 133823 # Table walker wait (enqueue to first request) latency 488system.cpu.itb.walker.walkWaitTime::0 133823 100.00% 100.00% # Table walker wait (enqueue to first request) latency 489system.cpu.itb.walker.walkWaitTime::total 133823 # Table walker wait (enqueue to first request) latency 490system.cpu.itb.walker.walkCompletionTime::samples 117989 # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::mean 30581.308427 # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::gmean 25983.502451 # Table walker service (enqueue to completion) latency 493system.cpu.itb.walker.walkCompletionTime::stdev 24251.357512 # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::0-65535 115208 97.64% 97.64% # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 97.65% # Table walker service (enqueue to completion) latency 496system.cpu.itb.walker.walkCompletionTime::131072-196607 2538 2.15% 99.80% # Table walker service (enqueue to completion) latency 497system.cpu.itb.walker.walkCompletionTime::196608-262143 65 0.06% 99.85% # Table walker service (enqueue to completion) latency 498system.cpu.itb.walker.walkCompletionTime::262144-327679 122 0.10% 99.96% # Table walker service (enqueue to completion) latency 499system.cpu.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.98% # Table walker service (enqueue to completion) latency 500system.cpu.itb.walker.walkCompletionTime::393216-458751 18 0.02% 100.00% # Table walker service (enqueue to completion) latency 501system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 502system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 503system.cpu.itb.walker.walkCompletionTime::total 117989 # Table walker service (enqueue to completion) latency 504system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution 505system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution 506system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution 507system.cpu.itb.walker.walkPageSizes::4K 116932 99.10% 99.10% # Table walker page sizes translated 508system.cpu.itb.walker.walkPageSizes::2M 1057 0.90% 100.00% # Table walker page sizes translated 509system.cpu.itb.walker.walkPageSizes::total 117989 # Table walker page sizes translated 510system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 511system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 133823 # Table walker requests started/completed, data/inst 512system.cpu.itb.walker.walkRequestOrigin_Requested::total 133823 # Table walker requests started/completed, data/inst 513system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 514system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 117989 # Table walker requests started/completed, data/inst 515system.cpu.itb.walker.walkRequestOrigin_Completed::total 117989 # Table walker requests started/completed, data/inst 516system.cpu.itb.walker.walkRequestOrigin::total 251812 # Table walker requests started/completed, data/inst 517system.cpu.itb.inst_hits 442793055 # ITB inst hits 518system.cpu.itb.inst_misses 133823 # ITB inst misses 519system.cpu.itb.read_hits 0 # DTB read hits 520system.cpu.itb.read_misses 0 # DTB read misses 521system.cpu.itb.write_hits 0 # DTB write hits 522system.cpu.itb.write_misses 0 # DTB write misses 523system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 524system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 525system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 526system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID
527system.cpu.itb.flush_entries 56590 # Number of entries that have been flushed from TLB	527system.cpu.itb.flush_entries 56526 # Number of entries that have been flushed from TLB
528system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 529system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 530system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 531system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions 532system.cpu.itb.read_accesses 0 # DTB read accesses 533system.cpu.itb.write_accesses 0 # DTB write accesses 534system.cpu.itb.inst_accesses 442926878 # ITB inst accesses 535system.cpu.itb.hits 442793055 # DTB hits 536system.cpu.itb.misses 133823 # DTB misses 537system.cpu.itb.accesses 442926878 # DTB accesses 538system.cpu.numPwrStateTransitions 33032 # Number of power state transitions 539system.cpu.pwrStateClkGateDist::samples 16516 # Distribution of time spent in the clock gated state 540system.cpu.pwrStateClkGateDist::mean 3050356912.427888 # Distribution of time spent in the clock gated state 541system.cpu.pwrStateClkGateDist::stdev 59773934276.156128 # Distribution of time spent in the clock gated state 542system.cpu.pwrStateClkGateDist::underflows 7219 43.71% 43.71% # Distribution of time spent in the clock gated state 543system.cpu.pwrStateClkGateDist::1000-5e+10 9262 56.08% 99.79% # Distribution of time spent in the clock gated state 544system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state 545system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state 546system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 547system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 548system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 549system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 550system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 551system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 552system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 553system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 554system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 555system.cpu.pwrStateClkGateDist::max_value 1988777743356 # Distribution of time spent in the clock gated state 556system.cpu.pwrStateClkGateDist::total 16516 # Distribution of time spent in the clock gated state 557system.cpu.pwrStateResidencyTicks::ON 1280958181341 # Cumulative time (in ticks) in various power states 558system.cpu.pwrStateResidencyTicks::CLK_GATED 50379694765659 # Cumulative time (in ticks) in various power states 559system.cpu.numCycles 2561963341 # number of cpu cycles simulated 560system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 561system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 562system.cpu.committedInsts 929398934 # Number of instructions committed 563system.cpu.committedOps 1092086880 # Number of ops (including micro ops) committed 564system.cpu.discardedOps 94664249 # Number of ops (including micro ops) which were discarded before commit 565system.cpu.numFetchSuspends 7656 # Number of times Execute suspended instruction fetching 566system.cpu.quiesceCycles 100760459460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 567system.cpu.cpi 2.756581 # CPI: cycles per instruction 568system.cpu.ipc 0.362768 # IPC: instructions per cycle 569system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 570system.cpu.op_class_0::IntAlu 756821893 69.30% 69.30% # Class of committed instruction 571system.cpu.op_class_0::IntMult 2277263 0.21% 69.51% # Class of committed instruction 572system.cpu.op_class_0::IntDiv 98455 0.01% 69.52% # Class of committed instruction 573system.cpu.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction 574system.cpu.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction 575system.cpu.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction 576system.cpu.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction 577system.cpu.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction 578system.cpu.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction 579system.cpu.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction 580system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction 581system.cpu.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction 582system.cpu.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction 583system.cpu.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction 584system.cpu.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction 585system.cpu.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction 586system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction 587system.cpu.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction 588system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction 589system.cpu.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction 590system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction 591system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction 592system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction 593system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction 594system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction 595system.cpu.op_class_0::SimdFloatMisc 109444 0.01% 69.53% # Class of committed instruction 596system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction 597system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction 598system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction 599system.cpu.op_class_0::MemRead 174118935 15.94% 85.47% # Class of committed instruction 600system.cpu.op_class_0::MemWrite 158660847 14.53% 100.00% # Class of committed instruction 601system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 602system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 603system.cpu.op_class_0::total 1092086880 # Class of committed instruction 604system.cpu.kern.inst.arm 0 # number of arm instructions executed 605system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed 606system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked 607system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped 608system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 609system.cpu.dcache.tags.replacements 10826762 # number of replacements 610system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use 611system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks. 612system.cpu.dcache.tags.sampled_refs 10827274 # Sample count of references to valid blocks. 613system.cpu.dcache.tags.avg_refs 29.813150 # Average number of references to valid blocks. 614system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. 615system.cpu.dcache.tags.occ_blocks::cpu.data 511.930071 # Average occupied blocks per requestor 616system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 617system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 618system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 619system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 620system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 621system.cpu.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 622system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 623system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 624system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses 625system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses 626system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 627system.cpu.dcache.ReadReq_hits::cpu.data 165131668 # number of ReadReq hits 628system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits 629system.cpu.dcache.WriteReq_hits::cpu.data 148654336 # number of WriteReq hits 630system.cpu.dcache.WriteReq_hits::total 148654336 # number of WriteReq hits 631system.cpu.dcache.SoftPFReq_hits::cpu.data 515490 # number of SoftPFReq hits 632system.cpu.dcache.SoftPFReq_hits::total 515490 # number of SoftPFReq hits 633system.cpu.dcache.WriteLineReq_hits::cpu.data 336587 # number of WriteLineReq hits 634system.cpu.dcache.WriteLineReq_hits::total 336587 # number of WriteLineReq hits 635system.cpu.dcache.LoadLockedReq_hits::cpu.data 3899601 # number of LoadLockedReq hits 636system.cpu.dcache.LoadLockedReq_hits::total 3899601 # number of LoadLockedReq hits 637system.cpu.dcache.StoreCondReq_hits::cpu.data 4208890 # number of StoreCondReq hits 638system.cpu.dcache.StoreCondReq_hits::total 4208890 # number of StoreCondReq hits 639system.cpu.dcache.demand_hits::cpu.data 314122591 # number of demand (read+write) hits 640system.cpu.dcache.demand_hits::total 314122591 # number of demand (read+write) hits 641system.cpu.dcache.overall_hits::cpu.data 314638081 # number of overall hits 642system.cpu.dcache.overall_hits::total 314638081 # number of overall hits 643system.cpu.dcache.ReadReq_misses::cpu.data 6423881 # number of ReadReq misses 644system.cpu.dcache.ReadReq_misses::total 6423881 # number of ReadReq misses 645system.cpu.dcache.WriteReq_misses::cpu.data 4177328 # number of WriteReq misses 646system.cpu.dcache.WriteReq_misses::total 4177328 # number of WriteReq misses 647system.cpu.dcache.SoftPFReq_misses::cpu.data 1420881 # number of SoftPFReq misses 648system.cpu.dcache.SoftPFReq_misses::total 1420881 # number of SoftPFReq misses 649system.cpu.dcache.WriteLineReq_misses::cpu.data 1240100 # number of WriteLineReq misses 650system.cpu.dcache.WriteLineReq_misses::total 1240100 # number of WriteLineReq misses 651system.cpu.dcache.LoadLockedReq_misses::cpu.data 311002 # number of LoadLockedReq misses 652system.cpu.dcache.LoadLockedReq_misses::total 311002 # number of LoadLockedReq misses 653system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 654system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 655system.cpu.dcache.demand_misses::cpu.data 11841309 # number of demand (read+write) misses 656system.cpu.dcache.demand_misses::total 11841309 # number of demand (read+write) misses 657system.cpu.dcache.overall_misses::cpu.data 13262190 # number of overall misses 658system.cpu.dcache.overall_misses::total 13262190 # number of overall misses 659system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500 # number of ReadReq miss cycles 660system.cpu.dcache.ReadReq_miss_latency::total 119203222500 # number of ReadReq miss cycles 661system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500 # number of WriteReq miss cycles 662system.cpu.dcache.WriteReq_miss_latency::total 206322817500 # number of WriteReq miss cycles 663system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53471775500 # number of WriteLineReq miss cycles 664system.cpu.dcache.WriteLineReq_miss_latency::total 53471775500 # number of WriteLineReq miss cycles 665system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5200645500 # number of LoadLockedReq miss cycles 666system.cpu.dcache.LoadLockedReq_miss_latency::total 5200645500 # number of LoadLockedReq miss cycles 667system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles 668system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles 669system.cpu.dcache.demand_miss_latency::cpu.data 378997815500 # number of demand (read+write) miss cycles 670system.cpu.dcache.demand_miss_latency::total 378997815500 # number of demand (read+write) miss cycles 671system.cpu.dcache.overall_miss_latency::cpu.data 378997815500 # number of overall miss cycles 672system.cpu.dcache.overall_miss_latency::total 378997815500 # number of overall miss cycles 673system.cpu.dcache.ReadReq_accesses::cpu.data 171555549 # number of ReadReq accesses(hits+misses) 674system.cpu.dcache.ReadReq_accesses::total 171555549 # number of ReadReq accesses(hits+misses) 675system.cpu.dcache.WriteReq_accesses::cpu.data 152831664 # number of WriteReq accesses(hits+misses) 676system.cpu.dcache.WriteReq_accesses::total 152831664 # number of WriteReq accesses(hits+misses) 677system.cpu.dcache.SoftPFReq_accesses::cpu.data 1936371 # number of SoftPFReq accesses(hits+misses) 678system.cpu.dcache.SoftPFReq_accesses::total 1936371 # number of SoftPFReq accesses(hits+misses) 679system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576687 # number of WriteLineReq accesses(hits+misses) 680system.cpu.dcache.WriteLineReq_accesses::total 1576687 # number of WriteLineReq accesses(hits+misses) 681system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4210603 # number of LoadLockedReq accesses(hits+misses) 682system.cpu.dcache.LoadLockedReq_accesses::total 4210603 # number of LoadLockedReq accesses(hits+misses) 683system.cpu.dcache.StoreCondReq_accesses::cpu.data 4208892 # number of StoreCondReq accesses(hits+misses) 684system.cpu.dcache.StoreCondReq_accesses::total 4208892 # number of StoreCondReq accesses(hits+misses) 685system.cpu.dcache.demand_accesses::cpu.data 325963900 # number of demand (read+write) accesses 686system.cpu.dcache.demand_accesses::total 325963900 # number of demand (read+write) accesses 687system.cpu.dcache.overall_accesses::cpu.data 327900271 # number of overall (read+write) accesses 688system.cpu.dcache.overall_accesses::total 327900271 # number of overall (read+write) accesses 689system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037445 # miss rate for ReadReq accesses 690system.cpu.dcache.ReadReq_miss_rate::total 0.037445 # miss rate for ReadReq accesses 691system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027333 # miss rate for WriteReq accesses 692system.cpu.dcache.WriteReq_miss_rate::total 0.027333 # miss rate for WriteReq accesses 693system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733786 # miss rate for SoftPFReq accesses 694system.cpu.dcache.SoftPFReq_miss_rate::total 0.733786 # miss rate for SoftPFReq accesses 695system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786523 # miss rate for WriteLineReq accesses 696system.cpu.dcache.WriteLineReq_miss_rate::total 0.786523 # miss rate for WriteLineReq accesses 697system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073862 # miss rate for LoadLockedReq accesses 698system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073862 # miss rate for LoadLockedReq accesses 699system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 700system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 701system.cpu.dcache.demand_miss_rate::cpu.data 0.036327 # miss rate for demand accesses 702system.cpu.dcache.demand_miss_rate::total 0.036327 # miss rate for demand accesses 703system.cpu.dcache.overall_miss_rate::cpu.data 0.040446 # miss rate for overall accesses 704system.cpu.dcache.overall_miss_rate::total 0.040446 # miss rate for overall accesses 705system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562 # average ReadReq miss latency 706system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562 # average ReadReq miss latency 707system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209 # average WriteReq miss latency 708system.cpu.dcache.WriteReq_avg_miss_latency::total 49391.098209 # average WriteReq miss latency 709system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43118.922264 # average WriteLineReq miss latency 710system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43118.922264 # average WriteLineReq miss latency 711system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259 # average LoadLockedReq miss latency 712system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259 # average LoadLockedReq miss latency 713system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency 714system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency 715system.cpu.dcache.demand_avg_miss_latency::cpu.data 32006.412087 # average overall miss latency 716system.cpu.dcache.demand_avg_miss_latency::total 32006.412087 # average overall miss latency 717system.cpu.dcache.overall_avg_miss_latency::cpu.data 28577.317585 # average overall miss latency 718system.cpu.dcache.overall_avg_miss_latency::total 28577.317585 # average overall miss latency 719system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 720system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 721system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 722system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 723system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 724system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 725system.cpu.dcache.writebacks::writebacks 8312311 # number of writebacks 726system.cpu.dcache.writebacks::total 8312311 # number of writebacks 727system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778551 # number of ReadReq MSHR hits 728system.cpu.dcache.ReadReq_mshr_hits::total 778551 # number of ReadReq MSHR hits 729system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841560 # number of WriteReq MSHR hits 730system.cpu.dcache.WriteReq_mshr_hits::total 1841560 # number of WriteReq MSHR hits 731system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 166 # number of WriteLineReq MSHR hits 732system.cpu.dcache.WriteLineReq_mshr_hits::total 166 # number of WriteLineReq MSHR hits 733system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69564 # number of LoadLockedReq MSHR hits 734system.cpu.dcache.LoadLockedReq_mshr_hits::total 69564 # number of LoadLockedReq MSHR hits 735system.cpu.dcache.demand_mshr_hits::cpu.data 2620277 # number of demand (read+write) MSHR hits 736system.cpu.dcache.demand_mshr_hits::total 2620277 # number of demand (read+write) MSHR hits 737system.cpu.dcache.overall_mshr_hits::cpu.data 2620277 # number of overall MSHR hits 738system.cpu.dcache.overall_mshr_hits::total 2620277 # number of overall MSHR hits 739system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5645330 # number of ReadReq MSHR misses 740system.cpu.dcache.ReadReq_mshr_misses::total 5645330 # number of ReadReq MSHR misses 741system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2335768 # number of WriteReq MSHR misses 742system.cpu.dcache.WriteReq_mshr_misses::total 2335768 # number of WriteReq MSHR misses 743system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1413353 # number of SoftPFReq MSHR misses 744system.cpu.dcache.SoftPFReq_mshr_misses::total 1413353 # number of SoftPFReq MSHR misses 745system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1239934 # number of WriteLineReq MSHR misses 746system.cpu.dcache.WriteLineReq_mshr_misses::total 1239934 # number of WriteLineReq MSHR misses 747system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241438 # number of LoadLockedReq MSHR misses 748system.cpu.dcache.LoadLockedReq_mshr_misses::total 241438 # number of LoadLockedReq MSHR misses 749system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 750system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 751system.cpu.dcache.demand_mshr_misses::cpu.data 9221032 # number of demand (read+write) MSHR misses 752system.cpu.dcache.demand_mshr_misses::total 9221032 # number of demand (read+write) MSHR misses 753system.cpu.dcache.overall_mshr_misses::cpu.data 10634385 # number of overall MSHR misses 754system.cpu.dcache.overall_mshr_misses::total 10634385 # number of overall MSHR misses 755system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 756system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 757system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 758system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 759system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 760system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 761system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97557432500 # number of ReadReq MSHR miss cycles 762system.cpu.dcache.ReadReq_mshr_miss_latency::total 97557432500 # number of ReadReq MSHR miss cycles 763system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109336281500 # number of WriteReq MSHR miss cycles 764system.cpu.dcache.WriteReq_mshr_miss_latency::total 109336281500 # number of WriteReq MSHR miss cycles 765system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26901290500 # number of SoftPFReq MSHR miss cycles 766system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26901290500 # number of SoftPFReq MSHR miss cycles 767system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52221764000 # number of WriteLineReq MSHR miss cycles 768system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52221764000 # number of WriteLineReq MSHR miss cycles 769system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3529658500 # number of LoadLockedReq MSHR miss cycles 770system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3529658500 # number of LoadLockedReq MSHR miss cycles 771system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles 772system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles 773system.cpu.dcache.demand_mshr_miss_latency::cpu.data 259115478000 # number of demand (read+write) MSHR miss cycles 774system.cpu.dcache.demand_mshr_miss_latency::total 259115478000 # number of demand (read+write) MSHR miss cycles 775system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286016768500 # number of overall MSHR miss cycles 776system.cpu.dcache.overall_mshr_miss_latency::total 286016768500 # number of overall MSHR miss cycles 777system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197628500 # number of ReadReq MSHR uncacheable cycles 778system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197628500 # number of ReadReq MSHR uncacheable cycles 779system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197628500 # number of overall MSHR uncacheable cycles 780system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197628500 # number of overall MSHR uncacheable cycles 781system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032907 # mshr miss rate for ReadReq accesses 782system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032907 # mshr miss rate for ReadReq accesses 783system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015283 # mshr miss rate for WriteReq accesses 784system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015283 # mshr miss rate for WriteReq accesses 785system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729898 # mshr miss rate for SoftPFReq accesses 786system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729898 # mshr miss rate for SoftPFReq accesses 787system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786417 # mshr miss rate for WriteLineReq accesses 788system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786417 # mshr miss rate for WriteLineReq accesses 789system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057340 # mshr miss rate for LoadLockedReq accesses 790system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057340 # mshr miss rate for LoadLockedReq accesses 791system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 792system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 793system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028289 # mshr miss rate for demand accesses 794system.cpu.dcache.demand_mshr_miss_rate::total 0.028289 # mshr miss rate for demand accesses 795system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032432 # mshr miss rate for overall accesses 796system.cpu.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses 797system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871 # average ReadReq mshr miss latency 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871 # average ReadReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921 # average WriteReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46809.563921 # average WriteReq mshr miss latency 801system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19033.667102 # average SoftPFReq mshr miss latency 802system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19033.667102 # average SoftPFReq mshr miss latency 803system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42116.567495 # average WriteLineReq mshr miss latency 804system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42116.567495 # average WriteLineReq mshr miss latency 805system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346 # average LoadLockedReq mshr miss latency 806system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346 # average LoadLockedReq mshr miss latency 807system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency 808system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency 809system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716 # average overall mshr miss latency 810system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716 # average overall mshr miss latency 811system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661 # average overall mshr miss latency 812system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661 # average overall mshr miss latency 813system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency 814system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency 815system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency 816system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency 817system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 818system.cpu.icache.tags.replacements 24339101 # number of replacements 819system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use 820system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. 821system.cpu.icache.tags.sampled_refs 24339613 # Sample count of references to valid blocks. 822system.cpu.icache.tags.avg_refs 17.178953 # Average number of references to valid blocks. 823system.cpu.icache.tags.warmup_cycle 32773385500 # Cycle when the warmup percentage was hit. 824system.cpu.icache.tags.occ_blocks::cpu.inst 511.885333 # Average occupied blocks per requestor 825system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy 826system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy 827system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 828system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 829system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 830system.cpu.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id 831system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 832system.cpu.icache.tags.tag_accesses 466808304 # Number of tag accesses 833system.cpu.icache.tags.data_accesses 466808304 # Number of data accesses 834system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 835system.cpu.icache.ReadReq_hits::cpu.inst 418129059 # number of ReadReq hits 836system.cpu.icache.ReadReq_hits::total 418129059 # number of ReadReq hits 837system.cpu.icache.demand_hits::cpu.inst 418129059 # number of demand (read+write) hits 838system.cpu.icache.demand_hits::total 418129059 # number of demand (read+write) hits 839system.cpu.icache.overall_hits::cpu.inst 418129059 # number of overall hits 840system.cpu.icache.overall_hits::total 418129059 # number of overall hits 841system.cpu.icache.ReadReq_misses::cpu.inst 24339623 # number of ReadReq misses 842system.cpu.icache.ReadReq_misses::total 24339623 # number of ReadReq misses 843system.cpu.icache.demand_misses::cpu.inst 24339623 # number of demand (read+write) misses 844system.cpu.icache.demand_misses::total 24339623 # number of demand (read+write) misses 845system.cpu.icache.overall_misses::cpu.inst 24339623 # number of overall misses 846system.cpu.icache.overall_misses::total 24339623 # number of overall misses 847system.cpu.icache.ReadReq_miss_latency::cpu.inst 329768536500 # number of ReadReq miss cycles 848system.cpu.icache.ReadReq_miss_latency::total 329768536500 # number of ReadReq miss cycles 849system.cpu.icache.demand_miss_latency::cpu.inst 329768536500 # number of demand (read+write) miss cycles 850system.cpu.icache.demand_miss_latency::total 329768536500 # number of demand (read+write) miss cycles 851system.cpu.icache.overall_miss_latency::cpu.inst 329768536500 # number of overall miss cycles 852system.cpu.icache.overall_miss_latency::total 329768536500 # number of overall miss cycles 853system.cpu.icache.ReadReq_accesses::cpu.inst 442468682 # number of ReadReq accesses(hits+misses) 854system.cpu.icache.ReadReq_accesses::total 442468682 # number of ReadReq accesses(hits+misses) 855system.cpu.icache.demand_accesses::cpu.inst 442468682 # number of demand (read+write) accesses 856system.cpu.icache.demand_accesses::total 442468682 # number of demand (read+write) accesses 857system.cpu.icache.overall_accesses::cpu.inst 442468682 # number of overall (read+write) accesses 858system.cpu.icache.overall_accesses::total 442468682 # number of overall (read+write) accesses 859system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055009 # miss rate for ReadReq accesses 860system.cpu.icache.ReadReq_miss_rate::total 0.055009 # miss rate for ReadReq accesses 861system.cpu.icache.demand_miss_rate::cpu.inst 0.055009 # miss rate for demand accesses 862system.cpu.icache.demand_miss_rate::total 0.055009 # miss rate for demand accesses 863system.cpu.icache.overall_miss_rate::cpu.inst 0.055009 # miss rate for overall accesses 864system.cpu.icache.overall_miss_rate::total 0.055009 # miss rate for overall accesses 865system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.629595 # average ReadReq miss latency 866system.cpu.icache.ReadReq_avg_miss_latency::total 13548.629595 # average ReadReq miss latency 867system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.629595 # average overall miss latency 868system.cpu.icache.demand_avg_miss_latency::total 13548.629595 # average overall miss latency 869system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.629595 # average overall miss latency 870system.cpu.icache.overall_avg_miss_latency::total 13548.629595 # average overall miss latency 871system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 872system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 873system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 874system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 875system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 876system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 877system.cpu.icache.writebacks::writebacks 24339101 # number of writebacks 878system.cpu.icache.writebacks::total 24339101 # number of writebacks 879system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24339623 # number of ReadReq MSHR misses 880system.cpu.icache.ReadReq_mshr_misses::total 24339623 # number of ReadReq MSHR misses 881system.cpu.icache.demand_mshr_misses::cpu.inst 24339623 # number of demand (read+write) MSHR misses 882system.cpu.icache.demand_mshr_misses::total 24339623 # number of demand (read+write) MSHR misses 883system.cpu.icache.overall_mshr_misses::cpu.inst 24339623 # number of overall MSHR misses 884system.cpu.icache.overall_mshr_misses::total 24339623 # number of overall MSHR misses 885system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 886system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 887system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 888system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 889system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305428914500 # number of ReadReq MSHR miss cycles 890system.cpu.icache.ReadReq_mshr_miss_latency::total 305428914500 # number of ReadReq MSHR miss cycles 891system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305428914500 # number of demand (read+write) MSHR miss cycles 892system.cpu.icache.demand_mshr_miss_latency::total 305428914500 # number of demand (read+write) MSHR miss cycles 893system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305428914500 # number of overall MSHR miss cycles 894system.cpu.icache.overall_mshr_miss_latency::total 305428914500 # number of overall MSHR miss cycles 895system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles 896system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles 897system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles 898system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles 899system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for ReadReq accesses 900system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055009 # mshr miss rate for ReadReq accesses 901system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for demand accesses 902system.cpu.icache.demand_mshr_miss_rate::total 0.055009 # mshr miss rate for demand accesses 903system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for overall accesses 904system.cpu.icache.overall_mshr_miss_rate::total 0.055009 # mshr miss rate for overall accesses 905system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12548.629636 # average ReadReq mshr miss latency 906system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12548.629636 # average ReadReq mshr miss latency 907system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 908system.cpu.icache.demand_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 909system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 910system.cpu.icache.overall_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 911system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 912system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 913system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 914system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency 915system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 916system.cpu.l2cache.tags.replacements 1529682 # number of replacements 917system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use 918system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks. 919system.cpu.l2cache.tags.sampled_refs 1592715 # Sample count of references to valid blocks. 920system.cpu.l2cache.tags.avg_refs 41.651953 # Average number of references to valid blocks. 921system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit. 922system.cpu.l2cache.tags.occ_blocks::writebacks 36843.538434 # Average occupied blocks per requestor 923system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 325.022996 # Average occupied blocks per requestor 924system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 386.025396 # Average occupied blocks per requestor 925system.cpu.l2cache.tags.occ_blocks::cpu.inst 8031.083741 # Average occupied blocks per requestor 926system.cpu.l2cache.tags.occ_blocks::cpu.data 19745.157287 # Average occupied blocks per requestor 927system.cpu.l2cache.tags.occ_percent::writebacks 0.562188 # Average percentage of cache occupancy 928system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004959 # Average percentage of cache occupancy 929system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005890 # Average percentage of cache occupancy 930system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122545 # Average percentage of cache occupancy 931system.cpu.l2cache.tags.occ_percent::cpu.data 0.301287 # Average percentage of cache occupancy 932system.cpu.l2cache.tags.occ_percent::total 0.996869 # Average percentage of cache occupancy 933system.cpu.l2cache.tags.occ_task_id_blocks::1023 238 # Occupied blocks per task id 934system.cpu.l2cache.tags.occ_task_id_blocks::1024 62795 # Occupied blocks per task id 935system.cpu.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 936system.cpu.l2cache.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id 937system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 938system.cpu.l2cache.tags.age_task_id_blocks_1024::1 461 # Occupied blocks per task id 939system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2479 # Occupied blocks per task id 940system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5541 # Occupied blocks per task id 941system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54260 # Occupied blocks per task id 942system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003632 # Percentage of cache occupancy per task id 943system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958176 # Percentage of cache occupancy per task id 944system.cpu.l2cache.tags.tag_accesses 577322417 # Number of tag accesses 945system.cpu.l2cache.tags.data_accesses 577322417 # Number of data accesses 946system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 947system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 919591 # number of ReadReq hits 948system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 277608 # number of ReadReq hits 949system.cpu.l2cache.ReadReq_hits::total 1197199 # number of ReadReq hits 950system.cpu.l2cache.WritebackDirty_hits::writebacks 8312311 # number of WritebackDirty hits 951system.cpu.l2cache.WritebackDirty_hits::total 8312311 # number of WritebackDirty hits 952system.cpu.l2cache.WritebackClean_hits::writebacks 24335620 # number of WritebackClean hits 953system.cpu.l2cache.WritebackClean_hits::total 24335620 # number of WritebackClean hits 954system.cpu.l2cache.UpgradeReq_hits::cpu.data 10528 # number of UpgradeReq hits 955system.cpu.l2cache.UpgradeReq_hits::total 10528 # number of UpgradeReq hits 956system.cpu.l2cache.ReadExReq_hits::cpu.data 1643656 # number of ReadExReq hits 957system.cpu.l2cache.ReadExReq_hits::total 1643656 # number of ReadExReq hits 958system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24232057 # number of ReadCleanReq hits 959system.cpu.l2cache.ReadCleanReq_hits::total 24232057 # number of ReadCleanReq hits 960system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6978048 # number of ReadSharedReq hits 961system.cpu.l2cache.ReadSharedReq_hits::total 6978048 # number of ReadSharedReq hits 962system.cpu.l2cache.InvalidateReq_hits::cpu.data 702797 # number of InvalidateReq hits 963system.cpu.l2cache.InvalidateReq_hits::total 702797 # number of InvalidateReq hits 964system.cpu.l2cache.demand_hits::cpu.dtb.walker 919591 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.itb.walker 277608 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.inst 24232057 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::cpu.data 8621704 # number of demand (read+write) hits 968system.cpu.l2cache.demand_hits::total 34050960 # number of demand (read+write) hits 969system.cpu.l2cache.overall_hits::cpu.dtb.walker 919591 # number of overall hits 970system.cpu.l2cache.overall_hits::cpu.itb.walker 277608 # number of overall hits 971system.cpu.l2cache.overall_hits::cpu.inst 24232057 # number of overall hits 972system.cpu.l2cache.overall_hits::cpu.data 8621704 # number of overall hits 973system.cpu.l2cache.overall_hits::total 34050960 # number of overall hits 974system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5915 # number of ReadReq misses 975system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4899 # number of ReadReq misses 976system.cpu.l2cache.ReadReq_misses::total 10814 # number of ReadReq misses 977system.cpu.l2cache.UpgradeReq_misses::cpu.data 37973 # number of UpgradeReq misses 978system.cpu.l2cache.UpgradeReq_misses::total 37973 # number of UpgradeReq misses 979system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 980system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 981system.cpu.l2cache.ReadExReq_misses::cpu.data 643878 # number of ReadExReq misses 982system.cpu.l2cache.ReadExReq_misses::total 643878 # number of ReadExReq misses 983system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107562 # number of ReadCleanReq misses 984system.cpu.l2cache.ReadCleanReq_misses::total 107562 # number of ReadCleanReq misses 985system.cpu.l2cache.ReadSharedReq_misses::cpu.data 321806 # number of ReadSharedReq misses 986system.cpu.l2cache.ReadSharedReq_misses::total 321806 # number of ReadSharedReq misses 987system.cpu.l2cache.InvalidateReq_misses::cpu.data 537137 # number of InvalidateReq misses 988system.cpu.l2cache.InvalidateReq_misses::total 537137 # number of InvalidateReq misses 989system.cpu.l2cache.demand_misses::cpu.dtb.walker 5915 # number of demand (read+write) misses 990system.cpu.l2cache.demand_misses::cpu.itb.walker 4899 # number of demand (read+write) misses 991system.cpu.l2cache.demand_misses::cpu.inst 107562 # number of demand (read+write) misses 992system.cpu.l2cache.demand_misses::cpu.data 965684 # number of demand (read+write) misses 993system.cpu.l2cache.demand_misses::total 1084060 # number of demand (read+write) misses 994system.cpu.l2cache.overall_misses::cpu.dtb.walker 5915 # number of overall misses 995system.cpu.l2cache.overall_misses::cpu.itb.walker 4899 # number of overall misses 996system.cpu.l2cache.overall_misses::cpu.inst 107562 # number of overall misses 997system.cpu.l2cache.overall_misses::cpu.data 965684 # number of overall misses 998system.cpu.l2cache.overall_misses::total 1084060 # number of overall misses 999system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 811806000 # number of ReadReq miss cycles 1000system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 672654000 # number of ReadReq miss cycles 1001system.cpu.l2cache.ReadReq_miss_latency::total 1484460000 # number of ReadReq miss cycles 1002system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1453703500 # number of UpgradeReq miss cycles 1003system.cpu.l2cache.UpgradeReq_miss_latency::total 1453703500 # number of UpgradeReq miss cycles 1004system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles 1005system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles 1006system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85473673000 # number of ReadExReq miss cycles 1007system.cpu.l2cache.ReadExReq_miss_latency::total 85473673000 # number of ReadExReq miss cycles 1008system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14248124000 # number of ReadCleanReq miss cycles 1009system.cpu.l2cache.ReadCleanReq_miss_latency::total 14248124000 # number of ReadCleanReq miss cycles 1010system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43454810500 # number of ReadSharedReq miss cycles 1011system.cpu.l2cache.ReadSharedReq_miss_latency::total 43454810500 # number of ReadSharedReq miss cycles 1012system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 9911500 # number of InvalidateReq miss cycles 1013system.cpu.l2cache.InvalidateReq_miss_latency::total 9911500 # number of InvalidateReq miss cycles 1014system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 811806000 # number of demand (read+write) miss cycles 1015system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 672654000 # number of demand (read+write) miss cycles 1016system.cpu.l2cache.demand_miss_latency::cpu.inst 14248124000 # number of demand (read+write) miss cycles 1017system.cpu.l2cache.demand_miss_latency::cpu.data 128928483500 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.demand_miss_latency::total 144661067500 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 811806000 # number of overall miss cycles 1020system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 672654000 # number of overall miss cycles 1021system.cpu.l2cache.overall_miss_latency::cpu.inst 14248124000 # number of overall miss cycles 1022system.cpu.l2cache.overall_miss_latency::cpu.data 128928483500 # number of overall miss cycles 1023system.cpu.l2cache.overall_miss_latency::total 144661067500 # number of overall miss cycles 1024system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 925506 # number of ReadReq accesses(hits+misses) 1025system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 282507 # number of ReadReq accesses(hits+misses) 1026system.cpu.l2cache.ReadReq_accesses::total 1208013 # number of ReadReq accesses(hits+misses) 1027system.cpu.l2cache.WritebackDirty_accesses::writebacks 8312311 # number of WritebackDirty accesses(hits+misses) 1028system.cpu.l2cache.WritebackDirty_accesses::total 8312311 # number of WritebackDirty accesses(hits+misses) 1029system.cpu.l2cache.WritebackClean_accesses::writebacks 24335620 # number of WritebackClean accesses(hits+misses) 1030system.cpu.l2cache.WritebackClean_accesses::total 24335620 # number of WritebackClean accesses(hits+misses) 1031system.cpu.l2cache.UpgradeReq_accesses::cpu.data 48501 # number of UpgradeReq accesses(hits+misses) 1032system.cpu.l2cache.UpgradeReq_accesses::total 48501 # number of UpgradeReq accesses(hits+misses) 1033system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1034system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 1035system.cpu.l2cache.ReadExReq_accesses::cpu.data 2287534 # number of ReadExReq accesses(hits+misses) 1036system.cpu.l2cache.ReadExReq_accesses::total 2287534 # number of ReadExReq accesses(hits+misses) 1037system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24339619 # number of ReadCleanReq accesses(hits+misses) 1038system.cpu.l2cache.ReadCleanReq_accesses::total 24339619 # number of ReadCleanReq accesses(hits+misses) 1039system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7299854 # number of ReadSharedReq accesses(hits+misses) 1040system.cpu.l2cache.ReadSharedReq_accesses::total 7299854 # number of ReadSharedReq accesses(hits+misses) 1041system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1239934 # number of InvalidateReq accesses(hits+misses) 1042system.cpu.l2cache.InvalidateReq_accesses::total 1239934 # number of InvalidateReq accesses(hits+misses) 1043system.cpu.l2cache.demand_accesses::cpu.dtb.walker 925506 # number of demand (read+write) accesses 1044system.cpu.l2cache.demand_accesses::cpu.itb.walker 282507 # number of demand (read+write) accesses 1045system.cpu.l2cache.demand_accesses::cpu.inst 24339619 # number of demand (read+write) accesses 1046system.cpu.l2cache.demand_accesses::cpu.data 9587388 # number of demand (read+write) accesses 1047system.cpu.l2cache.demand_accesses::total 35135020 # number of demand (read+write) accesses 1048system.cpu.l2cache.overall_accesses::cpu.dtb.walker 925506 # number of overall (read+write) accesses 1049system.cpu.l2cache.overall_accesses::cpu.itb.walker 282507 # number of overall (read+write) accesses 1050system.cpu.l2cache.overall_accesses::cpu.inst 24339619 # number of overall (read+write) accesses 1051system.cpu.l2cache.overall_accesses::cpu.data 9587388 # number of overall (read+write) accesses 1052system.cpu.l2cache.overall_accesses::total 35135020 # number of overall (read+write) accesses 1053system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006391 # miss rate for ReadReq accesses 1054system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.017341 # miss rate for ReadReq accesses 1055system.cpu.l2cache.ReadReq_miss_rate::total 0.008952 # miss rate for ReadReq accesses 1056system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782932 # miss rate for UpgradeReq accesses 1057system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782932 # miss rate for UpgradeReq accesses 1058system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1059system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1060system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.281473 # miss rate for ReadExReq accesses 1061system.cpu.l2cache.ReadExReq_miss_rate::total 0.281473 # miss rate for ReadExReq accesses 1062system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004419 # miss rate for ReadCleanReq accesses 1063system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004419 # miss rate for ReadCleanReq accesses 1064system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044084 # miss rate for ReadSharedReq accesses 1065system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044084 # miss rate for ReadSharedReq accesses 1066system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.433198 # miss rate for InvalidateReq accesses 1067system.cpu.l2cache.InvalidateReq_miss_rate::total 0.433198 # miss rate for InvalidateReq accesses 1068system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006391 # miss rate for demand accesses 1069system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017341 # miss rate for demand accesses 1070system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004419 # miss rate for demand accesses 1071system.cpu.l2cache.demand_miss_rate::cpu.data 0.100724 # miss rate for demand accesses 1072system.cpu.l2cache.demand_miss_rate::total 0.030854 # miss rate for demand accesses 1073system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006391 # miss rate for overall accesses 1074system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017341 # miss rate for overall accesses 1075system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004419 # miss rate for overall accesses 1076system.cpu.l2cache.overall_miss_rate::cpu.data 0.100724 # miss rate for overall accesses 1077system.cpu.l2cache.overall_miss_rate::total 0.030854 # miss rate for overall accesses 1078system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137245.308538 # average ReadReq miss latency 1079system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137304.347826 # average ReadReq miss latency 1080system.cpu.l2cache.ReadReq_avg_miss_latency::total 137272.054744 # average ReadReq miss latency 1081system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38282.556027 # average UpgradeReq miss latency 1082system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38282.556027 # average UpgradeReq miss latency 1083system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency 1084system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency 1085system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132748.242680 # average ReadExReq miss latency 1086system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132748.242680 # average ReadExReq miss latency 1087system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132464.290363 # average ReadCleanReq miss latency 1088system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132464.290363 # average ReadCleanReq miss latency 1089system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135034.183639 # average ReadSharedReq miss latency 1090system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135034.183639 # average ReadSharedReq miss latency 1091system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 18.452462 # average InvalidateReq miss latency 1092system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 18.452462 # average InvalidateReq miss latency 1093system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137245.308538 # average overall miss latency 1094system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137304.347826 # average overall miss latency 1095system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132464.290363 # average overall miss latency 1096system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133510.013110 # average overall miss latency 1097system.cpu.l2cache.demand_avg_miss_latency::total 133443.783093 # average overall miss latency 1098system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137245.308538 # average overall miss latency 1099system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137304.347826 # average overall miss latency 1100system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132464.290363 # average overall miss latency 1101system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133510.013110 # average overall miss latency 1102system.cpu.l2cache.overall_avg_miss_latency::total 133443.783093 # average overall miss latency 1103system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1104system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1105system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1106system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1107system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1108system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1109system.cpu.l2cache.writebacks::writebacks 1293856 # number of writebacks 1110system.cpu.l2cache.writebacks::total 1293856 # number of writebacks 1111system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1112system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1113system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1114system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1115system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1116system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1117system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 1118system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1119system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1120system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 1121system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5915 # number of ReadReq MSHR misses 1122system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4899 # number of ReadReq MSHR misses 1123system.cpu.l2cache.ReadReq_mshr_misses::total 10814 # number of ReadReq MSHR misses 1124system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses 1125system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses 1126system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37973 # number of UpgradeReq MSHR misses 1127system.cpu.l2cache.UpgradeReq_mshr_misses::total 37973 # number of UpgradeReq MSHR misses 1128system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1129system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1130system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 643878 # number of ReadExReq MSHR misses 1131system.cpu.l2cache.ReadExReq_mshr_misses::total 643878 # number of ReadExReq MSHR misses 1132system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107559 # number of ReadCleanReq MSHR misses 1133system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107559 # number of ReadCleanReq MSHR misses 1134system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 321785 # number of ReadSharedReq MSHR misses 1135system.cpu.l2cache.ReadSharedReq_mshr_misses::total 321785 # number of ReadSharedReq MSHR misses 1136system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 537137 # number of InvalidateReq MSHR misses 1137system.cpu.l2cache.InvalidateReq_mshr_misses::total 537137 # number of InvalidateReq MSHR misses 1138system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5915 # number of demand (read+write) MSHR misses 1139system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4899 # number of demand (read+write) MSHR misses 1140system.cpu.l2cache.demand_mshr_misses::cpu.inst 107559 # number of demand (read+write) MSHR misses 1141system.cpu.l2cache.demand_mshr_misses::cpu.data 965663 # number of demand (read+write) MSHR misses 1142system.cpu.l2cache.demand_mshr_misses::total 1084036 # number of demand (read+write) MSHR misses 1143system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5915 # number of overall MSHR misses 1144system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4899 # number of overall MSHR misses 1145system.cpu.l2cache.overall_mshr_misses::cpu.inst 107559 # number of overall MSHR misses 1146system.cpu.l2cache.overall_mshr_misses::cpu.data 965663 # number of overall MSHR misses 1147system.cpu.l2cache.overall_mshr_misses::total 1084036 # number of overall MSHR misses 1148system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 1149system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 1150system.cpu.l2cache.ReadReq_mshr_uncacheable::total 86006 # number of ReadReq MSHR uncacheable 1151system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 1152system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 1153system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 1154system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 1155system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119712 # number of overall MSHR uncacheable misses 1156system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 752655502 # number of ReadReq MSHR miss cycles 1157system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 623664000 # number of ReadReq MSHR miss cycles 1158system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1376319502 # number of ReadReq MSHR miss cycles 1159system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2582673500 # number of UpgradeReq MSHR miss cycles 1160system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2582673500 # number of UpgradeReq MSHR miss cycles 1161system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles 1162system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles 1163system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79034877032 # number of ReadExReq MSHR miss cycles 1164system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79034877032 # number of ReadExReq MSHR miss cycles 1165system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13172156574 # number of ReadCleanReq MSHR miss cycles 1166system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13172156574 # number of ReadCleanReq MSHR miss cycles 1167system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40234614920 # number of ReadSharedReq MSHR miss cycles 1168system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40234614920 # number of ReadSharedReq MSHR miss cycles 1169system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 37418286000 # number of InvalidateReq MSHR miss cycles 1170system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 37418286000 # number of InvalidateReq MSHR miss cycles 1171system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 752655502 # number of demand (read+write) MSHR miss cycles 1172system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 623664000 # number of demand (read+write) MSHR miss cycles 1173system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13172156574 # number of demand (read+write) MSHR miss cycles 1174system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119269491952 # number of demand (read+write) MSHR miss cycles 1175system.cpu.l2cache.demand_mshr_miss_latency::total 133817968028 # number of demand (read+write) MSHR miss cycles 1176system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 752655502 # number of overall MSHR miss cycles 1177system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 623664000 # number of overall MSHR miss cycles 1178system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13172156574 # number of overall MSHR miss cycles 1179system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119269491952 # number of overall MSHR miss cycles 1180system.cpu.l2cache.overall_mshr_miss_latency::total 133817968028 # number of overall MSHR miss cycles 1181system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles 1182system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776326000 # number of ReadReq MSHR uncacheable cycles 1183system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712400000 # number of ReadReq MSHR uncacheable cycles 1184system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles 1185system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5776326000 # number of overall MSHR uncacheable cycles 1186system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11712400000 # number of overall MSHR uncacheable cycles 1187system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for ReadReq accesses 1188system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for ReadReq accesses 1189system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008952 # mshr miss rate for ReadReq accesses 1190system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1191system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1192system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782932 # mshr miss rate for UpgradeReq accesses 1193system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782932 # mshr miss rate for UpgradeReq accesses 1194system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1195system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1196system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.281473 # mshr miss rate for ReadExReq accesses 1197system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.281473 # mshr miss rate for ReadExReq accesses 1198system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for ReadCleanReq accesses 1199system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004419 # mshr miss rate for ReadCleanReq accesses 1200system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044081 # mshr miss rate for ReadSharedReq accesses 1201system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044081 # mshr miss rate for ReadSharedReq accesses 1202system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.433198 # mshr miss rate for InvalidateReq accesses 1203system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.433198 # mshr miss rate for InvalidateReq accesses 1204system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for demand accesses 1205system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for demand accesses 1206system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for demand accesses 1207system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.100722 # mshr miss rate for demand accesses 1208system.cpu.l2cache.demand_mshr_miss_rate::total 0.030853 # mshr miss rate for demand accesses 1209system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for overall accesses 1210system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for overall accesses 1211system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for overall accesses 1212system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.100722 # mshr miss rate for overall accesses 1213system.cpu.l2cache.overall_mshr_miss_rate::total 0.030853 # mshr miss rate for overall accesses 1214system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average ReadReq mshr miss latency 1215system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average ReadReq mshr miss latency 1216system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127272.008692 # average ReadReq mshr miss latency 1217system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.417428 # average UpgradeReq mshr miss latency 1218system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.417428 # average UpgradeReq mshr miss latency 1219system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency 1220system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency 1221system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122748.217880 # average ReadExReq mshr miss latency 1222system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122748.217880 # average ReadExReq mshr miss latency 1223system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122464.475999 # average ReadCleanReq mshr miss latency 1224system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122464.475999 # average ReadCleanReq mshr miss latency 1225system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125035.706823 # average ReadSharedReq mshr miss latency 1226system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125035.706823 # average ReadSharedReq mshr miss latency 1227system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.462277 # average InvalidateReq mshr miss latency 1228system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.462277 # average InvalidateReq mshr miss latency 1229system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency 1230system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency 1231system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency 1232system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency 1233system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123444.210366 # average overall mshr miss latency 1234system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency 1235system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency 1236system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency 1237system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency 1238system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123444.210366 # average overall mshr miss latency 1239system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency 1240system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171419.592249 # average ReadReq mshr uncacheable latency 1241system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136181.196661 # average ReadReq mshr uncacheable latency 1242system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency 1243system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85698.351705 # average overall mshr uncacheable latency 1244system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97838.144881 # average overall mshr uncacheable latency 1245system.cpu.toL2Bus.snoop_filter.tot_requests 71082854 # Total number of requests made to the snoop filter. 1246system.cpu.toL2Bus.snoop_filter.hit_single_requests 35915919 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1247system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1248system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter. 1249system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1250system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1251system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1252system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution 1253system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution 1254system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution 1255system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution 1256system.cpu.toL2Bus.trans_dist::WritebackDirty 9712830 # Transaction distribution 1257system.cpu.toL2Bus.trans_dist::WritebackClean 24339101 # Transaction distribution 1258system.cpu.toL2Bus.trans_dist::CleanEvict 2759131 # Transaction distribution 1259system.cpu.toL2Bus.trans_dist::UpgradeReq 48504 # Transaction distribution 1260system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1261system.cpu.toL2Bus.trans_dist::UpgradeResp 48506 # Transaction distribution 1262system.cpu.toL2Bus.trans_dist::ReadExReq 2287534 # Transaction distribution 1263system.cpu.toL2Bus.trans_dist::ReadExResp 2287534 # Transaction distribution 1264system.cpu.toL2Bus.trans_dist::ReadCleanReq 24339623 # Transaction distribution 1265system.cpu.toL2Bus.trans_dist::ReadSharedReq 7308730 # Transaction distribution 1266system.cpu.toL2Bus.trans_dist::InvalidateReq 1346598 # Transaction distribution 1267system.cpu.toL2Bus.trans_dist::InvalidateResp 1239934 # Transaction distribution 1268system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73122960 # Packet count per connected master and slave (bytes) 1269system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32713992 # Packet count per connected master and slave (bytes) 1270system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 682590 # Packet count per connected master and slave (bytes) 1271system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2171018 # Packet count per connected master and slave (bytes) 1272system.cpu.toL2Bus.pkt_count::total 108690560 # Packet count per connected master and slave (bytes) 1273system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3118785792 # Cumulative packet size per connected master and slave (bytes) 1274system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1145820498 # Cumulative packet size per connected master and slave (bytes) 1275system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2260056 # Cumulative packet size per connected master and slave (bytes) 1276system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7404048 # Cumulative packet size per connected master and slave (bytes) 1277system.cpu.toL2Bus.pkt_size::total 4274270394 # Cumulative packet size per connected master and slave (bytes) 1278system.cpu.toL2Bus.snoops 2199102 # Total snoops (count) 1279system.cpu.toL2Bus.snoop_fanout::samples 38741497 # Request fanout histogram 1280system.cpu.toL2Bus.snoop_fanout::mean 0.018274 # Request fanout histogram 1281system.cpu.toL2Bus.snoop_fanout::stdev 0.133941 # Request fanout histogram 1282system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1283system.cpu.toL2Bus.snoop_fanout::0 38033532 98.17% 98.17% # Request fanout histogram 1284system.cpu.toL2Bus.snoop_fanout::1 707965 1.83% 100.00% # Request fanout histogram 1285system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1286system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1287system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1288system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1289system.cpu.toL2Bus.snoop_fanout::total 38741497 # Request fanout histogram 1290system.cpu.toL2Bus.reqLayer0.occupancy 68741576495 # Layer occupancy (ticks) 1291system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1292system.cpu.toL2Bus.snoopLayer0.occupancy 1462889 # Layer occupancy (ticks) 1293system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1294system.cpu.toL2Bus.respLayer0.occupancy 36594790182 # Layer occupancy (ticks) 1295system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1296system.cpu.toL2Bus.respLayer1.occupancy 15076717704 # Layer occupancy (ticks) 1297system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1298system.cpu.toL2Bus.respLayer2.occupancy 400149367 # Layer occupancy (ticks) 1299system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1300system.cpu.toL2Bus.respLayer3.occupancy 1245546930 # Layer occupancy (ticks) 1301system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1302system.iobus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1303system.iobus.trans_dist::ReadReq 40324 # Transaction distribution 1304system.iobus.trans_dist::ReadResp 40324 # Transaction distribution 1305system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1306system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1307system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1308system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1309system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1310system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1311system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1312system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1313system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1314system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1315system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1316system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1317system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1318system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1319system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1320system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1321system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) 1322system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) 1323system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1324system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1325system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) 1326system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1327system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1328system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1329system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1330system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1331system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1332system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1333system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1334system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1335system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1336system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1337system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1338system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1339system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1340system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) 1341system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) 1342system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1343system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1344system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) 1345system.iobus.reqLayer0.occupancy 37107000 # Layer occupancy (ticks) 1346system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1347system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1348system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1349system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) 1350system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1351system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) 1352system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1353system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 1354system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1355system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) 1356system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1357system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 1358system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1359system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 1360system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1361system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 1362system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1363system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) 1364system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1365system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1366system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1367system.iobus.reqLayer23.occupancy 25573000 # Layer occupancy (ticks) 1368system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1369system.iobus.reqLayer24.occupancy 34140500 # Layer occupancy (ticks) 1370system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1371system.iobus.reqLayer25.occupancy 567103107 # Layer occupancy (ticks) 1372system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1373system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1374system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1375system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) 1376system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1377system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1378system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1379system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1380system.iocache.tags.replacements 115484 # number of replacements 1381system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use 1382system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1383system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. 1384system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1385system.iocache.tags.warmup_cycle 13153318095000 # Cycle when the warmup percentage was hit. 1386system.iocache.tags.occ_blocks::realview.ethernet 3.521307 # Average occupied blocks per requestor 1387system.iocache.tags.occ_blocks::realview.ide 6.919947 # Average occupied blocks per requestor 1388system.iocache.tags.occ_percent::realview.ethernet 0.220082 # Average percentage of cache occupancy 1389system.iocache.tags.occ_percent::realview.ide 0.432497 # Average percentage of cache occupancy 1390system.iocache.tags.occ_percent::total 0.652578 # Average percentage of cache occupancy 1391system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1392system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1393system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1394system.iocache.tags.tag_accesses 1039884 # Number of tag accesses 1395system.iocache.tags.data_accesses 1039884 # Number of data accesses 1396system.iocache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1397system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1398system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses 1399system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses 1400system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1401system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1402system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1403system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1404system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1405system.iocache.demand_misses::realview.ide 115503 # number of demand (read+write) misses 1406system.iocache.demand_misses::total 115543 # number of demand (read+write) misses 1407system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1408system.iocache.overall_misses::realview.ide 115503 # number of overall misses 1409system.iocache.overall_misses::total 115543 # number of overall misses 1410system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles 1411system.iocache.ReadReq_miss_latency::realview.ide 1644126101 # number of ReadReq miss cycles 1412system.iocache.ReadReq_miss_latency::total 1649196101 # number of ReadReq miss cycles 1413system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1414system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1415system.iocache.WriteLineReq_miss_latency::realview.ide 13411893006 # number of WriteLineReq miss cycles 1416system.iocache.WriteLineReq_miss_latency::total 13411893006 # number of WriteLineReq miss cycles 1417system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles 1418system.iocache.demand_miss_latency::realview.ide 15056019107 # number of demand (read+write) miss cycles 1419system.iocache.demand_miss_latency::total 15061440107 # number of demand (read+write) miss cycles 1420system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles 1421system.iocache.overall_miss_latency::realview.ide 15056019107 # number of overall miss cycles 1422system.iocache.overall_miss_latency::total 15061440107 # number of overall miss cycles 1423system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1424system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) 1425system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) 1426system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1427system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1428system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1429system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1430system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1431system.iocache.demand_accesses::realview.ide 115503 # number of demand (read+write) accesses 1432system.iocache.demand_accesses::total 115543 # number of demand (read+write) accesses 1433system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1434system.iocache.overall_accesses::realview.ide 115503 # number of overall (read+write) accesses 1435system.iocache.overall_accesses::total 115543 # number of overall (read+write) accesses 1436system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1437system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1438system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1439system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1440system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1441system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1442system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1443system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1444system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1445system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1446system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1447system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1448system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1449system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency 1450system.iocache.ReadReq_avg_miss_latency::realview.ide 186008.157144 # average ReadReq miss latency 1451system.iocache.ReadReq_avg_miss_latency::total 185803.977129 # average ReadReq miss latency 1452system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1453system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1454system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.640422 # average WriteLineReq miss latency 1455system.iocache.WriteLineReq_avg_miss_latency::total 125739.640422 # average WriteLineReq miss latency 1456system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency 1457system.iocache.demand_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency 1458system.iocache.demand_avg_miss_latency::total 130353.548956 # average overall miss latency 1459system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency 1460system.iocache.overall_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency 1461system.iocache.overall_avg_miss_latency::total 130353.548956 # average overall miss latency 1462system.iocache.blocked_cycles::no_mshrs 32855 # number of cycles access was blocked 1463system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1464system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked 1465system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1466system.iocache.avg_blocked_cycles::no_mshrs 9.711794 # average number of cycles each access was blocked 1467system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1468system.iocache.writebacks::writebacks 106630 # number of writebacks 1469system.iocache.writebacks::total 106630 # number of writebacks 1470system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1471system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses 1472system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses 1473system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1474system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1475system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1476system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1477system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1478system.iocache.demand_mshr_misses::realview.ide 115503 # number of demand (read+write) MSHR misses 1479system.iocache.demand_mshr_misses::total 115543 # number of demand (read+write) MSHR misses 1480system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1481system.iocache.overall_mshr_misses::realview.ide 115503 # number of overall MSHR misses 1482system.iocache.overall_mshr_misses::total 115543 # number of overall MSHR misses 1483system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles 1484system.iocache.ReadReq_mshr_miss_latency::realview.ide 1202176101 # number of ReadReq MSHR miss cycles 1485system.iocache.ReadReq_mshr_miss_latency::total 1205396101 # number of ReadReq MSHR miss cycles 1486system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1487system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1488system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073547861 # number of WriteLineReq MSHR miss cycles 1489system.iocache.WriteLineReq_mshr_miss_latency::total 8073547861 # number of WriteLineReq MSHR miss cycles 1490system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles 1491system.iocache.demand_mshr_miss_latency::realview.ide 9275723962 # number of demand (read+write) MSHR miss cycles 1492system.iocache.demand_mshr_miss_latency::total 9279144962 # number of demand (read+write) MSHR miss cycles 1493system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles 1494system.iocache.overall_mshr_miss_latency::realview.ide 9275723962 # number of overall MSHR miss cycles 1495system.iocache.overall_mshr_miss_latency::total 9279144962 # number of overall MSHR miss cycles 1496system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1497system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1498system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1499system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1500system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1501system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1502system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1503system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1504system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1505system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1506system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1507system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1508system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1509system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency 1510system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136008.157144 # average ReadReq mshr miss latency 1511system.iocache.ReadReq_avg_mshr_miss_latency::total 135803.977129 # average ReadReq mshr miss latency 1512system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1513system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1514system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482 # average WriteLineReq mshr miss latency 1515system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482 # average WriteLineReq mshr miss latency 1516system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1517system.iocache.demand_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency 1518system.iocache.demand_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency 1519system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1520system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency 1521system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency 1522system.membus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1523system.membus.trans_dist::ReadReq 86006 # Transaction distribution 1524system.membus.trans_dist::ReadResp 535040 # Transaction distribution 1525system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1526system.membus.trans_dist::WriteResp 33706 # Transaction distribution 1527system.membus.trans_dist::WritebackDirty 1400486 # Transaction distribution 1528system.membus.trans_dist::CleanEvict 243574 # Transaction distribution 1529system.membus.trans_dist::UpgradeReq 38729 # Transaction distribution 1530system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1531system.membus.trans_dist::UpgradeResp 8 # Transaction distribution 1532system.membus.trans_dist::ReadExReq 643252 # Transaction distribution 1533system.membus.trans_dist::ReadExResp 643252 # Transaction distribution 1534system.membus.trans_dist::ReadSharedReq 449034 # Transaction distribution 1535system.membus.trans_dist::InvalidateReq 643674 # Transaction distribution 1536system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1537system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1538system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) 1539system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4380248 # Packet count per connected master and slave (bytes) 1540system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4509900 # Packet count per connected master and slave (bytes) 1541system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237195 # Packet count per connected master and slave (bytes) 1542system.membus.pkt_count_system.iocache.mem_side::total 237195 # Packet count per connected master and slave (bytes) 1543system.membus.pkt_count::total 4747095 # Packet count per connected master and slave (bytes) 1544system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1545system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1546system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) 1547system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155470700 # Cumulative packet size per connected master and slave (bytes) 1548system.membus.pkt_size_system.cpu.l2cache.mem_side::total 155641106 # Cumulative packet size per connected master and slave (bytes) 1549system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7219072 # Cumulative packet size per connected master and slave (bytes) 1550system.membus.pkt_size_system.iocache.mem_side::total 7219072 # Cumulative packet size per connected master and slave (bytes) 1551system.membus.pkt_size::total 162860178 # Cumulative packet size per connected master and slave (bytes) 1552system.membus.snoops 3374 # Total snoops (count) 1553system.membus.snoop_fanout::samples 3538498 # Request fanout histogram 1554system.membus.snoop_fanout::mean 1 # Request fanout histogram 1555system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1556system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1557system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1558system.membus.snoop_fanout::1 3538498 100.00% 100.00% # Request fanout histogram 1559system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1560system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1561system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1562system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1563system.membus.snoop_fanout::total 3538498 # Request fanout histogram 1564system.membus.reqLayer0.occupancy 97241000 # Layer occupancy (ticks) 1565system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1566system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1567system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1568system.membus.reqLayer2.occupancy 5639000 # Layer occupancy (ticks) 1569system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1570system.membus.reqLayer5.occupancy 9317752261 # Layer occupancy (ticks) 1571system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1572system.membus.respLayer2.occupancy 6128850630 # Layer occupancy (ticks) 1573system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1574system.membus.respLayer3.occupancy 44857615 # Layer occupancy (ticks) 1575system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1576system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1577system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1578system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1579system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1580system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1581system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1582system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1583system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1584system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1585system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1586system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1587system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1588system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1589system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1590system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1591system.realview.ethernet.txBytes 966 # Bytes Transmitted 1592system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1593system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1594system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1595system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1596system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1597system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1598system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1599system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1600system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 1601system.realview.ethernet.totPackets 3 # Total Packets 1602system.realview.ethernet.totBytes 966 # Total Bytes 1603system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1604system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 1605system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1606system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1607system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1608system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1609system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1610system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1611system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1612system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1613system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1614system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1615system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1616system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1617system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1618system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1619system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1620system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1621system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1622system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1623system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1624system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1625system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1626system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1627system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1628system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1629system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1630system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1631system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1632system.realview.ethernet.droppedPackets 0 # number of packets dropped 1633system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1634system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1635system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1636system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1637system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1638system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1639system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1640system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1641system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1642system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1643system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1644system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1645system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1646system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1647system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1648system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1649system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1650system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1651system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1652system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1653system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1654system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1655system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1656 1657---------- End Simulation Statistics ----------	528system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 529system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 530system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 531system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions 532system.cpu.itb.read_accesses 0 # DTB read accesses 533system.cpu.itb.write_accesses 0 # DTB write accesses 534system.cpu.itb.inst_accesses 442926878 # ITB inst accesses 535system.cpu.itb.hits 442793055 # DTB hits 536system.cpu.itb.misses 133823 # DTB misses 537system.cpu.itb.accesses 442926878 # DTB accesses 538system.cpu.numPwrStateTransitions 33032 # Number of power state transitions 539system.cpu.pwrStateClkGateDist::samples 16516 # Distribution of time spent in the clock gated state 540system.cpu.pwrStateClkGateDist::mean 3050356912.427888 # Distribution of time spent in the clock gated state 541system.cpu.pwrStateClkGateDist::stdev 59773934276.156128 # Distribution of time spent in the clock gated state 542system.cpu.pwrStateClkGateDist::underflows 7219 43.71% 43.71% # Distribution of time spent in the clock gated state 543system.cpu.pwrStateClkGateDist::1000-5e+10 9262 56.08% 99.79% # Distribution of time spent in the clock gated state 544system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state 545system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state 546system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 547system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 548system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 549system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 550system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 551system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 552system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 553system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 554system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 555system.cpu.pwrStateClkGateDist::max_value 1988777743356 # Distribution of time spent in the clock gated state 556system.cpu.pwrStateClkGateDist::total 16516 # Distribution of time spent in the clock gated state 557system.cpu.pwrStateResidencyTicks::ON 1280958181341 # Cumulative time (in ticks) in various power states 558system.cpu.pwrStateResidencyTicks::CLK_GATED 50379694765659 # Cumulative time (in ticks) in various power states 559system.cpu.numCycles 2561963341 # number of cpu cycles simulated 560system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 561system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 562system.cpu.committedInsts 929398934 # Number of instructions committed 563system.cpu.committedOps 1092086880 # Number of ops (including micro ops) committed 564system.cpu.discardedOps 94664249 # Number of ops (including micro ops) which were discarded before commit 565system.cpu.numFetchSuspends 7656 # Number of times Execute suspended instruction fetching 566system.cpu.quiesceCycles 100760459460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 567system.cpu.cpi 2.756581 # CPI: cycles per instruction 568system.cpu.ipc 0.362768 # IPC: instructions per cycle 569system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 570system.cpu.op_class_0::IntAlu 756821893 69.30% 69.30% # Class of committed instruction 571system.cpu.op_class_0::IntMult 2277263 0.21% 69.51% # Class of committed instruction 572system.cpu.op_class_0::IntDiv 98455 0.01% 69.52% # Class of committed instruction 573system.cpu.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction 574system.cpu.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction 575system.cpu.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction 576system.cpu.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction 577system.cpu.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction 578system.cpu.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction 579system.cpu.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction 580system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction 581system.cpu.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction 582system.cpu.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction 583system.cpu.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction 584system.cpu.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction 585system.cpu.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction 586system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction 587system.cpu.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction 588system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction 589system.cpu.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction 590system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction 591system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction 592system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction 593system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction 594system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction 595system.cpu.op_class_0::SimdFloatMisc 109444 0.01% 69.53% # Class of committed instruction 596system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction 597system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction 598system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction 599system.cpu.op_class_0::MemRead 174118935 15.94% 85.47% # Class of committed instruction 600system.cpu.op_class_0::MemWrite 158660847 14.53% 100.00% # Class of committed instruction 601system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 602system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 603system.cpu.op_class_0::total 1092086880 # Class of committed instruction 604system.cpu.kern.inst.arm 0 # number of arm instructions executed 605system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed 606system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked 607system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped 608system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 609system.cpu.dcache.tags.replacements 10826762 # number of replacements 610system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use 611system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks. 612system.cpu.dcache.tags.sampled_refs 10827274 # Sample count of references to valid blocks. 613system.cpu.dcache.tags.avg_refs 29.813150 # Average number of references to valid blocks. 614system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. 615system.cpu.dcache.tags.occ_blocks::cpu.data 511.930071 # Average occupied blocks per requestor 616system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 617system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 618system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 619system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 620system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 621system.cpu.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 622system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 623system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 624system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses 625system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses 626system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 627system.cpu.dcache.ReadReq_hits::cpu.data 165131668 # number of ReadReq hits 628system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits 629system.cpu.dcache.WriteReq_hits::cpu.data 148654336 # number of WriteReq hits 630system.cpu.dcache.WriteReq_hits::total 148654336 # number of WriteReq hits 631system.cpu.dcache.SoftPFReq_hits::cpu.data 515490 # number of SoftPFReq hits 632system.cpu.dcache.SoftPFReq_hits::total 515490 # number of SoftPFReq hits 633system.cpu.dcache.WriteLineReq_hits::cpu.data 336587 # number of WriteLineReq hits 634system.cpu.dcache.WriteLineReq_hits::total 336587 # number of WriteLineReq hits 635system.cpu.dcache.LoadLockedReq_hits::cpu.data 3899601 # number of LoadLockedReq hits 636system.cpu.dcache.LoadLockedReq_hits::total 3899601 # number of LoadLockedReq hits 637system.cpu.dcache.StoreCondReq_hits::cpu.data 4208890 # number of StoreCondReq hits 638system.cpu.dcache.StoreCondReq_hits::total 4208890 # number of StoreCondReq hits 639system.cpu.dcache.demand_hits::cpu.data 314122591 # number of demand (read+write) hits 640system.cpu.dcache.demand_hits::total 314122591 # number of demand (read+write) hits 641system.cpu.dcache.overall_hits::cpu.data 314638081 # number of overall hits 642system.cpu.dcache.overall_hits::total 314638081 # number of overall hits 643system.cpu.dcache.ReadReq_misses::cpu.data 6423881 # number of ReadReq misses 644system.cpu.dcache.ReadReq_misses::total 6423881 # number of ReadReq misses 645system.cpu.dcache.WriteReq_misses::cpu.data 4177328 # number of WriteReq misses 646system.cpu.dcache.WriteReq_misses::total 4177328 # number of WriteReq misses 647system.cpu.dcache.SoftPFReq_misses::cpu.data 1420881 # number of SoftPFReq misses 648system.cpu.dcache.SoftPFReq_misses::total 1420881 # number of SoftPFReq misses 649system.cpu.dcache.WriteLineReq_misses::cpu.data 1240100 # number of WriteLineReq misses 650system.cpu.dcache.WriteLineReq_misses::total 1240100 # number of WriteLineReq misses 651system.cpu.dcache.LoadLockedReq_misses::cpu.data 311002 # number of LoadLockedReq misses 652system.cpu.dcache.LoadLockedReq_misses::total 311002 # number of LoadLockedReq misses 653system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 654system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 655system.cpu.dcache.demand_misses::cpu.data 11841309 # number of demand (read+write) misses 656system.cpu.dcache.demand_misses::total 11841309 # number of demand (read+write) misses 657system.cpu.dcache.overall_misses::cpu.data 13262190 # number of overall misses 658system.cpu.dcache.overall_misses::total 13262190 # number of overall misses 659system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500 # number of ReadReq miss cycles 660system.cpu.dcache.ReadReq_miss_latency::total 119203222500 # number of ReadReq miss cycles 661system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500 # number of WriteReq miss cycles 662system.cpu.dcache.WriteReq_miss_latency::total 206322817500 # number of WriteReq miss cycles 663system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53471775500 # number of WriteLineReq miss cycles 664system.cpu.dcache.WriteLineReq_miss_latency::total 53471775500 # number of WriteLineReq miss cycles 665system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5200645500 # number of LoadLockedReq miss cycles 666system.cpu.dcache.LoadLockedReq_miss_latency::total 5200645500 # number of LoadLockedReq miss cycles 667system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles 668system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles 669system.cpu.dcache.demand_miss_latency::cpu.data 378997815500 # number of demand (read+write) miss cycles 670system.cpu.dcache.demand_miss_latency::total 378997815500 # number of demand (read+write) miss cycles 671system.cpu.dcache.overall_miss_latency::cpu.data 378997815500 # number of overall miss cycles 672system.cpu.dcache.overall_miss_latency::total 378997815500 # number of overall miss cycles 673system.cpu.dcache.ReadReq_accesses::cpu.data 171555549 # number of ReadReq accesses(hits+misses) 674system.cpu.dcache.ReadReq_accesses::total 171555549 # number of ReadReq accesses(hits+misses) 675system.cpu.dcache.WriteReq_accesses::cpu.data 152831664 # number of WriteReq accesses(hits+misses) 676system.cpu.dcache.WriteReq_accesses::total 152831664 # number of WriteReq accesses(hits+misses) 677system.cpu.dcache.SoftPFReq_accesses::cpu.data 1936371 # number of SoftPFReq accesses(hits+misses) 678system.cpu.dcache.SoftPFReq_accesses::total 1936371 # number of SoftPFReq accesses(hits+misses) 679system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576687 # number of WriteLineReq accesses(hits+misses) 680system.cpu.dcache.WriteLineReq_accesses::total 1576687 # number of WriteLineReq accesses(hits+misses) 681system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4210603 # number of LoadLockedReq accesses(hits+misses) 682system.cpu.dcache.LoadLockedReq_accesses::total 4210603 # number of LoadLockedReq accesses(hits+misses) 683system.cpu.dcache.StoreCondReq_accesses::cpu.data 4208892 # number of StoreCondReq accesses(hits+misses) 684system.cpu.dcache.StoreCondReq_accesses::total 4208892 # number of StoreCondReq accesses(hits+misses) 685system.cpu.dcache.demand_accesses::cpu.data 325963900 # number of demand (read+write) accesses 686system.cpu.dcache.demand_accesses::total 325963900 # number of demand (read+write) accesses 687system.cpu.dcache.overall_accesses::cpu.data 327900271 # number of overall (read+write) accesses 688system.cpu.dcache.overall_accesses::total 327900271 # number of overall (read+write) accesses 689system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037445 # miss rate for ReadReq accesses 690system.cpu.dcache.ReadReq_miss_rate::total 0.037445 # miss rate for ReadReq accesses 691system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027333 # miss rate for WriteReq accesses 692system.cpu.dcache.WriteReq_miss_rate::total 0.027333 # miss rate for WriteReq accesses 693system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733786 # miss rate for SoftPFReq accesses 694system.cpu.dcache.SoftPFReq_miss_rate::total 0.733786 # miss rate for SoftPFReq accesses 695system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786523 # miss rate for WriteLineReq accesses 696system.cpu.dcache.WriteLineReq_miss_rate::total 0.786523 # miss rate for WriteLineReq accesses 697system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073862 # miss rate for LoadLockedReq accesses 698system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073862 # miss rate for LoadLockedReq accesses 699system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 700system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 701system.cpu.dcache.demand_miss_rate::cpu.data 0.036327 # miss rate for demand accesses 702system.cpu.dcache.demand_miss_rate::total 0.036327 # miss rate for demand accesses 703system.cpu.dcache.overall_miss_rate::cpu.data 0.040446 # miss rate for overall accesses 704system.cpu.dcache.overall_miss_rate::total 0.040446 # miss rate for overall accesses 705system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562 # average ReadReq miss latency 706system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562 # average ReadReq miss latency 707system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209 # average WriteReq miss latency 708system.cpu.dcache.WriteReq_avg_miss_latency::total 49391.098209 # average WriteReq miss latency 709system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43118.922264 # average WriteLineReq miss latency 710system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43118.922264 # average WriteLineReq miss latency 711system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259 # average LoadLockedReq miss latency 712system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259 # average LoadLockedReq miss latency 713system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency 714system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency 715system.cpu.dcache.demand_avg_miss_latency::cpu.data 32006.412087 # average overall miss latency 716system.cpu.dcache.demand_avg_miss_latency::total 32006.412087 # average overall miss latency 717system.cpu.dcache.overall_avg_miss_latency::cpu.data 28577.317585 # average overall miss latency 718system.cpu.dcache.overall_avg_miss_latency::total 28577.317585 # average overall miss latency 719system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 720system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 721system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 722system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 723system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 724system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 725system.cpu.dcache.writebacks::writebacks 8312311 # number of writebacks 726system.cpu.dcache.writebacks::total 8312311 # number of writebacks 727system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778551 # number of ReadReq MSHR hits 728system.cpu.dcache.ReadReq_mshr_hits::total 778551 # number of ReadReq MSHR hits 729system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841560 # number of WriteReq MSHR hits 730system.cpu.dcache.WriteReq_mshr_hits::total 1841560 # number of WriteReq MSHR hits 731system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 166 # number of WriteLineReq MSHR hits 732system.cpu.dcache.WriteLineReq_mshr_hits::total 166 # number of WriteLineReq MSHR hits 733system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69564 # number of LoadLockedReq MSHR hits 734system.cpu.dcache.LoadLockedReq_mshr_hits::total 69564 # number of LoadLockedReq MSHR hits 735system.cpu.dcache.demand_mshr_hits::cpu.data 2620277 # number of demand (read+write) MSHR hits 736system.cpu.dcache.demand_mshr_hits::total 2620277 # number of demand (read+write) MSHR hits 737system.cpu.dcache.overall_mshr_hits::cpu.data 2620277 # number of overall MSHR hits 738system.cpu.dcache.overall_mshr_hits::total 2620277 # number of overall MSHR hits 739system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5645330 # number of ReadReq MSHR misses 740system.cpu.dcache.ReadReq_mshr_misses::total 5645330 # number of ReadReq MSHR misses 741system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2335768 # number of WriteReq MSHR misses 742system.cpu.dcache.WriteReq_mshr_misses::total 2335768 # number of WriteReq MSHR misses 743system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1413353 # number of SoftPFReq MSHR misses 744system.cpu.dcache.SoftPFReq_mshr_misses::total 1413353 # number of SoftPFReq MSHR misses 745system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1239934 # number of WriteLineReq MSHR misses 746system.cpu.dcache.WriteLineReq_mshr_misses::total 1239934 # number of WriteLineReq MSHR misses 747system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241438 # number of LoadLockedReq MSHR misses 748system.cpu.dcache.LoadLockedReq_mshr_misses::total 241438 # number of LoadLockedReq MSHR misses 749system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 750system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 751system.cpu.dcache.demand_mshr_misses::cpu.data 9221032 # number of demand (read+write) MSHR misses 752system.cpu.dcache.demand_mshr_misses::total 9221032 # number of demand (read+write) MSHR misses 753system.cpu.dcache.overall_mshr_misses::cpu.data 10634385 # number of overall MSHR misses 754system.cpu.dcache.overall_mshr_misses::total 10634385 # number of overall MSHR misses 755system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 756system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 757system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 758system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 759system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 760system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 761system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97557432500 # number of ReadReq MSHR miss cycles 762system.cpu.dcache.ReadReq_mshr_miss_latency::total 97557432500 # number of ReadReq MSHR miss cycles 763system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109336281500 # number of WriteReq MSHR miss cycles 764system.cpu.dcache.WriteReq_mshr_miss_latency::total 109336281500 # number of WriteReq MSHR miss cycles 765system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26901290500 # number of SoftPFReq MSHR miss cycles 766system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26901290500 # number of SoftPFReq MSHR miss cycles 767system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52221764000 # number of WriteLineReq MSHR miss cycles 768system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52221764000 # number of WriteLineReq MSHR miss cycles 769system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3529658500 # number of LoadLockedReq MSHR miss cycles 770system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3529658500 # number of LoadLockedReq MSHR miss cycles 771system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles 772system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles 773system.cpu.dcache.demand_mshr_miss_latency::cpu.data 259115478000 # number of demand (read+write) MSHR miss cycles 774system.cpu.dcache.demand_mshr_miss_latency::total 259115478000 # number of demand (read+write) MSHR miss cycles 775system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286016768500 # number of overall MSHR miss cycles 776system.cpu.dcache.overall_mshr_miss_latency::total 286016768500 # number of overall MSHR miss cycles 777system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197628500 # number of ReadReq MSHR uncacheable cycles 778system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197628500 # number of ReadReq MSHR uncacheable cycles 779system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197628500 # number of overall MSHR uncacheable cycles 780system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197628500 # number of overall MSHR uncacheable cycles 781system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032907 # mshr miss rate for ReadReq accesses 782system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032907 # mshr miss rate for ReadReq accesses 783system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015283 # mshr miss rate for WriteReq accesses 784system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015283 # mshr miss rate for WriteReq accesses 785system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729898 # mshr miss rate for SoftPFReq accesses 786system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729898 # mshr miss rate for SoftPFReq accesses 787system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786417 # mshr miss rate for WriteLineReq accesses 788system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786417 # mshr miss rate for WriteLineReq accesses 789system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057340 # mshr miss rate for LoadLockedReq accesses 790system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057340 # mshr miss rate for LoadLockedReq accesses 791system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 792system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 793system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028289 # mshr miss rate for demand accesses 794system.cpu.dcache.demand_mshr_miss_rate::total 0.028289 # mshr miss rate for demand accesses 795system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032432 # mshr miss rate for overall accesses 796system.cpu.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses 797system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871 # average ReadReq mshr miss latency 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871 # average ReadReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921 # average WriteReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46809.563921 # average WriteReq mshr miss latency 801system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19033.667102 # average SoftPFReq mshr miss latency 802system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19033.667102 # average SoftPFReq mshr miss latency 803system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42116.567495 # average WriteLineReq mshr miss latency 804system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42116.567495 # average WriteLineReq mshr miss latency 805system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346 # average LoadLockedReq mshr miss latency 806system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346 # average LoadLockedReq mshr miss latency 807system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency 808system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency 809system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716 # average overall mshr miss latency 810system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716 # average overall mshr miss latency 811system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661 # average overall mshr miss latency 812system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661 # average overall mshr miss latency 813system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency 814system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency 815system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency 816system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency 817system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 818system.cpu.icache.tags.replacements 24339101 # number of replacements 819system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use 820system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. 821system.cpu.icache.tags.sampled_refs 24339613 # Sample count of references to valid blocks. 822system.cpu.icache.tags.avg_refs 17.178953 # Average number of references to valid blocks. 823system.cpu.icache.tags.warmup_cycle 32773385500 # Cycle when the warmup percentage was hit. 824system.cpu.icache.tags.occ_blocks::cpu.inst 511.885333 # Average occupied blocks per requestor 825system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy 826system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy 827system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 828system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 829system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 830system.cpu.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id 831system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 832system.cpu.icache.tags.tag_accesses 466808304 # Number of tag accesses 833system.cpu.icache.tags.data_accesses 466808304 # Number of data accesses 834system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 835system.cpu.icache.ReadReq_hits::cpu.inst 418129059 # number of ReadReq hits 836system.cpu.icache.ReadReq_hits::total 418129059 # number of ReadReq hits 837system.cpu.icache.demand_hits::cpu.inst 418129059 # number of demand (read+write) hits 838system.cpu.icache.demand_hits::total 418129059 # number of demand (read+write) hits 839system.cpu.icache.overall_hits::cpu.inst 418129059 # number of overall hits 840system.cpu.icache.overall_hits::total 418129059 # number of overall hits 841system.cpu.icache.ReadReq_misses::cpu.inst 24339623 # number of ReadReq misses 842system.cpu.icache.ReadReq_misses::total 24339623 # number of ReadReq misses 843system.cpu.icache.demand_misses::cpu.inst 24339623 # number of demand (read+write) misses 844system.cpu.icache.demand_misses::total 24339623 # number of demand (read+write) misses 845system.cpu.icache.overall_misses::cpu.inst 24339623 # number of overall misses 846system.cpu.icache.overall_misses::total 24339623 # number of overall misses 847system.cpu.icache.ReadReq_miss_latency::cpu.inst 329768536500 # number of ReadReq miss cycles 848system.cpu.icache.ReadReq_miss_latency::total 329768536500 # number of ReadReq miss cycles 849system.cpu.icache.demand_miss_latency::cpu.inst 329768536500 # number of demand (read+write) miss cycles 850system.cpu.icache.demand_miss_latency::total 329768536500 # number of demand (read+write) miss cycles 851system.cpu.icache.overall_miss_latency::cpu.inst 329768536500 # number of overall miss cycles 852system.cpu.icache.overall_miss_latency::total 329768536500 # number of overall miss cycles 853system.cpu.icache.ReadReq_accesses::cpu.inst 442468682 # number of ReadReq accesses(hits+misses) 854system.cpu.icache.ReadReq_accesses::total 442468682 # number of ReadReq accesses(hits+misses) 855system.cpu.icache.demand_accesses::cpu.inst 442468682 # number of demand (read+write) accesses 856system.cpu.icache.demand_accesses::total 442468682 # number of demand (read+write) accesses 857system.cpu.icache.overall_accesses::cpu.inst 442468682 # number of overall (read+write) accesses 858system.cpu.icache.overall_accesses::total 442468682 # number of overall (read+write) accesses 859system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055009 # miss rate for ReadReq accesses 860system.cpu.icache.ReadReq_miss_rate::total 0.055009 # miss rate for ReadReq accesses 861system.cpu.icache.demand_miss_rate::cpu.inst 0.055009 # miss rate for demand accesses 862system.cpu.icache.demand_miss_rate::total 0.055009 # miss rate for demand accesses 863system.cpu.icache.overall_miss_rate::cpu.inst 0.055009 # miss rate for overall accesses 864system.cpu.icache.overall_miss_rate::total 0.055009 # miss rate for overall accesses 865system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.629595 # average ReadReq miss latency 866system.cpu.icache.ReadReq_avg_miss_latency::total 13548.629595 # average ReadReq miss latency 867system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.629595 # average overall miss latency 868system.cpu.icache.demand_avg_miss_latency::total 13548.629595 # average overall miss latency 869system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.629595 # average overall miss latency 870system.cpu.icache.overall_avg_miss_latency::total 13548.629595 # average overall miss latency 871system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 872system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 873system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 874system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 875system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 876system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 877system.cpu.icache.writebacks::writebacks 24339101 # number of writebacks 878system.cpu.icache.writebacks::total 24339101 # number of writebacks 879system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24339623 # number of ReadReq MSHR misses 880system.cpu.icache.ReadReq_mshr_misses::total 24339623 # number of ReadReq MSHR misses 881system.cpu.icache.demand_mshr_misses::cpu.inst 24339623 # number of demand (read+write) MSHR misses 882system.cpu.icache.demand_mshr_misses::total 24339623 # number of demand (read+write) MSHR misses 883system.cpu.icache.overall_mshr_misses::cpu.inst 24339623 # number of overall MSHR misses 884system.cpu.icache.overall_mshr_misses::total 24339623 # number of overall MSHR misses 885system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 886system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 887system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 888system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 889system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305428914500 # number of ReadReq MSHR miss cycles 890system.cpu.icache.ReadReq_mshr_miss_latency::total 305428914500 # number of ReadReq MSHR miss cycles 891system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305428914500 # number of demand (read+write) MSHR miss cycles 892system.cpu.icache.demand_mshr_miss_latency::total 305428914500 # number of demand (read+write) MSHR miss cycles 893system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305428914500 # number of overall MSHR miss cycles 894system.cpu.icache.overall_mshr_miss_latency::total 305428914500 # number of overall MSHR miss cycles 895system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles 896system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles 897system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles 898system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles 899system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for ReadReq accesses 900system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055009 # mshr miss rate for ReadReq accesses 901system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for demand accesses 902system.cpu.icache.demand_mshr_miss_rate::total 0.055009 # mshr miss rate for demand accesses 903system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for overall accesses 904system.cpu.icache.overall_mshr_miss_rate::total 0.055009 # mshr miss rate for overall accesses 905system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12548.629636 # average ReadReq mshr miss latency 906system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12548.629636 # average ReadReq mshr miss latency 907system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 908system.cpu.icache.demand_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 909system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 910system.cpu.icache.overall_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 911system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 912system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 913system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 914system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency 915system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 916system.cpu.l2cache.tags.replacements 1529682 # number of replacements 917system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use 918system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks. 919system.cpu.l2cache.tags.sampled_refs 1592715 # Sample count of references to valid blocks. 920system.cpu.l2cache.tags.avg_refs 41.651953 # Average number of references to valid blocks. 921system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit. 922system.cpu.l2cache.tags.occ_blocks::writebacks 36843.538434 # Average occupied blocks per requestor 923system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 325.022996 # Average occupied blocks per requestor 924system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 386.025396 # Average occupied blocks per requestor 925system.cpu.l2cache.tags.occ_blocks::cpu.inst 8031.083741 # Average occupied blocks per requestor 926system.cpu.l2cache.tags.occ_blocks::cpu.data 19745.157287 # Average occupied blocks per requestor 927system.cpu.l2cache.tags.occ_percent::writebacks 0.562188 # Average percentage of cache occupancy 928system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004959 # Average percentage of cache occupancy 929system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005890 # Average percentage of cache occupancy 930system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122545 # Average percentage of cache occupancy 931system.cpu.l2cache.tags.occ_percent::cpu.data 0.301287 # Average percentage of cache occupancy 932system.cpu.l2cache.tags.occ_percent::total 0.996869 # Average percentage of cache occupancy 933system.cpu.l2cache.tags.occ_task_id_blocks::1023 238 # Occupied blocks per task id 934system.cpu.l2cache.tags.occ_task_id_blocks::1024 62795 # Occupied blocks per task id 935system.cpu.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 936system.cpu.l2cache.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id 937system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 938system.cpu.l2cache.tags.age_task_id_blocks_1024::1 461 # Occupied blocks per task id 939system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2479 # Occupied blocks per task id 940system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5541 # Occupied blocks per task id 941system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54260 # Occupied blocks per task id 942system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003632 # Percentage of cache occupancy per task id 943system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958176 # Percentage of cache occupancy per task id 944system.cpu.l2cache.tags.tag_accesses 577322417 # Number of tag accesses 945system.cpu.l2cache.tags.data_accesses 577322417 # Number of data accesses 946system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 947system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 919591 # number of ReadReq hits 948system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 277608 # number of ReadReq hits 949system.cpu.l2cache.ReadReq_hits::total 1197199 # number of ReadReq hits 950system.cpu.l2cache.WritebackDirty_hits::writebacks 8312311 # number of WritebackDirty hits 951system.cpu.l2cache.WritebackDirty_hits::total 8312311 # number of WritebackDirty hits 952system.cpu.l2cache.WritebackClean_hits::writebacks 24335620 # number of WritebackClean hits 953system.cpu.l2cache.WritebackClean_hits::total 24335620 # number of WritebackClean hits 954system.cpu.l2cache.UpgradeReq_hits::cpu.data 10528 # number of UpgradeReq hits 955system.cpu.l2cache.UpgradeReq_hits::total 10528 # number of UpgradeReq hits 956system.cpu.l2cache.ReadExReq_hits::cpu.data 1643656 # number of ReadExReq hits 957system.cpu.l2cache.ReadExReq_hits::total 1643656 # number of ReadExReq hits 958system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24232057 # number of ReadCleanReq hits 959system.cpu.l2cache.ReadCleanReq_hits::total 24232057 # number of ReadCleanReq hits 960system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6978048 # number of ReadSharedReq hits 961system.cpu.l2cache.ReadSharedReq_hits::total 6978048 # number of ReadSharedReq hits 962system.cpu.l2cache.InvalidateReq_hits::cpu.data 702797 # number of InvalidateReq hits 963system.cpu.l2cache.InvalidateReq_hits::total 702797 # number of InvalidateReq hits 964system.cpu.l2cache.demand_hits::cpu.dtb.walker 919591 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.itb.walker 277608 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.inst 24232057 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::cpu.data 8621704 # number of demand (read+write) hits 968system.cpu.l2cache.demand_hits::total 34050960 # number of demand (read+write) hits 969system.cpu.l2cache.overall_hits::cpu.dtb.walker 919591 # number of overall hits 970system.cpu.l2cache.overall_hits::cpu.itb.walker 277608 # number of overall hits 971system.cpu.l2cache.overall_hits::cpu.inst 24232057 # number of overall hits 972system.cpu.l2cache.overall_hits::cpu.data 8621704 # number of overall hits 973system.cpu.l2cache.overall_hits::total 34050960 # number of overall hits 974system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5915 # number of ReadReq misses 975system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4899 # number of ReadReq misses 976system.cpu.l2cache.ReadReq_misses::total 10814 # number of ReadReq misses 977system.cpu.l2cache.UpgradeReq_misses::cpu.data 37973 # number of UpgradeReq misses 978system.cpu.l2cache.UpgradeReq_misses::total 37973 # number of UpgradeReq misses 979system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 980system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 981system.cpu.l2cache.ReadExReq_misses::cpu.data 643878 # number of ReadExReq misses 982system.cpu.l2cache.ReadExReq_misses::total 643878 # number of ReadExReq misses 983system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107562 # number of ReadCleanReq misses 984system.cpu.l2cache.ReadCleanReq_misses::total 107562 # number of ReadCleanReq misses 985system.cpu.l2cache.ReadSharedReq_misses::cpu.data 321806 # number of ReadSharedReq misses 986system.cpu.l2cache.ReadSharedReq_misses::total 321806 # number of ReadSharedReq misses 987system.cpu.l2cache.InvalidateReq_misses::cpu.data 537137 # number of InvalidateReq misses 988system.cpu.l2cache.InvalidateReq_misses::total 537137 # number of InvalidateReq misses 989system.cpu.l2cache.demand_misses::cpu.dtb.walker 5915 # number of demand (read+write) misses 990system.cpu.l2cache.demand_misses::cpu.itb.walker 4899 # number of demand (read+write) misses 991system.cpu.l2cache.demand_misses::cpu.inst 107562 # number of demand (read+write) misses 992system.cpu.l2cache.demand_misses::cpu.data 965684 # number of demand (read+write) misses 993system.cpu.l2cache.demand_misses::total 1084060 # number of demand (read+write) misses 994system.cpu.l2cache.overall_misses::cpu.dtb.walker 5915 # number of overall misses 995system.cpu.l2cache.overall_misses::cpu.itb.walker 4899 # number of overall misses 996system.cpu.l2cache.overall_misses::cpu.inst 107562 # number of overall misses 997system.cpu.l2cache.overall_misses::cpu.data 965684 # number of overall misses 998system.cpu.l2cache.overall_misses::total 1084060 # number of overall misses 999system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 811806000 # number of ReadReq miss cycles 1000system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 672654000 # number of ReadReq miss cycles 1001system.cpu.l2cache.ReadReq_miss_latency::total 1484460000 # number of ReadReq miss cycles 1002system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1453703500 # number of UpgradeReq miss cycles 1003system.cpu.l2cache.UpgradeReq_miss_latency::total 1453703500 # number of UpgradeReq miss cycles 1004system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles 1005system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles 1006system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85473673000 # number of ReadExReq miss cycles 1007system.cpu.l2cache.ReadExReq_miss_latency::total 85473673000 # number of ReadExReq miss cycles 1008system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14248124000 # number of ReadCleanReq miss cycles 1009system.cpu.l2cache.ReadCleanReq_miss_latency::total 14248124000 # number of ReadCleanReq miss cycles 1010system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43454810500 # number of ReadSharedReq miss cycles 1011system.cpu.l2cache.ReadSharedReq_miss_latency::total 43454810500 # number of ReadSharedReq miss cycles 1012system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 9911500 # number of InvalidateReq miss cycles 1013system.cpu.l2cache.InvalidateReq_miss_latency::total 9911500 # number of InvalidateReq miss cycles 1014system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 811806000 # number of demand (read+write) miss cycles 1015system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 672654000 # number of demand (read+write) miss cycles 1016system.cpu.l2cache.demand_miss_latency::cpu.inst 14248124000 # number of demand (read+write) miss cycles 1017system.cpu.l2cache.demand_miss_latency::cpu.data 128928483500 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.demand_miss_latency::total 144661067500 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 811806000 # number of overall miss cycles 1020system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 672654000 # number of overall miss cycles 1021system.cpu.l2cache.overall_miss_latency::cpu.inst 14248124000 # number of overall miss cycles 1022system.cpu.l2cache.overall_miss_latency::cpu.data 128928483500 # number of overall miss cycles 1023system.cpu.l2cache.overall_miss_latency::total 144661067500 # number of overall miss cycles 1024system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 925506 # number of ReadReq accesses(hits+misses) 1025system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 282507 # number of ReadReq accesses(hits+misses) 1026system.cpu.l2cache.ReadReq_accesses::total 1208013 # number of ReadReq accesses(hits+misses) 1027system.cpu.l2cache.WritebackDirty_accesses::writebacks 8312311 # number of WritebackDirty accesses(hits+misses) 1028system.cpu.l2cache.WritebackDirty_accesses::total 8312311 # number of WritebackDirty accesses(hits+misses) 1029system.cpu.l2cache.WritebackClean_accesses::writebacks 24335620 # number of WritebackClean accesses(hits+misses) 1030system.cpu.l2cache.WritebackClean_accesses::total 24335620 # number of WritebackClean accesses(hits+misses) 1031system.cpu.l2cache.UpgradeReq_accesses::cpu.data 48501 # number of UpgradeReq accesses(hits+misses) 1032system.cpu.l2cache.UpgradeReq_accesses::total 48501 # number of UpgradeReq accesses(hits+misses) 1033system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1034system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 1035system.cpu.l2cache.ReadExReq_accesses::cpu.data 2287534 # number of ReadExReq accesses(hits+misses) 1036system.cpu.l2cache.ReadExReq_accesses::total 2287534 # number of ReadExReq accesses(hits+misses) 1037system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24339619 # number of ReadCleanReq accesses(hits+misses) 1038system.cpu.l2cache.ReadCleanReq_accesses::total 24339619 # number of ReadCleanReq accesses(hits+misses) 1039system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7299854 # number of ReadSharedReq accesses(hits+misses) 1040system.cpu.l2cache.ReadSharedReq_accesses::total 7299854 # number of ReadSharedReq accesses(hits+misses) 1041system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1239934 # number of InvalidateReq accesses(hits+misses) 1042system.cpu.l2cache.InvalidateReq_accesses::total 1239934 # number of InvalidateReq accesses(hits+misses) 1043system.cpu.l2cache.demand_accesses::cpu.dtb.walker 925506 # number of demand (read+write) accesses 1044system.cpu.l2cache.demand_accesses::cpu.itb.walker 282507 # number of demand (read+write) accesses 1045system.cpu.l2cache.demand_accesses::cpu.inst 24339619 # number of demand (read+write) accesses 1046system.cpu.l2cache.demand_accesses::cpu.data 9587388 # number of demand (read+write) accesses 1047system.cpu.l2cache.demand_accesses::total 35135020 # number of demand (read+write) accesses 1048system.cpu.l2cache.overall_accesses::cpu.dtb.walker 925506 # number of overall (read+write) accesses 1049system.cpu.l2cache.overall_accesses::cpu.itb.walker 282507 # number of overall (read+write) accesses 1050system.cpu.l2cache.overall_accesses::cpu.inst 24339619 # number of overall (read+write) accesses 1051system.cpu.l2cache.overall_accesses::cpu.data 9587388 # number of overall (read+write) accesses 1052system.cpu.l2cache.overall_accesses::total 35135020 # number of overall (read+write) accesses 1053system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006391 # miss rate for ReadReq accesses 1054system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.017341 # miss rate for ReadReq accesses 1055system.cpu.l2cache.ReadReq_miss_rate::total 0.008952 # miss rate for ReadReq accesses 1056system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782932 # miss rate for UpgradeReq accesses 1057system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782932 # miss rate for UpgradeReq accesses 1058system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1059system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1060system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.281473 # miss rate for ReadExReq accesses 1061system.cpu.l2cache.ReadExReq_miss_rate::total 0.281473 # miss rate for ReadExReq accesses 1062system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004419 # miss rate for ReadCleanReq accesses 1063system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004419 # miss rate for ReadCleanReq accesses 1064system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044084 # miss rate for ReadSharedReq accesses 1065system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044084 # miss rate for ReadSharedReq accesses 1066system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.433198 # miss rate for InvalidateReq accesses 1067system.cpu.l2cache.InvalidateReq_miss_rate::total 0.433198 # miss rate for InvalidateReq accesses 1068system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006391 # miss rate for demand accesses 1069system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017341 # miss rate for demand accesses 1070system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004419 # miss rate for demand accesses 1071system.cpu.l2cache.demand_miss_rate::cpu.data 0.100724 # miss rate for demand accesses 1072system.cpu.l2cache.demand_miss_rate::total 0.030854 # miss rate for demand accesses 1073system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006391 # miss rate for overall accesses 1074system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017341 # miss rate for overall accesses 1075system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004419 # miss rate for overall accesses 1076system.cpu.l2cache.overall_miss_rate::cpu.data 0.100724 # miss rate for overall accesses 1077system.cpu.l2cache.overall_miss_rate::total 0.030854 # miss rate for overall accesses 1078system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137245.308538 # average ReadReq miss latency 1079system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137304.347826 # average ReadReq miss latency 1080system.cpu.l2cache.ReadReq_avg_miss_latency::total 137272.054744 # average ReadReq miss latency 1081system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38282.556027 # average UpgradeReq miss latency 1082system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38282.556027 # average UpgradeReq miss latency 1083system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency 1084system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency 1085system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132748.242680 # average ReadExReq miss latency 1086system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132748.242680 # average ReadExReq miss latency 1087system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132464.290363 # average ReadCleanReq miss latency 1088system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132464.290363 # average ReadCleanReq miss latency 1089system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135034.183639 # average ReadSharedReq miss latency 1090system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135034.183639 # average ReadSharedReq miss latency 1091system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 18.452462 # average InvalidateReq miss latency 1092system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 18.452462 # average InvalidateReq miss latency 1093system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137245.308538 # average overall miss latency 1094system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137304.347826 # average overall miss latency 1095system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132464.290363 # average overall miss latency 1096system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133510.013110 # average overall miss latency 1097system.cpu.l2cache.demand_avg_miss_latency::total 133443.783093 # average overall miss latency 1098system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137245.308538 # average overall miss latency 1099system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137304.347826 # average overall miss latency 1100system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132464.290363 # average overall miss latency 1101system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133510.013110 # average overall miss latency 1102system.cpu.l2cache.overall_avg_miss_latency::total 133443.783093 # average overall miss latency 1103system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1104system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1105system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1106system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1107system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1108system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1109system.cpu.l2cache.writebacks::writebacks 1293856 # number of writebacks 1110system.cpu.l2cache.writebacks::total 1293856 # number of writebacks 1111system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1112system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1113system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1114system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1115system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1116system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1117system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 1118system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1119system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1120system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 1121system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5915 # number of ReadReq MSHR misses 1122system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4899 # number of ReadReq MSHR misses 1123system.cpu.l2cache.ReadReq_mshr_misses::total 10814 # number of ReadReq MSHR misses 1124system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses 1125system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses 1126system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37973 # number of UpgradeReq MSHR misses 1127system.cpu.l2cache.UpgradeReq_mshr_misses::total 37973 # number of UpgradeReq MSHR misses 1128system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1129system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1130system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 643878 # number of ReadExReq MSHR misses 1131system.cpu.l2cache.ReadExReq_mshr_misses::total 643878 # number of ReadExReq MSHR misses 1132system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107559 # number of ReadCleanReq MSHR misses 1133system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107559 # number of ReadCleanReq MSHR misses 1134system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 321785 # number of ReadSharedReq MSHR misses 1135system.cpu.l2cache.ReadSharedReq_mshr_misses::total 321785 # number of ReadSharedReq MSHR misses 1136system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 537137 # number of InvalidateReq MSHR misses 1137system.cpu.l2cache.InvalidateReq_mshr_misses::total 537137 # number of InvalidateReq MSHR misses 1138system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5915 # number of demand (read+write) MSHR misses 1139system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4899 # number of demand (read+write) MSHR misses 1140system.cpu.l2cache.demand_mshr_misses::cpu.inst 107559 # number of demand (read+write) MSHR misses 1141system.cpu.l2cache.demand_mshr_misses::cpu.data 965663 # number of demand (read+write) MSHR misses 1142system.cpu.l2cache.demand_mshr_misses::total 1084036 # number of demand (read+write) MSHR misses 1143system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5915 # number of overall MSHR misses 1144system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4899 # number of overall MSHR misses 1145system.cpu.l2cache.overall_mshr_misses::cpu.inst 107559 # number of overall MSHR misses 1146system.cpu.l2cache.overall_mshr_misses::cpu.data 965663 # number of overall MSHR misses 1147system.cpu.l2cache.overall_mshr_misses::total 1084036 # number of overall MSHR misses 1148system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 1149system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 1150system.cpu.l2cache.ReadReq_mshr_uncacheable::total 86006 # number of ReadReq MSHR uncacheable 1151system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 1152system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 1153system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 1154system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 1155system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119712 # number of overall MSHR uncacheable misses 1156system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 752655502 # number of ReadReq MSHR miss cycles 1157system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 623664000 # number of ReadReq MSHR miss cycles 1158system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1376319502 # number of ReadReq MSHR miss cycles 1159system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2582673500 # number of UpgradeReq MSHR miss cycles 1160system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2582673500 # number of UpgradeReq MSHR miss cycles 1161system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles 1162system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles 1163system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79034877032 # number of ReadExReq MSHR miss cycles 1164system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79034877032 # number of ReadExReq MSHR miss cycles 1165system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13172156574 # number of ReadCleanReq MSHR miss cycles 1166system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13172156574 # number of ReadCleanReq MSHR miss cycles 1167system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40234614920 # number of ReadSharedReq MSHR miss cycles 1168system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40234614920 # number of ReadSharedReq MSHR miss cycles 1169system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 37418286000 # number of InvalidateReq MSHR miss cycles 1170system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 37418286000 # number of InvalidateReq MSHR miss cycles 1171system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 752655502 # number of demand (read+write) MSHR miss cycles 1172system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 623664000 # number of demand (read+write) MSHR miss cycles 1173system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13172156574 # number of demand (read+write) MSHR miss cycles 1174system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119269491952 # number of demand (read+write) MSHR miss cycles 1175system.cpu.l2cache.demand_mshr_miss_latency::total 133817968028 # number of demand (read+write) MSHR miss cycles 1176system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 752655502 # number of overall MSHR miss cycles 1177system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 623664000 # number of overall MSHR miss cycles 1178system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13172156574 # number of overall MSHR miss cycles 1179system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119269491952 # number of overall MSHR miss cycles 1180system.cpu.l2cache.overall_mshr_miss_latency::total 133817968028 # number of overall MSHR miss cycles 1181system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles 1182system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776326000 # number of ReadReq MSHR uncacheable cycles 1183system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712400000 # number of ReadReq MSHR uncacheable cycles 1184system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles 1185system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5776326000 # number of overall MSHR uncacheable cycles 1186system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11712400000 # number of overall MSHR uncacheable cycles 1187system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for ReadReq accesses 1188system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for ReadReq accesses 1189system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008952 # mshr miss rate for ReadReq accesses 1190system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1191system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1192system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782932 # mshr miss rate for UpgradeReq accesses 1193system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782932 # mshr miss rate for UpgradeReq accesses 1194system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1195system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1196system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.281473 # mshr miss rate for ReadExReq accesses 1197system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.281473 # mshr miss rate for ReadExReq accesses 1198system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for ReadCleanReq accesses 1199system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004419 # mshr miss rate for ReadCleanReq accesses 1200system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044081 # mshr miss rate for ReadSharedReq accesses 1201system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044081 # mshr miss rate for ReadSharedReq accesses 1202system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.433198 # mshr miss rate for InvalidateReq accesses 1203system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.433198 # mshr miss rate for InvalidateReq accesses 1204system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for demand accesses 1205system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for demand accesses 1206system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for demand accesses 1207system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.100722 # mshr miss rate for demand accesses 1208system.cpu.l2cache.demand_mshr_miss_rate::total 0.030853 # mshr miss rate for demand accesses 1209system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for overall accesses 1210system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for overall accesses 1211system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for overall accesses 1212system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.100722 # mshr miss rate for overall accesses 1213system.cpu.l2cache.overall_mshr_miss_rate::total 0.030853 # mshr miss rate for overall accesses 1214system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average ReadReq mshr miss latency 1215system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average ReadReq mshr miss latency 1216system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127272.008692 # average ReadReq mshr miss latency 1217system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.417428 # average UpgradeReq mshr miss latency 1218system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.417428 # average UpgradeReq mshr miss latency 1219system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency 1220system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency 1221system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122748.217880 # average ReadExReq mshr miss latency 1222system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122748.217880 # average ReadExReq mshr miss latency 1223system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122464.475999 # average ReadCleanReq mshr miss latency 1224system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122464.475999 # average ReadCleanReq mshr miss latency 1225system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125035.706823 # average ReadSharedReq mshr miss latency 1226system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125035.706823 # average ReadSharedReq mshr miss latency 1227system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.462277 # average InvalidateReq mshr miss latency 1228system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.462277 # average InvalidateReq mshr miss latency 1229system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency 1230system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency 1231system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency 1232system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency 1233system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123444.210366 # average overall mshr miss latency 1234system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency 1235system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency 1236system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency 1237system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency 1238system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123444.210366 # average overall mshr miss latency 1239system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency 1240system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171419.592249 # average ReadReq mshr uncacheable latency 1241system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136181.196661 # average ReadReq mshr uncacheable latency 1242system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency 1243system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85698.351705 # average overall mshr uncacheable latency 1244system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97838.144881 # average overall mshr uncacheable latency 1245system.cpu.toL2Bus.snoop_filter.tot_requests 71082854 # Total number of requests made to the snoop filter. 1246system.cpu.toL2Bus.snoop_filter.hit_single_requests 35915919 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1247system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1248system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter. 1249system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1250system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1251system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1252system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution 1253system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution 1254system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution 1255system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution 1256system.cpu.toL2Bus.trans_dist::WritebackDirty 9712830 # Transaction distribution 1257system.cpu.toL2Bus.trans_dist::WritebackClean 24339101 # Transaction distribution 1258system.cpu.toL2Bus.trans_dist::CleanEvict 2759131 # Transaction distribution 1259system.cpu.toL2Bus.trans_dist::UpgradeReq 48504 # Transaction distribution 1260system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1261system.cpu.toL2Bus.trans_dist::UpgradeResp 48506 # Transaction distribution 1262system.cpu.toL2Bus.trans_dist::ReadExReq 2287534 # Transaction distribution 1263system.cpu.toL2Bus.trans_dist::ReadExResp 2287534 # Transaction distribution 1264system.cpu.toL2Bus.trans_dist::ReadCleanReq 24339623 # Transaction distribution 1265system.cpu.toL2Bus.trans_dist::ReadSharedReq 7308730 # Transaction distribution 1266system.cpu.toL2Bus.trans_dist::InvalidateReq 1346598 # Transaction distribution 1267system.cpu.toL2Bus.trans_dist::InvalidateResp 1239934 # Transaction distribution 1268system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73122960 # Packet count per connected master and slave (bytes) 1269system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32713992 # Packet count per connected master and slave (bytes) 1270system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 682590 # Packet count per connected master and slave (bytes) 1271system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2171018 # Packet count per connected master and slave (bytes) 1272system.cpu.toL2Bus.pkt_count::total 108690560 # Packet count per connected master and slave (bytes) 1273system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3118785792 # Cumulative packet size per connected master and slave (bytes) 1274system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1145820498 # Cumulative packet size per connected master and slave (bytes) 1275system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2260056 # Cumulative packet size per connected master and slave (bytes) 1276system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7404048 # Cumulative packet size per connected master and slave (bytes) 1277system.cpu.toL2Bus.pkt_size::total 4274270394 # Cumulative packet size per connected master and slave (bytes) 1278system.cpu.toL2Bus.snoops 2199102 # Total snoops (count) 1279system.cpu.toL2Bus.snoop_fanout::samples 38741497 # Request fanout histogram 1280system.cpu.toL2Bus.snoop_fanout::mean 0.018274 # Request fanout histogram 1281system.cpu.toL2Bus.snoop_fanout::stdev 0.133941 # Request fanout histogram 1282system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1283system.cpu.toL2Bus.snoop_fanout::0 38033532 98.17% 98.17% # Request fanout histogram 1284system.cpu.toL2Bus.snoop_fanout::1 707965 1.83% 100.00% # Request fanout histogram 1285system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1286system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1287system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1288system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1289system.cpu.toL2Bus.snoop_fanout::total 38741497 # Request fanout histogram 1290system.cpu.toL2Bus.reqLayer0.occupancy 68741576495 # Layer occupancy (ticks) 1291system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1292system.cpu.toL2Bus.snoopLayer0.occupancy 1462889 # Layer occupancy (ticks) 1293system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1294system.cpu.toL2Bus.respLayer0.occupancy 36594790182 # Layer occupancy (ticks) 1295system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1296system.cpu.toL2Bus.respLayer1.occupancy 15076717704 # Layer occupancy (ticks) 1297system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1298system.cpu.toL2Bus.respLayer2.occupancy 400149367 # Layer occupancy (ticks) 1299system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1300system.cpu.toL2Bus.respLayer3.occupancy 1245546930 # Layer occupancy (ticks) 1301system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1302system.iobus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1303system.iobus.trans_dist::ReadReq 40324 # Transaction distribution 1304system.iobus.trans_dist::ReadResp 40324 # Transaction distribution 1305system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1306system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1307system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1308system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1309system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1310system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1311system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1312system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1313system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1314system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1315system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1316system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1317system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1318system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1319system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1320system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1321system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) 1322system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) 1323system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1324system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1325system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) 1326system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1327system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1328system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1329system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1330system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1331system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1332system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1333system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1334system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1335system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1336system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1337system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1338system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1339system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1340system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) 1341system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) 1342system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1343system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1344system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) 1345system.iobus.reqLayer0.occupancy 37107000 # Layer occupancy (ticks) 1346system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1347system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1348system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1349system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) 1350system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1351system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) 1352system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1353system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 1354system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1355system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) 1356system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1357system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 1358system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1359system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 1360system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1361system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 1362system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1363system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) 1364system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1365system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1366system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1367system.iobus.reqLayer23.occupancy 25573000 # Layer occupancy (ticks) 1368system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1369system.iobus.reqLayer24.occupancy 34140500 # Layer occupancy (ticks) 1370system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1371system.iobus.reqLayer25.occupancy 567103107 # Layer occupancy (ticks) 1372system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1373system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1374system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1375system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) 1376system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1377system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1378system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1379system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1380system.iocache.tags.replacements 115484 # number of replacements 1381system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use 1382system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1383system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. 1384system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1385system.iocache.tags.warmup_cycle 13153318095000 # Cycle when the warmup percentage was hit. 1386system.iocache.tags.occ_blocks::realview.ethernet 3.521307 # Average occupied blocks per requestor 1387system.iocache.tags.occ_blocks::realview.ide 6.919947 # Average occupied blocks per requestor 1388system.iocache.tags.occ_percent::realview.ethernet 0.220082 # Average percentage of cache occupancy 1389system.iocache.tags.occ_percent::realview.ide 0.432497 # Average percentage of cache occupancy 1390system.iocache.tags.occ_percent::total 0.652578 # Average percentage of cache occupancy 1391system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1392system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1393system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1394system.iocache.tags.tag_accesses 1039884 # Number of tag accesses 1395system.iocache.tags.data_accesses 1039884 # Number of data accesses 1396system.iocache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1397system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1398system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses 1399system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses 1400system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1401system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1402system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1403system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1404system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1405system.iocache.demand_misses::realview.ide 115503 # number of demand (read+write) misses 1406system.iocache.demand_misses::total 115543 # number of demand (read+write) misses 1407system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1408system.iocache.overall_misses::realview.ide 115503 # number of overall misses 1409system.iocache.overall_misses::total 115543 # number of overall misses 1410system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles 1411system.iocache.ReadReq_miss_latency::realview.ide 1644126101 # number of ReadReq miss cycles 1412system.iocache.ReadReq_miss_latency::total 1649196101 # number of ReadReq miss cycles 1413system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1414system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1415system.iocache.WriteLineReq_miss_latency::realview.ide 13411893006 # number of WriteLineReq miss cycles 1416system.iocache.WriteLineReq_miss_latency::total 13411893006 # number of WriteLineReq miss cycles 1417system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles 1418system.iocache.demand_miss_latency::realview.ide 15056019107 # number of demand (read+write) miss cycles 1419system.iocache.demand_miss_latency::total 15061440107 # number of demand (read+write) miss cycles 1420system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles 1421system.iocache.overall_miss_latency::realview.ide 15056019107 # number of overall miss cycles 1422system.iocache.overall_miss_latency::total 15061440107 # number of overall miss cycles 1423system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1424system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) 1425system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) 1426system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1427system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1428system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1429system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1430system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1431system.iocache.demand_accesses::realview.ide 115503 # number of demand (read+write) accesses 1432system.iocache.demand_accesses::total 115543 # number of demand (read+write) accesses 1433system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1434system.iocache.overall_accesses::realview.ide 115503 # number of overall (read+write) accesses 1435system.iocache.overall_accesses::total 115543 # number of overall (read+write) accesses 1436system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1437system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1438system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1439system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1440system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1441system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1442system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1443system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1444system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1445system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1446system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1447system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1448system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1449system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency 1450system.iocache.ReadReq_avg_miss_latency::realview.ide 186008.157144 # average ReadReq miss latency 1451system.iocache.ReadReq_avg_miss_latency::total 185803.977129 # average ReadReq miss latency 1452system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1453system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1454system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.640422 # average WriteLineReq miss latency 1455system.iocache.WriteLineReq_avg_miss_latency::total 125739.640422 # average WriteLineReq miss latency 1456system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency 1457system.iocache.demand_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency 1458system.iocache.demand_avg_miss_latency::total 130353.548956 # average overall miss latency 1459system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency 1460system.iocache.overall_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency 1461system.iocache.overall_avg_miss_latency::total 130353.548956 # average overall miss latency 1462system.iocache.blocked_cycles::no_mshrs 32855 # number of cycles access was blocked 1463system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1464system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked 1465system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1466system.iocache.avg_blocked_cycles::no_mshrs 9.711794 # average number of cycles each access was blocked 1467system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1468system.iocache.writebacks::writebacks 106630 # number of writebacks 1469system.iocache.writebacks::total 106630 # number of writebacks 1470system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1471system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses 1472system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses 1473system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1474system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1475system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1476system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1477system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1478system.iocache.demand_mshr_misses::realview.ide 115503 # number of demand (read+write) MSHR misses 1479system.iocache.demand_mshr_misses::total 115543 # number of demand (read+write) MSHR misses 1480system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1481system.iocache.overall_mshr_misses::realview.ide 115503 # number of overall MSHR misses 1482system.iocache.overall_mshr_misses::total 115543 # number of overall MSHR misses 1483system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles 1484system.iocache.ReadReq_mshr_miss_latency::realview.ide 1202176101 # number of ReadReq MSHR miss cycles 1485system.iocache.ReadReq_mshr_miss_latency::total 1205396101 # number of ReadReq MSHR miss cycles 1486system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1487system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1488system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073547861 # number of WriteLineReq MSHR miss cycles 1489system.iocache.WriteLineReq_mshr_miss_latency::total 8073547861 # number of WriteLineReq MSHR miss cycles 1490system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles 1491system.iocache.demand_mshr_miss_latency::realview.ide 9275723962 # number of demand (read+write) MSHR miss cycles 1492system.iocache.demand_mshr_miss_latency::total 9279144962 # number of demand (read+write) MSHR miss cycles 1493system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles 1494system.iocache.overall_mshr_miss_latency::realview.ide 9275723962 # number of overall MSHR miss cycles 1495system.iocache.overall_mshr_miss_latency::total 9279144962 # number of overall MSHR miss cycles 1496system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1497system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1498system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1499system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1500system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1501system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1502system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1503system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1504system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1505system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1506system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1507system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1508system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1509system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency 1510system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136008.157144 # average ReadReq mshr miss latency 1511system.iocache.ReadReq_avg_mshr_miss_latency::total 135803.977129 # average ReadReq mshr miss latency 1512system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1513system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1514system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482 # average WriteLineReq mshr miss latency 1515system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482 # average WriteLineReq mshr miss latency 1516system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1517system.iocache.demand_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency 1518system.iocache.demand_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency 1519system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1520system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency 1521system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency 1522system.membus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1523system.membus.trans_dist::ReadReq 86006 # Transaction distribution 1524system.membus.trans_dist::ReadResp 535040 # Transaction distribution 1525system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1526system.membus.trans_dist::WriteResp 33706 # Transaction distribution 1527system.membus.trans_dist::WritebackDirty 1400486 # Transaction distribution 1528system.membus.trans_dist::CleanEvict 243574 # Transaction distribution 1529system.membus.trans_dist::UpgradeReq 38729 # Transaction distribution 1530system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1531system.membus.trans_dist::UpgradeResp 8 # Transaction distribution 1532system.membus.trans_dist::ReadExReq 643252 # Transaction distribution 1533system.membus.trans_dist::ReadExResp 643252 # Transaction distribution 1534system.membus.trans_dist::ReadSharedReq 449034 # Transaction distribution 1535system.membus.trans_dist::InvalidateReq 643674 # Transaction distribution 1536system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1537system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1538system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) 1539system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4380248 # Packet count per connected master and slave (bytes) 1540system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4509900 # Packet count per connected master and slave (bytes) 1541system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237195 # Packet count per connected master and slave (bytes) 1542system.membus.pkt_count_system.iocache.mem_side::total 237195 # Packet count per connected master and slave (bytes) 1543system.membus.pkt_count::total 4747095 # Packet count per connected master and slave (bytes) 1544system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1545system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1546system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) 1547system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155470700 # Cumulative packet size per connected master and slave (bytes) 1548system.membus.pkt_size_system.cpu.l2cache.mem_side::total 155641106 # Cumulative packet size per connected master and slave (bytes) 1549system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7219072 # Cumulative packet size per connected master and slave (bytes) 1550system.membus.pkt_size_system.iocache.mem_side::total 7219072 # Cumulative packet size per connected master and slave (bytes) 1551system.membus.pkt_size::total 162860178 # Cumulative packet size per connected master and slave (bytes) 1552system.membus.snoops 3374 # Total snoops (count) 1553system.membus.snoop_fanout::samples 3538498 # Request fanout histogram 1554system.membus.snoop_fanout::mean 1 # Request fanout histogram 1555system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1556system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1557system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1558system.membus.snoop_fanout::1 3538498 100.00% 100.00% # Request fanout histogram 1559system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1560system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1561system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1562system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1563system.membus.snoop_fanout::total 3538498 # Request fanout histogram 1564system.membus.reqLayer0.occupancy 97241000 # Layer occupancy (ticks) 1565system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1566system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1567system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1568system.membus.reqLayer2.occupancy 5639000 # Layer occupancy (ticks) 1569system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1570system.membus.reqLayer5.occupancy 9317752261 # Layer occupancy (ticks) 1571system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1572system.membus.respLayer2.occupancy 6128850630 # Layer occupancy (ticks) 1573system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1574system.membus.respLayer3.occupancy 44857615 # Layer occupancy (ticks) 1575system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1576system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1577system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1578system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1579system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1580system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1581system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1582system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1583system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1584system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1585system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1586system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1587system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1588system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1589system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1590system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1591system.realview.ethernet.txBytes 966 # Bytes Transmitted 1592system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1593system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1594system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1595system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1596system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1597system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1598system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1599system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1600system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 1601system.realview.ethernet.totPackets 3 # Total Packets 1602system.realview.ethernet.totBytes 966 # Total Bytes 1603system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1604system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 1605system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1606system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1607system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1608system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1609system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1610system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1611system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1612system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1613system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1614system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1615system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1616system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1617system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1618system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1619system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1620system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1621system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1622system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1623system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1624system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1625system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1626system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1627system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1628system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1629system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1630system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1631system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1632system.realview.ethernet.droppedPackets 0 # number of packets dropped 1633system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1634system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1635system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1636system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1637system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1638system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1639system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1640system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1641system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1642system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1643system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1644system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1645system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1646system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1647system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1648system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1649system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1650system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1651system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1652system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1653system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1654system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1655system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states 1656 1657---------- End Simulation Statistics ----------