Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

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stats.txt (11441:0edcf757b6a2)	stats.txt (11456:c0fb4435b80f)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660653 # Number of seconds simulated 4sim_ticks 51660652947000 # Number of ticks simulated 5final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.660653 # Number of seconds simulated 4sim_ticks 51660652947000 # Number of ticks simulated 5final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 204210 # Simulator instruction rate (inst/s) 8host_op_rate 239956 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11350998190 # Simulator tick rate (ticks/s) 10host_mem_usage 682908 # Number of bytes of host memory used 11host_seconds 4551.20 # Real time elapsed on the host	7host_inst_rate 286668 # Simulator instruction rate (inst/s) 8host_op_rate 336848 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15934426663 # Simulator tick rate (ticks/s) 10host_mem_usage 682904 # Number of bytes of host memory used 11host_seconds 3242.08 # Real time elapsed on the host
12sim_insts 929398934 # Number of instructions simulated 13sim_ops 1092086880 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 394752 # Number of bytes read from this memory 21system.physmem.bytes_read::total 73038088 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 10229888 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 10229888 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 89631104 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 89651684 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 5915 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 4899 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 159842 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 964409 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6168 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1141233 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1400486 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1403059 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 7328 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 6069 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 198021 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1194746 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7641 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1413805 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 198021 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 198021 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1734998 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1735396 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1734998 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 7328 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 6069 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 198021 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1195144 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7641 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3149201 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1141233 # Number of read requests accepted 55system.physmem.writeReqs 1403059 # Number of write requests accepted 56system.physmem.readBursts 1141233 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1403059 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 72990656 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 48256 # Total number of bytes read from write queue 60system.physmem.bytesWritten 89651072 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 73038088 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 89651684 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 754 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 69460 # Per bank write bursts 67system.physmem.perBankRdBursts::1 75077 # Per bank write bursts 68system.physmem.perBankRdBursts::2 69733 # Per bank write bursts 69system.physmem.perBankRdBursts::3 63631 # Per bank write bursts 70system.physmem.perBankRdBursts::4 66485 # Per bank write bursts 71system.physmem.perBankRdBursts::5 73840 # Per bank write bursts 72system.physmem.perBankRdBursts::6 65699 # Per bank write bursts 73system.physmem.perBankRdBursts::7 65290 # Per bank write bursts 74system.physmem.perBankRdBursts::8 63012 # Per bank write bursts 75system.physmem.perBankRdBursts::9 121917 # Per bank write bursts 76system.physmem.perBankRdBursts::10 71008 # Per bank write bursts 77system.physmem.perBankRdBursts::11 72120 # Per bank write bursts 78system.physmem.perBankRdBursts::12 67529 # Per bank write bursts 79system.physmem.perBankRdBursts::13 67730 # Per bank write bursts 80system.physmem.perBankRdBursts::14 61491 # Per bank write bursts 81system.physmem.perBankRdBursts::15 66457 # Per bank write bursts 82system.physmem.perBankWrBursts::0 88448 # Per bank write bursts 83system.physmem.perBankWrBursts::1 89667 # Per bank write bursts 84system.physmem.perBankWrBursts::2 88153 # Per bank write bursts 85system.physmem.perBankWrBursts::3 85223 # Per bank write bursts 86system.physmem.perBankWrBursts::4 87614 # Per bank write bursts 87system.physmem.perBankWrBursts::5 91670 # Per bank write bursts 88system.physmem.perBankWrBursts::6 83331 # Per bank write bursts 89system.physmem.perBankWrBursts::7 85393 # Per bank write bursts 90system.physmem.perBankWrBursts::8 84672 # Per bank write bursts 91system.physmem.perBankWrBursts::9 89835 # Per bank write bursts 92system.physmem.perBankWrBursts::10 89185 # Per bank write bursts 93system.physmem.perBankWrBursts::11 91387 # Per bank write bursts 94system.physmem.perBankWrBursts::12 86991 # Per bank write bursts 95system.physmem.perBankWrBursts::13 87934 # Per bank write bursts 96system.physmem.perBankWrBursts::14 84251 # Per bank write bursts 97system.physmem.perBankWrBursts::15 87044 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 34 # Number of times write queue was full causing retry 100system.physmem.totGap 51660651059000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 1141218 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1400486 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1073017 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 61473 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 751 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 541 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1073 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 679 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 307 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 335 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 34323 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 39840 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 78472 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 80418 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 82705 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 81025 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 81933 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 85813 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 85053 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 81235 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 82570 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 85921 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 82664 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 82805 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 85182 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 80817 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 79743 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 79137 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 1073 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 741 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 625 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 472 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 563 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 387 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 330 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 327 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 265 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 275 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 294 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 263 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 272 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 180 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 209 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 233 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 155 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 122 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 119 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 164 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 648791 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 250.683724 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 151.960276 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 285.693480 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 280366 43.21% 43.21% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 167406 25.80% 69.02% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 61019 9.41% 78.42% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 33573 5.17% 83.60% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 23084 3.56% 87.15% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 16255 2.51% 89.66% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 11383 1.75% 91.41% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 9506 1.47% 92.88% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 46199 7.12% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 648791 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 76825 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 14.845063 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 142.168306 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-1023 76822 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 76825 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 76825 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 18.233622 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 17.685886 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 7.065993 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 64901 84.48% 84.48% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 9488 12.35% 96.83% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 481 0.63% 97.46% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 307 0.40% 97.85% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 57 0.07% 97.93% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 121 0.16% 98.09% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 251 0.33% 98.41% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 28 0.04% 98.45% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 303 0.39% 98.84% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 81 0.11% 98.95% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 29 0.04% 98.99% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 51 0.07% 99.05% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 317 0.41% 99.47% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 31 0.04% 99.51% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 113 0.15% 99.69% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 181 0.24% 99.92% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 5 0.01% 99.93% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::92-95 1 0.00% 99.93% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::128-131 10 0.01% 99.96% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::total 76825 # Writes before turning the bus around for reads 273system.physmem.totQLat 16555348236 # Total ticks spent queuing 274system.physmem.totMemAccLat 37939329486 # Total ticks spent from burst creation until serviced by the DRAM 275system.physmem.totBusLat 5702395000 # Total ticks spent in databus transfers 276system.physmem.avgQLat 14516.14 # Average queueing delay per DRAM burst 277system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 278system.physmem.avgMemAccLat 33266.14 # Average memory access latency per DRAM burst 279system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s 280system.physmem.avgWrBW 1.74 # Average achieved write bandwidth in MiByte/s 281system.physmem.avgRdBWSys 1.41 # Average system read bandwidth in MiByte/s 282system.physmem.avgWrBWSys 1.74 # Average system write bandwidth in MiByte/s 283system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 284system.physmem.busUtil 0.02 # Data bus utilization in percentage 285system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 286system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 287system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 288system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing 289system.physmem.readRowHits 872195 # Number of row buffer hits during reads 290system.physmem.writeRowHits 1020290 # Number of row buffer hits during writes 291system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads 292system.physmem.writeRowHitRate 72.84 # Row buffer hit rate for writes 293system.physmem.avgGap 20304529.14 # Average gap between requests 294system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined 295system.physmem_0.actEnergy 2468362680 # Energy for activate commands per rank (pJ) 296system.physmem_0.preEnergy 1346824875 # Energy for precharge commands per rank (pJ) 297system.physmem_0.readEnergy 4283830200 # Energy for read commands per rank (pJ) 298system.physmem_0.writeEnergy 4532753520 # Energy for write commands per rank (pJ) 299system.physmem_0.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) 300system.physmem_0.actBackEnergy 1318333461255 # Energy for active background per rank (pJ) 301system.physmem_0.preBackEnergy 29839955813250 # Energy for precharge background per rank (pJ) 302system.physmem_0.totalEnergy 34545143413140 # Total energy per rank (pJ) 303system.physmem_0.averagePower 668.693578 # Core power per rank (mW) 304system.physmem_0.memoryStateTime::IDLE 49640663734133 # Time in different power states 305system.physmem_0.memoryStateTime::REF 1725062560000 # Time in different power states 306system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 307system.physmem_0.memoryStateTime::ACT 294925880867 # Time in different power states 308system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 309system.physmem_1.actEnergy 2436497280 # Energy for activate commands per rank (pJ) 310system.physmem_1.preEnergy 1329438000 # Energy for precharge commands per rank (pJ) 311system.physmem_1.readEnergy 4611859200 # Energy for read commands per rank (pJ) 312system.physmem_1.writeEnergy 4544417520 # Energy for write commands per rank (pJ) 313system.physmem_1.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) 314system.physmem_1.actBackEnergy 1316960739945 # Energy for active background per rank (pJ) 315system.physmem_1.preBackEnergy 29841159946500 # Energy for precharge background per rank (pJ) 316system.physmem_1.totalEnergy 34545265265805 # Total energy per rank (pJ) 317system.physmem_1.averagePower 668.695937 # Core power per rank (mW) 318system.physmem_1.memoryStateTime::IDLE 49642646529009 # Time in different power states 319system.physmem_1.memoryStateTime::REF 1725062560000 # Time in different power states 320system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 321system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states 322system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 323system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 326system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 327system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 328system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 329system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 330system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 331system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 332system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 337system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 338system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 339system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 340system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 341system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 342system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 343system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 344system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 345system.cpu.branchPred.lookups 256209592 # Number of BP lookups 346system.cpu.branchPred.condPredicted 178352168 # Number of conditional branches predicted 347system.cpu.branchPred.condIncorrect 12215343 # Number of conditional branches incorrect 348system.cpu.branchPred.BTBLookups 188533609 # Number of BTB lookups 349system.cpu.branchPred.BTBHits 127068742 # Number of BTB hits 350system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 351system.cpu.branchPred.BTBHitPct 67.398456 # BTB Hit Percentage 352system.cpu.branchPred.usedRAS 31319231 # Number of times the RAS was used to get a target. 353system.cpu.branchPred.RASInCorrect 2132154 # Number of incorrect RAS predictions. 354system.cpu.branchPred.indirectLookups 7072039 # Number of indirect predictor lookups. 355system.cpu.branchPred.indirectHits 5016643 # Number of indirect target hits. 356system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses. 357system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches. 358system.cpu_clk_domain.clock 500 # Clock period in ticks 359system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 366system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 367system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 368system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 369system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 370system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 371system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 372system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 373system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 374system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 375system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 376system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 377system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 378system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 379system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 380system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 381system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 382system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 383system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 384system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 385system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 386system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 387system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 388system.cpu.dtb.walker.walks 561578 # Table walker walks requested 389system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors 390system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate 391system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181761 # Level at which table walker walks with long descriptors terminate 392system.cpu.dtb.walker.walkWaitTime::samples 561578 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::0 561578 100.00% 100.00% # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::total 561578 # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkCompletionTime::samples 202628 # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::mean 27245.592909 # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::gmean 23033.802603 # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::stdev 21444.921579 # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::0-65535 200160 98.78% 98.78% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.78% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::131072-196607 2084 1.03% 99.81% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::196608-262143 75 0.04% 99.85% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::262144-327679 137 0.07% 99.92% # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::327680-393215 55 0.03% 99.94% # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::393216-458751 85 0.04% 99.99% # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 99.99% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::589824-655359 10 0.00% 100.00% # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::total 202628 # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution 412system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution 413system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution 414system.cpu.dtb.walker.walkPageSizes::4K 181762 89.70% 89.70% # Table walker page sizes translated 415system.cpu.dtb.walker.walkPageSizes::2M 20867 10.30% 100.00% # Table walker page sizes translated 416system.cpu.dtb.walker.walkPageSizes::total 202629 # Table walker page sizes translated 417system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561578 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561578 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202629 # Table walker requests started/completed, data/inst 421system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202629 # Table walker requests started/completed, data/inst 423system.cpu.dtb.walker.walkRequestOrigin::total 764207 # Table walker requests started/completed, data/inst 424system.cpu.dtb.inst_hits 0 # ITB inst hits 425system.cpu.dtb.inst_misses 0 # ITB inst misses 426system.cpu.dtb.read_hits 179568747 # DTB read hits 427system.cpu.dtb.read_misses 462708 # DTB read misses 428system.cpu.dtb.write_hits 159223685 # DTB write hits 429system.cpu.dtb.write_misses 98870 # DTB write misses 430system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 431system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 432system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 433system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID 434system.cpu.dtb.flush_entries 78994 # Number of entries that have been flushed from TLB 435system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions 436system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch 437system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 438system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions 439system.cpu.dtb.read_accesses 180031455 # DTB read accesses 440system.cpu.dtb.write_accesses 159322555 # DTB write accesses 441system.cpu.dtb.inst_accesses 0 # ITB inst accesses 442system.cpu.dtb.hits 338792432 # DTB hits 443system.cpu.dtb.misses 561578 # DTB misses 444system.cpu.dtb.accesses 339354010 # DTB accesses 445system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 454system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 455system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 456system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 457system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 458system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 459system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 460system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 461system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 462system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 463system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 464system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 465system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 466system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 468system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 469system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 470system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 471system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 472system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 473system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 474system.cpu.itb.walker.walks 133823 # Table walker walks requested 475system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors 476system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate 477system.cpu.itb.walker.walksLongTerminationLevel::Level3 116932 # Level at which table walker walks with long descriptors terminate 478system.cpu.itb.walker.walkWaitTime::samples 133823 # Table walker wait (enqueue to first request) latency 479system.cpu.itb.walker.walkWaitTime::0 133823 100.00% 100.00% # Table walker wait (enqueue to first request) latency 480system.cpu.itb.walker.walkWaitTime::total 133823 # Table walker wait (enqueue to first request) latency 481system.cpu.itb.walker.walkCompletionTime::samples 117989 # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::mean 30581.308427 # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::gmean 25983.502451 # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::stdev 24251.357512 # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::0-65535 115208 97.64% 97.64% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 97.65% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::131072-196607 2538 2.15% 99.80% # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::196608-262143 65 0.06% 99.85% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::262144-327679 122 0.10% 99.96% # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.98% # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::393216-458751 18 0.02% 100.00% # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 493system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::total 117989 # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution 496system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution 497system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution 498system.cpu.itb.walker.walkPageSizes::4K 116932 99.10% 99.10% # Table walker page sizes translated 499system.cpu.itb.walker.walkPageSizes::2M 1057 0.90% 100.00% # Table walker page sizes translated 500system.cpu.itb.walker.walkPageSizes::total 117989 # Table walker page sizes translated 501system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 502system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 133823 # Table walker requests started/completed, data/inst 503system.cpu.itb.walker.walkRequestOrigin_Requested::total 133823 # Table walker requests started/completed, data/inst 504system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 505system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 117989 # Table walker requests started/completed, data/inst 506system.cpu.itb.walker.walkRequestOrigin_Completed::total 117989 # Table walker requests started/completed, data/inst 507system.cpu.itb.walker.walkRequestOrigin::total 251812 # Table walker requests started/completed, data/inst 508system.cpu.itb.inst_hits 442793055 # ITB inst hits 509system.cpu.itb.inst_misses 133823 # ITB inst misses 510system.cpu.itb.read_hits 0 # DTB read hits 511system.cpu.itb.read_misses 0 # DTB read misses 512system.cpu.itb.write_hits 0 # DTB write hits 513system.cpu.itb.write_misses 0 # DTB write misses 514system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 515system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 517system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID 518system.cpu.itb.flush_entries 56590 # Number of entries that have been flushed from TLB 519system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 520system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 521system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions 523system.cpu.itb.read_accesses 0 # DTB read accesses 524system.cpu.itb.write_accesses 0 # DTB write accesses 525system.cpu.itb.inst_accesses 442926878 # ITB inst accesses 526system.cpu.itb.hits 442793055 # DTB hits 527system.cpu.itb.misses 133823 # DTB misses 528system.cpu.itb.accesses 442926878 # DTB accesses 529system.cpu.numCycles 2561963341 # number of cpu cycles simulated 530system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 531system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 532system.cpu.committedInsts 929398934 # Number of instructions committed 533system.cpu.committedOps 1092086880 # Number of ops (including micro ops) committed 534system.cpu.discardedOps 94664249 # Number of ops (including micro ops) which were discarded before commit 535system.cpu.numFetchSuspends 7656 # Number of times Execute suspended instruction fetching 536system.cpu.quiesceCycles 100760459460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 537system.cpu.cpi 2.756581 # CPI: cycles per instruction 538system.cpu.ipc 0.362768 # IPC: instructions per cycle 539system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 540system.cpu.op_class_0::IntAlu 756821893 69.30% 69.30% # Class of committed instruction 541system.cpu.op_class_0::IntMult 2277263 0.21% 69.51% # Class of committed instruction 542system.cpu.op_class_0::IntDiv 98455 0.01% 69.52% # Class of committed instruction 543system.cpu.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction 544system.cpu.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction 545system.cpu.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction 546system.cpu.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction 547system.cpu.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction 548system.cpu.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction 549system.cpu.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction 550system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction 551system.cpu.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction 552system.cpu.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction 553system.cpu.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction 554system.cpu.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction 555system.cpu.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction 556system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction 557system.cpu.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction 558system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction 559system.cpu.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction 560system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction 561system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction 562system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction 563system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction 564system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction 565system.cpu.op_class_0::SimdFloatMisc 109444 0.01% 69.53% # Class of committed instruction 566system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction 567system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction 568system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction 569system.cpu.op_class_0::MemRead 174118935 15.94% 85.47% # Class of committed instruction 570system.cpu.op_class_0::MemWrite 158660847 14.53% 100.00% # Class of committed instruction 571system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 572system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 573system.cpu.op_class_0::total 1092086880 # Class of committed instruction 574system.cpu.kern.inst.arm 0 # number of arm instructions executed 575system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed 576system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked 577system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped 578system.cpu.dcache.tags.replacements 10826762 # number of replacements 579system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use 580system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks. 581system.cpu.dcache.tags.sampled_refs 10827274 # Sample count of references to valid blocks. 582system.cpu.dcache.tags.avg_refs 29.813150 # Average number of references to valid blocks. 583system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. 584system.cpu.dcache.tags.occ_blocks::cpu.data 511.930071 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 587system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 590system.cpu.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 591system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 592system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 593system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses 594system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses 595system.cpu.dcache.ReadReq_hits::cpu.data 165131668 # number of ReadReq hits 596system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits 597system.cpu.dcache.WriteReq_hits::cpu.data 148654336 # number of WriteReq hits 598system.cpu.dcache.WriteReq_hits::total 148654336 # number of WriteReq hits 599system.cpu.dcache.SoftPFReq_hits::cpu.data 515490 # number of SoftPFReq hits 600system.cpu.dcache.SoftPFReq_hits::total 515490 # number of SoftPFReq hits 601system.cpu.dcache.WriteLineReq_hits::cpu.data 336587 # number of WriteLineReq hits 602system.cpu.dcache.WriteLineReq_hits::total 336587 # number of WriteLineReq hits 603system.cpu.dcache.LoadLockedReq_hits::cpu.data 3899601 # number of LoadLockedReq hits 604system.cpu.dcache.LoadLockedReq_hits::total 3899601 # number of LoadLockedReq hits 605system.cpu.dcache.StoreCondReq_hits::cpu.data 4208890 # number of StoreCondReq hits 606system.cpu.dcache.StoreCondReq_hits::total 4208890 # number of StoreCondReq hits	12sim_insts 929398934 # Number of instructions simulated 13sim_ops 1092086880 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 394752 # Number of bytes read from this memory 21system.physmem.bytes_read::total 73038088 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 10229888 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 10229888 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 89631104 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 89651684 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 5915 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 4899 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 159842 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 964409 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6168 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1141233 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1400486 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1403059 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 7328 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 6069 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 198021 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1194746 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7641 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1413805 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 198021 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 198021 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1734998 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1735396 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1734998 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 7328 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 6069 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 198021 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1195144 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7641 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3149201 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1141233 # Number of read requests accepted 55system.physmem.writeReqs 1403059 # Number of write requests accepted 56system.physmem.readBursts 1141233 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1403059 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 72990656 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 48256 # Total number of bytes read from write queue 60system.physmem.bytesWritten 89651072 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 73038088 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 89651684 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 754 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 69460 # Per bank write bursts 67system.physmem.perBankRdBursts::1 75077 # Per bank write bursts 68system.physmem.perBankRdBursts::2 69733 # Per bank write bursts 69system.physmem.perBankRdBursts::3 63631 # Per bank write bursts 70system.physmem.perBankRdBursts::4 66485 # Per bank write bursts 71system.physmem.perBankRdBursts::5 73840 # Per bank write bursts 72system.physmem.perBankRdBursts::6 65699 # Per bank write bursts 73system.physmem.perBankRdBursts::7 65290 # Per bank write bursts 74system.physmem.perBankRdBursts::8 63012 # Per bank write bursts 75system.physmem.perBankRdBursts::9 121917 # Per bank write bursts 76system.physmem.perBankRdBursts::10 71008 # Per bank write bursts 77system.physmem.perBankRdBursts::11 72120 # Per bank write bursts 78system.physmem.perBankRdBursts::12 67529 # Per bank write bursts 79system.physmem.perBankRdBursts::13 67730 # Per bank write bursts 80system.physmem.perBankRdBursts::14 61491 # Per bank write bursts 81system.physmem.perBankRdBursts::15 66457 # Per bank write bursts 82system.physmem.perBankWrBursts::0 88448 # Per bank write bursts 83system.physmem.perBankWrBursts::1 89667 # Per bank write bursts 84system.physmem.perBankWrBursts::2 88153 # Per bank write bursts 85system.physmem.perBankWrBursts::3 85223 # Per bank write bursts 86system.physmem.perBankWrBursts::4 87614 # Per bank write bursts 87system.physmem.perBankWrBursts::5 91670 # Per bank write bursts 88system.physmem.perBankWrBursts::6 83331 # Per bank write bursts 89system.physmem.perBankWrBursts::7 85393 # Per bank write bursts 90system.physmem.perBankWrBursts::8 84672 # Per bank write bursts 91system.physmem.perBankWrBursts::9 89835 # Per bank write bursts 92system.physmem.perBankWrBursts::10 89185 # Per bank write bursts 93system.physmem.perBankWrBursts::11 91387 # Per bank write bursts 94system.physmem.perBankWrBursts::12 86991 # Per bank write bursts 95system.physmem.perBankWrBursts::13 87934 # Per bank write bursts 96system.physmem.perBankWrBursts::14 84251 # Per bank write bursts 97system.physmem.perBankWrBursts::15 87044 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 34 # Number of times write queue was full causing retry 100system.physmem.totGap 51660651059000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 1141218 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1400486 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1073017 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 61473 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 751 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 541 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1073 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 679 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 307 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 335 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 34323 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 39840 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 78472 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 80418 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 82705 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 81025 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 81933 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 85813 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 85053 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 81235 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 82570 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 85921 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 82664 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 82805 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 85182 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 80817 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 79743 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 79137 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 1073 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 741 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 625 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 472 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 563 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 387 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 330 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 327 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 265 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 275 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 294 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 263 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 272 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 180 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 209 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 233 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 155 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 122 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 119 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 164 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 648791 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 250.683724 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 151.960276 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 285.693480 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 280366 43.21% 43.21% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 167406 25.80% 69.02% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 61019 9.41% 78.42% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 33573 5.17% 83.60% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 23084 3.56% 87.15% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 16255 2.51% 89.66% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 11383 1.75% 91.41% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 9506 1.47% 92.88% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 46199 7.12% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 648791 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 76825 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 14.845063 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 142.168306 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-1023 76822 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 76825 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 76825 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 18.233622 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 17.685886 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 7.065993 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 64901 84.48% 84.48% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 9488 12.35% 96.83% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 481 0.63% 97.46% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 307 0.40% 97.85% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 57 0.07% 97.93% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 121 0.16% 98.09% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 251 0.33% 98.41% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 28 0.04% 98.45% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 303 0.39% 98.84% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 81 0.11% 98.95% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 29 0.04% 98.99% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 51 0.07% 99.05% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 317 0.41% 99.47% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 31 0.04% 99.51% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 113 0.15% 99.69% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 181 0.24% 99.92% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 5 0.01% 99.93% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::92-95 1 0.00% 99.93% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::128-131 10 0.01% 99.96% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::total 76825 # Writes before turning the bus around for reads 273system.physmem.totQLat 16555348236 # Total ticks spent queuing 274system.physmem.totMemAccLat 37939329486 # Total ticks spent from burst creation until serviced by the DRAM 275system.physmem.totBusLat 5702395000 # Total ticks spent in databus transfers 276system.physmem.avgQLat 14516.14 # Average queueing delay per DRAM burst 277system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 278system.physmem.avgMemAccLat 33266.14 # Average memory access latency per DRAM burst 279system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s 280system.physmem.avgWrBW 1.74 # Average achieved write bandwidth in MiByte/s 281system.physmem.avgRdBWSys 1.41 # Average system read bandwidth in MiByte/s 282system.physmem.avgWrBWSys 1.74 # Average system write bandwidth in MiByte/s 283system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 284system.physmem.busUtil 0.02 # Data bus utilization in percentage 285system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 286system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 287system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 288system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing 289system.physmem.readRowHits 872195 # Number of row buffer hits during reads 290system.physmem.writeRowHits 1020290 # Number of row buffer hits during writes 291system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads 292system.physmem.writeRowHitRate 72.84 # Row buffer hit rate for writes 293system.physmem.avgGap 20304529.14 # Average gap between requests 294system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined 295system.physmem_0.actEnergy 2468362680 # Energy for activate commands per rank (pJ) 296system.physmem_0.preEnergy 1346824875 # Energy for precharge commands per rank (pJ) 297system.physmem_0.readEnergy 4283830200 # Energy for read commands per rank (pJ) 298system.physmem_0.writeEnergy 4532753520 # Energy for write commands per rank (pJ) 299system.physmem_0.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) 300system.physmem_0.actBackEnergy 1318333461255 # Energy for active background per rank (pJ) 301system.physmem_0.preBackEnergy 29839955813250 # Energy for precharge background per rank (pJ) 302system.physmem_0.totalEnergy 34545143413140 # Total energy per rank (pJ) 303system.physmem_0.averagePower 668.693578 # Core power per rank (mW) 304system.physmem_0.memoryStateTime::IDLE 49640663734133 # Time in different power states 305system.physmem_0.memoryStateTime::REF 1725062560000 # Time in different power states 306system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 307system.physmem_0.memoryStateTime::ACT 294925880867 # Time in different power states 308system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 309system.physmem_1.actEnergy 2436497280 # Energy for activate commands per rank (pJ) 310system.physmem_1.preEnergy 1329438000 # Energy for precharge commands per rank (pJ) 311system.physmem_1.readEnergy 4611859200 # Energy for read commands per rank (pJ) 312system.physmem_1.writeEnergy 4544417520 # Energy for write commands per rank (pJ) 313system.physmem_1.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) 314system.physmem_1.actBackEnergy 1316960739945 # Energy for active background per rank (pJ) 315system.physmem_1.preBackEnergy 29841159946500 # Energy for precharge background per rank (pJ) 316system.physmem_1.totalEnergy 34545265265805 # Total energy per rank (pJ) 317system.physmem_1.averagePower 668.695937 # Core power per rank (mW) 318system.physmem_1.memoryStateTime::IDLE 49642646529009 # Time in different power states 319system.physmem_1.memoryStateTime::REF 1725062560000 # Time in different power states 320system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 321system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states 322system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 323system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 326system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 327system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 328system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 329system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 330system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 331system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 332system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 337system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 338system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 339system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 340system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 341system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 342system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 343system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 344system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 345system.cpu.branchPred.lookups 256209592 # Number of BP lookups 346system.cpu.branchPred.condPredicted 178352168 # Number of conditional branches predicted 347system.cpu.branchPred.condIncorrect 12215343 # Number of conditional branches incorrect 348system.cpu.branchPred.BTBLookups 188533609 # Number of BTB lookups 349system.cpu.branchPred.BTBHits 127068742 # Number of BTB hits 350system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 351system.cpu.branchPred.BTBHitPct 67.398456 # BTB Hit Percentage 352system.cpu.branchPred.usedRAS 31319231 # Number of times the RAS was used to get a target. 353system.cpu.branchPred.RASInCorrect 2132154 # Number of incorrect RAS predictions. 354system.cpu.branchPred.indirectLookups 7072039 # Number of indirect predictor lookups. 355system.cpu.branchPred.indirectHits 5016643 # Number of indirect target hits. 356system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses. 357system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches. 358system.cpu_clk_domain.clock 500 # Clock period in ticks 359system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 366system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 367system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 368system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 369system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 370system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 371system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 372system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 373system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 374system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 375system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 376system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 377system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 378system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 379system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 380system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 381system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 382system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 383system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 384system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 385system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 386system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 387system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 388system.cpu.dtb.walker.walks 561578 # Table walker walks requested 389system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors 390system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate 391system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181761 # Level at which table walker walks with long descriptors terminate 392system.cpu.dtb.walker.walkWaitTime::samples 561578 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::0 561578 100.00% 100.00% # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::total 561578 # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkCompletionTime::samples 202628 # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::mean 27245.592909 # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::gmean 23033.802603 # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::stdev 21444.921579 # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::0-65535 200160 98.78% 98.78% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.78% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::131072-196607 2084 1.03% 99.81% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::196608-262143 75 0.04% 99.85% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::262144-327679 137 0.07% 99.92% # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::327680-393215 55 0.03% 99.94% # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::393216-458751 85 0.04% 99.99% # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 99.99% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::589824-655359 10 0.00% 100.00% # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::total 202628 # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution 412system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution 413system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution 414system.cpu.dtb.walker.walkPageSizes::4K 181762 89.70% 89.70% # Table walker page sizes translated 415system.cpu.dtb.walker.walkPageSizes::2M 20867 10.30% 100.00% # Table walker page sizes translated 416system.cpu.dtb.walker.walkPageSizes::total 202629 # Table walker page sizes translated 417system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561578 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561578 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202629 # Table walker requests started/completed, data/inst 421system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202629 # Table walker requests started/completed, data/inst 423system.cpu.dtb.walker.walkRequestOrigin::total 764207 # Table walker requests started/completed, data/inst 424system.cpu.dtb.inst_hits 0 # ITB inst hits 425system.cpu.dtb.inst_misses 0 # ITB inst misses 426system.cpu.dtb.read_hits 179568747 # DTB read hits 427system.cpu.dtb.read_misses 462708 # DTB read misses 428system.cpu.dtb.write_hits 159223685 # DTB write hits 429system.cpu.dtb.write_misses 98870 # DTB write misses 430system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 431system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 432system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 433system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID 434system.cpu.dtb.flush_entries 78994 # Number of entries that have been flushed from TLB 435system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions 436system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch 437system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 438system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions 439system.cpu.dtb.read_accesses 180031455 # DTB read accesses 440system.cpu.dtb.write_accesses 159322555 # DTB write accesses 441system.cpu.dtb.inst_accesses 0 # ITB inst accesses 442system.cpu.dtb.hits 338792432 # DTB hits 443system.cpu.dtb.misses 561578 # DTB misses 444system.cpu.dtb.accesses 339354010 # DTB accesses 445system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 454system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 455system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 456system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 457system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 458system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 459system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 460system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 461system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 462system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 463system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 464system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 465system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 466system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 468system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 469system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 470system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 471system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 472system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 473system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 474system.cpu.itb.walker.walks 133823 # Table walker walks requested 475system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors 476system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate 477system.cpu.itb.walker.walksLongTerminationLevel::Level3 116932 # Level at which table walker walks with long descriptors terminate 478system.cpu.itb.walker.walkWaitTime::samples 133823 # Table walker wait (enqueue to first request) latency 479system.cpu.itb.walker.walkWaitTime::0 133823 100.00% 100.00% # Table walker wait (enqueue to first request) latency 480system.cpu.itb.walker.walkWaitTime::total 133823 # Table walker wait (enqueue to first request) latency 481system.cpu.itb.walker.walkCompletionTime::samples 117989 # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::mean 30581.308427 # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::gmean 25983.502451 # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::stdev 24251.357512 # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::0-65535 115208 97.64% 97.64% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 97.65% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::131072-196607 2538 2.15% 99.80% # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::196608-262143 65 0.06% 99.85% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::262144-327679 122 0.10% 99.96% # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.98% # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::393216-458751 18 0.02% 100.00% # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 493system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::total 117989 # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution 496system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution 497system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution 498system.cpu.itb.walker.walkPageSizes::4K 116932 99.10% 99.10% # Table walker page sizes translated 499system.cpu.itb.walker.walkPageSizes::2M 1057 0.90% 100.00% # Table walker page sizes translated 500system.cpu.itb.walker.walkPageSizes::total 117989 # Table walker page sizes translated 501system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 502system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 133823 # Table walker requests started/completed, data/inst 503system.cpu.itb.walker.walkRequestOrigin_Requested::total 133823 # Table walker requests started/completed, data/inst 504system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 505system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 117989 # Table walker requests started/completed, data/inst 506system.cpu.itb.walker.walkRequestOrigin_Completed::total 117989 # Table walker requests started/completed, data/inst 507system.cpu.itb.walker.walkRequestOrigin::total 251812 # Table walker requests started/completed, data/inst 508system.cpu.itb.inst_hits 442793055 # ITB inst hits 509system.cpu.itb.inst_misses 133823 # ITB inst misses 510system.cpu.itb.read_hits 0 # DTB read hits 511system.cpu.itb.read_misses 0 # DTB read misses 512system.cpu.itb.write_hits 0 # DTB write hits 513system.cpu.itb.write_misses 0 # DTB write misses 514system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 515system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID 517system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID 518system.cpu.itb.flush_entries 56590 # Number of entries that have been flushed from TLB 519system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 520system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 521system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions 523system.cpu.itb.read_accesses 0 # DTB read accesses 524system.cpu.itb.write_accesses 0 # DTB write accesses 525system.cpu.itb.inst_accesses 442926878 # ITB inst accesses 526system.cpu.itb.hits 442793055 # DTB hits 527system.cpu.itb.misses 133823 # DTB misses 528system.cpu.itb.accesses 442926878 # DTB accesses 529system.cpu.numCycles 2561963341 # number of cpu cycles simulated 530system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 531system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 532system.cpu.committedInsts 929398934 # Number of instructions committed 533system.cpu.committedOps 1092086880 # Number of ops (including micro ops) committed 534system.cpu.discardedOps 94664249 # Number of ops (including micro ops) which were discarded before commit 535system.cpu.numFetchSuspends 7656 # Number of times Execute suspended instruction fetching 536system.cpu.quiesceCycles 100760459460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 537system.cpu.cpi 2.756581 # CPI: cycles per instruction 538system.cpu.ipc 0.362768 # IPC: instructions per cycle 539system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 540system.cpu.op_class_0::IntAlu 756821893 69.30% 69.30% # Class of committed instruction 541system.cpu.op_class_0::IntMult 2277263 0.21% 69.51% # Class of committed instruction 542system.cpu.op_class_0::IntDiv 98455 0.01% 69.52% # Class of committed instruction 543system.cpu.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction 544system.cpu.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction 545system.cpu.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction 546system.cpu.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction 547system.cpu.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction 548system.cpu.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction 549system.cpu.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction 550system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction 551system.cpu.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction 552system.cpu.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction 553system.cpu.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction 554system.cpu.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction 555system.cpu.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction 556system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction 557system.cpu.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction 558system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction 559system.cpu.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction 560system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction 561system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction 562system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction 563system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction 564system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction 565system.cpu.op_class_0::SimdFloatMisc 109444 0.01% 69.53% # Class of committed instruction 566system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction 567system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction 568system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction 569system.cpu.op_class_0::MemRead 174118935 15.94% 85.47% # Class of committed instruction 570system.cpu.op_class_0::MemWrite 158660847 14.53% 100.00% # Class of committed instruction 571system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 572system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 573system.cpu.op_class_0::total 1092086880 # Class of committed instruction 574system.cpu.kern.inst.arm 0 # number of arm instructions executed 575system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed 576system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked 577system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped 578system.cpu.dcache.tags.replacements 10826762 # number of replacements 579system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use 580system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks. 581system.cpu.dcache.tags.sampled_refs 10827274 # Sample count of references to valid blocks. 582system.cpu.dcache.tags.avg_refs 29.813150 # Average number of references to valid blocks. 583system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. 584system.cpu.dcache.tags.occ_blocks::cpu.data 511.930071 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 587system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 590system.cpu.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 591system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 592system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 593system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses 594system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses 595system.cpu.dcache.ReadReq_hits::cpu.data 165131668 # number of ReadReq hits 596system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits 597system.cpu.dcache.WriteReq_hits::cpu.data 148654336 # number of WriteReq hits 598system.cpu.dcache.WriteReq_hits::total 148654336 # number of WriteReq hits 599system.cpu.dcache.SoftPFReq_hits::cpu.data 515490 # number of SoftPFReq hits 600system.cpu.dcache.SoftPFReq_hits::total 515490 # number of SoftPFReq hits 601system.cpu.dcache.WriteLineReq_hits::cpu.data 336587 # number of WriteLineReq hits 602system.cpu.dcache.WriteLineReq_hits::total 336587 # number of WriteLineReq hits 603system.cpu.dcache.LoadLockedReq_hits::cpu.data 3899601 # number of LoadLockedReq hits 604system.cpu.dcache.LoadLockedReq_hits::total 3899601 # number of LoadLockedReq hits 605system.cpu.dcache.StoreCondReq_hits::cpu.data 4208890 # number of StoreCondReq hits 606system.cpu.dcache.StoreCondReq_hits::total 4208890 # number of StoreCondReq hits
607system.cpu.dcache.demand_hits::cpu.data 313786004 # number of demand (read+write) hits 608system.cpu.dcache.demand_hits::total 313786004 # number of demand (read+write) hits 609system.cpu.dcache.overall_hits::cpu.data 314301494 # number of overall hits 610system.cpu.dcache.overall_hits::total 314301494 # number of overall hits	607system.cpu.dcache.demand_hits::cpu.data 314122591 # number of demand (read+write) hits 608system.cpu.dcache.demand_hits::total 314122591 # number of demand (read+write) hits 609system.cpu.dcache.overall_hits::cpu.data 314638081 # number of overall hits 610system.cpu.dcache.overall_hits::total 314638081 # number of overall hits
611system.cpu.dcache.ReadReq_misses::cpu.data 6423881 # number of ReadReq misses 612system.cpu.dcache.ReadReq_misses::total 6423881 # number of ReadReq misses 613system.cpu.dcache.WriteReq_misses::cpu.data 4177328 # number of WriteReq misses 614system.cpu.dcache.WriteReq_misses::total 4177328 # number of WriteReq misses 615system.cpu.dcache.SoftPFReq_misses::cpu.data 1420881 # number of SoftPFReq misses 616system.cpu.dcache.SoftPFReq_misses::total 1420881 # number of SoftPFReq misses 617system.cpu.dcache.WriteLineReq_misses::cpu.data 1240100 # number of WriteLineReq misses 618system.cpu.dcache.WriteLineReq_misses::total 1240100 # number of WriteLineReq misses 619system.cpu.dcache.LoadLockedReq_misses::cpu.data 311002 # number of LoadLockedReq misses 620system.cpu.dcache.LoadLockedReq_misses::total 311002 # number of LoadLockedReq misses 621system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 622system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses	611system.cpu.dcache.ReadReq_misses::cpu.data 6423881 # number of ReadReq misses 612system.cpu.dcache.ReadReq_misses::total 6423881 # number of ReadReq misses 613system.cpu.dcache.WriteReq_misses::cpu.data 4177328 # number of WriteReq misses 614system.cpu.dcache.WriteReq_misses::total 4177328 # number of WriteReq misses 615system.cpu.dcache.SoftPFReq_misses::cpu.data 1420881 # number of SoftPFReq misses 616system.cpu.dcache.SoftPFReq_misses::total 1420881 # number of SoftPFReq misses 617system.cpu.dcache.WriteLineReq_misses::cpu.data 1240100 # number of WriteLineReq misses 618system.cpu.dcache.WriteLineReq_misses::total 1240100 # number of WriteLineReq misses 619system.cpu.dcache.LoadLockedReq_misses::cpu.data 311002 # number of LoadLockedReq misses 620system.cpu.dcache.LoadLockedReq_misses::total 311002 # number of LoadLockedReq misses 621system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 622system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
623system.cpu.dcache.demand_misses::cpu.data 10601209 # number of demand (read+write) misses 624system.cpu.dcache.demand_misses::total 10601209 # number of demand (read+write) misses 625system.cpu.dcache.overall_misses::cpu.data 12022090 # number of overall misses 626system.cpu.dcache.overall_misses::total 12022090 # number of overall misses	623system.cpu.dcache.demand_misses::cpu.data 11841309 # number of demand (read+write) misses 624system.cpu.dcache.demand_misses::total 11841309 # number of demand (read+write) misses 625system.cpu.dcache.overall_misses::cpu.data 13262190 # number of overall misses 626system.cpu.dcache.overall_misses::total 13262190 # number of overall misses
627system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500 # number of ReadReq miss cycles 628system.cpu.dcache.ReadReq_miss_latency::total 119203222500 # number of ReadReq miss cycles 629system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500 # number of WriteReq miss cycles 630system.cpu.dcache.WriteReq_miss_latency::total 206322817500 # number of WriteReq miss cycles 631system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53471775500 # number of WriteLineReq miss cycles 632system.cpu.dcache.WriteLineReq_miss_latency::total 53471775500 # number of WriteLineReq miss cycles 633system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5200645500 # number of LoadLockedReq miss cycles 634system.cpu.dcache.LoadLockedReq_miss_latency::total 5200645500 # number of LoadLockedReq miss cycles 635system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles 636system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles	627system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500 # number of ReadReq miss cycles 628system.cpu.dcache.ReadReq_miss_latency::total 119203222500 # number of ReadReq miss cycles 629system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500 # number of WriteReq miss cycles 630system.cpu.dcache.WriteReq_miss_latency::total 206322817500 # number of WriteReq miss cycles 631system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53471775500 # number of WriteLineReq miss cycles 632system.cpu.dcache.WriteLineReq_miss_latency::total 53471775500 # number of WriteLineReq miss cycles 633system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5200645500 # number of LoadLockedReq miss cycles 634system.cpu.dcache.LoadLockedReq_miss_latency::total 5200645500 # number of LoadLockedReq miss cycles 635system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles 636system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
637system.cpu.dcache.demand_miss_latency::cpu.data 325526040000 # number of demand (read+write) miss cycles 638system.cpu.dcache.demand_miss_latency::total 325526040000 # number of demand (read+write) miss cycles 639system.cpu.dcache.overall_miss_latency::cpu.data 325526040000 # number of overall miss cycles 640system.cpu.dcache.overall_miss_latency::total 325526040000 # number of overall miss cycles	637system.cpu.dcache.demand_miss_latency::cpu.data 378997815500 # number of demand (read+write) miss cycles 638system.cpu.dcache.demand_miss_latency::total 378997815500 # number of demand (read+write) miss cycles 639system.cpu.dcache.overall_miss_latency::cpu.data 378997815500 # number of overall miss cycles 640system.cpu.dcache.overall_miss_latency::total 378997815500 # number of overall miss cycles
641system.cpu.dcache.ReadReq_accesses::cpu.data 171555549 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.ReadReq_accesses::total 171555549 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::cpu.data 152831664 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::total 152831664 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.SoftPFReq_accesses::cpu.data 1936371 # number of SoftPFReq accesses(hits+misses) 646system.cpu.dcache.SoftPFReq_accesses::total 1936371 # number of SoftPFReq accesses(hits+misses) 647system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576687 # number of WriteLineReq accesses(hits+misses) 648system.cpu.dcache.WriteLineReq_accesses::total 1576687 # number of WriteLineReq accesses(hits+misses) 649system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4210603 # number of LoadLockedReq accesses(hits+misses) 650system.cpu.dcache.LoadLockedReq_accesses::total 4210603 # number of LoadLockedReq accesses(hits+misses) 651system.cpu.dcache.StoreCondReq_accesses::cpu.data 4208892 # number of StoreCondReq accesses(hits+misses) 652system.cpu.dcache.StoreCondReq_accesses::total 4208892 # number of StoreCondReq accesses(hits+misses)	641system.cpu.dcache.ReadReq_accesses::cpu.data 171555549 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.ReadReq_accesses::total 171555549 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::cpu.data 152831664 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::total 152831664 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.SoftPFReq_accesses::cpu.data 1936371 # number of SoftPFReq accesses(hits+misses) 646system.cpu.dcache.SoftPFReq_accesses::total 1936371 # number of SoftPFReq accesses(hits+misses) 647system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576687 # number of WriteLineReq accesses(hits+misses) 648system.cpu.dcache.WriteLineReq_accesses::total 1576687 # number of WriteLineReq accesses(hits+misses) 649system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4210603 # number of LoadLockedReq accesses(hits+misses) 650system.cpu.dcache.LoadLockedReq_accesses::total 4210603 # number of LoadLockedReq accesses(hits+misses) 651system.cpu.dcache.StoreCondReq_accesses::cpu.data 4208892 # number of StoreCondReq accesses(hits+misses) 652system.cpu.dcache.StoreCondReq_accesses::total 4208892 # number of StoreCondReq accesses(hits+misses)
653system.cpu.dcache.demand_accesses::cpu.data 324387213 # number of demand (read+write) accesses 654system.cpu.dcache.demand_accesses::total 324387213 # number of demand (read+write) accesses 655system.cpu.dcache.overall_accesses::cpu.data 326323584 # number of overall (read+write) accesses 656system.cpu.dcache.overall_accesses::total 326323584 # number of overall (read+write) accesses	653system.cpu.dcache.demand_accesses::cpu.data 325963900 # number of demand (read+write) accesses 654system.cpu.dcache.demand_accesses::total 325963900 # number of demand (read+write) accesses 655system.cpu.dcache.overall_accesses::cpu.data 327900271 # number of overall (read+write) accesses 656system.cpu.dcache.overall_accesses::total 327900271 # number of overall (read+write) accesses
657system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037445 # miss rate for ReadReq accesses 658system.cpu.dcache.ReadReq_miss_rate::total 0.037445 # miss rate for ReadReq accesses 659system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027333 # miss rate for WriteReq accesses 660system.cpu.dcache.WriteReq_miss_rate::total 0.027333 # miss rate for WriteReq accesses 661system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733786 # miss rate for SoftPFReq accesses 662system.cpu.dcache.SoftPFReq_miss_rate::total 0.733786 # miss rate for SoftPFReq accesses 663system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786523 # miss rate for WriteLineReq accesses 664system.cpu.dcache.WriteLineReq_miss_rate::total 0.786523 # miss rate for WriteLineReq accesses 665system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073862 # miss rate for LoadLockedReq accesses 666system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073862 # miss rate for LoadLockedReq accesses 667system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 668system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses	657system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037445 # miss rate for ReadReq accesses 658system.cpu.dcache.ReadReq_miss_rate::total 0.037445 # miss rate for ReadReq accesses 659system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027333 # miss rate for WriteReq accesses 660system.cpu.dcache.WriteReq_miss_rate::total 0.027333 # miss rate for WriteReq accesses 661system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733786 # miss rate for SoftPFReq accesses 662system.cpu.dcache.SoftPFReq_miss_rate::total 0.733786 # miss rate for SoftPFReq accesses 663system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786523 # miss rate for WriteLineReq accesses 664system.cpu.dcache.WriteLineReq_miss_rate::total 0.786523 # miss rate for WriteLineReq accesses 665system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073862 # miss rate for LoadLockedReq accesses 666system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073862 # miss rate for LoadLockedReq accesses 667system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 668system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
669system.cpu.dcache.demand_miss_rate::cpu.data 0.032681 # miss rate for demand accesses 670system.cpu.dcache.demand_miss_rate::total 0.032681 # miss rate for demand accesses 671system.cpu.dcache.overall_miss_rate::cpu.data 0.036841 # miss rate for overall accesses 672system.cpu.dcache.overall_miss_rate::total 0.036841 # miss rate for overall accesses	669system.cpu.dcache.demand_miss_rate::cpu.data 0.036327 # miss rate for demand accesses 670system.cpu.dcache.demand_miss_rate::total 0.036327 # miss rate for demand accesses 671system.cpu.dcache.overall_miss_rate::cpu.data 0.040446 # miss rate for overall accesses 672system.cpu.dcache.overall_miss_rate::total 0.040446 # miss rate for overall accesses
673system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562 # average ReadReq miss latency 674system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562 # average ReadReq miss latency 675system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209 # average WriteReq miss latency 676system.cpu.dcache.WriteReq_avg_miss_latency::total 49391.098209 # average WriteReq miss latency 677system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43118.922264 # average WriteLineReq miss latency 678system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43118.922264 # average WriteLineReq miss latency 679system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259 # average LoadLockedReq miss latency 680system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259 # average LoadLockedReq miss latency 681system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency 682system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency	673system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562 # average ReadReq miss latency 674system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562 # average ReadReq miss latency 675system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209 # average WriteReq miss latency 676system.cpu.dcache.WriteReq_avg_miss_latency::total 49391.098209 # average WriteReq miss latency 677system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43118.922264 # average WriteLineReq miss latency 678system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43118.922264 # average WriteLineReq miss latency 679system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259 # average LoadLockedReq miss latency 680system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259 # average LoadLockedReq miss latency 681system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency 682system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
683system.cpu.dcache.demand_avg_miss_latency::cpu.data 30706.501494 # average overall miss latency 684system.cpu.dcache.demand_avg_miss_latency::total 30706.501494 # average overall miss latency 685system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.325157 # average overall miss latency 686system.cpu.dcache.overall_avg_miss_latency::total 27077.325157 # average overall miss latency	683system.cpu.dcache.demand_avg_miss_latency::cpu.data 32006.412087 # average overall miss latency 684system.cpu.dcache.demand_avg_miss_latency::total 32006.412087 # average overall miss latency 685system.cpu.dcache.overall_avg_miss_latency::cpu.data 28577.317585 # average overall miss latency 686system.cpu.dcache.overall_avg_miss_latency::total 28577.317585 # average overall miss latency
687system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 688system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 690system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 692system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	687system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 688system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 690system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 692system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
693system.cpu.dcache.fast_writes 0 # number of fast writes performed 694system.cpu.dcache.cache_copies 0 # number of cache copies performed
695system.cpu.dcache.writebacks::writebacks 8312311 # number of writebacks 696system.cpu.dcache.writebacks::total 8312311 # number of writebacks 697system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778551 # number of ReadReq MSHR hits 698system.cpu.dcache.ReadReq_mshr_hits::total 778551 # number of ReadReq MSHR hits 699system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841560 # number of WriteReq MSHR hits 700system.cpu.dcache.WriteReq_mshr_hits::total 1841560 # number of WriteReq MSHR hits 701system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 166 # number of WriteLineReq MSHR hits 702system.cpu.dcache.WriteLineReq_mshr_hits::total 166 # number of WriteLineReq MSHR hits 703system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69564 # number of LoadLockedReq MSHR hits 704system.cpu.dcache.LoadLockedReq_mshr_hits::total 69564 # number of LoadLockedReq MSHR hits	693system.cpu.dcache.writebacks::writebacks 8312311 # number of writebacks 694system.cpu.dcache.writebacks::total 8312311 # number of writebacks 695system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778551 # number of ReadReq MSHR hits 696system.cpu.dcache.ReadReq_mshr_hits::total 778551 # number of ReadReq MSHR hits 697system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841560 # number of WriteReq MSHR hits 698system.cpu.dcache.WriteReq_mshr_hits::total 1841560 # number of WriteReq MSHR hits 699system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 166 # number of WriteLineReq MSHR hits 700system.cpu.dcache.WriteLineReq_mshr_hits::total 166 # number of WriteLineReq MSHR hits 701system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69564 # number of LoadLockedReq MSHR hits 702system.cpu.dcache.LoadLockedReq_mshr_hits::total 69564 # number of LoadLockedReq MSHR hits
705system.cpu.dcache.demand_mshr_hits::cpu.data 2620111 # number of demand (read+write) MSHR hits 706system.cpu.dcache.demand_mshr_hits::total 2620111 # number of demand (read+write) MSHR hits 707system.cpu.dcache.overall_mshr_hits::cpu.data 2620111 # number of overall MSHR hits 708system.cpu.dcache.overall_mshr_hits::total 2620111 # number of overall MSHR hits	703system.cpu.dcache.demand_mshr_hits::cpu.data 2620277 # number of demand (read+write) MSHR hits 704system.cpu.dcache.demand_mshr_hits::total 2620277 # number of demand (read+write) MSHR hits 705system.cpu.dcache.overall_mshr_hits::cpu.data 2620277 # number of overall MSHR hits 706system.cpu.dcache.overall_mshr_hits::total 2620277 # number of overall MSHR hits
709system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5645330 # number of ReadReq MSHR misses 710system.cpu.dcache.ReadReq_mshr_misses::total 5645330 # number of ReadReq MSHR misses 711system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2335768 # number of WriteReq MSHR misses 712system.cpu.dcache.WriteReq_mshr_misses::total 2335768 # number of WriteReq MSHR misses 713system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1413353 # number of SoftPFReq MSHR misses 714system.cpu.dcache.SoftPFReq_mshr_misses::total 1413353 # number of SoftPFReq MSHR misses 715system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1239934 # number of WriteLineReq MSHR misses 716system.cpu.dcache.WriteLineReq_mshr_misses::total 1239934 # number of WriteLineReq MSHR misses 717system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241438 # number of LoadLockedReq MSHR misses 718system.cpu.dcache.LoadLockedReq_mshr_misses::total 241438 # number of LoadLockedReq MSHR misses 719system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 720system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses	707system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5645330 # number of ReadReq MSHR misses 708system.cpu.dcache.ReadReq_mshr_misses::total 5645330 # number of ReadReq MSHR misses 709system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2335768 # number of WriteReq MSHR misses 710system.cpu.dcache.WriteReq_mshr_misses::total 2335768 # number of WriteReq MSHR misses 711system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1413353 # number of SoftPFReq MSHR misses 712system.cpu.dcache.SoftPFReq_mshr_misses::total 1413353 # number of SoftPFReq MSHR misses 713system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1239934 # number of WriteLineReq MSHR misses 714system.cpu.dcache.WriteLineReq_mshr_misses::total 1239934 # number of WriteLineReq MSHR misses 715system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241438 # number of LoadLockedReq MSHR misses 716system.cpu.dcache.LoadLockedReq_mshr_misses::total 241438 # number of LoadLockedReq MSHR misses 717system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 718system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
721system.cpu.dcache.demand_mshr_misses::cpu.data 7981098 # number of demand (read+write) MSHR misses 722system.cpu.dcache.demand_mshr_misses::total 7981098 # number of demand (read+write) MSHR misses 723system.cpu.dcache.overall_mshr_misses::cpu.data 9394451 # number of overall MSHR misses 724system.cpu.dcache.overall_mshr_misses::total 9394451 # number of overall MSHR misses	719system.cpu.dcache.demand_mshr_misses::cpu.data 9221032 # number of demand (read+write) MSHR misses 720system.cpu.dcache.demand_mshr_misses::total 9221032 # number of demand (read+write) MSHR misses 721system.cpu.dcache.overall_mshr_misses::cpu.data 10634385 # number of overall MSHR misses 722system.cpu.dcache.overall_mshr_misses::total 10634385 # number of overall MSHR misses
725system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 726system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 727system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 728system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 729system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 730system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 731system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97557432500 # number of ReadReq MSHR miss cycles 732system.cpu.dcache.ReadReq_mshr_miss_latency::total 97557432500 # number of ReadReq MSHR miss cycles 733system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109336281500 # number of WriteReq MSHR miss cycles 734system.cpu.dcache.WriteReq_mshr_miss_latency::total 109336281500 # number of WriteReq MSHR miss cycles 735system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26901290500 # number of SoftPFReq MSHR miss cycles 736system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26901290500 # number of SoftPFReq MSHR miss cycles 737system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52221764000 # number of WriteLineReq MSHR miss cycles 738system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52221764000 # number of WriteLineReq MSHR miss cycles 739system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3529658500 # number of LoadLockedReq MSHR miss cycles 740system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3529658500 # number of LoadLockedReq MSHR miss cycles 741system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles 742system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles	723system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 724system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 725system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 726system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 727system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 728system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 729system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97557432500 # number of ReadReq MSHR miss cycles 730system.cpu.dcache.ReadReq_mshr_miss_latency::total 97557432500 # number of ReadReq MSHR miss cycles 731system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109336281500 # number of WriteReq MSHR miss cycles 732system.cpu.dcache.WriteReq_mshr_miss_latency::total 109336281500 # number of WriteReq MSHR miss cycles 733system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26901290500 # number of SoftPFReq MSHR miss cycles 734system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26901290500 # number of SoftPFReq MSHR miss cycles 735system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52221764000 # number of WriteLineReq MSHR miss cycles 736system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52221764000 # number of WriteLineReq MSHR miss cycles 737system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3529658500 # number of LoadLockedReq MSHR miss cycles 738system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3529658500 # number of LoadLockedReq MSHR miss cycles 739system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles 740system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles
743system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206893714000 # number of demand (read+write) MSHR miss cycles 744system.cpu.dcache.demand_mshr_miss_latency::total 206893714000 # number of demand (read+write) MSHR miss cycles 745system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233795004500 # number of overall MSHR miss cycles 746system.cpu.dcache.overall_mshr_miss_latency::total 233795004500 # number of overall MSHR miss cycles	741system.cpu.dcache.demand_mshr_miss_latency::cpu.data 259115478000 # number of demand (read+write) MSHR miss cycles 742system.cpu.dcache.demand_mshr_miss_latency::total 259115478000 # number of demand (read+write) MSHR miss cycles 743system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286016768500 # number of overall MSHR miss cycles 744system.cpu.dcache.overall_mshr_miss_latency::total 286016768500 # number of overall MSHR miss cycles
747system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197628500 # number of ReadReq MSHR uncacheable cycles 748system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197628500 # number of ReadReq MSHR uncacheable cycles	745system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197628500 # number of ReadReq MSHR uncacheable cycles 746system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197628500 # number of ReadReq MSHR uncacheable cycles
749system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6191865500 # number of WriteReq MSHR uncacheable cycles 750system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6191865500 # number of WriteReq MSHR uncacheable cycles 751system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12389494000 # number of overall MSHR uncacheable cycles 752system.cpu.dcache.overall_mshr_uncacheable_latency::total 12389494000 # number of overall MSHR uncacheable cycles	747system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197628500 # number of overall MSHR uncacheable cycles 748system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197628500 # number of overall MSHR uncacheable cycles
753system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032907 # mshr miss rate for ReadReq accesses 754system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032907 # mshr miss rate for ReadReq accesses 755system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015283 # mshr miss rate for WriteReq accesses 756system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015283 # mshr miss rate for WriteReq accesses 757system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729898 # mshr miss rate for SoftPFReq accesses 758system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729898 # mshr miss rate for SoftPFReq accesses 759system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786417 # mshr miss rate for WriteLineReq accesses 760system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786417 # mshr miss rate for WriteLineReq accesses 761system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057340 # mshr miss rate for LoadLockedReq accesses 762system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057340 # mshr miss rate for LoadLockedReq accesses 763system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 764system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses	749system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032907 # mshr miss rate for ReadReq accesses 750system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032907 # mshr miss rate for ReadReq accesses 751system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015283 # mshr miss rate for WriteReq accesses 752system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015283 # mshr miss rate for WriteReq accesses 753system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729898 # mshr miss rate for SoftPFReq accesses 754system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729898 # mshr miss rate for SoftPFReq accesses 755system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786417 # mshr miss rate for WriteLineReq accesses 756system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786417 # mshr miss rate for WriteLineReq accesses 757system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057340 # mshr miss rate for LoadLockedReq accesses 758system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057340 # mshr miss rate for LoadLockedReq accesses 759system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 760system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
765system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024604 # mshr miss rate for demand accesses 766system.cpu.dcache.demand_mshr_miss_rate::total 0.024604 # mshr miss rate for demand accesses 767system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028789 # mshr miss rate for overall accesses 768system.cpu.dcache.overall_mshr_miss_rate::total 0.028789 # mshr miss rate for overall accesses	761system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028289 # mshr miss rate for demand accesses 762system.cpu.dcache.demand_mshr_miss_rate::total 0.028289 # mshr miss rate for demand accesses 763system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032432 # mshr miss rate for overall accesses 764system.cpu.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses
769system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871 # average ReadReq mshr miss latency 770system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871 # average ReadReq mshr miss latency 771system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921 # average WriteReq mshr miss latency 772system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46809.563921 # average WriteReq mshr miss latency 773system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19033.667102 # average SoftPFReq mshr miss latency 774system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19033.667102 # average SoftPFReq mshr miss latency 775system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42116.567495 # average WriteLineReq mshr miss latency 776system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42116.567495 # average WriteLineReq mshr miss latency 777system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346 # average LoadLockedReq mshr miss latency 778system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346 # average LoadLockedReq mshr miss latency 779system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency 780system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency	765system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871 # average ReadReq mshr miss latency 766system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871 # average ReadReq mshr miss latency 767system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921 # average WriteReq mshr miss latency 768system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46809.563921 # average WriteReq mshr miss latency 769system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19033.667102 # average SoftPFReq mshr miss latency 770system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19033.667102 # average SoftPFReq mshr miss latency 771system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42116.567495 # average WriteLineReq mshr miss latency 772system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42116.567495 # average WriteLineReq mshr miss latency 773system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346 # average LoadLockedReq mshr miss latency 774system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346 # average LoadLockedReq mshr miss latency 775system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency 776system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency
781system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25922.963733 # average overall mshr miss latency 782system.cpu.dcache.demand_avg_mshr_miss_latency::total 25922.963733 # average overall mshr miss latency 783system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24886.499967 # average overall mshr miss latency 784system.cpu.dcache.overall_avg_mshr_miss_latency::total 24886.499967 # average overall mshr miss latency	777system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716 # average overall mshr miss latency 778system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716 # average overall mshr miss latency 779system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661 # average overall mshr miss latency 780system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661 # average overall mshr miss latency
785system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency 786system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency	781system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency 782system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency
787system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183702.174687 # average WriteReq mshr uncacheable latency 788system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183702.174687 # average WriteReq mshr uncacheable latency 789system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 183812.204205 # average overall mshr uncacheable latency 790system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 183812.204205 # average overall mshr uncacheable latency 791system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate	783system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency 784system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency
792system.cpu.icache.tags.replacements 24339101 # number of replacements 793system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use 794system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. 795system.cpu.icache.tags.sampled_refs 24339613 # Sample count of references to valid blocks. 796system.cpu.icache.tags.avg_refs 17.178953 # Average number of references to valid blocks. 797system.cpu.icache.tags.warmup_cycle 32773385500 # Cycle when the warmup percentage was hit. 798system.cpu.icache.tags.occ_blocks::cpu.inst 511.885333 # Average occupied blocks per requestor 799system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy 800system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy 801system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 802system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 803system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 804system.cpu.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id 805system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 806system.cpu.icache.tags.tag_accesses 466808304 # Number of tag accesses 807system.cpu.icache.tags.data_accesses 466808304 # Number of data accesses 808system.cpu.icache.ReadReq_hits::cpu.inst 418129059 # number of ReadReq hits 809system.cpu.icache.ReadReq_hits::total 418129059 # number of ReadReq hits 810system.cpu.icache.demand_hits::cpu.inst 418129059 # number of demand (read+write) hits 811system.cpu.icache.demand_hits::total 418129059 # number of demand (read+write) hits 812system.cpu.icache.overall_hits::cpu.inst 418129059 # number of overall hits 813system.cpu.icache.overall_hits::total 418129059 # number of overall hits 814system.cpu.icache.ReadReq_misses::cpu.inst 24339623 # number of ReadReq misses 815system.cpu.icache.ReadReq_misses::total 24339623 # number of ReadReq misses 816system.cpu.icache.demand_misses::cpu.inst 24339623 # number of demand (read+write) misses 817system.cpu.icache.demand_misses::total 24339623 # number of demand (read+write) misses 818system.cpu.icache.overall_misses::cpu.inst 24339623 # number of overall misses 819system.cpu.icache.overall_misses::total 24339623 # number of overall misses 820system.cpu.icache.ReadReq_miss_latency::cpu.inst 329768536500 # number of ReadReq miss cycles 821system.cpu.icache.ReadReq_miss_latency::total 329768536500 # number of ReadReq miss cycles 822system.cpu.icache.demand_miss_latency::cpu.inst 329768536500 # number of demand (read+write) miss cycles 823system.cpu.icache.demand_miss_latency::total 329768536500 # number of demand (read+write) miss cycles 824system.cpu.icache.overall_miss_latency::cpu.inst 329768536500 # number of overall miss cycles 825system.cpu.icache.overall_miss_latency::total 329768536500 # number of overall miss cycles 826system.cpu.icache.ReadReq_accesses::cpu.inst 442468682 # number of ReadReq accesses(hits+misses) 827system.cpu.icache.ReadReq_accesses::total 442468682 # number of ReadReq accesses(hits+misses) 828system.cpu.icache.demand_accesses::cpu.inst 442468682 # number of demand (read+write) accesses 829system.cpu.icache.demand_accesses::total 442468682 # number of demand (read+write) accesses 830system.cpu.icache.overall_accesses::cpu.inst 442468682 # number of overall (read+write) accesses 831system.cpu.icache.overall_accesses::total 442468682 # number of overall (read+write) accesses 832system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055009 # miss rate for ReadReq accesses 833system.cpu.icache.ReadReq_miss_rate::total 0.055009 # miss rate for ReadReq accesses 834system.cpu.icache.demand_miss_rate::cpu.inst 0.055009 # miss rate for demand accesses 835system.cpu.icache.demand_miss_rate::total 0.055009 # miss rate for demand accesses 836system.cpu.icache.overall_miss_rate::cpu.inst 0.055009 # miss rate for overall accesses 837system.cpu.icache.overall_miss_rate::total 0.055009 # miss rate for overall accesses 838system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.629595 # average ReadReq miss latency 839system.cpu.icache.ReadReq_avg_miss_latency::total 13548.629595 # average ReadReq miss latency 840system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.629595 # average overall miss latency 841system.cpu.icache.demand_avg_miss_latency::total 13548.629595 # average overall miss latency 842system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.629595 # average overall miss latency 843system.cpu.icache.overall_avg_miss_latency::total 13548.629595 # average overall miss latency 844system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 845system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 846system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 847system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 848system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 849system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	785system.cpu.icache.tags.replacements 24339101 # number of replacements 786system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use 787system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. 788system.cpu.icache.tags.sampled_refs 24339613 # Sample count of references to valid blocks. 789system.cpu.icache.tags.avg_refs 17.178953 # Average number of references to valid blocks. 790system.cpu.icache.tags.warmup_cycle 32773385500 # Cycle when the warmup percentage was hit. 791system.cpu.icache.tags.occ_blocks::cpu.inst 511.885333 # Average occupied blocks per requestor 792system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy 793system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy 794system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 795system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 796system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 797system.cpu.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id 798system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 799system.cpu.icache.tags.tag_accesses 466808304 # Number of tag accesses 800system.cpu.icache.tags.data_accesses 466808304 # Number of data accesses 801system.cpu.icache.ReadReq_hits::cpu.inst 418129059 # number of ReadReq hits 802system.cpu.icache.ReadReq_hits::total 418129059 # number of ReadReq hits 803system.cpu.icache.demand_hits::cpu.inst 418129059 # number of demand (read+write) hits 804system.cpu.icache.demand_hits::total 418129059 # number of demand (read+write) hits 805system.cpu.icache.overall_hits::cpu.inst 418129059 # number of overall hits 806system.cpu.icache.overall_hits::total 418129059 # number of overall hits 807system.cpu.icache.ReadReq_misses::cpu.inst 24339623 # number of ReadReq misses 808system.cpu.icache.ReadReq_misses::total 24339623 # number of ReadReq misses 809system.cpu.icache.demand_misses::cpu.inst 24339623 # number of demand (read+write) misses 810system.cpu.icache.demand_misses::total 24339623 # number of demand (read+write) misses 811system.cpu.icache.overall_misses::cpu.inst 24339623 # number of overall misses 812system.cpu.icache.overall_misses::total 24339623 # number of overall misses 813system.cpu.icache.ReadReq_miss_latency::cpu.inst 329768536500 # number of ReadReq miss cycles 814system.cpu.icache.ReadReq_miss_latency::total 329768536500 # number of ReadReq miss cycles 815system.cpu.icache.demand_miss_latency::cpu.inst 329768536500 # number of demand (read+write) miss cycles 816system.cpu.icache.demand_miss_latency::total 329768536500 # number of demand (read+write) miss cycles 817system.cpu.icache.overall_miss_latency::cpu.inst 329768536500 # number of overall miss cycles 818system.cpu.icache.overall_miss_latency::total 329768536500 # number of overall miss cycles 819system.cpu.icache.ReadReq_accesses::cpu.inst 442468682 # number of ReadReq accesses(hits+misses) 820system.cpu.icache.ReadReq_accesses::total 442468682 # number of ReadReq accesses(hits+misses) 821system.cpu.icache.demand_accesses::cpu.inst 442468682 # number of demand (read+write) accesses 822system.cpu.icache.demand_accesses::total 442468682 # number of demand (read+write) accesses 823system.cpu.icache.overall_accesses::cpu.inst 442468682 # number of overall (read+write) accesses 824system.cpu.icache.overall_accesses::total 442468682 # number of overall (read+write) accesses 825system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055009 # miss rate for ReadReq accesses 826system.cpu.icache.ReadReq_miss_rate::total 0.055009 # miss rate for ReadReq accesses 827system.cpu.icache.demand_miss_rate::cpu.inst 0.055009 # miss rate for demand accesses 828system.cpu.icache.demand_miss_rate::total 0.055009 # miss rate for demand accesses 829system.cpu.icache.overall_miss_rate::cpu.inst 0.055009 # miss rate for overall accesses 830system.cpu.icache.overall_miss_rate::total 0.055009 # miss rate for overall accesses 831system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.629595 # average ReadReq miss latency 832system.cpu.icache.ReadReq_avg_miss_latency::total 13548.629595 # average ReadReq miss latency 833system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.629595 # average overall miss latency 834system.cpu.icache.demand_avg_miss_latency::total 13548.629595 # average overall miss latency 835system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.629595 # average overall miss latency 836system.cpu.icache.overall_avg_miss_latency::total 13548.629595 # average overall miss latency 837system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 838system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 839system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 840system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 841system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 842system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
850system.cpu.icache.fast_writes 0 # number of fast writes performed 851system.cpu.icache.cache_copies 0 # number of cache copies performed
852system.cpu.icache.writebacks::writebacks 24339101 # number of writebacks 853system.cpu.icache.writebacks::total 24339101 # number of writebacks 854system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24339623 # number of ReadReq MSHR misses 855system.cpu.icache.ReadReq_mshr_misses::total 24339623 # number of ReadReq MSHR misses 856system.cpu.icache.demand_mshr_misses::cpu.inst 24339623 # number of demand (read+write) MSHR misses 857system.cpu.icache.demand_mshr_misses::total 24339623 # number of demand (read+write) MSHR misses 858system.cpu.icache.overall_mshr_misses::cpu.inst 24339623 # number of overall MSHR misses 859system.cpu.icache.overall_mshr_misses::total 24339623 # number of overall MSHR misses 860system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 861system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 862system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 863system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 864system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305428914500 # number of ReadReq MSHR miss cycles 865system.cpu.icache.ReadReq_mshr_miss_latency::total 305428914500 # number of ReadReq MSHR miss cycles 866system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305428914500 # number of demand (read+write) MSHR miss cycles 867system.cpu.icache.demand_mshr_miss_latency::total 305428914500 # number of demand (read+write) MSHR miss cycles 868system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305428914500 # number of overall MSHR miss cycles 869system.cpu.icache.overall_mshr_miss_latency::total 305428914500 # number of overall MSHR miss cycles 870system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles 871system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles 872system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles 873system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles 874system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for ReadReq accesses 875system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055009 # mshr miss rate for ReadReq accesses 876system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for demand accesses 877system.cpu.icache.demand_mshr_miss_rate::total 0.055009 # mshr miss rate for demand accesses 878system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for overall accesses 879system.cpu.icache.overall_mshr_miss_rate::total 0.055009 # mshr miss rate for overall accesses 880system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12548.629636 # average ReadReq mshr miss latency 881system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12548.629636 # average ReadReq mshr miss latency 882system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 883system.cpu.icache.demand_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 884system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 885system.cpu.icache.overall_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 886system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 887system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 888system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 889system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency	843system.cpu.icache.writebacks::writebacks 24339101 # number of writebacks 844system.cpu.icache.writebacks::total 24339101 # number of writebacks 845system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24339623 # number of ReadReq MSHR misses 846system.cpu.icache.ReadReq_mshr_misses::total 24339623 # number of ReadReq MSHR misses 847system.cpu.icache.demand_mshr_misses::cpu.inst 24339623 # number of demand (read+write) MSHR misses 848system.cpu.icache.demand_mshr_misses::total 24339623 # number of demand (read+write) MSHR misses 849system.cpu.icache.overall_mshr_misses::cpu.inst 24339623 # number of overall MSHR misses 850system.cpu.icache.overall_mshr_misses::total 24339623 # number of overall MSHR misses 851system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 852system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 853system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 854system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 855system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305428914500 # number of ReadReq MSHR miss cycles 856system.cpu.icache.ReadReq_mshr_miss_latency::total 305428914500 # number of ReadReq MSHR miss cycles 857system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305428914500 # number of demand (read+write) MSHR miss cycles 858system.cpu.icache.demand_mshr_miss_latency::total 305428914500 # number of demand (read+write) MSHR miss cycles 859system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305428914500 # number of overall MSHR miss cycles 860system.cpu.icache.overall_mshr_miss_latency::total 305428914500 # number of overall MSHR miss cycles 861system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles 862system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles 863system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles 864system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles 865system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for ReadReq accesses 866system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055009 # mshr miss rate for ReadReq accesses 867system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for demand accesses 868system.cpu.icache.demand_mshr_miss_rate::total 0.055009 # mshr miss rate for demand accesses 869system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for overall accesses 870system.cpu.icache.overall_mshr_miss_rate::total 0.055009 # mshr miss rate for overall accesses 871system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12548.629636 # average ReadReq mshr miss latency 872system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12548.629636 # average ReadReq mshr miss latency 873system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 874system.cpu.icache.demand_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 875system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency 876system.cpu.icache.overall_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency 877system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 878system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 879system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 880system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency
890system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
891system.cpu.l2cache.tags.replacements 1529682 # number of replacements 892system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use 893system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks. 894system.cpu.l2cache.tags.sampled_refs 1592715 # Sample count of references to valid blocks. 895system.cpu.l2cache.tags.avg_refs 41.651953 # Average number of references to valid blocks. 896system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit. 897system.cpu.l2cache.tags.occ_blocks::writebacks 36843.538434 # Average occupied blocks per requestor 898system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 325.022996 # Average occupied blocks per requestor 899system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 386.025396 # Average occupied blocks per requestor 900system.cpu.l2cache.tags.occ_blocks::cpu.inst 8031.083741 # Average occupied blocks per requestor 901system.cpu.l2cache.tags.occ_blocks::cpu.data 19745.157287 # Average occupied blocks per requestor 902system.cpu.l2cache.tags.occ_percent::writebacks 0.562188 # Average percentage of cache occupancy 903system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004959 # Average percentage of cache occupancy 904system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005890 # Average percentage of cache occupancy 905system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122545 # Average percentage of cache occupancy 906system.cpu.l2cache.tags.occ_percent::cpu.data 0.301287 # Average percentage of cache occupancy 907system.cpu.l2cache.tags.occ_percent::total 0.996869 # Average percentage of cache occupancy 908system.cpu.l2cache.tags.occ_task_id_blocks::1023 238 # Occupied blocks per task id 909system.cpu.l2cache.tags.occ_task_id_blocks::1024 62795 # Occupied blocks per task id 910system.cpu.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 911system.cpu.l2cache.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id 912system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 913system.cpu.l2cache.tags.age_task_id_blocks_1024::1 461 # Occupied blocks per task id 914system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2479 # Occupied blocks per task id 915system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5541 # Occupied blocks per task id 916system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54260 # Occupied blocks per task id 917system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003632 # Percentage of cache occupancy per task id 918system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958176 # Percentage of cache occupancy per task id 919system.cpu.l2cache.tags.tag_accesses 577322417 # Number of tag accesses 920system.cpu.l2cache.tags.data_accesses 577322417 # Number of data accesses 921system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 919591 # number of ReadReq hits 922system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 277608 # number of ReadReq hits 923system.cpu.l2cache.ReadReq_hits::total 1197199 # number of ReadReq hits 924system.cpu.l2cache.WritebackDirty_hits::writebacks 8312311 # number of WritebackDirty hits 925system.cpu.l2cache.WritebackDirty_hits::total 8312311 # number of WritebackDirty hits 926system.cpu.l2cache.WritebackClean_hits::writebacks 24335620 # number of WritebackClean hits 927system.cpu.l2cache.WritebackClean_hits::total 24335620 # number of WritebackClean hits 928system.cpu.l2cache.UpgradeReq_hits::cpu.data 10528 # number of UpgradeReq hits 929system.cpu.l2cache.UpgradeReq_hits::total 10528 # number of UpgradeReq hits 930system.cpu.l2cache.ReadExReq_hits::cpu.data 1643656 # number of ReadExReq hits 931system.cpu.l2cache.ReadExReq_hits::total 1643656 # number of ReadExReq hits 932system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24232057 # number of ReadCleanReq hits 933system.cpu.l2cache.ReadCleanReq_hits::total 24232057 # number of ReadCleanReq hits 934system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6978048 # number of ReadSharedReq hits 935system.cpu.l2cache.ReadSharedReq_hits::total 6978048 # number of ReadSharedReq hits 936system.cpu.l2cache.InvalidateReq_hits::cpu.data 702797 # number of InvalidateReq hits 937system.cpu.l2cache.InvalidateReq_hits::total 702797 # number of InvalidateReq hits 938system.cpu.l2cache.demand_hits::cpu.dtb.walker 919591 # number of demand (read+write) hits 939system.cpu.l2cache.demand_hits::cpu.itb.walker 277608 # number of demand (read+write) hits 940system.cpu.l2cache.demand_hits::cpu.inst 24232057 # number of demand (read+write) hits 941system.cpu.l2cache.demand_hits::cpu.data 8621704 # number of demand (read+write) hits 942system.cpu.l2cache.demand_hits::total 34050960 # number of demand (read+write) hits 943system.cpu.l2cache.overall_hits::cpu.dtb.walker 919591 # number of overall hits 944system.cpu.l2cache.overall_hits::cpu.itb.walker 277608 # number of overall hits 945system.cpu.l2cache.overall_hits::cpu.inst 24232057 # number of overall hits 946system.cpu.l2cache.overall_hits::cpu.data 8621704 # number of overall hits 947system.cpu.l2cache.overall_hits::total 34050960 # number of overall hits 948system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5915 # number of ReadReq misses 949system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4899 # number of ReadReq misses 950system.cpu.l2cache.ReadReq_misses::total 10814 # number of ReadReq misses 951system.cpu.l2cache.UpgradeReq_misses::cpu.data 37973 # number of UpgradeReq misses 952system.cpu.l2cache.UpgradeReq_misses::total 37973 # number of UpgradeReq misses 953system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 954system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 955system.cpu.l2cache.ReadExReq_misses::cpu.data 643878 # number of ReadExReq misses 956system.cpu.l2cache.ReadExReq_misses::total 643878 # number of ReadExReq misses 957system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107562 # number of ReadCleanReq misses 958system.cpu.l2cache.ReadCleanReq_misses::total 107562 # number of ReadCleanReq misses 959system.cpu.l2cache.ReadSharedReq_misses::cpu.data 321806 # number of ReadSharedReq misses 960system.cpu.l2cache.ReadSharedReq_misses::total 321806 # number of ReadSharedReq misses 961system.cpu.l2cache.InvalidateReq_misses::cpu.data 537137 # number of InvalidateReq misses 962system.cpu.l2cache.InvalidateReq_misses::total 537137 # number of InvalidateReq misses 963system.cpu.l2cache.demand_misses::cpu.dtb.walker 5915 # number of demand (read+write) misses 964system.cpu.l2cache.demand_misses::cpu.itb.walker 4899 # number of demand (read+write) misses 965system.cpu.l2cache.demand_misses::cpu.inst 107562 # number of demand (read+write) misses 966system.cpu.l2cache.demand_misses::cpu.data 965684 # number of demand (read+write) misses 967system.cpu.l2cache.demand_misses::total 1084060 # number of demand (read+write) misses 968system.cpu.l2cache.overall_misses::cpu.dtb.walker 5915 # number of overall misses 969system.cpu.l2cache.overall_misses::cpu.itb.walker 4899 # number of overall misses 970system.cpu.l2cache.overall_misses::cpu.inst 107562 # number of overall misses 971system.cpu.l2cache.overall_misses::cpu.data 965684 # number of overall misses 972system.cpu.l2cache.overall_misses::total 1084060 # number of overall misses 973system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 811806000 # number of ReadReq miss cycles 974system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 672654000 # number of ReadReq miss cycles 975system.cpu.l2cache.ReadReq_miss_latency::total 1484460000 # number of ReadReq miss cycles 976system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1453703500 # number of UpgradeReq miss cycles 977system.cpu.l2cache.UpgradeReq_miss_latency::total 1453703500 # number of UpgradeReq miss cycles 978system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles 979system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles 980system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85473673000 # number of ReadExReq miss cycles 981system.cpu.l2cache.ReadExReq_miss_latency::total 85473673000 # number of ReadExReq miss cycles 982system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14248124000 # number of ReadCleanReq miss cycles 983system.cpu.l2cache.ReadCleanReq_miss_latency::total 14248124000 # number of ReadCleanReq miss cycles 984system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43454810500 # number of ReadSharedReq miss cycles 985system.cpu.l2cache.ReadSharedReq_miss_latency::total 43454810500 # number of ReadSharedReq miss cycles 986system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 9911500 # number of InvalidateReq miss cycles 987system.cpu.l2cache.InvalidateReq_miss_latency::total 9911500 # number of InvalidateReq miss cycles 988system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 811806000 # number of demand (read+write) miss cycles 989system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 672654000 # number of demand (read+write) miss cycles 990system.cpu.l2cache.demand_miss_latency::cpu.inst 14248124000 # number of demand (read+write) miss cycles 991system.cpu.l2cache.demand_miss_latency::cpu.data 128928483500 # number of demand (read+write) miss cycles 992system.cpu.l2cache.demand_miss_latency::total 144661067500 # number of demand (read+write) miss cycles 993system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 811806000 # number of overall miss cycles 994system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 672654000 # number of overall miss cycles 995system.cpu.l2cache.overall_miss_latency::cpu.inst 14248124000 # number of overall miss cycles 996system.cpu.l2cache.overall_miss_latency::cpu.data 128928483500 # number of overall miss cycles 997system.cpu.l2cache.overall_miss_latency::total 144661067500 # number of overall miss cycles 998system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 925506 # number of ReadReq accesses(hits+misses) 999system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 282507 # number of ReadReq accesses(hits+misses) 1000system.cpu.l2cache.ReadReq_accesses::total 1208013 # number of ReadReq accesses(hits+misses) 1001system.cpu.l2cache.WritebackDirty_accesses::writebacks 8312311 # number of WritebackDirty accesses(hits+misses) 1002system.cpu.l2cache.WritebackDirty_accesses::total 8312311 # number of WritebackDirty accesses(hits+misses) 1003system.cpu.l2cache.WritebackClean_accesses::writebacks 24335620 # number of WritebackClean accesses(hits+misses) 1004system.cpu.l2cache.WritebackClean_accesses::total 24335620 # number of WritebackClean accesses(hits+misses) 1005system.cpu.l2cache.UpgradeReq_accesses::cpu.data 48501 # number of UpgradeReq accesses(hits+misses) 1006system.cpu.l2cache.UpgradeReq_accesses::total 48501 # number of UpgradeReq accesses(hits+misses) 1007system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1008system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 1009system.cpu.l2cache.ReadExReq_accesses::cpu.data 2287534 # number of ReadExReq accesses(hits+misses) 1010system.cpu.l2cache.ReadExReq_accesses::total 2287534 # number of ReadExReq accesses(hits+misses) 1011system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24339619 # number of ReadCleanReq accesses(hits+misses) 1012system.cpu.l2cache.ReadCleanReq_accesses::total 24339619 # number of ReadCleanReq accesses(hits+misses) 1013system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7299854 # number of ReadSharedReq accesses(hits+misses) 1014system.cpu.l2cache.ReadSharedReq_accesses::total 7299854 # number of ReadSharedReq accesses(hits+misses) 1015system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1239934 # number of InvalidateReq accesses(hits+misses) 1016system.cpu.l2cache.InvalidateReq_accesses::total 1239934 # number of InvalidateReq accesses(hits+misses) 1017system.cpu.l2cache.demand_accesses::cpu.dtb.walker 925506 # number of demand (read+write) accesses 1018system.cpu.l2cache.demand_accesses::cpu.itb.walker 282507 # number of demand (read+write) accesses 1019system.cpu.l2cache.demand_accesses::cpu.inst 24339619 # number of demand (read+write) accesses 1020system.cpu.l2cache.demand_accesses::cpu.data 9587388 # number of demand (read+write) accesses 1021system.cpu.l2cache.demand_accesses::total 35135020 # number of demand (read+write) accesses 1022system.cpu.l2cache.overall_accesses::cpu.dtb.walker 925506 # number of overall (read+write) accesses 1023system.cpu.l2cache.overall_accesses::cpu.itb.walker 282507 # number of overall (read+write) accesses 1024system.cpu.l2cache.overall_accesses::cpu.inst 24339619 # number of overall (read+write) accesses 1025system.cpu.l2cache.overall_accesses::cpu.data 9587388 # number of overall (read+write) accesses 1026system.cpu.l2cache.overall_accesses::total 35135020 # number of overall (read+write) accesses 1027system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006391 # miss rate for ReadReq accesses 1028system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.017341 # miss rate for ReadReq accesses 1029system.cpu.l2cache.ReadReq_miss_rate::total 0.008952 # miss rate for ReadReq accesses 1030system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782932 # miss rate for UpgradeReq accesses 1031system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782932 # miss rate for UpgradeReq accesses 1032system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1033system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1034system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.281473 # miss rate for ReadExReq accesses 1035system.cpu.l2cache.ReadExReq_miss_rate::total 0.281473 # miss rate for ReadExReq accesses 1036system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004419 # miss rate for ReadCleanReq accesses 1037system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004419 # miss rate for ReadCleanReq accesses 1038system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044084 # miss rate for ReadSharedReq accesses 1039system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044084 # miss rate for ReadSharedReq accesses 1040system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.433198 # miss rate for InvalidateReq accesses 1041system.cpu.l2cache.InvalidateReq_miss_rate::total 0.433198 # miss rate for InvalidateReq accesses 1042system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006391 # miss rate for demand accesses 1043system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017341 # miss rate for demand accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004419 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::cpu.data 0.100724 # miss rate for demand accesses 1046system.cpu.l2cache.demand_miss_rate::total 0.030854 # miss rate for demand accesses 1047system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006391 # miss rate for overall accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017341 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004419 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::cpu.data 0.100724 # miss rate for overall accesses 1051system.cpu.l2cache.overall_miss_rate::total 0.030854 # miss rate for overall accesses 1052system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137245.308538 # average ReadReq miss latency 1053system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137304.347826 # average ReadReq miss latency 1054system.cpu.l2cache.ReadReq_avg_miss_latency::total 137272.054744 # average ReadReq miss latency 1055system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38282.556027 # average UpgradeReq miss latency 1056system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38282.556027 # average UpgradeReq miss latency 1057system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency 1058system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency 1059system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132748.242680 # average ReadExReq miss latency 1060system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132748.242680 # average ReadExReq miss latency 1061system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132464.290363 # average ReadCleanReq miss latency 1062system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132464.290363 # average ReadCleanReq miss latency 1063system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135034.183639 # average ReadSharedReq miss latency 1064system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135034.183639 # average ReadSharedReq miss latency 1065system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 18.452462 # average InvalidateReq miss latency 1066system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 18.452462 # average InvalidateReq miss latency 1067system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137245.308538 # average overall miss latency 1068system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137304.347826 # average overall miss latency 1069system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132464.290363 # average overall miss latency 1070system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133510.013110 # average overall miss latency 1071system.cpu.l2cache.demand_avg_miss_latency::total 133443.783093 # average overall miss latency 1072system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137245.308538 # average overall miss latency 1073system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137304.347826 # average overall miss latency 1074system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132464.290363 # average overall miss latency 1075system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133510.013110 # average overall miss latency 1076system.cpu.l2cache.overall_avg_miss_latency::total 133443.783093 # average overall miss latency 1077system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1078system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1080system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1082system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	881system.cpu.l2cache.tags.replacements 1529682 # number of replacements 882system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use 883system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks. 884system.cpu.l2cache.tags.sampled_refs 1592715 # Sample count of references to valid blocks. 885system.cpu.l2cache.tags.avg_refs 41.651953 # Average number of references to valid blocks. 886system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit. 887system.cpu.l2cache.tags.occ_blocks::writebacks 36843.538434 # Average occupied blocks per requestor 888system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 325.022996 # Average occupied blocks per requestor 889system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 386.025396 # Average occupied blocks per requestor 890system.cpu.l2cache.tags.occ_blocks::cpu.inst 8031.083741 # Average occupied blocks per requestor 891system.cpu.l2cache.tags.occ_blocks::cpu.data 19745.157287 # Average occupied blocks per requestor 892system.cpu.l2cache.tags.occ_percent::writebacks 0.562188 # Average percentage of cache occupancy 893system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004959 # Average percentage of cache occupancy 894system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005890 # Average percentage of cache occupancy 895system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122545 # Average percentage of cache occupancy 896system.cpu.l2cache.tags.occ_percent::cpu.data 0.301287 # Average percentage of cache occupancy 897system.cpu.l2cache.tags.occ_percent::total 0.996869 # Average percentage of cache occupancy 898system.cpu.l2cache.tags.occ_task_id_blocks::1023 238 # Occupied blocks per task id 899system.cpu.l2cache.tags.occ_task_id_blocks::1024 62795 # Occupied blocks per task id 900system.cpu.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 901system.cpu.l2cache.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id 902system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 903system.cpu.l2cache.tags.age_task_id_blocks_1024::1 461 # Occupied blocks per task id 904system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2479 # Occupied blocks per task id 905system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5541 # Occupied blocks per task id 906system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54260 # Occupied blocks per task id 907system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003632 # Percentage of cache occupancy per task id 908system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958176 # Percentage of cache occupancy per task id 909system.cpu.l2cache.tags.tag_accesses 577322417 # Number of tag accesses 910system.cpu.l2cache.tags.data_accesses 577322417 # Number of data accesses 911system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 919591 # number of ReadReq hits 912system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 277608 # number of ReadReq hits 913system.cpu.l2cache.ReadReq_hits::total 1197199 # number of ReadReq hits 914system.cpu.l2cache.WritebackDirty_hits::writebacks 8312311 # number of WritebackDirty hits 915system.cpu.l2cache.WritebackDirty_hits::total 8312311 # number of WritebackDirty hits 916system.cpu.l2cache.WritebackClean_hits::writebacks 24335620 # number of WritebackClean hits 917system.cpu.l2cache.WritebackClean_hits::total 24335620 # number of WritebackClean hits 918system.cpu.l2cache.UpgradeReq_hits::cpu.data 10528 # number of UpgradeReq hits 919system.cpu.l2cache.UpgradeReq_hits::total 10528 # number of UpgradeReq hits 920system.cpu.l2cache.ReadExReq_hits::cpu.data 1643656 # number of ReadExReq hits 921system.cpu.l2cache.ReadExReq_hits::total 1643656 # number of ReadExReq hits 922system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24232057 # number of ReadCleanReq hits 923system.cpu.l2cache.ReadCleanReq_hits::total 24232057 # number of ReadCleanReq hits 924system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6978048 # number of ReadSharedReq hits 925system.cpu.l2cache.ReadSharedReq_hits::total 6978048 # number of ReadSharedReq hits 926system.cpu.l2cache.InvalidateReq_hits::cpu.data 702797 # number of InvalidateReq hits 927system.cpu.l2cache.InvalidateReq_hits::total 702797 # number of InvalidateReq hits 928system.cpu.l2cache.demand_hits::cpu.dtb.walker 919591 # number of demand (read+write) hits 929system.cpu.l2cache.demand_hits::cpu.itb.walker 277608 # number of demand (read+write) hits 930system.cpu.l2cache.demand_hits::cpu.inst 24232057 # number of demand (read+write) hits 931system.cpu.l2cache.demand_hits::cpu.data 8621704 # number of demand (read+write) hits 932system.cpu.l2cache.demand_hits::total 34050960 # number of demand (read+write) hits 933system.cpu.l2cache.overall_hits::cpu.dtb.walker 919591 # number of overall hits 934system.cpu.l2cache.overall_hits::cpu.itb.walker 277608 # number of overall hits 935system.cpu.l2cache.overall_hits::cpu.inst 24232057 # number of overall hits 936system.cpu.l2cache.overall_hits::cpu.data 8621704 # number of overall hits 937system.cpu.l2cache.overall_hits::total 34050960 # number of overall hits 938system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5915 # number of ReadReq misses 939system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4899 # number of ReadReq misses 940system.cpu.l2cache.ReadReq_misses::total 10814 # number of ReadReq misses 941system.cpu.l2cache.UpgradeReq_misses::cpu.data 37973 # number of UpgradeReq misses 942system.cpu.l2cache.UpgradeReq_misses::total 37973 # number of UpgradeReq misses 943system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 944system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 945system.cpu.l2cache.ReadExReq_misses::cpu.data 643878 # number of ReadExReq misses 946system.cpu.l2cache.ReadExReq_misses::total 643878 # number of ReadExReq misses 947system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107562 # number of ReadCleanReq misses 948system.cpu.l2cache.ReadCleanReq_misses::total 107562 # number of ReadCleanReq misses 949system.cpu.l2cache.ReadSharedReq_misses::cpu.data 321806 # number of ReadSharedReq misses 950system.cpu.l2cache.ReadSharedReq_misses::total 321806 # number of ReadSharedReq misses 951system.cpu.l2cache.InvalidateReq_misses::cpu.data 537137 # number of InvalidateReq misses 952system.cpu.l2cache.InvalidateReq_misses::total 537137 # number of InvalidateReq misses 953system.cpu.l2cache.demand_misses::cpu.dtb.walker 5915 # number of demand (read+write) misses 954system.cpu.l2cache.demand_misses::cpu.itb.walker 4899 # number of demand (read+write) misses 955system.cpu.l2cache.demand_misses::cpu.inst 107562 # number of demand (read+write) misses 956system.cpu.l2cache.demand_misses::cpu.data 965684 # number of demand (read+write) misses 957system.cpu.l2cache.demand_misses::total 1084060 # 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number of demand (read+write) miss cycles 979system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 672654000 # number of demand (read+write) miss cycles 980system.cpu.l2cache.demand_miss_latency::cpu.inst 14248124000 # number of demand (read+write) miss cycles 981system.cpu.l2cache.demand_miss_latency::cpu.data 128928483500 # number of demand (read+write) miss cycles 982system.cpu.l2cache.demand_miss_latency::total 144661067500 # number of demand (read+write) miss cycles 983system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 811806000 # number of overall miss cycles 984system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 672654000 # number of overall miss cycles 985system.cpu.l2cache.overall_miss_latency::cpu.inst 14248124000 # number of overall miss cycles 986system.cpu.l2cache.overall_miss_latency::cpu.data 128928483500 # number of overall miss cycles 987system.cpu.l2cache.overall_miss_latency::total 144661067500 # number of overall miss cycles 988system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 925506 # number of ReadReq accesses(hits+misses) 989system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 282507 # number of ReadReq accesses(hits+misses) 990system.cpu.l2cache.ReadReq_accesses::total 1208013 # number of ReadReq accesses(hits+misses) 991system.cpu.l2cache.WritebackDirty_accesses::writebacks 8312311 # number of WritebackDirty accesses(hits+misses) 992system.cpu.l2cache.WritebackDirty_accesses::total 8312311 # number of WritebackDirty accesses(hits+misses) 993system.cpu.l2cache.WritebackClean_accesses::writebacks 24335620 # number of WritebackClean accesses(hits+misses) 994system.cpu.l2cache.WritebackClean_accesses::total 24335620 # number of WritebackClean accesses(hits+misses) 995system.cpu.l2cache.UpgradeReq_accesses::cpu.data 48501 # number of UpgradeReq accesses(hits+misses) 996system.cpu.l2cache.UpgradeReq_accesses::total 48501 # number of UpgradeReq accesses(hits+misses) 997system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 998system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # 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miss rate for ReadSharedReq accesses 1030system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.433198 # miss rate for InvalidateReq accesses 1031system.cpu.l2cache.InvalidateReq_miss_rate::total 0.433198 # miss rate for InvalidateReq accesses 1032system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006391 # miss rate for demand accesses 1033system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017341 # miss rate for demand accesses 1034system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004419 # miss rate for demand accesses 1035system.cpu.l2cache.demand_miss_rate::cpu.data 0.100724 # miss rate for demand accesses 1036system.cpu.l2cache.demand_miss_rate::total 0.030854 # miss rate for demand accesses 1037system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006391 # miss rate for overall accesses 1038system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017341 # miss rate for overall accesses 1039system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004419 # miss rate for overall accesses 1040system.cpu.l2cache.overall_miss_rate::cpu.data 0.100724 # miss rate for overall accesses 1041system.cpu.l2cache.overall_miss_rate::total 0.030854 # miss rate for overall accesses 1042system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137245.308538 # average ReadReq miss latency 1043system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137304.347826 # average ReadReq miss latency 1044system.cpu.l2cache.ReadReq_avg_miss_latency::total 137272.054744 # average ReadReq miss latency 1045system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38282.556027 # average UpgradeReq miss latency 1046system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38282.556027 # average UpgradeReq miss latency 1047system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency 1048system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency 1049system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132748.242680 # average ReadExReq miss latency 1050system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132748.242680 # average ReadExReq miss latency 1051system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132464.290363 # average ReadCleanReq miss latency 1052system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132464.290363 # average ReadCleanReq miss latency 1053system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135034.183639 # average ReadSharedReq miss latency 1054system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135034.183639 # average ReadSharedReq miss latency 1055system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 18.452462 # average InvalidateReq miss latency 1056system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 18.452462 # average InvalidateReq miss latency 1057system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137245.308538 # average overall miss latency 1058system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137304.347826 # average overall miss latency 1059system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132464.290363 # average overall miss latency 1060system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133510.013110 # average overall miss latency 1061system.cpu.l2cache.demand_avg_miss_latency::total 133443.783093 # average overall miss latency 1062system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137245.308538 # average overall miss latency 1063system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137304.347826 # average overall miss latency 1064system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132464.290363 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133510.013110 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::total 133443.783093 # average overall miss latency 1067system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1068system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1069system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1070system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1071system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1072system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1083system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1084system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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