Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.609999 # Number of seconds simulated
4sim_ticks 51609998980000 # Number of ticks simulated
5final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 125549 # Simulator instruction rate (inst/s)
8host_op_rate 147521 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 6837484784 # Simulator tick rate (ticks/s)
10host_mem_usage 653616 # Number of bytes of host memory used
11host_seconds 7548.10 # Real time elapsed on the host

7host_inst_rate 182485 # Simulator instruction rate (inst/s)
8host_op_rate 214421 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 9938249935 # Simulator tick rate (ticks/s)
10host_mem_usage 720032 # Number of bytes of host memory used
11host_seconds 5193.07 # Real time elapsed on the host

12sim_insts 947659008 # Number of instructions simulated
13sim_ops 1113505098 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 398592 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 332160 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 10228032 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 65553800 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 419072 # Number of bytes read from this memory
21system.physmem.bytes_read::total 76931656 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 10228032 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 10228032 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 93992704 # Number of bytes written to this memory
25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
26system.physmem.bytes_written::total 94013284 # Number of bytes written to this memory
27system.physmem.num_reads::cpu.dtb.walker 6228 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 5190 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.inst 159813 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 1024291 # Number of read requests responded to by this memory
31system.physmem.num_reads::realview.ide 6548 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 1202070 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 1468636 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 1471209 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu.dtb.walker 7723 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.itb.walker 6436 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.inst 198179 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 1270176 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::realview.ide 8120 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 1490635 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 198179 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 198179 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 1821211 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 1821610 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 1821211 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.dtb.walker 7723 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.itb.walker 6436 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.inst 198179 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 1270575 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::realview.ide 8120 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 3312245 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 1202070 # Number of read requests accepted
55system.physmem.writeReqs 2120779 # Number of write requests accepted
56system.physmem.readBursts 1202070 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 2120779 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 76896960 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue
60system.physmem.bytesWritten 132496640 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 76931656 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 135585764 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 50494 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 39336 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 72977 # Per bank write bursts
67system.physmem.perBankRdBursts::1 77412 # Per bank write bursts
68system.physmem.perBankRdBursts::2 73227 # Per bank write bursts
69system.physmem.perBankRdBursts::3 70716 # Per bank write bursts
70system.physmem.perBankRdBursts::4 69716 # Per bank write bursts
71system.physmem.perBankRdBursts::5 78531 # Per bank write bursts
72system.physmem.perBankRdBursts::6 70002 # Per bank write bursts
73system.physmem.perBankRdBursts::7 72888 # Per bank write bursts
74system.physmem.perBankRdBursts::8 66687 # Per bank write bursts
75system.physmem.perBankRdBursts::9 126636 # Per bank write bursts
76system.physmem.perBankRdBursts::10 72169 # Per bank write bursts
77system.physmem.perBankRdBursts::11 76842 # Per bank write bursts
78system.physmem.perBankRdBursts::12 69750 # Per bank write bursts
79system.physmem.perBankRdBursts::13 69617 # Per bank write bursts
80system.physmem.perBankRdBursts::14 66498 # Per bank write bursts
81system.physmem.perBankRdBursts::15 67847 # Per bank write bursts
82system.physmem.perBankWrBursts::0 128572 # Per bank write bursts
83system.physmem.perBankWrBursts::1 129591 # Per bank write bursts
84system.physmem.perBankWrBursts::2 133621 # Per bank write bursts
85system.physmem.perBankWrBursts::3 133794 # Per bank write bursts
86system.physmem.perBankWrBursts::4 127990 # Per bank write bursts
87system.physmem.perBankWrBursts::5 135547 # Per bank write bursts
88system.physmem.perBankWrBursts::6 129190 # Per bank write bursts
89system.physmem.perBankWrBursts::7 132517 # Per bank write bursts
90system.physmem.perBankWrBursts::8 125103 # Per bank write bursts
91system.physmem.perBankWrBursts::9 133352 # Per bank write bursts
92system.physmem.perBankWrBursts::10 128272 # Per bank write bursts
93system.physmem.perBankWrBursts::11 129497 # Per bank write bursts
94system.physmem.perBankWrBursts::12 125797 # Per bank write bursts
95system.physmem.perBankWrBursts::13 127747 # Per bank write bursts
96system.physmem.perBankWrBursts::14 124476 # Per bank write bursts
97system.physmem.perBankWrBursts::15 125194 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 166 # Number of times write queue was full causing retry
100system.physmem.totGap 51609997338500 # Total gap between requests
101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 0 # Read request sizes (log2)
104system.physmem.readPktSize::3 13 # Read request sizes (log2)
105system.physmem.readPktSize::4 2 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)
107system.physmem.readPktSize::6 1202055 # Read request sizes (log2)
108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 1 # Write request sizes (log2)
111system.physmem.writePktSize::3 2572 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)
114system.physmem.writePktSize::6 2118206 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 1132428 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 62352 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 724 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 310 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 460 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 547 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 490 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 762 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 454 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::9 1875 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 234 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::12 113 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::13 114 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::14 110 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::15 51481 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 61019 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 101890 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 106045 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 113976 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 152332 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 126167 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 115190 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 114656 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 107766 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 107346 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::26 140408 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::27 114567 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 109101 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 121792 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 109844 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 105744 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 103641 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 5730 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 5398 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 6493 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 7698 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 7852 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 7029 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 7221 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 7920 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 6653 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 6549 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::43 5561 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::44 5785 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 4638 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 4213 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 3839 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 3050 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 2469 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 1608 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::51 1325 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::52 953 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 771 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 631 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 600 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 605 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 519 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 469 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 428 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 385 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 337 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 232 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 344 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 720627 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 290.570872 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 167.798815 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 325.942314 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 295355 40.99% 40.99% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 175877 24.41% 65.39% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 63976 8.88% 74.27% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 35683 4.95% 79.22% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 24604 3.41% 82.64% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 16955 2.35% 84.99% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 13020 1.81% 86.80% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 11401 1.58% 88.38% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 83756 11.62% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 720627 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 99482 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 12.077512 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 124.901364 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-1023 99480 100.00% 100.00% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 99482 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 99482 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 20.810398 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 19.292150 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 17.172998 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-31 95801 96.30% 96.30% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::32-47 1933 1.94% 98.24% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::48-63 403 0.41% 98.65% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::64-79 315 0.32% 98.96% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::80-95 148 0.15% 99.11% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::96-111 160 0.16% 99.27% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::112-127 333 0.33% 99.61% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::128-143 129 0.13% 99.74% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::144-159 31 0.03% 99.77% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::160-175 15 0.02% 99.78% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::176-191 63 0.06% 99.85% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::192-207 32 0.03% 99.88% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::208-223 14 0.01% 99.89% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::224-239 6 0.01% 99.90% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::240-255 1 0.00% 99.90% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::256-271 2 0.00% 99.90% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::272-287 4 0.00% 99.91% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::288-303 7 0.01% 99.91% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::304-319 7 0.01% 99.92% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::320-335 9 0.01% 99.93% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::352-367 20 0.02% 99.96% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::368-383 6 0.01% 99.96% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::384-399 4 0.00% 99.97% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::400-415 5 0.01% 99.97% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::416-431 1 0.00% 99.97% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::448-463 1 0.00% 99.98% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::480-495 2 0.00% 99.98% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::512-527 1 0.00% 99.98% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::528-543 8 0.01% 99.99% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::544-559 1 0.00% 99.99% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::total 99482 # Writes before turning the bus around for reads
276system.physmem.totQLat 16741886044 # Total ticks spent queuing
277system.physmem.totMemAccLat 39270292294 # Total ticks spent from burst creation until serviced by the DRAM
278system.physmem.totBusLat 6007575000 # Total ticks spent in databus transfers
279system.physmem.avgQLat 13933.98 # Average queueing delay per DRAM burst
280system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
281system.physmem.avgMemAccLat 32683.98 # Average memory access latency per DRAM burst
282system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s
283system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s
284system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s
285system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s
286system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
287system.physmem.busUtil 0.03 # Data bus utilization in percentage
288system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
289system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
290system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
291system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing
292system.physmem.readRowHits 927538 # Number of row buffer hits during reads
293system.physmem.writeRowHits 1623609 # Number of row buffer hits during writes
294system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads
295system.physmem.writeRowHitRate 78.42 # Row buffer hit rate for writes
296system.physmem.avgGap 15531851.53 # Average gap between requests
297system.physmem.pageHitRate 77.97 # Row buffer hit rate, read and write combined
298system.physmem_0.actEnergy 2802990960 # Energy for activate commands per rank (pJ)
299system.physmem_0.preEnergy 1529409750 # Energy for precharge commands per rank (pJ)
300system.physmem_0.readEnergy 4566611400 # Energy for read commands per rank (pJ)
301system.physmem_0.writeEnergy 6809326560 # Energy for write commands per rank (pJ)
302system.physmem_0.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ)
303system.physmem_0.actBackEnergy 1308588544890 # Energy for active background per rank (pJ)
304system.physmem_0.preBackEnergy 29818114243500 # Energy for precharge background per rank (pJ)
305system.physmem_0.totalEnergy 34513325311620 # Total energy per rank (pJ)
306system.physmem_0.averagePower 668.733317 # Core power per rank (mW)
307system.physmem_0.memoryStateTime::IDLE 49604286854347 # Time in different power states
308system.physmem_0.memoryStateTime::REF 1723371260000 # Time in different power states
309system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
310system.physmem_0.memoryStateTime::ACT 282340388153 # Time in different power states
311system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
312system.physmem_1.actEnergy 2644949160 # Energy for activate commands per rank (pJ)
313system.physmem_1.preEnergy 1443176625 # Energy for precharge commands per rank (pJ)
314system.physmem_1.readEnergy 4805158800 # Energy for read commands per rank (pJ)
315system.physmem_1.writeEnergy 6605958240 # Energy for write commands per rank (pJ)
316system.physmem_1.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ)
317system.physmem_1.actBackEnergy 1300507873200 # Energy for active background per rank (pJ)
318system.physmem_1.preBackEnergy 29825202552000 # Energy for precharge background per rank (pJ)
319system.physmem_1.totalEnergy 34512123852585 # Total energy per rank (pJ)
320system.physmem_1.averagePower 668.710038 # Core power per rank (mW)
321system.physmem_1.memoryStateTime::IDLE 49616091454429 # Time in different power states
322system.physmem_1.memoryStateTime::REF 1723371260000 # Time in different power states
323system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
324system.physmem_1.memoryStateTime::ACT 270535519321 # Time in different power states
325system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
326system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory
327system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
328system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory
329system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory
330system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
331system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory
332system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
333system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory
334system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s)
335system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
336system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s)
337system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s)
338system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s)
339system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s)
340system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
341system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s)
342system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
343system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
344system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
345system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
346system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
347system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
348system.cpu.branchPred.lookups 260066829 # Number of BP lookups
349system.cpu.branchPred.condPredicted 182351604 # Number of conditional branches predicted
350system.cpu.branchPred.condIncorrect 12179122 # Number of conditional branches incorrect
351system.cpu.branchPred.BTBLookups 192997810 # Number of BTB lookups
352system.cpu.branchPred.BTBHits 135975989 # Number of BTB hits
353system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
354system.cpu.branchPred.BTBHitPct 70.454680 # BTB Hit Percentage
355system.cpu.branchPred.usedRAS 31593975 # Number of times the RAS was used to get a target.
356system.cpu.branchPred.RASInCorrect 2147293 # Number of incorrect RAS predictions.
357system.cpu_clk_domain.clock 500 # Clock period in ticks
358system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
365system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
366system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
367system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
368system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
369system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
370system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
371system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
372system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
373system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
374system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
375system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
376system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
377system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
378system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
379system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
380system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
381system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
382system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
383system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
384system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
385system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
386system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
387system.cpu.dtb.walker.walks 583127 # Table walker walks requested
388system.cpu.dtb.walker.walksLong 583127 # Table walker walks initiated with long descriptors
389system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22581 # Level at which table walker walks with long descriptors terminate
390system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191165 # Level at which table walker walks with long descriptors terminate
391system.cpu.dtb.walker.walkWaitTime::samples 583127 # Table walker wait (enqueue to first request) latency
392system.cpu.dtb.walker.walkWaitTime::0 583127 100.00% 100.00% # Table walker wait (enqueue to first request) latency
393system.cpu.dtb.walker.walkWaitTime::total 583127 # Table walker wait (enqueue to first request) latency
394system.cpu.dtb.walker.walkCompletionTime::samples 213746 # Table walker service (enqueue to completion) latency
395system.cpu.dtb.walker.walkCompletionTime::mean 24576.454072 # Table walker service (enqueue to completion) latency
396system.cpu.dtb.walker.walkCompletionTime::gmean 20707.683114 # Table walker service (enqueue to completion) latency
397system.cpu.dtb.walker.walkCompletionTime::stdev 15710.461946 # Table walker service (enqueue to completion) latency
398system.cpu.dtb.walker.walkCompletionTime::0-65535 211230 98.82% 98.82% # Table walker service (enqueue to completion) latency
399system.cpu.dtb.walker.walkCompletionTime::65536-131071 2148 1.00% 99.83% # Table walker service (enqueue to completion) latency
400system.cpu.dtb.walker.walkCompletionTime::131072-196607 131 0.06% 99.89% # Table walker service (enqueue to completion) latency
401system.cpu.dtb.walker.walkCompletionTime::196608-262143 118 0.06% 99.94% # Table walker service (enqueue to completion) latency
402system.cpu.dtb.walker.walkCompletionTime::262144-327679 73 0.03% 99.98% # Table walker service (enqueue to completion) latency
403system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.99% # Table walker service (enqueue to completion) latency
404system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
405system.cpu.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
406system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
407system.cpu.dtb.walker.walkCompletionTime::total 213746 # Table walker service (enqueue to completion) latency
408system.cpu.dtb.walker.walksPending::samples -15748296 # Table walker pending requests distribution
409system.cpu.dtb.walker.walksPending::0 -15748296 100.00% 100.00% # Table walker pending requests distribution
410system.cpu.dtb.walker.walksPending::total -15748296 # Table walker pending requests distribution
411system.cpu.dtb.walker.walkPageSizes::4K 191166 89.44% 89.44% # Table walker page sizes translated
412system.cpu.dtb.walker.walkPageSizes::2M 22581 10.56% 100.00% # Table walker page sizes translated
413system.cpu.dtb.walker.walkPageSizes::total 213747 # Table walker page sizes translated
414system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 583127 # Table walker requests started/completed, data/inst
415system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
416system.cpu.dtb.walker.walkRequestOrigin_Requested::total 583127 # Table walker requests started/completed, data/inst
417system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213747 # Table walker requests started/completed, data/inst
418system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
419system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213747 # Table walker requests started/completed, data/inst
420system.cpu.dtb.walker.walkRequestOrigin::total 796874 # Table walker requests started/completed, data/inst
421system.cpu.dtb.inst_hits 0 # ITB inst hits
422system.cpu.dtb.inst_misses 0 # ITB inst misses
423system.cpu.dtb.read_hits 182952995 # DTB read hits
424system.cpu.dtb.read_misses 481784 # DTB read misses
425system.cpu.dtb.write_hits 162354187 # DTB write hits
426system.cpu.dtb.write_misses 101343 # DTB write misses
427system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
428system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
429system.cpu.dtb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID
430system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID
431system.cpu.dtb.flush_entries 80213 # Number of entries that have been flushed from TLB
432system.cpu.dtb.align_faults 854 # Number of TLB faults due to alignment restrictions
433system.cpu.dtb.prefetch_faults 14789 # Number of TLB faults due to prefetch
434system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
435system.cpu.dtb.perms_faults 23472 # Number of TLB faults due to permissions restrictions
436system.cpu.dtb.read_accesses 183434779 # DTB read accesses
437system.cpu.dtb.write_accesses 162455530 # DTB write accesses
438system.cpu.dtb.inst_accesses 0 # ITB inst accesses
439system.cpu.dtb.hits 345307182 # DTB hits
440system.cpu.dtb.misses 583127 # DTB misses
441system.cpu.dtb.accesses 345890309 # DTB accesses
442system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
450system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
451system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
452system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
453system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
454system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
455system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
456system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
457system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
458system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
459system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
460system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
461system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
462system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
463system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
464system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
465system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
466system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
467system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
468system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
469system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
470system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
471system.cpu.itb.walker.walks 136411 # Table walker walks requested
472system.cpu.itb.walker.walksLong 136411 # Table walker walks initiated with long descriptors
473system.cpu.itb.walker.walksLongTerminationLevel::Level2 1074 # Level at which table walker walks with long descriptors terminate
474system.cpu.itb.walker.walksLongTerminationLevel::Level3 118764 # Level at which table walker walks with long descriptors terminate
475system.cpu.itb.walker.walkWaitTime::samples 136411 # Table walker wait (enqueue to first request) latency
476system.cpu.itb.walker.walkWaitTime::0 136411 100.00% 100.00% # Table walker wait (enqueue to first request) latency
477system.cpu.itb.walker.walkWaitTime::total 136411 # Table walker wait (enqueue to first request) latency
478system.cpu.itb.walker.walkCompletionTime::samples 119838 # Table walker service (enqueue to completion) latency
479system.cpu.itb.walker.walkCompletionTime::mean 26864.678099 # Table walker service (enqueue to completion) latency
480system.cpu.itb.walker.walkCompletionTime::gmean 23079.638443 # Table walker service (enqueue to completion) latency
481system.cpu.itb.walker.walkCompletionTime::stdev 17315.603436 # Table walker service (enqueue to completion) latency
482system.cpu.itb.walker.walkCompletionTime::0-65535 117018 97.65% 97.65% # Table walker service (enqueue to completion) latency
483system.cpu.itb.walker.walkCompletionTime::65536-131071 2553 2.13% 99.78% # Table walker service (enqueue to completion) latency
484system.cpu.itb.walker.walkCompletionTime::131072-196607 159 0.13% 99.91% # Table walker service (enqueue to completion) latency
485system.cpu.itb.walker.walkCompletionTime::196608-262143 57 0.05% 99.96% # Table walker service (enqueue to completion) latency
486system.cpu.itb.walker.walkCompletionTime::262144-327679 28 0.02% 99.98% # Table walker service (enqueue to completion) latency
487system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.02% 100.00% # Table walker service (enqueue to completion) latency
488system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
489system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
490system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
491system.cpu.itb.walker.walkCompletionTime::total 119838 # Table walker service (enqueue to completion) latency
492system.cpu.itb.walker.walksPending::samples -16365796 # Table walker pending requests distribution
493system.cpu.itb.walker.walksPending::0 -16365796 100.00% 100.00% # Table walker pending requests distribution
494system.cpu.itb.walker.walksPending::total -16365796 # Table walker pending requests distribution
495system.cpu.itb.walker.walkPageSizes::4K 118764 99.10% 99.10% # Table walker page sizes translated
496system.cpu.itb.walker.walkPageSizes::2M 1074 0.90% 100.00% # Table walker page sizes translated
497system.cpu.itb.walker.walkPageSizes::total 119838 # Table walker page sizes translated
498system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
499system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136411 # Table walker requests started/completed, data/inst
500system.cpu.itb.walker.walkRequestOrigin_Requested::total 136411 # Table walker requests started/completed, data/inst
501system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
502system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119838 # Table walker requests started/completed, data/inst
503system.cpu.itb.walker.walkRequestOrigin_Completed::total 119838 # Table walker requests started/completed, data/inst
504system.cpu.itb.walker.walkRequestOrigin::total 256249 # Table walker requests started/completed, data/inst
505system.cpu.itb.inst_hits 452746266 # ITB inst hits
506system.cpu.itb.inst_misses 136411 # ITB inst misses
507system.cpu.itb.read_hits 0 # DTB read hits
508system.cpu.itb.read_misses 0 # DTB read misses
509system.cpu.itb.write_hits 0 # DTB write hits
510system.cpu.itb.write_misses 0 # DTB write misses
511system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
512system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
513system.cpu.itb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID
514system.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID
515system.cpu.itb.flush_entries 57592 # Number of entries that have been flushed from TLB
516system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
517system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
518system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
519system.cpu.itb.perms_faults 369764 # Number of TLB faults due to permissions restrictions
520system.cpu.itb.read_accesses 0 # DTB read accesses
521system.cpu.itb.write_accesses 0 # DTB write accesses
522system.cpu.itb.inst_accesses 452882677 # ITB inst accesses
523system.cpu.itb.hits 452746266 # DTB hits
524system.cpu.itb.misses 136411 # DTB misses
525system.cpu.itb.accesses 452882677 # DTB accesses
526system.cpu.numCycles 2486475408 # number of cpu cycles simulated
527system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
528system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
529system.cpu.committedInsts 947659008 # Number of instructions committed
530system.cpu.committedOps 1113505098 # Number of ops (including micro ops) committed
531system.cpu.discardedOps 96546934 # Number of ops (including micro ops) which were discarded before commit
532system.cpu.numFetchSuspends 7735 # Number of times Execute suspended instruction fetching
533system.cpu.quiesceCycles 100734690731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
534system.cpu.cpi 2.623808 # CPI: cycles per instruction
535system.cpu.ipc 0.381125 # IPC: instructions per cycle
536system.cpu.kern.inst.arm 0 # number of arm instructions executed
537system.cpu.kern.inst.quiesce 16595 # number of quiesce instructions executed
538system.cpu.tickCycles 1791502894 # Number of cycles that the object actually ticked
539system.cpu.idleCycles 694972514 # Total number of cycles that the object has spent stopped
540system.cpu.dcache.tags.replacements 11092406 # number of replacements
541system.cpu.dcache.tags.tagsinuse 511.957332 # Cycle average of tags in use
542system.cpu.dcache.tags.total_refs 328965151 # Total number of references to valid blocks.
543system.cpu.dcache.tags.sampled_refs 11092918 # Sample count of references to valid blocks.
544system.cpu.dcache.tags.avg_refs 29.655421 # Average number of references to valid blocks.
545system.cpu.dcache.tags.warmup_cycle 4320792250 # Cycle when the warmup percentage was hit.
546system.cpu.dcache.tags.occ_blocks::cpu.data 511.957332 # Average occupied blocks per requestor
547system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy
548system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy
549system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
550system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
551system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id
552system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
553system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
554system.cpu.dcache.tags.tag_accesses 1382417296 # Number of tag accesses
555system.cpu.dcache.tags.data_accesses 1382417296 # Number of data accesses
556system.cpu.dcache.ReadReq_hits::cpu.data 168207875 # number of ReadReq hits
557system.cpu.dcache.ReadReq_hits::total 168207875 # number of ReadReq hits
558system.cpu.dcache.WriteReq_hits::cpu.data 151549113 # number of WriteReq hits
559system.cpu.dcache.WriteReq_hits::total 151549113 # number of WriteReq hits
560system.cpu.dcache.SoftPFReq_hits::cpu.data 490930 # number of SoftPFReq hits
561system.cpu.dcache.SoftPFReq_hits::total 490930 # number of SoftPFReq hits
562system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 335942 # number of WriteInvalidateReq hits
563system.cpu.dcache.WriteInvalidateReq_hits::total 335942 # number of WriteInvalidateReq hits
564system.cpu.dcache.LoadLockedReq_hits::cpu.data 4008865 # number of LoadLockedReq hits
565system.cpu.dcache.LoadLockedReq_hits::total 4008865 # number of LoadLockedReq hits
566system.cpu.dcache.StoreCondReq_hits::cpu.data 4323127 # number of StoreCondReq hits
567system.cpu.dcache.StoreCondReq_hits::total 4323127 # number of StoreCondReq hits
568system.cpu.dcache.demand_hits::cpu.data 319756988 # number of demand (read+write) hits
569system.cpu.dcache.demand_hits::total 319756988 # number of demand (read+write) hits
570system.cpu.dcache.overall_hits::cpu.data 320247918 # number of overall hits
571system.cpu.dcache.overall_hits::total 320247918 # number of overall hits
572system.cpu.dcache.ReadReq_misses::cpu.data 6578537 # number of ReadReq misses
573system.cpu.dcache.ReadReq_misses::total 6578537 # number of ReadReq misses
574system.cpu.dcache.WriteReq_misses::cpu.data 4302299 # number of WriteReq misses
575system.cpu.dcache.WriteReq_misses::total 4302299 # number of WriteReq misses
576system.cpu.dcache.SoftPFReq_misses::cpu.data 1473808 # number of SoftPFReq misses
577system.cpu.dcache.SoftPFReq_misses::total 1473808 # number of SoftPFReq misses
578system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1244599 # number of WriteInvalidateReq misses
579system.cpu.dcache.WriteInvalidateReq_misses::total 1244599 # number of WriteInvalidateReq misses
580system.cpu.dcache.LoadLockedReq_misses::cpu.data 315993 # number of LoadLockedReq misses
581system.cpu.dcache.LoadLockedReq_misses::total 315993 # number of LoadLockedReq misses
582system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
583system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
584system.cpu.dcache.demand_misses::cpu.data 10880836 # number of demand (read+write) misses
585system.cpu.dcache.demand_misses::total 10880836 # number of demand (read+write) misses
586system.cpu.dcache.overall_misses::cpu.data 12354644 # number of overall misses
587system.cpu.dcache.overall_misses::total 12354644 # number of overall misses
588system.cpu.dcache.ReadReq_miss_latency::cpu.data 106697920457 # number of ReadReq miss cycles
589system.cpu.dcache.ReadReq_miss_latency::total 106697920457 # number of ReadReq miss cycles
590system.cpu.dcache.WriteReq_miss_latency::cpu.data 153242376598 # number of WriteReq miss cycles
591system.cpu.dcache.WriteReq_miss_latency::total 153242376598 # number of WriteReq miss cycles
592system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35461255171 # number of WriteInvalidateReq miss cycles
593system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35461255171 # number of WriteInvalidateReq miss cycles
594system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4805977234 # number of LoadLockedReq miss cycles
595system.cpu.dcache.LoadLockedReq_miss_latency::total 4805977234 # number of LoadLockedReq miss cycles
596system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles
597system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles
598system.cpu.dcache.demand_miss_latency::cpu.data 259940297055 # number of demand (read+write) miss cycles
599system.cpu.dcache.demand_miss_latency::total 259940297055 # number of demand (read+write) miss cycles
600system.cpu.dcache.overall_miss_latency::cpu.data 259940297055 # number of overall miss cycles
601system.cpu.dcache.overall_miss_latency::total 259940297055 # number of overall miss cycles
602system.cpu.dcache.ReadReq_accesses::cpu.data 174786412 # number of ReadReq accesses(hits+misses)
603system.cpu.dcache.ReadReq_accesses::total 174786412 # number of ReadReq accesses(hits+misses)
604system.cpu.dcache.WriteReq_accesses::cpu.data 155851412 # number of WriteReq accesses(hits+misses)
605system.cpu.dcache.WriteReq_accesses::total 155851412 # number of WriteReq accesses(hits+misses)
606system.cpu.dcache.SoftPFReq_accesses::cpu.data 1964738 # number of SoftPFReq accesses(hits+misses)
607system.cpu.dcache.SoftPFReq_accesses::total 1964738 # number of SoftPFReq accesses(hits+misses)
608system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1580541 # number of WriteInvalidateReq accesses(hits+misses)
609system.cpu.dcache.WriteInvalidateReq_accesses::total 1580541 # number of WriteInvalidateReq accesses(hits+misses)
610system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4324858 # number of LoadLockedReq accesses(hits+misses)
611system.cpu.dcache.LoadLockedReq_accesses::total 4324858 # number of LoadLockedReq accesses(hits+misses)
612system.cpu.dcache.StoreCondReq_accesses::cpu.data 4323128 # number of StoreCondReq accesses(hits+misses)
613system.cpu.dcache.StoreCondReq_accesses::total 4323128 # number of StoreCondReq accesses(hits+misses)
614system.cpu.dcache.demand_accesses::cpu.data 330637824 # number of demand (read+write) accesses
615system.cpu.dcache.demand_accesses::total 330637824 # number of demand (read+write) accesses
616system.cpu.dcache.overall_accesses::cpu.data 332602562 # number of overall (read+write) accesses
617system.cpu.dcache.overall_accesses::total 332602562 # number of overall (read+write) accesses
618system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037638 # miss rate for ReadReq accesses
619system.cpu.dcache.ReadReq_miss_rate::total 0.037638 # miss rate for ReadReq accesses
620system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027605 # miss rate for WriteReq accesses
621system.cpu.dcache.WriteReq_miss_rate::total 0.027605 # miss rate for WriteReq accesses
622system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.750130 # miss rate for SoftPFReq accesses
623system.cpu.dcache.SoftPFReq_miss_rate::total 0.750130 # miss rate for SoftPFReq accesses
624system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787451 # miss rate for WriteInvalidateReq accesses
625system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787451 # miss rate for WriteInvalidateReq accesses
626system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073064 # miss rate for LoadLockedReq accesses
627system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073064 # miss rate for LoadLockedReq accesses
628system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
629system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
630system.cpu.dcache.demand_miss_rate::cpu.data 0.032909 # miss rate for demand accesses
631system.cpu.dcache.demand_miss_rate::total 0.032909 # miss rate for demand accesses
632system.cpu.dcache.overall_miss_rate::cpu.data 0.037145 # miss rate for overall accesses
633system.cpu.dcache.overall_miss_rate::total 0.037145 # miss rate for overall accesses
634system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.095592 # average ReadReq miss latency
635system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.095592 # average ReadReq miss latency
636system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35618.718410 # average WriteReq miss latency
637system.cpu.dcache.WriteReq_avg_miss_latency::total 35618.718410 # average WriteReq miss latency
638system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28492.112858 # average WriteInvalidateReq miss latency
639system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28492.112858 # average WriteInvalidateReq miss latency
640system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15209.125626 # average LoadLockedReq miss latency
641system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15209.125626 # average LoadLockedReq miss latency
642system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
643system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
644system.cpu.dcache.demand_avg_miss_latency::cpu.data 23889.735775 # average overall miss latency
645system.cpu.dcache.demand_avg_miss_latency::total 23889.735775 # average overall miss latency
646system.cpu.dcache.overall_avg_miss_latency::cpu.data 21039.885654 # average overall miss latency
647system.cpu.dcache.overall_avg_miss_latency::total 21039.885654 # average overall miss latency
648system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
649system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
650system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
651system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
652system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
653system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
654system.cpu.dcache.fast_writes 0 # number of fast writes performed
655system.cpu.dcache.cache_copies 0 # number of cache copies performed
656system.cpu.dcache.writebacks::writebacks 8509656 # number of writebacks
657system.cpu.dcache.writebacks::total 8509656 # number of writebacks
658system.cpu.dcache.ReadReq_mshr_hits::cpu.data 799615 # number of ReadReq MSHR hits
659system.cpu.dcache.ReadReq_mshr_hits::total 799615 # number of ReadReq MSHR hits
660system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1895946 # number of WriteReq MSHR hits
661system.cpu.dcache.WriteReq_mshr_hits::total 1895946 # number of WriteReq MSHR hits
662system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 144 # number of WriteInvalidateReq MSHR hits
663system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 144 # number of WriteInvalidateReq MSHR hits
664system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69791 # number of LoadLockedReq MSHR hits
665system.cpu.dcache.LoadLockedReq_mshr_hits::total 69791 # number of LoadLockedReq MSHR hits
666system.cpu.dcache.demand_mshr_hits::cpu.data 2695561 # number of demand (read+write) MSHR hits
667system.cpu.dcache.demand_mshr_hits::total 2695561 # number of demand (read+write) MSHR hits
668system.cpu.dcache.overall_mshr_hits::cpu.data 2695561 # number of overall MSHR hits
669system.cpu.dcache.overall_mshr_hits::total 2695561 # number of overall MSHR hits
670system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5778922 # number of ReadReq MSHR misses
671system.cpu.dcache.ReadReq_mshr_misses::total 5778922 # number of ReadReq MSHR misses
672system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2406353 # number of WriteReq MSHR misses
673system.cpu.dcache.WriteReq_mshr_misses::total 2406353 # number of WriteReq MSHR misses
674system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1466300 # number of SoftPFReq MSHR misses
675system.cpu.dcache.SoftPFReq_mshr_misses::total 1466300 # number of SoftPFReq MSHR misses
676system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244455 # number of WriteInvalidateReq MSHR misses
677system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244455 # number of WriteInvalidateReq MSHR misses
678system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246202 # number of LoadLockedReq MSHR misses
679system.cpu.dcache.LoadLockedReq_mshr_misses::total 246202 # number of LoadLockedReq MSHR misses
680system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
681system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
682system.cpu.dcache.demand_mshr_misses::cpu.data 8185275 # number of demand (read+write) MSHR misses
683system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses
684system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses
685system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses

686system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable
687system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable
688system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable
689system.cpu.dcache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable
690system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses
691system.cpu.dcache.overall_mshr_uncacheable_misses::total 67401 # number of overall MSHR uncacheable misses

686system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles
687system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles
688system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles
689system.cpu.dcache.WriteReq_mshr_miss_latency::total 78901247228 # number of WriteReq MSHR miss cycles
690system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22730570766 # number of SoftPFReq MSHR miss cycles
691system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22730570766 # number of SoftPFReq MSHR miss cycles
692system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33591268829 # number of WriteInvalidateReq MSHR miss cycles
693system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33591268829 # number of WriteInvalidateReq MSHR miss cycles
694system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3240983258 # number of LoadLockedReq MSHR miss cycles
695system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3240983258 # number of LoadLockedReq MSHR miss cycles
696system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 80500 # number of StoreCondReq MSHR miss cycles
697system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 80500 # number of StoreCondReq MSHR miss cycles
698system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163468245028 # number of demand (read+write) MSHR miss cycles
699system.cpu.dcache.demand_mshr_miss_latency::total 163468245028 # number of demand (read+write) MSHR miss cycles
700system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186198815794 # number of overall MSHR miss cycles
701system.cpu.dcache.overall_mshr_miss_latency::total 186198815794 # number of overall MSHR miss cycles
702system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751743992 # number of ReadReq MSHR uncacheable cycles
703system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751743992 # number of ReadReq MSHR uncacheable cycles
704system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611366250 # number of WriteReq MSHR uncacheable cycles
705system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611366250 # number of WriteReq MSHR uncacheable cycles
706system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363110242 # number of overall MSHR uncacheable cycles
707system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363110242 # number of overall MSHR uncacheable cycles
708system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033063 # mshr miss rate for ReadReq accesses
709system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033063 # mshr miss rate for ReadReq accesses
710system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015440 # mshr miss rate for WriteReq accesses
711system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015440 # mshr miss rate for WriteReq accesses
712system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746308 # mshr miss rate for SoftPFReq accesses
713system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746308 # mshr miss rate for SoftPFReq accesses
714system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787360 # mshr miss rate for WriteInvalidateReq accesses
715system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787360 # mshr miss rate for WriteInvalidateReq accesses
716system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056927 # mshr miss rate for LoadLockedReq accesses
717system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056927 # mshr miss rate for LoadLockedReq accesses
718system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
719system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
720system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024756 # mshr miss rate for demand accesses
721system.cpu.dcache.demand_mshr_miss_rate::total 0.024756 # mshr miss rate for demand accesses
722system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029018 # mshr miss rate for overall accesses
723system.cpu.dcache.overall_mshr_miss_rate::total 0.029018 # mshr miss rate for overall accesses
724system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14633.697738 # average ReadReq mshr miss latency
725system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14633.697738 # average ReadReq mshr miss latency
726system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32788.725190 # average WriteReq mshr miss latency
727system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32788.725190 # average WriteReq mshr miss latency
728system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15501.991929 # average SoftPFReq mshr miss latency
729system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15501.991929 # average SoftPFReq mshr miss latency
730system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 26992.754924 # average WriteInvalidateReq mshr miss latency
731system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26992.754924 # average WriteInvalidateReq mshr miss latency
732system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13163.919294 # average LoadLockedReq mshr miss latency
733system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13163.919294 # average LoadLockedReq mshr miss latency
734system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency
735system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency
736system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416 # average overall mshr miss latency
737system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency
738system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency
739system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency

692system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles
693system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles
694system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles
695system.cpu.dcache.WriteReq_mshr_miss_latency::total 78901247228 # number of WriteReq MSHR miss cycles
696system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22730570766 # number of SoftPFReq MSHR miss cycles
697system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22730570766 # number of SoftPFReq MSHR miss cycles
698system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33591268829 # number of WriteInvalidateReq MSHR miss cycles
699system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33591268829 # number of WriteInvalidateReq MSHR miss cycles
700system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3240983258 # number of LoadLockedReq MSHR miss cycles
701system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3240983258 # number of LoadLockedReq MSHR miss cycles
702system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 80500 # number of StoreCondReq MSHR miss cycles
703system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 80500 # number of StoreCondReq MSHR miss cycles
704system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163468245028 # number of demand (read+write) MSHR miss cycles
705system.cpu.dcache.demand_mshr_miss_latency::total 163468245028 # number of demand (read+write) MSHR miss cycles
706system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186198815794 # number of overall MSHR miss cycles
707system.cpu.dcache.overall_mshr_miss_latency::total 186198815794 # number of overall MSHR miss cycles
708system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751743992 # number of ReadReq MSHR uncacheable cycles
709system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751743992 # number of ReadReq MSHR uncacheable cycles
710system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611366250 # number of WriteReq MSHR uncacheable cycles
711system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611366250 # number of WriteReq MSHR uncacheable cycles
712system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363110242 # number of overall MSHR uncacheable cycles
713system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363110242 # number of overall MSHR uncacheable cycles
714system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033063 # mshr miss rate for ReadReq accesses
715system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033063 # mshr miss rate for ReadReq accesses
716system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015440 # mshr miss rate for WriteReq accesses
717system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015440 # mshr miss rate for WriteReq accesses
718system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746308 # mshr miss rate for SoftPFReq accesses
719system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746308 # mshr miss rate for SoftPFReq accesses
720system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787360 # mshr miss rate for WriteInvalidateReq accesses
721system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787360 # mshr miss rate for WriteInvalidateReq accesses
722system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056927 # mshr miss rate for LoadLockedReq accesses
723system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056927 # mshr miss rate for LoadLockedReq accesses
724system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
725system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
726system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024756 # mshr miss rate for demand accesses
727system.cpu.dcache.demand_mshr_miss_rate::total 0.024756 # mshr miss rate for demand accesses
728system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029018 # mshr miss rate for overall accesses
729system.cpu.dcache.overall_mshr_miss_rate::total 0.029018 # mshr miss rate for overall accesses
730system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14633.697738 # average ReadReq mshr miss latency
731system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14633.697738 # average ReadReq mshr miss latency
732system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32788.725190 # average WriteReq mshr miss latency
733system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32788.725190 # average WriteReq mshr miss latency
734system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15501.991929 # average SoftPFReq mshr miss latency
735system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15501.991929 # average SoftPFReq mshr miss latency
736system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 26992.754924 # average WriteInvalidateReq mshr miss latency
737system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26992.754924 # average WriteInvalidateReq mshr miss latency
738system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13163.919294 # average LoadLockedReq mshr miss latency
739system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13163.919294 # average LoadLockedReq mshr miss latency
740system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency
741system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency
742system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416 # average overall mshr miss latency
743system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency
744system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency
745system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency

740system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
741system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
742system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
743system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
744system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
745system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

746system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170695.156458 # average ReadReq mshr uncacheable latency
747system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170695.156458 # average ReadReq mshr uncacheable latency
748system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166484.683281 # average WriteReq mshr uncacheable latency
749system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166484.683281 # average WriteReq mshr uncacheable latency
750system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168589.638759 # average overall mshr uncacheable latency
751system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168589.638759 # average overall mshr uncacheable latency

746system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
747system.cpu.icache.tags.replacements 24538707 # number of replacements
748system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use
749system.cpu.icache.tags.total_refs 427825373 # Total number of references to valid blocks.
750system.cpu.icache.tags.sampled_refs 24539219 # Sample count of references to valid blocks.
751system.cpu.icache.tags.avg_refs 17.434352 # Average number of references to valid blocks.
752system.cpu.icache.tags.warmup_cycle 22330853250 # Cycle when the warmup percentage was hit.
753system.cpu.icache.tags.occ_blocks::cpu.inst 511.926996 # Average occupied blocks per requestor
754system.cpu.icache.tags.occ_percent::cpu.inst 0.999857 # Average percentage of cache occupancy
755system.cpu.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy
756system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
757system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
758system.cpu.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
759system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id
760system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
761system.cpu.icache.tags.tag_accesses 476903830 # Number of tag accesses
762system.cpu.icache.tags.data_accesses 476903830 # Number of data accesses
763system.cpu.icache.ReadReq_hits::cpu.inst 427825373 # number of ReadReq hits
764system.cpu.icache.ReadReq_hits::total 427825373 # number of ReadReq hits
765system.cpu.icache.demand_hits::cpu.inst 427825373 # number of demand (read+write) hits
766system.cpu.icache.demand_hits::total 427825373 # number of demand (read+write) hits
767system.cpu.icache.overall_hits::cpu.inst 427825373 # number of overall hits
768system.cpu.icache.overall_hits::total 427825373 # number of overall hits
769system.cpu.icache.ReadReq_misses::cpu.inst 24539229 # number of ReadReq misses
770system.cpu.icache.ReadReq_misses::total 24539229 # number of ReadReq misses
771system.cpu.icache.demand_misses::cpu.inst 24539229 # number of demand (read+write) misses
772system.cpu.icache.demand_misses::total 24539229 # number of demand (read+write) misses
773system.cpu.icache.overall_misses::cpu.inst 24539229 # number of overall misses
774system.cpu.icache.overall_misses::total 24539229 # number of overall misses
775system.cpu.icache.ReadReq_miss_latency::cpu.inst 326974610838 # number of ReadReq miss cycles
776system.cpu.icache.ReadReq_miss_latency::total 326974610838 # number of ReadReq miss cycles
777system.cpu.icache.demand_miss_latency::cpu.inst 326974610838 # number of demand (read+write) miss cycles
778system.cpu.icache.demand_miss_latency::total 326974610838 # number of demand (read+write) miss cycles
779system.cpu.icache.overall_miss_latency::cpu.inst 326974610838 # number of overall miss cycles
780system.cpu.icache.overall_miss_latency::total 326974610838 # number of overall miss cycles
781system.cpu.icache.ReadReq_accesses::cpu.inst 452364602 # number of ReadReq accesses(hits+misses)
782system.cpu.icache.ReadReq_accesses::total 452364602 # number of ReadReq accesses(hits+misses)
783system.cpu.icache.demand_accesses::cpu.inst 452364602 # number of demand (read+write) accesses
784system.cpu.icache.demand_accesses::total 452364602 # number of demand (read+write) accesses
785system.cpu.icache.overall_accesses::cpu.inst 452364602 # number of overall (read+write) accesses
786system.cpu.icache.overall_accesses::total 452364602 # number of overall (read+write) accesses
787system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054247 # miss rate for ReadReq accesses
788system.cpu.icache.ReadReq_miss_rate::total 0.054247 # miss rate for ReadReq accesses
789system.cpu.icache.demand_miss_rate::cpu.inst 0.054247 # miss rate for demand accesses
790system.cpu.icache.demand_miss_rate::total 0.054247 # miss rate for demand accesses
791system.cpu.icache.overall_miss_rate::cpu.inst 0.054247 # miss rate for overall accesses
792system.cpu.icache.overall_miss_rate::total 0.054247 # miss rate for overall accesses
793system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13324.567403 # average ReadReq miss latency
794system.cpu.icache.ReadReq_avg_miss_latency::total 13324.567403 # average ReadReq miss latency
795system.cpu.icache.demand_avg_miss_latency::cpu.inst 13324.567403 # average overall miss latency
796system.cpu.icache.demand_avg_miss_latency::total 13324.567403 # average overall miss latency
797system.cpu.icache.overall_avg_miss_latency::cpu.inst 13324.567403 # average overall miss latency
798system.cpu.icache.overall_avg_miss_latency::total 13324.567403 # average overall miss latency
799system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
800system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
801system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
802system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
803system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
804system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
805system.cpu.icache.fast_writes 0 # number of fast writes performed
806system.cpu.icache.cache_copies 0 # number of cache copies performed
807system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24539229 # number of ReadReq MSHR misses
808system.cpu.icache.ReadReq_mshr_misses::total 24539229 # number of ReadReq MSHR misses
809system.cpu.icache.demand_mshr_misses::cpu.inst 24539229 # number of demand (read+write) MSHR misses
810system.cpu.icache.demand_mshr_misses::total 24539229 # number of demand (read+write) MSHR misses
811system.cpu.icache.overall_mshr_misses::cpu.inst 24539229 # number of overall MSHR misses
812system.cpu.icache.overall_mshr_misses::total 24539229 # number of overall MSHR misses

752system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
753system.cpu.icache.tags.replacements 24538707 # number of replacements
754system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use
755system.cpu.icache.tags.total_refs 427825373 # Total number of references to valid blocks.
756system.cpu.icache.tags.sampled_refs 24539219 # Sample count of references to valid blocks.
757system.cpu.icache.tags.avg_refs 17.434352 # Average number of references to valid blocks.
758system.cpu.icache.tags.warmup_cycle 22330853250 # Cycle when the warmup percentage was hit.
759system.cpu.icache.tags.occ_blocks::cpu.inst 511.926996 # Average occupied blocks per requestor
760system.cpu.icache.tags.occ_percent::cpu.inst 0.999857 # Average percentage of cache occupancy
761system.cpu.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy
762system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
763system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
764system.cpu.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
765system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id
766system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
767system.cpu.icache.tags.tag_accesses 476903830 # Number of tag accesses
768system.cpu.icache.tags.data_accesses 476903830 # Number of data accesses
769system.cpu.icache.ReadReq_hits::cpu.inst 427825373 # number of ReadReq hits
770system.cpu.icache.ReadReq_hits::total 427825373 # number of ReadReq hits
771system.cpu.icache.demand_hits::cpu.inst 427825373 # number of demand (read+write) hits
772system.cpu.icache.demand_hits::total 427825373 # number of demand (read+write) hits
773system.cpu.icache.overall_hits::cpu.inst 427825373 # number of overall hits
774system.cpu.icache.overall_hits::total 427825373 # number of overall hits
775system.cpu.icache.ReadReq_misses::cpu.inst 24539229 # number of ReadReq misses
776system.cpu.icache.ReadReq_misses::total 24539229 # number of ReadReq misses
777system.cpu.icache.demand_misses::cpu.inst 24539229 # number of demand (read+write) misses
778system.cpu.icache.demand_misses::total 24539229 # number of demand (read+write) misses
779system.cpu.icache.overall_misses::cpu.inst 24539229 # number of overall misses
780system.cpu.icache.overall_misses::total 24539229 # number of overall misses
781system.cpu.icache.ReadReq_miss_latency::cpu.inst 326974610838 # number of ReadReq miss cycles
782system.cpu.icache.ReadReq_miss_latency::total 326974610838 # number of ReadReq miss cycles
783system.cpu.icache.demand_miss_latency::cpu.inst 326974610838 # number of demand (read+write) miss cycles
784system.cpu.icache.demand_miss_latency::total 326974610838 # number of demand (read+write) miss cycles
785system.cpu.icache.overall_miss_latency::cpu.inst 326974610838 # number of overall miss cycles
786system.cpu.icache.overall_miss_latency::total 326974610838 # number of overall miss cycles
787system.cpu.icache.ReadReq_accesses::cpu.inst 452364602 # number of ReadReq accesses(hits+misses)
788system.cpu.icache.ReadReq_accesses::total 452364602 # number of ReadReq accesses(hits+misses)
789system.cpu.icache.demand_accesses::cpu.inst 452364602 # number of demand (read+write) accesses
790system.cpu.icache.demand_accesses::total 452364602 # number of demand (read+write) accesses
791system.cpu.icache.overall_accesses::cpu.inst 452364602 # number of overall (read+write) accesses
792system.cpu.icache.overall_accesses::total 452364602 # number of overall (read+write) accesses
793system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054247 # miss rate for ReadReq accesses
794system.cpu.icache.ReadReq_miss_rate::total 0.054247 # miss rate for ReadReq accesses
795system.cpu.icache.demand_miss_rate::cpu.inst 0.054247 # miss rate for demand accesses
796system.cpu.icache.demand_miss_rate::total 0.054247 # miss rate for demand accesses
797system.cpu.icache.overall_miss_rate::cpu.inst 0.054247 # miss rate for overall accesses
798system.cpu.icache.overall_miss_rate::total 0.054247 # miss rate for overall accesses
799system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13324.567403 # average ReadReq miss latency
800system.cpu.icache.ReadReq_avg_miss_latency::total 13324.567403 # average ReadReq miss latency
801system.cpu.icache.demand_avg_miss_latency::cpu.inst 13324.567403 # average overall miss latency
802system.cpu.icache.demand_avg_miss_latency::total 13324.567403 # average overall miss latency
803system.cpu.icache.overall_avg_miss_latency::cpu.inst 13324.567403 # average overall miss latency
804system.cpu.icache.overall_avg_miss_latency::total 13324.567403 # average overall miss latency
805system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
806system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
807system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
808system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
809system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
810system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
811system.cpu.icache.fast_writes 0 # number of fast writes performed
812system.cpu.icache.cache_copies 0 # number of cache copies performed
813system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24539229 # number of ReadReq MSHR misses
814system.cpu.icache.ReadReq_mshr_misses::total 24539229 # number of ReadReq MSHR misses
815system.cpu.icache.demand_mshr_misses::cpu.inst 24539229 # number of demand (read+write) MSHR misses
816system.cpu.icache.demand_mshr_misses::total 24539229 # number of demand (read+write) MSHR misses
817system.cpu.icache.overall_mshr_misses::cpu.inst 24539229 # number of overall MSHR misses
818system.cpu.icache.overall_mshr_misses::total 24539229 # number of overall MSHR misses

819system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable
820system.cpu.icache.ReadReq_mshr_uncacheable::total 52294 # number of ReadReq MSHR uncacheable
821system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses
822system.cpu.icache.overall_mshr_uncacheable_misses::total 52294 # number of overall MSHR uncacheable misses

813system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082 # number of ReadReq MSHR miss cycles
814system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082 # number of ReadReq MSHR miss cycles
815system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082 # number of demand (read+write) MSHR miss cycles
816system.cpu.icache.demand_mshr_miss_latency::total 290116862082 # number of demand (read+write) MSHR miss cycles
817system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290116862082 # number of overall MSHR miss cycles
818system.cpu.icache.overall_mshr_miss_latency::total 290116862082 # number of overall MSHR miss cycles
819system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4024065500 # number of ReadReq MSHR uncacheable cycles
820system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4024065500 # number of ReadReq MSHR uncacheable cycles
821system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4024065500 # number of overall MSHR uncacheable cycles
822system.cpu.icache.overall_mshr_uncacheable_latency::total 4024065500 # number of overall MSHR uncacheable cycles
823system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for ReadReq accesses
824system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054247 # mshr miss rate for ReadReq accesses
825system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for demand accesses
826system.cpu.icache.demand_mshr_miss_rate::total 0.054247 # mshr miss rate for demand accesses
827system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for overall accesses
828system.cpu.icache.overall_mshr_miss_rate::total 0.054247 # mshr miss rate for overall accesses
829system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11822.574462 # average ReadReq mshr miss latency
830system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11822.574462 # average ReadReq mshr miss latency
831system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency
832system.cpu.icache.demand_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency
833system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency
834system.cpu.icache.overall_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency

823system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082 # number of ReadReq MSHR miss cycles
824system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082 # number of ReadReq MSHR miss cycles
825system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082 # number of demand (read+write) MSHR miss cycles
826system.cpu.icache.demand_mshr_miss_latency::total 290116862082 # number of demand (read+write) MSHR miss cycles
827system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290116862082 # number of overall MSHR miss cycles
828system.cpu.icache.overall_mshr_miss_latency::total 290116862082 # number of overall MSHR miss cycles
829system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4024065500 # number of ReadReq MSHR uncacheable cycles
830system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4024065500 # number of ReadReq MSHR uncacheable cycles
831system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4024065500 # number of overall MSHR uncacheable cycles
832system.cpu.icache.overall_mshr_uncacheable_latency::total 4024065500 # number of overall MSHR uncacheable cycles
833system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for ReadReq accesses
834system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054247 # mshr miss rate for ReadReq accesses
835system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for demand accesses
836system.cpu.icache.demand_mshr_miss_rate::total 0.054247 # mshr miss rate for demand accesses
837system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for overall accesses
838system.cpu.icache.overall_mshr_miss_rate::total 0.054247 # mshr miss rate for overall accesses
839system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11822.574462 # average ReadReq mshr miss latency
840system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11822.574462 # average ReadReq mshr miss latency
841system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency
842system.cpu.icache.demand_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency
843system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency
844system.cpu.icache.overall_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency

835system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
836system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
837system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
838system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

845system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average ReadReq mshr uncacheable latency
846system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76950.806976 # average ReadReq mshr uncacheable latency
847system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average overall mshr uncacheable latency
848system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76950.806976 # average overall mshr uncacheable latency

839system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
840system.cpu.l2cache.tags.replacements 1594461 # number of replacements
841system.cpu.l2cache.tags.tagsinuse 65370.145273 # Cycle average of tags in use
842system.cpu.l2cache.tags.total_refs 40075906 # Total number of references to valid blocks.
843system.cpu.l2cache.tags.sampled_refs 1658209 # Sample count of references to valid blocks.
844system.cpu.l2cache.tags.avg_refs 24.168187 # Average number of references to valid blocks.
845system.cpu.l2cache.tags.warmup_cycle 6394381000 # Cycle when the warmup percentage was hit.
846system.cpu.l2cache.tags.occ_blocks::writebacks 36356.724167 # Average occupied blocks per requestor
847system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 340.112458 # Average occupied blocks per requestor
848system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 426.747711 # Average occupied blocks per requestor
849system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.252666 # Average occupied blocks per requestor
850system.cpu.l2cache.tags.occ_blocks::cpu.data 20073.308271 # Average occupied blocks per requestor
851system.cpu.l2cache.tags.occ_percent::writebacks 0.554760 # Average percentage of cache occupancy
852system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005190 # Average percentage of cache occupancy
853system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006512 # Average percentage of cache occupancy
854system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124714 # Average percentage of cache occupancy
855system.cpu.l2cache.tags.occ_percent::cpu.data 0.306294 # Average percentage of cache occupancy
856system.cpu.l2cache.tags.occ_percent::total 0.997469 # Average percentage of cache occupancy
857system.cpu.l2cache.tags.occ_task_id_blocks::1023 294 # Occupied blocks per task id
858system.cpu.l2cache.tags.occ_task_id_blocks::1024 63454 # Occupied blocks per task id
859system.cpu.l2cache.tags.age_task_id_blocks_1023::4 294 # Occupied blocks per task id
860system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
861system.cpu.l2cache.tags.age_task_id_blocks_1024::1 492 # Occupied blocks per task id
862system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2445 # Occupied blocks per task id
863system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5512 # Occupied blocks per task id
864system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54953 # Occupied blocks per task id
865system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id
866system.cpu.l2cache.tags.occ_task_id_percent::1024 0.968231 # Percentage of cache occupancy per task id
867system.cpu.l2cache.tags.tag_accesses 368332557 # Number of tag accesses
868system.cpu.l2cache.tags.data_accesses 368332557 # Number of data accesses
869system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 961086 # number of ReadReq hits
870system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 281097 # number of ReadReq hits
871system.cpu.l2cache.ReadReq_hits::cpu.inst 24431679 # number of ReadReq hits
872system.cpu.l2cache.ReadReq_hits::cpu.data 7167695 # number of ReadReq hits
873system.cpu.l2cache.ReadReq_hits::total 32841557 # number of ReadReq hits
874system.cpu.l2cache.Writeback_hits::writebacks 8509656 # number of Writeback hits
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921system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 5340829 # number of WriteInvalidateReq miss cycles
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923system.cpu.l2cache.UpgradeReq_miss_latency::total 585352278 # number of UpgradeReq miss cycles
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927system.cpu.l2cache.ReadExReq_miss_latency::total 57779848170 # number of ReadExReq miss cycles
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935system.cpu.l2cache.overall_miss_latency::cpu.inst 8825389448 # number of overall miss cycles
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937system.cpu.l2cache.overall_miss_latency::total 95123969923 # number of overall miss cycles
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944system.cpu.l2cache.Writeback_accesses::total 8509656 # number of Writeback accesses(hits+misses)
945system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1244454 # number of WriteInvalidateReq accesses(hits+misses)
946system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244454 # number of WriteInvalidateReq accesses(hits+misses)
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952system.cpu.l2cache.ReadExReq_accesses::total 2357319 # number of ReadExReq accesses(hits+misses)
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954system.cpu.l2cache.demand_accesses::cpu.itb.walker 286287 # number of demand (read+write) accesses
955system.cpu.l2cache.demand_accesses::cpu.inst 24539226 # number of demand (read+write) accesses
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959system.cpu.l2cache.overall_accesses::cpu.itb.walker 286287 # number of overall (read+write) accesses
960system.cpu.l2cache.overall_accesses::cpu.inst 24539226 # number of overall (read+write) accesses
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964system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018129 # miss rate for ReadReq accesses
965system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004383 # miss rate for ReadReq accesses
966system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043180 # miss rate for ReadReq accesses
967system.cpu.l2cache.ReadReq_miss_rate::total 0.013293 # miss rate for ReadReq accesses
968system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.436398 # miss rate for WriteInvalidateReq accesses
969system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.436398 # miss rate for WriteInvalidateReq accesses
970system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.781892 # miss rate for UpgradeReq accesses
971system.cpu.l2cache.UpgradeReq_miss_rate::total 0.781892 # miss rate for UpgradeReq accesses
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973system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
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975system.cpu.l2cache.ReadExReq_miss_rate::total 0.297836 # miss rate for ReadExReq accesses
976system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006438 # miss rate for demand accesses
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978system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004383 # miss rate for demand accesses
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982system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018129 # miss rate for overall accesses
983system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004383 # miss rate for overall accesses
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985system.cpu.l2cache.overall_miss_rate::total 0.032113 # miss rate for overall accesses
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987system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87144.460501 # average ReadReq miss latency
988system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82060.768297 # average ReadReq miss latency
989system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85101.234564 # average ReadReq miss latency
990system.cpu.l2cache.ReadReq_avg_miss_latency::total 84405.512543 # average ReadReq miss latency
991system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 9.834386 # average WriteInvalidateReq miss latency
992system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 9.834386 # average WriteInvalidateReq miss latency
993system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15187.781272 # average UpgradeReq miss latency
994system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15187.781272 # average UpgradeReq miss latency
995system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
996system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
997system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82296.339057 # average ReadExReq miss latency
998system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82296.339057 # average ReadExReq miss latency
999system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86478.164419 # average overall miss latency
1000system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87144.460501 # average overall miss latency
1001system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82060.768297 # average overall miss latency
1002system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.025440 # average overall miss latency
1003system.cpu.l2cache.demand_avg_miss_latency::total 83111.673525 # average overall miss latency
1004system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86478.164419 # average overall miss latency
1005system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87144.460501 # average overall miss latency
1006system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82060.768297 # average overall miss latency
1007system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.025440 # average overall miss latency
1008system.cpu.l2cache.overall_avg_miss_latency::total 83111.673525 # average overall miss latency
1009system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1010system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1011system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1012system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1013system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1014system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1015system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1016system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1017system.cpu.l2cache.writebacks::writebacks 1362005 # number of writebacks
1018system.cpu.l2cache.writebacks::total 1362005 # number of writebacks
1019system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
1020system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
1021system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits
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1023system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
1024system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits
1025system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1026system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
1027system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits
1028system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6228 # number of ReadReq MSHR misses
1029system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5190 # number of ReadReq MSHR misses
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1031system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 323451 # number of ReadReq MSHR misses
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1033system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 543077 # number of WriteInvalidateReq MSHR misses
1034system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 543077 # number of WriteInvalidateReq MSHR misses
1035system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38541 # number of UpgradeReq MSHR misses
1036system.cpu.l2cache.UpgradeReq_mshr_misses::total 38541 # number of UpgradeReq MSHR misses
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1038system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
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1048system.cpu.l2cache.overall_mshr_misses::cpu.inst 107545 # number of overall MSHR misses
1049system.cpu.l2cache.overall_mshr_misses::cpu.data 1025546 # number of overall MSHR misses
1050system.cpu.l2cache.overall_mshr_misses::total 1144509 # number of overall MSHR misses

849system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
850system.cpu.l2cache.tags.replacements 1594461 # number of replacements
851system.cpu.l2cache.tags.tagsinuse 65370.145273 # Cycle average of tags in use
852system.cpu.l2cache.tags.total_refs 40075906 # Total number of references to valid blocks.
853system.cpu.l2cache.tags.sampled_refs 1658209 # Sample count of references to valid blocks.
854system.cpu.l2cache.tags.avg_refs 24.168187 # Average number of references to valid blocks.
855system.cpu.l2cache.tags.warmup_cycle 6394381000 # Cycle when the warmup percentage was hit.
856system.cpu.l2cache.tags.occ_blocks::writebacks 36356.724167 # Average occupied blocks per requestor
857system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 340.112458 # Average occupied blocks per requestor
858system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 426.747711 # Average occupied blocks per requestor
859system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.252666 # Average occupied blocks per requestor
860system.cpu.l2cache.tags.occ_blocks::cpu.data 20073.308271 # Average occupied blocks per requestor
861system.cpu.l2cache.tags.occ_percent::writebacks 0.554760 # Average percentage of cache occupancy
862system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005190 # Average percentage of cache occupancy
863system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006512 # Average percentage of cache occupancy
864system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124714 # Average percentage of cache occupancy
865system.cpu.l2cache.tags.occ_percent::cpu.data 0.306294 # Average percentage of cache occupancy
866system.cpu.l2cache.tags.occ_percent::total 0.997469 # Average percentage of cache occupancy
867system.cpu.l2cache.tags.occ_task_id_blocks::1023 294 # Occupied blocks per task id
868system.cpu.l2cache.tags.occ_task_id_blocks::1024 63454 # Occupied blocks per task id
869system.cpu.l2cache.tags.age_task_id_blocks_1023::4 294 # Occupied blocks per task id
870system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
871system.cpu.l2cache.tags.age_task_id_blocks_1024::1 492 # Occupied blocks per task id
872system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2445 # Occupied blocks per task id
873system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5512 # Occupied blocks per task id
874system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54953 # Occupied blocks per task id
875system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id
876system.cpu.l2cache.tags.occ_task_id_percent::1024 0.968231 # Percentage of cache occupancy per task id
877system.cpu.l2cache.tags.tag_accesses 368332557 # Number of tag accesses
878system.cpu.l2cache.tags.data_accesses 368332557 # Number of data accesses
879system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 961086 # number of ReadReq hits
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883system.cpu.l2cache.ReadReq_hits::total 32841557 # number of ReadReq hits
884system.cpu.l2cache.Writeback_hits::writebacks 8509656 # number of Writeback hits
885system.cpu.l2cache.Writeback_hits::total 8509656 # number of Writeback hits
886system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 701377 # number of WriteInvalidateReq hits
887system.cpu.l2cache.WriteInvalidateReq_hits::total 701377 # number of WriteInvalidateReq hits
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889system.cpu.l2cache.UpgradeReq_hits::total 10751 # number of UpgradeReq hits
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891system.cpu.l2cache.ReadExReq_hits::total 1655224 # number of ReadExReq hits
892system.cpu.l2cache.demand_hits::cpu.dtb.walker 961086 # number of demand (read+write) hits
893system.cpu.l2cache.demand_hits::cpu.itb.walker 281097 # number of demand (read+write) hits
894system.cpu.l2cache.demand_hits::cpu.inst 24431679 # number of demand (read+write) hits
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898system.cpu.l2cache.overall_hits::cpu.itb.walker 281097 # number of overall hits
899system.cpu.l2cache.overall_hits::cpu.inst 24431679 # number of overall hits
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901system.cpu.l2cache.overall_hits::total 34496781 # number of overall hits
902system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6228 # number of ReadReq misses
903system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5190 # number of ReadReq misses
904system.cpu.l2cache.ReadReq_misses::cpu.inst 107547 # number of ReadReq misses
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906system.cpu.l2cache.ReadReq_misses::total 442437 # number of ReadReq misses
907system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 543077 # number of WriteInvalidateReq misses
908system.cpu.l2cache.WriteInvalidateReq_misses::total 543077 # number of WriteInvalidateReq misses
909system.cpu.l2cache.UpgradeReq_misses::cpu.data 38541 # number of UpgradeReq misses
910system.cpu.l2cache.UpgradeReq_misses::total 38541 # number of UpgradeReq misses
911system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
912system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
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915system.cpu.l2cache.demand_misses::cpu.dtb.walker 6228 # number of demand (read+write) misses
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1083system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for ReadReq accesses
1084system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for ReadReq accesses
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1087system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.436398 # mshr miss rate for WriteInvalidateReq accesses
1088system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.436398 # mshr miss rate for WriteInvalidateReq accesses
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1090system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781892 # mshr miss rate for UpgradeReq accesses
1091system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
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1116system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.835215 # average ReadExReq mshr miss latency
1117system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.835215 # average ReadExReq mshr miss latency
1118system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average overall mshr miss latency
1119system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average overall mshr miss latency
1120system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency
1121system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency
1122system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency
1123system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average overall mshr miss latency
1124system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average overall mshr miss latency
1125system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency
1126system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency
1127system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency

1069system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 460278992 # number of ReadReq MSHR miss cycles
1070system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 386982750 # number of ReadReq MSHR miss cycles
1071system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7477222552 # number of ReadReq MSHR miss cycles
1072system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23476189203 # number of ReadReq MSHR miss cycles
1073system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31800673497 # number of ReadReq MSHR miss cycles
1074system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 18301171671 # number of WriteInvalidateReq MSHR miss cycles
1075system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18301171671 # number of WriteInvalidateReq MSHR miss cycles
1076system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 683876035 # number of UpgradeReq MSHR miss cycles
1077system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 683876035 # number of UpgradeReq MSHR miss cycles
1078system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 67500 # number of SCUpgradeReq MSHR miss cycles
1079system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 67500 # number of SCUpgradeReq MSHR miss cycles
1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49002604830 # number of ReadExReq MSHR miss cycles
1081system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49002604830 # number of ReadExReq MSHR miss cycles
1082system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 460278992 # number of demand (read+write) MSHR miss cycles
1083system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 386982750 # number of demand (read+write) MSHR miss cycles
1084system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7477222552 # number of demand (read+write) MSHR miss cycles
1085system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 72478794033 # number of demand (read+write) MSHR miss cycles
1086system.cpu.l2cache.demand_mshr_miss_latency::total 80803278327 # number of demand (read+write) MSHR miss cycles
1087system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 460278992 # number of overall MSHR miss cycles
1088system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 386982750 # number of overall MSHR miss cycles
1089system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7477222552 # number of overall MSHR miss cycles
1090system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 72478794033 # number of overall MSHR miss cycles
1091system.cpu.l2cache.overall_mshr_miss_latency::total 80803278327 # number of overall MSHR miss cycles
1092system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3108920000 # number of ReadReq MSHR uncacheable cycles
1093system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279396750 # number of ReadReq MSHR uncacheable cycles
1094system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8388316750 # number of ReadReq MSHR uncacheable cycles
1095system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5172507000 # number of WriteReq MSHR uncacheable cycles
1096system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5172507000 # number of WriteReq MSHR uncacheable cycles
1097system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3108920000 # number of overall MSHR uncacheable cycles
1098system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10451903750 # number of overall MSHR uncacheable cycles
1099system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13560823750 # number of overall MSHR uncacheable cycles
1100system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006438 # mshr miss rate for ReadReq accesses
1101system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for ReadReq accesses
1102system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for ReadReq accesses
1103system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.043178 # mshr miss rate for ReadReq accesses
1104system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013292 # mshr miss rate for ReadReq accesses
1105system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.436398 # mshr miss rate for WriteInvalidateReq accesses
1106system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.436398 # mshr miss rate for WriteInvalidateReq accesses
1107system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781892 # mshr miss rate for UpgradeReq accesses
1108system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781892 # mshr miss rate for UpgradeReq accesses
1109system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1110system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1111system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.297836 # mshr miss rate for ReadExReq accesses
1112system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.297836 # mshr miss rate for ReadExReq accesses
1113system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006438 # mshr miss rate for demand accesses
1114system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for demand accesses
1115system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for demand accesses
1116system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104132 # mshr miss rate for demand accesses
1117system.cpu.l2cache.demand_mshr_miss_rate::total 0.032112 # mshr miss rate for demand accesses
1118system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006438 # mshr miss rate for overall accesses
1119system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for overall accesses
1120system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for overall accesses
1121system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104132 # mshr miss rate for overall accesses
1122system.cpu.l2cache.overall_mshr_miss_rate::total 0.032112 # mshr miss rate for overall accesses
1123system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average ReadReq mshr miss latency
1124system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average ReadReq mshr miss latency
1125system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69526.454526 # average ReadReq mshr miss latency
1126system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72580.357467 # average ReadReq mshr miss latency
1127system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71879.898685 # average ReadReq mshr miss latency
1128system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33699.036547 # average WriteInvalidateReq mshr miss latency
1129system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33699.036547 # average WriteInvalidateReq mshr miss latency
1130system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17744.117563 # average UpgradeReq mshr miss latency
1131system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17744.117563 # average UpgradeReq mshr miss latency
1132system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency
1133system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency
1134system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.835215 # average ReadExReq mshr miss latency
1135system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.835215 # average ReadExReq mshr miss latency
1136system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average overall mshr miss latency
1137system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average overall mshr miss latency
1138system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency
1139system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency
1140system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency
1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558 # average overall mshr miss latency
1142system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 # average overall mshr miss latency
1143system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency
1144system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency
1145system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency

1128system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1129system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1130system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1131system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1132system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1133system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1134system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1135system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

1146system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average ReadReq mshr uncacheable latency
1147system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156677.253977 # average ReadReq mshr uncacheable latency
1148system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97549.909873 # average ReadReq mshr uncacheable latency
1149system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153464.085447 # average WriteReq mshr uncacheable latency
1150system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153464.085447 # average WriteReq mshr uncacheable latency
1151system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average overall mshr uncacheable latency
1152system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155070.455186 # average overall mshr uncacheable latency
1153system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113294.822257 # average overall mshr uncacheable latency

1136system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1137system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution
1138system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution
1139system.cpu.toL2Bus.trans_dist::WriteReq 33705 # Transaction distribution
1140system.cpu.toL2Bus.trans_dist::WriteResp 33705 # Transaction distribution
1141system.cpu.toL2Bus.trans_dist::Writeback 8509656 # Transaction distribution
1142system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351233 # Transaction distribution
1143system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244454 # Transaction distribution
1144system.cpu.toL2Bus.trans_dist::UpgradeReq 49295 # Transaction distribution
1145system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
1146system.cpu.toL2Bus.trans_dist::UpgradeResp 49296 # Transaction distribution
1147system.cpu.toL2Bus.trans_dist::ReadExReq 2357319 # Transaction distribution
1148system.cpu.toL2Bus.trans_dist::ReadExResp 2357319 # Transaction distribution
1149system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49183042 # Packet count per connected master and slave (bytes)
1150system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30929702 # Packet count per connected master and slave (bytes)
1151system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 693856 # Packet count per connected master and slave (bytes)
1152system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2262449 # Packet count per connected master and slave (bytes)
1153system.cpu.toL2Bus.pkt_count::total 83069049 # Packet count per connected master and slave (bytes)
1154system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1573857216 # Cumulative packet size per connected master and slave (bytes)
1155system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1254806154 # Cumulative packet size per connected master and slave (bytes)
1156system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2290296 # Cumulative packet size per connected master and slave (bytes)
1157system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes)
1158system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes)
1159system.cpu.toL2Bus.snoops 565529 # Total snoops (count)

1154system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1155system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution
1156system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution
1157system.cpu.toL2Bus.trans_dist::WriteReq 33705 # Transaction distribution
1158system.cpu.toL2Bus.trans_dist::WriteResp 33705 # Transaction distribution
1159system.cpu.toL2Bus.trans_dist::Writeback 8509656 # Transaction distribution
1160system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351233 # Transaction distribution
1161system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244454 # Transaction distribution
1162system.cpu.toL2Bus.trans_dist::UpgradeReq 49295 # Transaction distribution
1163system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
1164system.cpu.toL2Bus.trans_dist::UpgradeResp 49296 # Transaction distribution
1165system.cpu.toL2Bus.trans_dist::ReadExReq 2357319 # Transaction distribution
1166system.cpu.toL2Bus.trans_dist::ReadExResp 2357319 # Transaction distribution
1167system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49183042 # Packet count per connected master and slave (bytes)
1168system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30929702 # Packet count per connected master and slave (bytes)
1169system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 693856 # Packet count per connected master and slave (bytes)
1170system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2262449 # Packet count per connected master and slave (bytes)
1171system.cpu.toL2Bus.pkt_count::total 83069049 # Packet count per connected master and slave (bytes)
1172system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1573857216 # Cumulative packet size per connected master and slave (bytes)
1173system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1254806154 # Cumulative packet size per connected master and slave (bytes)
1174system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2290296 # Cumulative packet size per connected master and slave (bytes)
1175system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes)
1176system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes)
1177system.cpu.toL2Bus.snoops 565529 # Total snoops (count)

1160system.cpu.toL2Bus.snoop_fanout::samples 46009467 # Request fanout histogram
1161system.cpu.toL2Bus.snoop_fanout::mean 3.002514 # Request fanout histogram
1162system.cpu.toL2Bus.snoop_fanout::stdev 0.050072 # Request fanout histogram

1178system.cpu.toL2Bus.snoop_fanout::samples 46129162 # Request fanout histogram
1179system.cpu.toL2Bus.snoop_fanout::mean 1.039419 # Request fanout histogram
1180system.cpu.toL2Bus.snoop_fanout::stdev 0.194589 # Request fanout histogram

1163system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1164system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1181system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1182system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1165system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1166system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1167system.cpu.toL2Bus.snoop_fanout::3 45893822 99.75% 99.75% # Request fanout histogram
1168system.cpu.toL2Bus.snoop_fanout::4 115645 0.25% 100.00% # Request fanout histogram

1183system.cpu.toL2Bus.snoop_fanout::1 44310813 96.06% 96.06% # Request fanout histogram
1184system.cpu.toL2Bus.snoop_fanout::2 1818349 3.94% 100.00% # Request fanout histogram

1169system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1185system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1170system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1171system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1172system.cpu.toL2Bus.snoop_fanout::total 46009467 # Request fanout histogram

1186system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1187system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1188system.cpu.toL2Bus.snoop_fanout::total 46129162 # Request fanout histogram

1173system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks)
1174system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1175system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks)
1176system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1177system.cpu.toL2Bus.respLayer0.occupancy 36924053878 # Layer occupancy (ticks)
1178system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1179system.cpu.toL2Bus.respLayer1.occupancy 15679140875 # Layer occupancy (ticks)
1180system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1181system.cpu.toL2Bus.respLayer2.occupancy 408249695 # Layer occupancy (ticks)
1182system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1183system.cpu.toL2Bus.respLayer3.occupancy 1295905979 # Layer occupancy (ticks)
1184system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1185system.iobus.trans_dist::ReadReq 40311 # Transaction distribution
1186system.iobus.trans_dist::ReadResp 40311 # Transaction distribution
1187system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1188system.iobus.trans_dist::WriteResp 29907 # Transaction distribution
1189system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
1190system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1191system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1192system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1193system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1194system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1195system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1196system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1197system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1198system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1199system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1200system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1201system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1202system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1203system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1204system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1205system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
1206system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes)
1207system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes)
1208system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1209system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1210system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes)
1211system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
1212system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1213system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1214system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1215system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1216system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1217system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1218system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1219system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1220system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1221system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1222system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
1223system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1224system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
1225system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1226system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
1227system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes)
1228system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes)
1229system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1230system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1231system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes)
1232system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
1233system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1234system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
1235system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1236system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
1237system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1238system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
1239system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1240system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1241system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1242system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1243system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1244system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1245system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1246system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1247system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1248system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1249system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1250system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1251system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1252system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
1253system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1254system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
1255system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1256system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
1257system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1258system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
1259system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1260system.iobus.reqLayer27.occupancy 607011706 # Layer occupancy (ticks)
1261system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1262system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1263system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1264system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1265system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1266system.iobus.respLayer3.occupancy 148422470 # Layer occupancy (ticks)
1267system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1268system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks)
1269system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1270system.iocache.tags.replacements 115472 # number of replacements
1271system.iocache.tags.tagsinuse 10.439528 # Cycle average of tags in use
1272system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1273system.iocache.tags.sampled_refs 115488 # Sample count of references to valid blocks.
1274system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1275system.iocache.tags.warmup_cycle 13142428728000 # Cycle when the warmup percentage was hit.
1276system.iocache.tags.occ_blocks::realview.ethernet 3.524738 # Average occupied blocks per requestor
1277system.iocache.tags.occ_blocks::realview.ide 6.914790 # Average occupied blocks per requestor
1278system.iocache.tags.occ_percent::realview.ethernet 0.220296 # Average percentage of cache occupancy
1279system.iocache.tags.occ_percent::realview.ide 0.432174 # Average percentage of cache occupancy
1280system.iocache.tags.occ_percent::total 0.652471 # Average percentage of cache occupancy
1281system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1282system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1283system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1284system.iocache.tags.tag_accesses 1039767 # Number of tag accesses
1285system.iocache.tags.data_accesses 1039767 # Number of data accesses
1286system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1287system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses
1288system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses
1289system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1290system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1291system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
1292system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
1293system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1294system.iocache.demand_misses::realview.ide 8826 # number of demand (read+write) misses
1295system.iocache.demand_misses::total 8866 # number of demand (read+write) misses
1296system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1297system.iocache.overall_misses::realview.ide 8826 # number of overall misses
1298system.iocache.overall_misses::total 8866 # number of overall misses
1299system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
1300system.iocache.ReadReq_miss_latency::realview.ide 1599431674 # number of ReadReq miss cycles
1301system.iocache.ReadReq_miss_latency::total 1604503674 # number of ReadReq miss cycles
1302system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles
1303system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles
1304system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19839532562 # number of WriteInvalidateReq miss cycles
1305system.iocache.WriteInvalidateReq_miss_latency::total 19839532562 # number of WriteInvalidateReq miss cycles
1306system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles
1307system.iocache.demand_miss_latency::realview.ide 1599431674 # number of demand (read+write) miss cycles
1308system.iocache.demand_miss_latency::total 1604856174 # number of demand (read+write) miss cycles
1309system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles
1310system.iocache.overall_miss_latency::realview.ide 1599431674 # number of overall miss cycles
1311system.iocache.overall_miss_latency::total 1604856174 # number of overall miss cycles
1312system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1313system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses)
1314system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses)
1315system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1316system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1317system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
1318system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
1319system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1320system.iocache.demand_accesses::realview.ide 8826 # number of demand (read+write) accesses
1321system.iocache.demand_accesses::total 8866 # number of demand (read+write) accesses
1322system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1323system.iocache.overall_accesses::realview.ide 8826 # number of overall (read+write) accesses
1324system.iocache.overall_accesses::total 8866 # number of overall (read+write) accesses
1325system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1326system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1327system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1328system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1329system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1330system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
1331system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1332system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1333system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1334system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1335system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1336system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1337system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1338system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
1339system.iocache.ReadReq_avg_miss_latency::realview.ide 181218.181962 # average ReadReq miss latency
1340system.iocache.ReadReq_avg_miss_latency::total 181033.924630 # average ReadReq miss latency
1341system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency
1342system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency
1343system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186000.267775 # average WriteInvalidateReq miss latency
1344system.iocache.WriteInvalidateReq_avg_miss_latency::total 186000.267775 # average WriteInvalidateReq miss latency
1345system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
1346system.iocache.demand_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency
1347system.iocache.demand_avg_miss_latency::total 181012.426573 # average overall miss latency
1348system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
1349system.iocache.overall_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency
1350system.iocache.overall_avg_miss_latency::total 181012.426573 # average overall miss latency
1351system.iocache.blocked_cycles::no_mshrs 109629 # number of cycles access was blocked
1352system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1353system.iocache.blocked::no_mshrs 16167 # number of cycles access was blocked
1354system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1355system.iocache.avg_blocked_cycles::no_mshrs 6.781035 # average number of cycles each access was blocked
1356system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1357system.iocache.fast_writes 0 # number of fast writes performed
1358system.iocache.cache_copies 0 # number of cache copies performed
1359system.iocache.writebacks::writebacks 106631 # number of writebacks
1360system.iocache.writebacks::total 106631 # number of writebacks
1361system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1362system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses
1363system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses
1364system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1365system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1366system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
1367system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
1368system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1369system.iocache.demand_mshr_misses::realview.ide 8826 # number of demand (read+write) MSHR misses
1370system.iocache.demand_mshr_misses::total 8866 # number of demand (read+write) MSHR misses
1371system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1372system.iocache.overall_mshr_misses::realview.ide 8826 # number of overall MSHR misses
1373system.iocache.overall_mshr_misses::total 8866 # number of overall MSHR misses
1374system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles
1375system.iocache.ReadReq_mshr_miss_latency::realview.ide 1139388578 # number of ReadReq MSHR miss cycles
1376system.iocache.ReadReq_mshr_miss_latency::total 1142530578 # number of ReadReq MSHR miss cycles
1377system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles
1378system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles
1379system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14292968598 # number of WriteInvalidateReq MSHR miss cycles
1380system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14292968598 # number of WriteInvalidateReq MSHR miss cycles
1381system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles
1382system.iocache.demand_mshr_miss_latency::realview.ide 1139388578 # number of demand (read+write) MSHR miss cycles
1383system.iocache.demand_mshr_miss_latency::total 1142724078 # number of demand (read+write) MSHR miss cycles
1384system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles
1385system.iocache.overall_mshr_miss_latency::realview.ide 1139388578 # number of overall MSHR miss cycles
1386system.iocache.overall_mshr_miss_latency::total 1142724078 # number of overall MSHR miss cycles
1387system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1388system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1389system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1390system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1391system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1392system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1393system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1394system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1395system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1396system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1397system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1398system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1399system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1400system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency
1401system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129094.559030 # average ReadReq mshr miss latency
1402system.iocache.ReadReq_avg_mshr_miss_latency::total 128910.140810 # average ReadReq mshr miss latency
1403system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency
1404system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency
1405system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133999.930605 # average WriteInvalidateReq mshr miss latency
1406system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133999.930605 # average WriteInvalidateReq mshr miss latency
1407system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
1408system.iocache.demand_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency
1409system.iocache.demand_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency
1410system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
1411system.iocache.overall_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency
1412system.iocache.overall_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency
1413system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1414system.membus.trans_dist::ReadReq 537267 # Transaction distribution
1415system.membus.trans_dist::ReadResp 537267 # Transaction distribution
1416system.membus.trans_dist::WriteReq 33705 # Transaction distribution
1417system.membus.trans_dist::WriteResp 33705 # Transaction distribution
1418system.membus.trans_dist::Writeback 1468636 # Transaction distribution
1419system.membus.trans_dist::WriteInvalidateReq 649570 # Transaction distribution
1420system.membus.trans_dist::WriteInvalidateResp 649570 # Transaction distribution
1421system.membus.trans_dist::UpgradeReq 39342 # Transaction distribution
1422system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
1423system.membus.trans_dist::UpgradeResp 39343 # Transaction distribution
1424system.membus.trans_dist::ReadExReq 701468 # Transaction distribution
1425system.membus.trans_dist::ReadExResp 701468 # Transaction distribution
1426system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
1427system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes)
1428system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6912 # Packet count per connected master and slave (bytes)
1429system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4923341 # Packet count per connected master and slave (bytes)
1430system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5052989 # Packet count per connected master and slave (bytes)
1431system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335373 # Packet count per connected master and slave (bytes)
1432system.membus.pkt_count_system.iocache.mem_side::total 335373 # Packet count per connected master and slave (bytes)
1433system.membus.pkt_count::total 5388362 # Packet count per connected master and slave (bytes)
1434system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
1435system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes)
1436system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13824 # Cumulative packet size per connected master and slave (bytes)
1437system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198447468 # Cumulative packet size per connected master and slave (bytes)
1438system.membus.pkt_size_system.cpu.l2cache.mem_side::total 198617866 # Cumulative packet size per connected master and slave (bytes)
1439system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952 # Cumulative packet size per connected master and slave (bytes)
1440system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes)
1441system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes)
1442system.membus.snoops 2980 # Total snoops (count)

1189system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks)
1190system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1191system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks)
1192system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1193system.cpu.toL2Bus.respLayer0.occupancy 36924053878 # Layer occupancy (ticks)
1194system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1195system.cpu.toL2Bus.respLayer1.occupancy 15679140875 # Layer occupancy (ticks)
1196system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1197system.cpu.toL2Bus.respLayer2.occupancy 408249695 # Layer occupancy (ticks)
1198system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1199system.cpu.toL2Bus.respLayer3.occupancy 1295905979 # Layer occupancy (ticks)
1200system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1201system.iobus.trans_dist::ReadReq 40311 # Transaction distribution
1202system.iobus.trans_dist::ReadResp 40311 # Transaction distribution
1203system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1204system.iobus.trans_dist::WriteResp 29907 # Transaction distribution
1205system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
1206system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1207system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1208system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1209system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1210system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1211system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1212system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1213system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1214system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1215system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1216system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1217system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1218system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1219system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1220system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1221system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
1222system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes)
1223system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes)
1224system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1225system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1226system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes)
1227system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
1228system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1229system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1230system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1231system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1232system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1233system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1234system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1235system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1236system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1237system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1238system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
1239system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1240system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
1241system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1242system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
1243system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes)
1244system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes)
1245system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1246system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1247system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes)
1248system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
1249system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1250system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
1251system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1252system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
1253system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1254system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
1255system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1256system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1257system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1258system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1259system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1260system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1261system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1262system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1263system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1264system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1265system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1266system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1267system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1268system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
1269system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1270system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
1271system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1272system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
1273system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1274system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
1275system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1276system.iobus.reqLayer27.occupancy 607011706 # Layer occupancy (ticks)
1277system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1278system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1279system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1280system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1281system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1282system.iobus.respLayer3.occupancy 148422470 # Layer occupancy (ticks)
1283system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1284system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks)
1285system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1286system.iocache.tags.replacements 115472 # number of replacements
1287system.iocache.tags.tagsinuse 10.439528 # Cycle average of tags in use
1288system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1289system.iocache.tags.sampled_refs 115488 # Sample count of references to valid blocks.
1290system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1291system.iocache.tags.warmup_cycle 13142428728000 # Cycle when the warmup percentage was hit.
1292system.iocache.tags.occ_blocks::realview.ethernet 3.524738 # Average occupied blocks per requestor
1293system.iocache.tags.occ_blocks::realview.ide 6.914790 # Average occupied blocks per requestor
1294system.iocache.tags.occ_percent::realview.ethernet 0.220296 # Average percentage of cache occupancy
1295system.iocache.tags.occ_percent::realview.ide 0.432174 # Average percentage of cache occupancy
1296system.iocache.tags.occ_percent::total 0.652471 # Average percentage of cache occupancy
1297system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1298system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1299system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1300system.iocache.tags.tag_accesses 1039767 # Number of tag accesses
1301system.iocache.tags.data_accesses 1039767 # Number of data accesses
1302system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1303system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses
1304system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses
1305system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1306system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1307system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
1308system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
1309system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1310system.iocache.demand_misses::realview.ide 8826 # number of demand (read+write) misses
1311system.iocache.demand_misses::total 8866 # number of demand (read+write) misses
1312system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1313system.iocache.overall_misses::realview.ide 8826 # number of overall misses
1314system.iocache.overall_misses::total 8866 # number of overall misses
1315system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
1316system.iocache.ReadReq_miss_latency::realview.ide 1599431674 # number of ReadReq miss cycles
1317system.iocache.ReadReq_miss_latency::total 1604503674 # number of ReadReq miss cycles
1318system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles
1319system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles
1320system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19839532562 # number of WriteInvalidateReq miss cycles
1321system.iocache.WriteInvalidateReq_miss_latency::total 19839532562 # number of WriteInvalidateReq miss cycles
1322system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles
1323system.iocache.demand_miss_latency::realview.ide 1599431674 # number of demand (read+write) miss cycles
1324system.iocache.demand_miss_latency::total 1604856174 # number of demand (read+write) miss cycles
1325system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles
1326system.iocache.overall_miss_latency::realview.ide 1599431674 # number of overall miss cycles
1327system.iocache.overall_miss_latency::total 1604856174 # number of overall miss cycles
1328system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1329system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses)
1330system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses)
1331system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1332system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1333system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
1334system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
1335system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1336system.iocache.demand_accesses::realview.ide 8826 # number of demand (read+write) accesses
1337system.iocache.demand_accesses::total 8866 # number of demand (read+write) accesses
1338system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1339system.iocache.overall_accesses::realview.ide 8826 # number of overall (read+write) accesses
1340system.iocache.overall_accesses::total 8866 # number of overall (read+write) accesses
1341system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1342system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1343system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1344system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1345system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1346system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
1347system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1348system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1349system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1350system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1351system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1352system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1353system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1354system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
1355system.iocache.ReadReq_avg_miss_latency::realview.ide 181218.181962 # average ReadReq miss latency
1356system.iocache.ReadReq_avg_miss_latency::total 181033.924630 # average ReadReq miss latency
1357system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency
1358system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency
1359system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186000.267775 # average WriteInvalidateReq miss latency
1360system.iocache.WriteInvalidateReq_avg_miss_latency::total 186000.267775 # average WriteInvalidateReq miss latency
1361system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
1362system.iocache.demand_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency
1363system.iocache.demand_avg_miss_latency::total 181012.426573 # average overall miss latency
1364system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
1365system.iocache.overall_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency
1366system.iocache.overall_avg_miss_latency::total 181012.426573 # average overall miss latency
1367system.iocache.blocked_cycles::no_mshrs 109629 # number of cycles access was blocked
1368system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1369system.iocache.blocked::no_mshrs 16167 # number of cycles access was blocked
1370system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1371system.iocache.avg_blocked_cycles::no_mshrs 6.781035 # average number of cycles each access was blocked
1372system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1373system.iocache.fast_writes 0 # number of fast writes performed
1374system.iocache.cache_copies 0 # number of cache copies performed
1375system.iocache.writebacks::writebacks 106631 # number of writebacks
1376system.iocache.writebacks::total 106631 # number of writebacks
1377system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1378system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses
1379system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses
1380system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1381system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1382system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
1383system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
1384system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1385system.iocache.demand_mshr_misses::realview.ide 8826 # number of demand (read+write) MSHR misses
1386system.iocache.demand_mshr_misses::total 8866 # number of demand (read+write) MSHR misses
1387system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1388system.iocache.overall_mshr_misses::realview.ide 8826 # number of overall MSHR misses
1389system.iocache.overall_mshr_misses::total 8866 # number of overall MSHR misses
1390system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles
1391system.iocache.ReadReq_mshr_miss_latency::realview.ide 1139388578 # number of ReadReq MSHR miss cycles
1392system.iocache.ReadReq_mshr_miss_latency::total 1142530578 # number of ReadReq MSHR miss cycles
1393system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles
1394system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles
1395system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14292968598 # number of WriteInvalidateReq MSHR miss cycles
1396system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14292968598 # number of WriteInvalidateReq MSHR miss cycles
1397system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles
1398system.iocache.demand_mshr_miss_latency::realview.ide 1139388578 # number of demand (read+write) MSHR miss cycles
1399system.iocache.demand_mshr_miss_latency::total 1142724078 # number of demand (read+write) MSHR miss cycles
1400system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles
1401system.iocache.overall_mshr_miss_latency::realview.ide 1139388578 # number of overall MSHR miss cycles
1402system.iocache.overall_mshr_miss_latency::total 1142724078 # number of overall MSHR miss cycles
1403system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1404system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1405system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1406system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1407system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1408system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1409system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1410system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1411system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1412system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1413system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1414system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1415system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1416system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency
1417system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129094.559030 # average ReadReq mshr miss latency
1418system.iocache.ReadReq_avg_mshr_miss_latency::total 128910.140810 # average ReadReq mshr miss latency
1419system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency
1420system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency
1421system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133999.930605 # average WriteInvalidateReq mshr miss latency
1422system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133999.930605 # average WriteInvalidateReq mshr miss latency
1423system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
1424system.iocache.demand_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency
1425system.iocache.demand_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency
1426system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
1427system.iocache.overall_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency
1428system.iocache.overall_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency
1429system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1430system.membus.trans_dist::ReadReq 537267 # Transaction distribution
1431system.membus.trans_dist::ReadResp 537267 # Transaction distribution
1432system.membus.trans_dist::WriteReq 33705 # Transaction distribution
1433system.membus.trans_dist::WriteResp 33705 # Transaction distribution
1434system.membus.trans_dist::Writeback 1468636 # Transaction distribution
1435system.membus.trans_dist::WriteInvalidateReq 649570 # Transaction distribution
1436system.membus.trans_dist::WriteInvalidateResp 649570 # Transaction distribution
1437system.membus.trans_dist::UpgradeReq 39342 # Transaction distribution
1438system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
1439system.membus.trans_dist::UpgradeResp 39343 # Transaction distribution
1440system.membus.trans_dist::ReadExReq 701468 # Transaction distribution
1441system.membus.trans_dist::ReadExResp 701468 # Transaction distribution
1442system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
1443system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes)
1444system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6912 # Packet count per connected master and slave (bytes)
1445system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4923341 # Packet count per connected master and slave (bytes)
1446system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5052989 # Packet count per connected master and slave (bytes)
1447system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335373 # Packet count per connected master and slave (bytes)
1448system.membus.pkt_count_system.iocache.mem_side::total 335373 # Packet count per connected master and slave (bytes)
1449system.membus.pkt_count::total 5388362 # Packet count per connected master and slave (bytes)
1450system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
1451system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes)
1452system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13824 # Cumulative packet size per connected master and slave (bytes)
1453system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198447468 # Cumulative packet size per connected master and slave (bytes)
1454system.membus.pkt_size_system.cpu.l2cache.mem_side::total 198617866 # Cumulative packet size per connected master and slave (bytes)
1455system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952 # Cumulative packet size per connected master and slave (bytes)
1456system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes)
1457system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes)
1458system.membus.snoops 2980 # Total snoops (count)

1443system.membus.snoop_fanout::samples 3310460 # Request fanout histogram

1459system.membus.snoop_fanout::samples 3430156 # Request fanout histogram

1444system.membus.snoop_fanout::mean 1 # Request fanout histogram
1445system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1446system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1447system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1460system.membus.snoop_fanout::mean 1 # Request fanout histogram
1461system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1462system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1463system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1448system.membus.snoop_fanout::1 3310460 100.00% 100.00% # Request fanout histogram

1464system.membus.snoop_fanout::1 3430156 100.00% 100.00% # Request fanout histogram

1449system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1450system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1451system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1452system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1465system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1466system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1467system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1468system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1453system.membus.snoop_fanout::total 3310460 # Request fanout histogram

1469system.membus.snoop_fanout::total 3430156 # Request fanout histogram