config.ini (9924:31ef410b6843) | config.ini (9988:0b2e590c85be) |
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1[root] 2type=Root 3children=system | 1[root] 2type=Root 3children=system |
4eventq_index=0 |
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4full_system=true | 5full_system=true |
6sim_quantum=0 |
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5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 12atags_addr=256 | 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 14atags_addr=256 |
13boot_loader=/dist/m5/system/binaries/boot.arm | 15boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm |
14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15cache_line_size=64 16clk_domain=system.clk_domain | 16boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 17cache_line_size=64 18clk_domain=system.clk_domain |
17dtb_filename=False | 19dtb_filename= |
18early_kernel_symbols=false 19enable_context_switch_stats_dump=false | 20early_kernel_symbols=false 21enable_context_switch_stats_dump=false |
22eventq_index=0 |
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20flags_addr=268435504 21gic_cpu_addr=520093952 22init_param=0 | 23flags_addr=268435504 24gic_cpu_addr=520093952 25init_param=0 |
23kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 | 26kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 |
24load_addr_mask=268435455 25machine_type=RealView_PBX 26mem_mode=timing 27mem_ranges=0:134217727 28memories=system.physmem system.realview.nvmem 29multi_proc=true 30num_work_ids=16 31panic_on_oops=true --- 8 unchanged lines hidden (view full) --- 40work_end_exit_count=0 41work_item_id=-1 42system_port=system.membus.slave[0] 43 44[system.bridge] 45type=Bridge 46clk_domain=system.clk_domain 47delay=50000 | 27load_addr_mask=268435455 28machine_type=RealView_PBX 29mem_mode=timing 30mem_ranges=0:134217727 31memories=system.physmem system.realview.nvmem 32multi_proc=true 33num_work_ids=16 34panic_on_oops=true --- 8 unchanged lines hidden (view full) --- 43work_end_exit_count=0 44work_item_id=-1 45system_port=system.membus.slave[0] 46 47[system.bridge] 48type=Bridge 49clk_domain=system.clk_domain 50delay=50000 |
51eventq_index=0 |
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48ranges=268435456:520093695 1073741824:1610612735 49req_size=16 50resp_size=16 51master=system.iobus.slave[0] 52slave=system.membus.master[0] 53 54[system.cf0] 55type=IdeDisk 56children=image 57delay=1000000 58driveID=master | 52ranges=268435456:520093695 1073741824:1610612735 53req_size=16 54resp_size=16 55master=system.iobus.slave[0] 56slave=system.membus.master[0] 57 58[system.cf0] 59type=IdeDisk 60children=image 61delay=1000000 62driveID=master |
63eventq_index=0 |
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59image=system.cf0.image 60 61[system.cf0.image] 62type=CowDiskImage 63children=child 64child=system.cf0.image.child | 64image=system.cf0.image 65 66[system.cf0.image] 67type=CowDiskImage 68children=child 69child=system.cf0.image.child |
70eventq_index=0 |
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65image_file= 66read_only=false 67table_size=65536 68 69[system.cf0.image.child] 70type=RawDiskImage | 71image_file= 72read_only=false 73table_size=65536 74 75[system.cf0.image.child] 76type=RawDiskImage |
71image_file=/dist/m5/system/disks/linux-arm-ael.img | 77eventq_index=0 78image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img |
72read_only=true 73 74[system.clk_domain] 75type=SrcClockDomain 76clock=1000 | 79read_only=true 80 81[system.clk_domain] 82type=SrcClockDomain 83clock=1000 |
84eventq_index=0 |
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77voltage_domain=system.voltage_domain 78 79[system.cpu0] 80type=DerivO3CPU 81children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 82LFSTSize=1024 83LQEntries=32 84LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 100decodeToFetchDelay=1 101decodeToRenameDelay=1 102decodeWidth=8 103dispatchWidth=8 104do_checkpoint_insts=true 105do_quiesce=true 106do_statistics_insts=true 107dtb=system.cpu0.dtb | 85voltage_domain=system.voltage_domain 86 87[system.cpu0] 88type=DerivO3CPU 89children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 90LFSTSize=1024 91LQEntries=32 92LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 108decodeToFetchDelay=1 109decodeToRenameDelay=1 110decodeWidth=8 111dispatchWidth=8 112do_checkpoint_insts=true 113do_quiesce=true 114do_statistics_insts=true 115dtb=system.cpu0.dtb |
116eventq_index=0 117fetchBufferSize=64 |
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108fetchToDecodeDelay=1 109fetchTrapLatency=1 110fetchWidth=8 111forwardComSize=5 112fuPool=system.cpu0.fuPool 113function_trace=false 114function_trace_start=0 115iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 164 165[system.cpu0.branchPred] 166type=BranchPredictor 167BTBEntries=4096 168BTBTagSize=16 169RASSize=16 170choiceCtrBits=2 171choicePredictorSize=8192 | 118fetchToDecodeDelay=1 119fetchTrapLatency=1 120fetchWidth=8 121forwardComSize=5 122fuPool=system.cpu0.fuPool 123function_trace=false 124function_trace_start=0 125iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 174 175[system.cpu0.branchPred] 176type=BranchPredictor 177BTBEntries=4096 178BTBTagSize=16 179RASSize=16 180choiceCtrBits=2 181choicePredictorSize=8192 |
182eventq_index=0 |
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172globalCtrBits=2 173globalPredictorSize=8192 174instShiftAmt=2 175localCtrBits=2 176localHistoryTableSize=2048 177localPredictorSize=2048 178numThreads=1 179predType=tournament 180 181[system.cpu0.dcache] 182type=BaseCache 183children=tags 184addr_ranges=0:18446744073709551615 185assoc=4 186clk_domain=system.cpu_clk_domain | 183globalCtrBits=2 184globalPredictorSize=8192 185instShiftAmt=2 186localCtrBits=2 187localHistoryTableSize=2048 188localPredictorSize=2048 189numThreads=1 190predType=tournament 191 192[system.cpu0.dcache] 193type=BaseCache 194children=tags 195addr_ranges=0:18446744073709551615 196assoc=4 197clk_domain=system.cpu_clk_domain |
198eventq_index=0 |
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187forward_snoops=true 188hit_latency=2 189is_top_level=true 190max_miss_count=0 191mshrs=4 192prefetch_on_access=false 193prefetcher=Null 194response_latency=2 --- 6 unchanged lines hidden (view full) --- 201cpu_side=system.cpu0.dcache_port 202mem_side=system.toL2Bus.slave[1] 203 204[system.cpu0.dcache.tags] 205type=LRU 206assoc=4 207block_size=64 208clk_domain=system.cpu_clk_domain | 199forward_snoops=true 200hit_latency=2 201is_top_level=true 202max_miss_count=0 203mshrs=4 204prefetch_on_access=false 205prefetcher=Null 206response_latency=2 --- 6 unchanged lines hidden (view full) --- 213cpu_side=system.cpu0.dcache_port 214mem_side=system.toL2Bus.slave[1] 215 216[system.cpu0.dcache.tags] 217type=LRU 218assoc=4 219block_size=64 220clk_domain=system.cpu_clk_domain |
221eventq_index=0 |
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209hit_latency=2 210size=32768 211 212[system.cpu0.dtb] 213type=ArmTLB 214children=walker | 222hit_latency=2 223size=32768 224 225[system.cpu0.dtb] 226type=ArmTLB 227children=walker |
228eventq_index=0 |
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215size=64 216walker=system.cpu0.dtb.walker 217 218[system.cpu0.dtb.walker] 219type=ArmTableWalker 220clk_domain=system.cpu_clk_domain | 229size=64 230walker=system.cpu0.dtb.walker 231 232[system.cpu0.dtb.walker] 233type=ArmTableWalker 234clk_domain=system.cpu_clk_domain |
235eventq_index=0 |
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221num_squash_per_cycle=2 222sys=system 223port=system.toL2Bus.slave[3] 224 225[system.cpu0.fuPool] 226type=FUPool 227children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 228FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 | 236num_squash_per_cycle=2 237sys=system 238port=system.toL2Bus.slave[3] 239 240[system.cpu0.fuPool] 241type=FUPool 242children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 243FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 |
244eventq_index=0 |
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229 230[system.cpu0.fuPool.FUList0] 231type=FUDesc 232children=opList 233count=6 | 245 246[system.cpu0.fuPool.FUList0] 247type=FUDesc 248children=opList 249count=6 |
250eventq_index=0 |
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234opList=system.cpu0.fuPool.FUList0.opList 235 236[system.cpu0.fuPool.FUList0.opList] 237type=OpDesc | 251opList=system.cpu0.fuPool.FUList0.opList 252 253[system.cpu0.fuPool.FUList0.opList] 254type=OpDesc |
255eventq_index=0 |
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238issueLat=1 239opClass=IntAlu 240opLat=1 241 242[system.cpu0.fuPool.FUList1] 243type=FUDesc 244children=opList0 opList1 245count=2 | 256issueLat=1 257opClass=IntAlu 258opLat=1 259 260[system.cpu0.fuPool.FUList1] 261type=FUDesc 262children=opList0 opList1 263count=2 |
264eventq_index=0 |
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246opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 247 248[system.cpu0.fuPool.FUList1.opList0] 249type=OpDesc | 265opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 266 267[system.cpu0.fuPool.FUList1.opList0] 268type=OpDesc |
269eventq_index=0 |
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250issueLat=1 251opClass=IntMult 252opLat=3 253 254[system.cpu0.fuPool.FUList1.opList1] 255type=OpDesc | 270issueLat=1 271opClass=IntMult 272opLat=3 273 274[system.cpu0.fuPool.FUList1.opList1] 275type=OpDesc |
276eventq_index=0 |
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256issueLat=19 257opClass=IntDiv 258opLat=20 259 260[system.cpu0.fuPool.FUList2] 261type=FUDesc 262children=opList0 opList1 opList2 263count=4 | 277issueLat=19 278opClass=IntDiv 279opLat=20 280 281[system.cpu0.fuPool.FUList2] 282type=FUDesc 283children=opList0 opList1 opList2 284count=4 |
285eventq_index=0 |
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264opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 265 266[system.cpu0.fuPool.FUList2.opList0] 267type=OpDesc | 286opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 287 288[system.cpu0.fuPool.FUList2.opList0] 289type=OpDesc |
290eventq_index=0 |
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268issueLat=1 269opClass=FloatAdd 270opLat=2 271 272[system.cpu0.fuPool.FUList2.opList1] 273type=OpDesc | 291issueLat=1 292opClass=FloatAdd 293opLat=2 294 295[system.cpu0.fuPool.FUList2.opList1] 296type=OpDesc |
297eventq_index=0 |
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274issueLat=1 275opClass=FloatCmp 276opLat=2 277 278[system.cpu0.fuPool.FUList2.opList2] 279type=OpDesc | 298issueLat=1 299opClass=FloatCmp 300opLat=2 301 302[system.cpu0.fuPool.FUList2.opList2] 303type=OpDesc |
304eventq_index=0 |
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280issueLat=1 281opClass=FloatCvt 282opLat=2 283 284[system.cpu0.fuPool.FUList3] 285type=FUDesc 286children=opList0 opList1 opList2 287count=2 | 305issueLat=1 306opClass=FloatCvt 307opLat=2 308 309[system.cpu0.fuPool.FUList3] 310type=FUDesc 311children=opList0 opList1 opList2 312count=2 |
313eventq_index=0 |
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288opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 289 290[system.cpu0.fuPool.FUList3.opList0] 291type=OpDesc | 314opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 315 316[system.cpu0.fuPool.FUList3.opList0] 317type=OpDesc |
318eventq_index=0 |
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292issueLat=1 293opClass=FloatMult 294opLat=4 295 296[system.cpu0.fuPool.FUList3.opList1] 297type=OpDesc | 319issueLat=1 320opClass=FloatMult 321opLat=4 322 323[system.cpu0.fuPool.FUList3.opList1] 324type=OpDesc |
325eventq_index=0 |
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298issueLat=12 299opClass=FloatDiv 300opLat=12 301 302[system.cpu0.fuPool.FUList3.opList2] 303type=OpDesc | 326issueLat=12 327opClass=FloatDiv 328opLat=12 329 330[system.cpu0.fuPool.FUList3.opList2] 331type=OpDesc |
332eventq_index=0 |
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304issueLat=24 305opClass=FloatSqrt 306opLat=24 307 308[system.cpu0.fuPool.FUList4] 309type=FUDesc 310children=opList 311count=0 | 333issueLat=24 334opClass=FloatSqrt 335opLat=24 336 337[system.cpu0.fuPool.FUList4] 338type=FUDesc 339children=opList 340count=0 |
341eventq_index=0 |
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312opList=system.cpu0.fuPool.FUList4.opList 313 314[system.cpu0.fuPool.FUList4.opList] 315type=OpDesc | 342opList=system.cpu0.fuPool.FUList4.opList 343 344[system.cpu0.fuPool.FUList4.opList] 345type=OpDesc |
346eventq_index=0 |
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316issueLat=1 317opClass=MemRead 318opLat=1 319 320[system.cpu0.fuPool.FUList5] 321type=FUDesc 322children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 323count=4 | 347issueLat=1 348opClass=MemRead 349opLat=1 350 351[system.cpu0.fuPool.FUList5] 352type=FUDesc 353children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 354count=4 |
355eventq_index=0 |
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324opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 325 326[system.cpu0.fuPool.FUList5.opList00] 327type=OpDesc | 356opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 357 358[system.cpu0.fuPool.FUList5.opList00] 359type=OpDesc |
360eventq_index=0 |
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328issueLat=1 329opClass=SimdAdd 330opLat=1 331 332[system.cpu0.fuPool.FUList5.opList01] 333type=OpDesc | 361issueLat=1 362opClass=SimdAdd 363opLat=1 364 365[system.cpu0.fuPool.FUList5.opList01] 366type=OpDesc |
367eventq_index=0 |
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334issueLat=1 335opClass=SimdAddAcc 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList02] 339type=OpDesc | 368issueLat=1 369opClass=SimdAddAcc 370opLat=1 371 372[system.cpu0.fuPool.FUList5.opList02] 373type=OpDesc |
374eventq_index=0 |
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340issueLat=1 341opClass=SimdAlu 342opLat=1 343 344[system.cpu0.fuPool.FUList5.opList03] 345type=OpDesc | 375issueLat=1 376opClass=SimdAlu 377opLat=1 378 379[system.cpu0.fuPool.FUList5.opList03] 380type=OpDesc |
381eventq_index=0 |
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346issueLat=1 347opClass=SimdCmp 348opLat=1 349 350[system.cpu0.fuPool.FUList5.opList04] 351type=OpDesc | 382issueLat=1 383opClass=SimdCmp 384opLat=1 385 386[system.cpu0.fuPool.FUList5.opList04] 387type=OpDesc |
388eventq_index=0 |
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352issueLat=1 353opClass=SimdCvt 354opLat=1 355 356[system.cpu0.fuPool.FUList5.opList05] 357type=OpDesc | 389issueLat=1 390opClass=SimdCvt 391opLat=1 392 393[system.cpu0.fuPool.FUList5.opList05] 394type=OpDesc |
395eventq_index=0 |
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358issueLat=1 359opClass=SimdMisc 360opLat=1 361 362[system.cpu0.fuPool.FUList5.opList06] 363type=OpDesc | 396issueLat=1 397opClass=SimdMisc 398opLat=1 399 400[system.cpu0.fuPool.FUList5.opList06] 401type=OpDesc |
402eventq_index=0 |
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364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList07] 369type=OpDesc | 403issueLat=1 404opClass=SimdMult 405opLat=1 406 407[system.cpu0.fuPool.FUList5.opList07] 408type=OpDesc |
409eventq_index=0 |
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370issueLat=1 371opClass=SimdMultAcc 372opLat=1 373 374[system.cpu0.fuPool.FUList5.opList08] 375type=OpDesc | 410issueLat=1 411opClass=SimdMultAcc 412opLat=1 413 414[system.cpu0.fuPool.FUList5.opList08] 415type=OpDesc |
416eventq_index=0 |
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376issueLat=1 377opClass=SimdShift 378opLat=1 379 380[system.cpu0.fuPool.FUList5.opList09] 381type=OpDesc | 417issueLat=1 418opClass=SimdShift 419opLat=1 420 421[system.cpu0.fuPool.FUList5.opList09] 422type=OpDesc |
423eventq_index=0 |
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382issueLat=1 383opClass=SimdShiftAcc 384opLat=1 385 386[system.cpu0.fuPool.FUList5.opList10] 387type=OpDesc | 424issueLat=1 425opClass=SimdShiftAcc 426opLat=1 427 428[system.cpu0.fuPool.FUList5.opList10] 429type=OpDesc |
430eventq_index=0 |
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388issueLat=1 389opClass=SimdSqrt 390opLat=1 391 392[system.cpu0.fuPool.FUList5.opList11] 393type=OpDesc | 431issueLat=1 432opClass=SimdSqrt 433opLat=1 434 435[system.cpu0.fuPool.FUList5.opList11] 436type=OpDesc |
437eventq_index=0 |
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394issueLat=1 395opClass=SimdFloatAdd 396opLat=1 397 398[system.cpu0.fuPool.FUList5.opList12] 399type=OpDesc | 438issueLat=1 439opClass=SimdFloatAdd 440opLat=1 441 442[system.cpu0.fuPool.FUList5.opList12] 443type=OpDesc |
444eventq_index=0 |
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400issueLat=1 401opClass=SimdFloatAlu 402opLat=1 403 404[system.cpu0.fuPool.FUList5.opList13] 405type=OpDesc | 445issueLat=1 446opClass=SimdFloatAlu 447opLat=1 448 449[system.cpu0.fuPool.FUList5.opList13] 450type=OpDesc |
451eventq_index=0 |
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406issueLat=1 407opClass=SimdFloatCmp 408opLat=1 409 410[system.cpu0.fuPool.FUList5.opList14] 411type=OpDesc | 452issueLat=1 453opClass=SimdFloatCmp 454opLat=1 455 456[system.cpu0.fuPool.FUList5.opList14] 457type=OpDesc |
458eventq_index=0 |
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412issueLat=1 413opClass=SimdFloatCvt 414opLat=1 415 416[system.cpu0.fuPool.FUList5.opList15] 417type=OpDesc | 459issueLat=1 460opClass=SimdFloatCvt 461opLat=1 462 463[system.cpu0.fuPool.FUList5.opList15] 464type=OpDesc |
465eventq_index=0 |
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418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu0.fuPool.FUList5.opList16] 423type=OpDesc | 466issueLat=1 467opClass=SimdFloatDiv 468opLat=1 469 470[system.cpu0.fuPool.FUList5.opList16] 471type=OpDesc |
472eventq_index=0 |
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424issueLat=1 425opClass=SimdFloatMisc 426opLat=1 427 428[system.cpu0.fuPool.FUList5.opList17] 429type=OpDesc | 473issueLat=1 474opClass=SimdFloatMisc 475opLat=1 476 477[system.cpu0.fuPool.FUList5.opList17] 478type=OpDesc |
479eventq_index=0 |
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430issueLat=1 431opClass=SimdFloatMult 432opLat=1 433 434[system.cpu0.fuPool.FUList5.opList18] 435type=OpDesc | 480issueLat=1 481opClass=SimdFloatMult 482opLat=1 483 484[system.cpu0.fuPool.FUList5.opList18] 485type=OpDesc |
486eventq_index=0 |
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436issueLat=1 437opClass=SimdFloatMultAcc 438opLat=1 439 440[system.cpu0.fuPool.FUList5.opList19] 441type=OpDesc | 487issueLat=1 488opClass=SimdFloatMultAcc 489opLat=1 490 491[system.cpu0.fuPool.FUList5.opList19] 492type=OpDesc |
493eventq_index=0 |
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442issueLat=1 443opClass=SimdFloatSqrt 444opLat=1 445 446[system.cpu0.fuPool.FUList6] 447type=FUDesc 448children=opList 449count=0 | 494issueLat=1 495opClass=SimdFloatSqrt 496opLat=1 497 498[system.cpu0.fuPool.FUList6] 499type=FUDesc 500children=opList 501count=0 |
502eventq_index=0 |
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450opList=system.cpu0.fuPool.FUList6.opList 451 452[system.cpu0.fuPool.FUList6.opList] 453type=OpDesc | 503opList=system.cpu0.fuPool.FUList6.opList 504 505[system.cpu0.fuPool.FUList6.opList] 506type=OpDesc |
507eventq_index=0 |
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454issueLat=1 455opClass=MemWrite 456opLat=1 457 458[system.cpu0.fuPool.FUList7] 459type=FUDesc 460children=opList0 opList1 461count=4 | 508issueLat=1 509opClass=MemWrite 510opLat=1 511 512[system.cpu0.fuPool.FUList7] 513type=FUDesc 514children=opList0 opList1 515count=4 |
516eventq_index=0 |
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462opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 463 464[system.cpu0.fuPool.FUList7.opList0] 465type=OpDesc | 517opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 518 519[system.cpu0.fuPool.FUList7.opList0] 520type=OpDesc |
521eventq_index=0 |
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466issueLat=1 467opClass=MemRead 468opLat=1 469 470[system.cpu0.fuPool.FUList7.opList1] 471type=OpDesc | 522issueLat=1 523opClass=MemRead 524opLat=1 525 526[system.cpu0.fuPool.FUList7.opList1] 527type=OpDesc |
528eventq_index=0 |
|
472issueLat=1 473opClass=MemWrite 474opLat=1 475 476[system.cpu0.fuPool.FUList8] 477type=FUDesc 478children=opList 479count=1 | 529issueLat=1 530opClass=MemWrite 531opLat=1 532 533[system.cpu0.fuPool.FUList8] 534type=FUDesc 535children=opList 536count=1 |
537eventq_index=0 |
|
480opList=system.cpu0.fuPool.FUList8.opList 481 482[system.cpu0.fuPool.FUList8.opList] 483type=OpDesc | 538opList=system.cpu0.fuPool.FUList8.opList 539 540[system.cpu0.fuPool.FUList8.opList] 541type=OpDesc |
542eventq_index=0 |
|
484issueLat=3 485opClass=IprAccess 486opLat=3 487 488[system.cpu0.icache] 489type=BaseCache 490children=tags 491addr_ranges=0:18446744073709551615 492assoc=1 493clk_domain=system.cpu_clk_domain | 543issueLat=3 544opClass=IprAccess 545opLat=3 546 547[system.cpu0.icache] 548type=BaseCache 549children=tags 550addr_ranges=0:18446744073709551615 551assoc=1 552clk_domain=system.cpu_clk_domain |
553eventq_index=0 |
|
494forward_snoops=true 495hit_latency=2 496is_top_level=true 497max_miss_count=0 498mshrs=4 499prefetch_on_access=false 500prefetcher=Null 501response_latency=2 --- 6 unchanged lines hidden (view full) --- 508cpu_side=system.cpu0.icache_port 509mem_side=system.toL2Bus.slave[0] 510 511[system.cpu0.icache.tags] 512type=LRU 513assoc=1 514block_size=64 515clk_domain=system.cpu_clk_domain | 554forward_snoops=true 555hit_latency=2 556is_top_level=true 557max_miss_count=0 558mshrs=4 559prefetch_on_access=false 560prefetcher=Null 561response_latency=2 --- 6 unchanged lines hidden (view full) --- 568cpu_side=system.cpu0.icache_port 569mem_side=system.toL2Bus.slave[0] 570 571[system.cpu0.icache.tags] 572type=LRU 573assoc=1 574block_size=64 575clk_domain=system.cpu_clk_domain |
576eventq_index=0 |
|
516hit_latency=2 517size=32768 518 519[system.cpu0.interrupts] 520type=ArmInterrupts | 577hit_latency=2 578size=32768 579 580[system.cpu0.interrupts] 581type=ArmInterrupts |
582eventq_index=0 |
|
521 522[system.cpu0.isa] 523type=ArmISA | 583 584[system.cpu0.isa] 585type=ArmISA |
586eventq_index=0 |
|
524fpsid=1090793632 525id_isar0=34607377 526id_isar1=34677009 527id_isar2=555950401 528id_isar3=17899825 529id_isar4=268501314 530id_isar5=0 531id_mmfr0=3 532id_mmfr1=0 533id_mmfr2=19070976 534id_mmfr3=4027589137 535id_pfr0=49 536id_pfr1=1 537midr=890224640 538 539[system.cpu0.itb] 540type=ArmTLB 541children=walker | 587fpsid=1090793632 588id_isar0=34607377 589id_isar1=34677009 590id_isar2=555950401 591id_isar3=17899825 592id_isar4=268501314 593id_isar5=0 594id_mmfr0=3 595id_mmfr1=0 596id_mmfr2=19070976 597id_mmfr3=4027589137 598id_pfr0=49 599id_pfr1=1 600midr=890224640 601 602[system.cpu0.itb] 603type=ArmTLB 604children=walker |
605eventq_index=0 |
|
542size=64 543walker=system.cpu0.itb.walker 544 545[system.cpu0.itb.walker] 546type=ArmTableWalker 547clk_domain=system.cpu_clk_domain | 606size=64 607walker=system.cpu0.itb.walker 608 609[system.cpu0.itb.walker] 610type=ArmTableWalker 611clk_domain=system.cpu_clk_domain |
612eventq_index=0 |
|
548num_squash_per_cycle=2 549sys=system 550port=system.toL2Bus.slave[2] 551 552[system.cpu0.tracer] 553type=ExeTracer | 613num_squash_per_cycle=2 614sys=system 615port=system.toL2Bus.slave[2] 616 617[system.cpu0.tracer] 618type=ExeTracer |
619eventq_index=0 |
|
554 555[system.cpu1] 556type=DerivO3CPU 557children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 558LFSTSize=1024 559LQEntries=32 560LSQCheckLoads=true 561LSQDepCheckShift=4 --- 14 unchanged lines hidden (view full) --- 576decodeToFetchDelay=1 577decodeToRenameDelay=1 578decodeWidth=8 579dispatchWidth=8 580do_checkpoint_insts=true 581do_quiesce=true 582do_statistics_insts=true 583dtb=system.cpu1.dtb | 620 621[system.cpu1] 622type=DerivO3CPU 623children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 624LFSTSize=1024 625LQEntries=32 626LSQCheckLoads=true 627LSQDepCheckShift=4 --- 14 unchanged lines hidden (view full) --- 642decodeToFetchDelay=1 643decodeToRenameDelay=1 644decodeWidth=8 645dispatchWidth=8 646do_checkpoint_insts=true 647do_quiesce=true 648do_statistics_insts=true 649dtb=system.cpu1.dtb |
650eventq_index=0 651fetchBufferSize=64 |
|
584fetchToDecodeDelay=1 585fetchTrapLatency=1 586fetchWidth=8 587forwardComSize=5 588fuPool=system.cpu1.fuPool 589function_trace=false 590function_trace_start=0 591iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 640 641[system.cpu1.branchPred] 642type=BranchPredictor 643BTBEntries=4096 644BTBTagSize=16 645RASSize=16 646choiceCtrBits=2 647choicePredictorSize=8192 | 652fetchToDecodeDelay=1 653fetchTrapLatency=1 654fetchWidth=8 655forwardComSize=5 656fuPool=system.cpu1.fuPool 657function_trace=false 658function_trace_start=0 659iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 708 709[system.cpu1.branchPred] 710type=BranchPredictor 711BTBEntries=4096 712BTBTagSize=16 713RASSize=16 714choiceCtrBits=2 715choicePredictorSize=8192 |
716eventq_index=0 |
|
648globalCtrBits=2 649globalPredictorSize=8192 650instShiftAmt=2 651localCtrBits=2 652localHistoryTableSize=2048 653localPredictorSize=2048 654numThreads=1 655predType=tournament 656 657[system.cpu1.dcache] 658type=BaseCache 659children=tags 660addr_ranges=0:18446744073709551615 661assoc=4 662clk_domain=system.cpu_clk_domain | 717globalCtrBits=2 718globalPredictorSize=8192 719instShiftAmt=2 720localCtrBits=2 721localHistoryTableSize=2048 722localPredictorSize=2048 723numThreads=1 724predType=tournament 725 726[system.cpu1.dcache] 727type=BaseCache 728children=tags 729addr_ranges=0:18446744073709551615 730assoc=4 731clk_domain=system.cpu_clk_domain |
732eventq_index=0 |
|
663forward_snoops=true 664hit_latency=2 665is_top_level=true 666max_miss_count=0 667mshrs=4 668prefetch_on_access=false 669prefetcher=Null 670response_latency=2 --- 6 unchanged lines hidden (view full) --- 677cpu_side=system.cpu1.dcache_port 678mem_side=system.toL2Bus.slave[5] 679 680[system.cpu1.dcache.tags] 681type=LRU 682assoc=4 683block_size=64 684clk_domain=system.cpu_clk_domain | 733forward_snoops=true 734hit_latency=2 735is_top_level=true 736max_miss_count=0 737mshrs=4 738prefetch_on_access=false 739prefetcher=Null 740response_latency=2 --- 6 unchanged lines hidden (view full) --- 747cpu_side=system.cpu1.dcache_port 748mem_side=system.toL2Bus.slave[5] 749 750[system.cpu1.dcache.tags] 751type=LRU 752assoc=4 753block_size=64 754clk_domain=system.cpu_clk_domain |
755eventq_index=0 |
|
685hit_latency=2 686size=32768 687 688[system.cpu1.dtb] 689type=ArmTLB 690children=walker | 756hit_latency=2 757size=32768 758 759[system.cpu1.dtb] 760type=ArmTLB 761children=walker |
762eventq_index=0 |
|
691size=64 692walker=system.cpu1.dtb.walker 693 694[system.cpu1.dtb.walker] 695type=ArmTableWalker 696clk_domain=system.cpu_clk_domain | 763size=64 764walker=system.cpu1.dtb.walker 765 766[system.cpu1.dtb.walker] 767type=ArmTableWalker 768clk_domain=system.cpu_clk_domain |
769eventq_index=0 |
|
697num_squash_per_cycle=2 698sys=system 699port=system.toL2Bus.slave[7] 700 701[system.cpu1.fuPool] 702type=FUPool 703children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 704FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 | 770num_squash_per_cycle=2 771sys=system 772port=system.toL2Bus.slave[7] 773 774[system.cpu1.fuPool] 775type=FUPool 776children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 777FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 |
778eventq_index=0 |
|
705 706[system.cpu1.fuPool.FUList0] 707type=FUDesc 708children=opList 709count=6 | 779 780[system.cpu1.fuPool.FUList0] 781type=FUDesc 782children=opList 783count=6 |
784eventq_index=0 |
|
710opList=system.cpu1.fuPool.FUList0.opList 711 712[system.cpu1.fuPool.FUList0.opList] 713type=OpDesc | 785opList=system.cpu1.fuPool.FUList0.opList 786 787[system.cpu1.fuPool.FUList0.opList] 788type=OpDesc |
789eventq_index=0 |
|
714issueLat=1 715opClass=IntAlu 716opLat=1 717 718[system.cpu1.fuPool.FUList1] 719type=FUDesc 720children=opList0 opList1 721count=2 | 790issueLat=1 791opClass=IntAlu 792opLat=1 793 794[system.cpu1.fuPool.FUList1] 795type=FUDesc 796children=opList0 opList1 797count=2 |
798eventq_index=0 |
|
722opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 723 724[system.cpu1.fuPool.FUList1.opList0] 725type=OpDesc | 799opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 800 801[system.cpu1.fuPool.FUList1.opList0] 802type=OpDesc |
803eventq_index=0 |
|
726issueLat=1 727opClass=IntMult 728opLat=3 729 730[system.cpu1.fuPool.FUList1.opList1] 731type=OpDesc | 804issueLat=1 805opClass=IntMult 806opLat=3 807 808[system.cpu1.fuPool.FUList1.opList1] 809type=OpDesc |
810eventq_index=0 |
|
732issueLat=19 733opClass=IntDiv 734opLat=20 735 736[system.cpu1.fuPool.FUList2] 737type=FUDesc 738children=opList0 opList1 opList2 739count=4 | 811issueLat=19 812opClass=IntDiv 813opLat=20 814 815[system.cpu1.fuPool.FUList2] 816type=FUDesc 817children=opList0 opList1 opList2 818count=4 |
819eventq_index=0 |
|
740opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 741 742[system.cpu1.fuPool.FUList2.opList0] 743type=OpDesc | 820opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 821 822[system.cpu1.fuPool.FUList2.opList0] 823type=OpDesc |
824eventq_index=0 |
|
744issueLat=1 745opClass=FloatAdd 746opLat=2 747 748[system.cpu1.fuPool.FUList2.opList1] 749type=OpDesc | 825issueLat=1 826opClass=FloatAdd 827opLat=2 828 829[system.cpu1.fuPool.FUList2.opList1] 830type=OpDesc |
831eventq_index=0 |
|
750issueLat=1 751opClass=FloatCmp 752opLat=2 753 754[system.cpu1.fuPool.FUList2.opList2] 755type=OpDesc | 832issueLat=1 833opClass=FloatCmp 834opLat=2 835 836[system.cpu1.fuPool.FUList2.opList2] 837type=OpDesc |
838eventq_index=0 |
|
756issueLat=1 757opClass=FloatCvt 758opLat=2 759 760[system.cpu1.fuPool.FUList3] 761type=FUDesc 762children=opList0 opList1 opList2 763count=2 | 839issueLat=1 840opClass=FloatCvt 841opLat=2 842 843[system.cpu1.fuPool.FUList3] 844type=FUDesc 845children=opList0 opList1 opList2 846count=2 |
847eventq_index=0 |
|
764opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 765 766[system.cpu1.fuPool.FUList3.opList0] 767type=OpDesc | 848opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 849 850[system.cpu1.fuPool.FUList3.opList0] 851type=OpDesc |
852eventq_index=0 |
|
768issueLat=1 769opClass=FloatMult 770opLat=4 771 772[system.cpu1.fuPool.FUList3.opList1] 773type=OpDesc | 853issueLat=1 854opClass=FloatMult 855opLat=4 856 857[system.cpu1.fuPool.FUList3.opList1] 858type=OpDesc |
859eventq_index=0 |
|
774issueLat=12 775opClass=FloatDiv 776opLat=12 777 778[system.cpu1.fuPool.FUList3.opList2] 779type=OpDesc | 860issueLat=12 861opClass=FloatDiv 862opLat=12 863 864[system.cpu1.fuPool.FUList3.opList2] 865type=OpDesc |
866eventq_index=0 |
|
780issueLat=24 781opClass=FloatSqrt 782opLat=24 783 784[system.cpu1.fuPool.FUList4] 785type=FUDesc 786children=opList 787count=0 | 867issueLat=24 868opClass=FloatSqrt 869opLat=24 870 871[system.cpu1.fuPool.FUList4] 872type=FUDesc 873children=opList 874count=0 |
875eventq_index=0 |
|
788opList=system.cpu1.fuPool.FUList4.opList 789 790[system.cpu1.fuPool.FUList4.opList] 791type=OpDesc | 876opList=system.cpu1.fuPool.FUList4.opList 877 878[system.cpu1.fuPool.FUList4.opList] 879type=OpDesc |
880eventq_index=0 |
|
792issueLat=1 793opClass=MemRead 794opLat=1 795 796[system.cpu1.fuPool.FUList5] 797type=FUDesc 798children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 799count=4 | 881issueLat=1 882opClass=MemRead 883opLat=1 884 885[system.cpu1.fuPool.FUList5] 886type=FUDesc 887children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 888count=4 |
889eventq_index=0 |
|
800opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 801 802[system.cpu1.fuPool.FUList5.opList00] 803type=OpDesc | 890opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 891 892[system.cpu1.fuPool.FUList5.opList00] 893type=OpDesc |
894eventq_index=0 |
|
804issueLat=1 805opClass=SimdAdd 806opLat=1 807 808[system.cpu1.fuPool.FUList5.opList01] 809type=OpDesc | 895issueLat=1 896opClass=SimdAdd 897opLat=1 898 899[system.cpu1.fuPool.FUList5.opList01] 900type=OpDesc |
901eventq_index=0 |
|
810issueLat=1 811opClass=SimdAddAcc 812opLat=1 813 814[system.cpu1.fuPool.FUList5.opList02] 815type=OpDesc | 902issueLat=1 903opClass=SimdAddAcc 904opLat=1 905 906[system.cpu1.fuPool.FUList5.opList02] 907type=OpDesc |
908eventq_index=0 |
|
816issueLat=1 817opClass=SimdAlu 818opLat=1 819 820[system.cpu1.fuPool.FUList5.opList03] 821type=OpDesc | 909issueLat=1 910opClass=SimdAlu 911opLat=1 912 913[system.cpu1.fuPool.FUList5.opList03] 914type=OpDesc |
915eventq_index=0 |
|
822issueLat=1 823opClass=SimdCmp 824opLat=1 825 826[system.cpu1.fuPool.FUList5.opList04] 827type=OpDesc | 916issueLat=1 917opClass=SimdCmp 918opLat=1 919 920[system.cpu1.fuPool.FUList5.opList04] 921type=OpDesc |
922eventq_index=0 |
|
828issueLat=1 829opClass=SimdCvt 830opLat=1 831 832[system.cpu1.fuPool.FUList5.opList05] 833type=OpDesc | 923issueLat=1 924opClass=SimdCvt 925opLat=1 926 927[system.cpu1.fuPool.FUList5.opList05] 928type=OpDesc |
929eventq_index=0 |
|
834issueLat=1 835opClass=SimdMisc 836opLat=1 837 838[system.cpu1.fuPool.FUList5.opList06] 839type=OpDesc | 930issueLat=1 931opClass=SimdMisc 932opLat=1 933 934[system.cpu1.fuPool.FUList5.opList06] 935type=OpDesc |
936eventq_index=0 |
|
840issueLat=1 841opClass=SimdMult 842opLat=1 843 844[system.cpu1.fuPool.FUList5.opList07] 845type=OpDesc | 937issueLat=1 938opClass=SimdMult 939opLat=1 940 941[system.cpu1.fuPool.FUList5.opList07] 942type=OpDesc |
943eventq_index=0 |
|
846issueLat=1 847opClass=SimdMultAcc 848opLat=1 849 850[system.cpu1.fuPool.FUList5.opList08] 851type=OpDesc | 944issueLat=1 945opClass=SimdMultAcc 946opLat=1 947 948[system.cpu1.fuPool.FUList5.opList08] 949type=OpDesc |
950eventq_index=0 |
|
852issueLat=1 853opClass=SimdShift 854opLat=1 855 856[system.cpu1.fuPool.FUList5.opList09] 857type=OpDesc | 951issueLat=1 952opClass=SimdShift 953opLat=1 954 955[system.cpu1.fuPool.FUList5.opList09] 956type=OpDesc |
957eventq_index=0 |
|
858issueLat=1 859opClass=SimdShiftAcc 860opLat=1 861 862[system.cpu1.fuPool.FUList5.opList10] 863type=OpDesc | 958issueLat=1 959opClass=SimdShiftAcc 960opLat=1 961 962[system.cpu1.fuPool.FUList5.opList10] 963type=OpDesc |
964eventq_index=0 |
|
864issueLat=1 865opClass=SimdSqrt 866opLat=1 867 868[system.cpu1.fuPool.FUList5.opList11] 869type=OpDesc | 965issueLat=1 966opClass=SimdSqrt 967opLat=1 968 969[system.cpu1.fuPool.FUList5.opList11] 970type=OpDesc |
971eventq_index=0 |
|
870issueLat=1 871opClass=SimdFloatAdd 872opLat=1 873 874[system.cpu1.fuPool.FUList5.opList12] 875type=OpDesc | 972issueLat=1 973opClass=SimdFloatAdd 974opLat=1 975 976[system.cpu1.fuPool.FUList5.opList12] 977type=OpDesc |
978eventq_index=0 |
|
876issueLat=1 877opClass=SimdFloatAlu 878opLat=1 879 880[system.cpu1.fuPool.FUList5.opList13] 881type=OpDesc | 979issueLat=1 980opClass=SimdFloatAlu 981opLat=1 982 983[system.cpu1.fuPool.FUList5.opList13] 984type=OpDesc |
985eventq_index=0 |
|
882issueLat=1 883opClass=SimdFloatCmp 884opLat=1 885 886[system.cpu1.fuPool.FUList5.opList14] 887type=OpDesc | 986issueLat=1 987opClass=SimdFloatCmp 988opLat=1 989 990[system.cpu1.fuPool.FUList5.opList14] 991type=OpDesc |
992eventq_index=0 |
|
888issueLat=1 889opClass=SimdFloatCvt 890opLat=1 891 892[system.cpu1.fuPool.FUList5.opList15] 893type=OpDesc | 993issueLat=1 994opClass=SimdFloatCvt 995opLat=1 996 997[system.cpu1.fuPool.FUList5.opList15] 998type=OpDesc |
999eventq_index=0 |
|
894issueLat=1 895opClass=SimdFloatDiv 896opLat=1 897 898[system.cpu1.fuPool.FUList5.opList16] 899type=OpDesc | 1000issueLat=1 1001opClass=SimdFloatDiv 1002opLat=1 1003 1004[system.cpu1.fuPool.FUList5.opList16] 1005type=OpDesc |
1006eventq_index=0 |
|
900issueLat=1 901opClass=SimdFloatMisc 902opLat=1 903 904[system.cpu1.fuPool.FUList5.opList17] 905type=OpDesc | 1007issueLat=1 1008opClass=SimdFloatMisc 1009opLat=1 1010 1011[system.cpu1.fuPool.FUList5.opList17] 1012type=OpDesc |
1013eventq_index=0 |
|
906issueLat=1 907opClass=SimdFloatMult 908opLat=1 909 910[system.cpu1.fuPool.FUList5.opList18] 911type=OpDesc | 1014issueLat=1 1015opClass=SimdFloatMult 1016opLat=1 1017 1018[system.cpu1.fuPool.FUList5.opList18] 1019type=OpDesc |
1020eventq_index=0 |
|
912issueLat=1 913opClass=SimdFloatMultAcc 914opLat=1 915 916[system.cpu1.fuPool.FUList5.opList19] 917type=OpDesc | 1021issueLat=1 1022opClass=SimdFloatMultAcc 1023opLat=1 1024 1025[system.cpu1.fuPool.FUList5.opList19] 1026type=OpDesc |
1027eventq_index=0 |
|
918issueLat=1 919opClass=SimdFloatSqrt 920opLat=1 921 922[system.cpu1.fuPool.FUList6] 923type=FUDesc 924children=opList 925count=0 | 1028issueLat=1 1029opClass=SimdFloatSqrt 1030opLat=1 1031 1032[system.cpu1.fuPool.FUList6] 1033type=FUDesc 1034children=opList 1035count=0 |
1036eventq_index=0 |
|
926opList=system.cpu1.fuPool.FUList6.opList 927 928[system.cpu1.fuPool.FUList6.opList] 929type=OpDesc | 1037opList=system.cpu1.fuPool.FUList6.opList 1038 1039[system.cpu1.fuPool.FUList6.opList] 1040type=OpDesc |
1041eventq_index=0 |
|
930issueLat=1 931opClass=MemWrite 932opLat=1 933 934[system.cpu1.fuPool.FUList7] 935type=FUDesc 936children=opList0 opList1 937count=4 | 1042issueLat=1 1043opClass=MemWrite 1044opLat=1 1045 1046[system.cpu1.fuPool.FUList7] 1047type=FUDesc 1048children=opList0 opList1 1049count=4 |
1050eventq_index=0 |
|
938opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 939 940[system.cpu1.fuPool.FUList7.opList0] 941type=OpDesc | 1051opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1052 1053[system.cpu1.fuPool.FUList7.opList0] 1054type=OpDesc |
1055eventq_index=0 |
|
942issueLat=1 943opClass=MemRead 944opLat=1 945 946[system.cpu1.fuPool.FUList7.opList1] 947type=OpDesc | 1056issueLat=1 1057opClass=MemRead 1058opLat=1 1059 1060[system.cpu1.fuPool.FUList7.opList1] 1061type=OpDesc |
1062eventq_index=0 |
|
948issueLat=1 949opClass=MemWrite 950opLat=1 951 952[system.cpu1.fuPool.FUList8] 953type=FUDesc 954children=opList 955count=1 | 1063issueLat=1 1064opClass=MemWrite 1065opLat=1 1066 1067[system.cpu1.fuPool.FUList8] 1068type=FUDesc 1069children=opList 1070count=1 |
1071eventq_index=0 |
|
956opList=system.cpu1.fuPool.FUList8.opList 957 958[system.cpu1.fuPool.FUList8.opList] 959type=OpDesc | 1072opList=system.cpu1.fuPool.FUList8.opList 1073 1074[system.cpu1.fuPool.FUList8.opList] 1075type=OpDesc |
1076eventq_index=0 |
|
960issueLat=3 961opClass=IprAccess 962opLat=3 963 964[system.cpu1.icache] 965type=BaseCache 966children=tags 967addr_ranges=0:18446744073709551615 968assoc=1 969clk_domain=system.cpu_clk_domain | 1077issueLat=3 1078opClass=IprAccess 1079opLat=3 1080 1081[system.cpu1.icache] 1082type=BaseCache 1083children=tags 1084addr_ranges=0:18446744073709551615 1085assoc=1 1086clk_domain=system.cpu_clk_domain |
1087eventq_index=0 |
|
970forward_snoops=true 971hit_latency=2 972is_top_level=true 973max_miss_count=0 974mshrs=4 975prefetch_on_access=false 976prefetcher=Null 977response_latency=2 --- 6 unchanged lines hidden (view full) --- 984cpu_side=system.cpu1.icache_port 985mem_side=system.toL2Bus.slave[4] 986 987[system.cpu1.icache.tags] 988type=LRU 989assoc=1 990block_size=64 991clk_domain=system.cpu_clk_domain | 1088forward_snoops=true 1089hit_latency=2 1090is_top_level=true 1091max_miss_count=0 1092mshrs=4 1093prefetch_on_access=false 1094prefetcher=Null 1095response_latency=2 --- 6 unchanged lines hidden (view full) --- 1102cpu_side=system.cpu1.icache_port 1103mem_side=system.toL2Bus.slave[4] 1104 1105[system.cpu1.icache.tags] 1106type=LRU 1107assoc=1 1108block_size=64 1109clk_domain=system.cpu_clk_domain |
1110eventq_index=0 |
|
992hit_latency=2 993size=32768 994 995[system.cpu1.interrupts] 996type=ArmInterrupts | 1111hit_latency=2 1112size=32768 1113 1114[system.cpu1.interrupts] 1115type=ArmInterrupts |
1116eventq_index=0 |
|
997 998[system.cpu1.isa] 999type=ArmISA | 1117 1118[system.cpu1.isa] 1119type=ArmISA |
1120eventq_index=0 |
|
1000fpsid=1090793632 1001id_isar0=34607377 1002id_isar1=34677009 1003id_isar2=555950401 1004id_isar3=17899825 1005id_isar4=268501314 1006id_isar5=0 1007id_mmfr0=3 1008id_mmfr1=0 1009id_mmfr2=19070976 1010id_mmfr3=4027589137 1011id_pfr0=49 1012id_pfr1=1 1013midr=890224640 1014 1015[system.cpu1.itb] 1016type=ArmTLB 1017children=walker | 1121fpsid=1090793632 1122id_isar0=34607377 1123id_isar1=34677009 1124id_isar2=555950401 1125id_isar3=17899825 1126id_isar4=268501314 1127id_isar5=0 1128id_mmfr0=3 1129id_mmfr1=0 1130id_mmfr2=19070976 1131id_mmfr3=4027589137 1132id_pfr0=49 1133id_pfr1=1 1134midr=890224640 1135 1136[system.cpu1.itb] 1137type=ArmTLB 1138children=walker |
1139eventq_index=0 |
|
1018size=64 1019walker=system.cpu1.itb.walker 1020 1021[system.cpu1.itb.walker] 1022type=ArmTableWalker 1023clk_domain=system.cpu_clk_domain | 1140size=64 1141walker=system.cpu1.itb.walker 1142 1143[system.cpu1.itb.walker] 1144type=ArmTableWalker 1145clk_domain=system.cpu_clk_domain |
1146eventq_index=0 |
|
1024num_squash_per_cycle=2 1025sys=system 1026port=system.toL2Bus.slave[6] 1027 1028[system.cpu1.tracer] 1029type=ExeTracer | 1147num_squash_per_cycle=2 1148sys=system 1149port=system.toL2Bus.slave[6] 1150 1151[system.cpu1.tracer] 1152type=ExeTracer |
1153eventq_index=0 |
|
1030 1031[system.cpu_clk_domain] 1032type=SrcClockDomain 1033clock=500 | 1154 1155[system.cpu_clk_domain] 1156type=SrcClockDomain 1157clock=500 |
1158eventq_index=0 |
|
1034voltage_domain=system.voltage_domain 1035 1036[system.intrctrl] 1037type=IntrControl | 1159voltage_domain=system.voltage_domain 1160 1161[system.intrctrl] 1162type=IntrControl |
1163eventq_index=0 |
|
1038sys=system 1039 1040[system.iobus] 1041type=NoncoherentBus 1042clk_domain=system.clk_domain | 1164sys=system 1165 1166[system.iobus] 1167type=NoncoherentBus 1168clk_domain=system.clk_domain |
1169eventq_index=0 |
|
1043header_cycles=1 1044use_default_range=false 1045width=8 1046master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 1047slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 1048 1049[system.iocache] 1050type=BaseCache 1051children=tags 1052addr_ranges=0:134217727 1053assoc=8 1054clk_domain=system.clk_domain | 1170header_cycles=1 1171use_default_range=false 1172width=8 1173master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 1174slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 1175 1176[system.iocache] 1177type=BaseCache 1178children=tags 1179addr_ranges=0:134217727 1180assoc=8 1181clk_domain=system.clk_domain |
1182eventq_index=0 |
|
1055forward_snoops=false 1056hit_latency=50 1057is_top_level=true 1058max_miss_count=0 1059mshrs=20 1060prefetch_on_access=false 1061prefetcher=Null 1062response_latency=50 --- 6 unchanged lines hidden (view full) --- 1069cpu_side=system.iobus.master[25] 1070mem_side=system.membus.slave[2] 1071 1072[system.iocache.tags] 1073type=LRU 1074assoc=8 1075block_size=64 1076clk_domain=system.clk_domain | 1183forward_snoops=false 1184hit_latency=50 1185is_top_level=true 1186max_miss_count=0 1187mshrs=20 1188prefetch_on_access=false 1189prefetcher=Null 1190response_latency=50 --- 6 unchanged lines hidden (view full) --- 1197cpu_side=system.iobus.master[25] 1198mem_side=system.membus.slave[2] 1199 1200[system.iocache.tags] 1201type=LRU 1202assoc=8 1203block_size=64 1204clk_domain=system.clk_domain |
1205eventq_index=0 |
|
1077hit_latency=50 1078size=1024 1079 1080[system.l2c] 1081type=BaseCache 1082children=tags 1083addr_ranges=0:18446744073709551615 1084assoc=8 1085clk_domain=system.cpu_clk_domain | 1206hit_latency=50 1207size=1024 1208 1209[system.l2c] 1210type=BaseCache 1211children=tags 1212addr_ranges=0:18446744073709551615 1213assoc=8 1214clk_domain=system.cpu_clk_domain |
1215eventq_index=0 |
|
1086forward_snoops=true 1087hit_latency=20 1088is_top_level=false 1089max_miss_count=0 1090mshrs=20 1091prefetch_on_access=false 1092prefetcher=Null 1093response_latency=20 --- 6 unchanged lines hidden (view full) --- 1100cpu_side=system.toL2Bus.master[0] 1101mem_side=system.membus.slave[1] 1102 1103[system.l2c.tags] 1104type=LRU 1105assoc=8 1106block_size=64 1107clk_domain=system.cpu_clk_domain | 1216forward_snoops=true 1217hit_latency=20 1218is_top_level=false 1219max_miss_count=0 1220mshrs=20 1221prefetch_on_access=false 1222prefetcher=Null 1223response_latency=20 --- 6 unchanged lines hidden (view full) --- 1230cpu_side=system.toL2Bus.master[0] 1231mem_side=system.membus.slave[1] 1232 1233[system.l2c.tags] 1234type=LRU 1235assoc=8 1236block_size=64 1237clk_domain=system.cpu_clk_domain |
1238eventq_index=0 |
|
1108hit_latency=20 1109size=4194304 1110 1111[system.membus] 1112type=CoherentBus 1113children=badaddr_responder 1114clk_domain=system.clk_domain | 1239hit_latency=20 1240size=4194304 1241 1242[system.membus] 1243type=CoherentBus 1244children=badaddr_responder 1245clk_domain=system.clk_domain |
1246eventq_index=0 |
|
1115header_cycles=1 1116system=system 1117use_default_range=false 1118width=8 1119default=system.membus.badaddr_responder.pio 1120master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 1121slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1122 1123[system.membus.badaddr_responder] 1124type=IsaFake 1125clk_domain=system.clk_domain | 1247header_cycles=1 1248system=system 1249use_default_range=false 1250width=8 1251default=system.membus.badaddr_responder.pio 1252master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 1253slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1254 1255[system.membus.badaddr_responder] 1256type=IsaFake 1257clk_domain=system.clk_domain |
1258eventq_index=0 |
|
1126fake_mem=false 1127pio_addr=0 1128pio_latency=100000 1129pio_size=8 1130ret_bad_addr=true 1131ret_data16=65535 1132ret_data32=4294967295 1133ret_data64=18446744073709551615 --- 10 unchanged lines hidden (view full) --- 1144banks_per_rank=8 1145burst_length=8 1146channels=1 1147clk_domain=system.clk_domain 1148conf_table_reported=true 1149device_bus_width=8 1150device_rowbuffer_size=1024 1151devices_per_rank=8 | 1259fake_mem=false 1260pio_addr=0 1261pio_latency=100000 1262pio_size=8 1263ret_bad_addr=true 1264ret_data16=65535 1265ret_data32=4294967295 1266ret_data64=18446744073709551615 --- 10 unchanged lines hidden (view full) --- 1277banks_per_rank=8 1278burst_length=8 1279channels=1 1280clk_domain=system.clk_domain 1281conf_table_reported=true 1282device_bus_width=8 1283device_rowbuffer_size=1024 1284devices_per_rank=8 |
1285eventq_index=0 |
|
1152in_addr_map=true 1153mem_sched_policy=frfcfs 1154null=false 1155page_policy=open 1156range=0:134217727 1157ranks_per_channel=2 1158read_buffer_size=32 1159static_backend_latency=10000 1160static_frontend_latency=10000 1161tBURST=5000 1162tCL=13750 | 1286in_addr_map=true 1287mem_sched_policy=frfcfs 1288null=false 1289page_policy=open 1290range=0:134217727 1291ranks_per_channel=2 1292read_buffer_size=32 1293static_backend_latency=10000 1294static_frontend_latency=10000 1295tBURST=5000 1296tCL=13750 |
1297tRAS=35000 |
|
1163tRCD=13750 1164tREFI=7800000 1165tRFC=300000 1166tRP=13750 | 1298tRCD=13750 1299tREFI=7800000 1300tRFC=300000 1301tRP=13750 |
1302tRRD=6250 |
|
1167tWTR=7500 1168tXAW=40000 1169write_buffer_size=32 | 1303tWTR=7500 1304tXAW=40000 1305write_buffer_size=32 |
1170write_thresh_perc=70 | 1306write_high_thresh_perc=70 1307write_low_thresh_perc=0 |
1171port=system.membus.master[6] 1172 1173[system.realview] 1174type=RealView 1175children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake | 1308port=system.membus.master[6] 1309 1310[system.realview] 1311type=RealView 1312children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake |
1313eventq_index=0 |
|
1176intrctrl=system.intrctrl 1177max_mem_size=268435456 1178mem_start_addr=0 1179pci_cfg_base=0 1180system=system 1181 1182[system.realview.a9scu] 1183type=A9SCU 1184clk_domain=system.clk_domain | 1314intrctrl=system.intrctrl 1315max_mem_size=268435456 1316mem_start_addr=0 1317pci_cfg_base=0 1318system=system 1319 1320[system.realview.a9scu] 1321type=A9SCU 1322clk_domain=system.clk_domain |
1323eventq_index=0 |
|
1185pio_addr=520093696 1186pio_latency=100000 1187system=system 1188pio=system.membus.master[4] 1189 1190[system.realview.aaci_fake] 1191type=AmbaFake 1192amba_id=0 1193clk_domain=system.clk_domain | 1324pio_addr=520093696 1325pio_latency=100000 1326system=system 1327pio=system.membus.master[4] 1328 1329[system.realview.aaci_fake] 1330type=AmbaFake 1331amba_id=0 1332clk_domain=system.clk_domain |
1333eventq_index=0 |
|
1194ignore_access=false 1195pio_addr=268451840 1196pio_latency=100000 1197system=system 1198pio=system.iobus.master[21] 1199 1200[system.realview.cf_ctrl] 1201type=IdeController --- 12 unchanged lines hidden (view full) --- 1214BAR4=1 1215BAR4LegacyIO=false 1216BAR4Size=16 1217BAR5=1 1218BAR5LegacyIO=false 1219BAR5Size=0 1220BIST=0 1221CacheLineSize=0 | 1334ignore_access=false 1335pio_addr=268451840 1336pio_latency=100000 1337system=system 1338pio=system.iobus.master[21] 1339 1340[system.realview.cf_ctrl] 1341type=IdeController --- 12 unchanged lines hidden (view full) --- 1354BAR4=1 1355BAR4LegacyIO=false 1356BAR4Size=16 1357BAR5=1 1358BAR5LegacyIO=false 1359BAR5Size=0 1360BIST=0 1361CacheLineSize=0 |
1362CapabilityPtr=0 |
|
1222CardbusCIS=0 1223ClassCode=1 1224Command=1 1225DeviceID=28945 1226ExpansionROM=0 1227HeaderType=0 1228InterruptLine=31 1229InterruptPin=1 1230LatencyTimer=0 | 1363CardbusCIS=0 1364ClassCode=1 1365Command=1 1366DeviceID=28945 1367ExpansionROM=0 1368HeaderType=0 1369InterruptLine=31 1370InterruptPin=1 1371LatencyTimer=0 |
1372MSICAPBaseOffset=0 1373MSICAPCapId=0 1374MSICAPMaskBits=0 1375MSICAPMsgAddr=0 1376MSICAPMsgCtrl=0 1377MSICAPMsgData=0 1378MSICAPMsgUpperAddr=0 1379MSICAPNextCapability=0 1380MSICAPPendingBits=0 1381MSIXCAPBaseOffset=0 1382MSIXCAPCapId=0 1383MSIXCAPNextCapability=0 1384MSIXMsgCtrl=0 1385MSIXPbaOffset=0 1386MSIXTableOffset=0 |
|
1231MaximumLatency=0 1232MinimumGrant=0 | 1387MaximumLatency=0 1388MinimumGrant=0 |
1389PMCAPBaseOffset=0 1390PMCAPCapId=0 1391PMCAPCapabilities=0 1392PMCAPCtrlStatus=0 1393PMCAPNextCapability=0 1394PXCAPBaseOffset=0 1395PXCAPCapId=0 1396PXCAPCapabilities=0 1397PXCAPDevCap2=0 1398PXCAPDevCapabilities=0 1399PXCAPDevCtrl=0 1400PXCAPDevCtrl2=0 1401PXCAPDevStatus=0 1402PXCAPLinkCap=0 1403PXCAPLinkCtrl=0 1404PXCAPLinkStatus=0 1405PXCAPNextCapability=0 |
|
1233ProgIF=133 1234Revision=0 1235Status=640 1236SubClassCode=1 1237SubsystemID=0 1238SubsystemVendorID=0 1239VendorID=32902 1240clk_domain=system.clk_domain 1241config_latency=20000 1242ctrl_offset=2 1243disks=system.cf0 | 1406ProgIF=133 1407Revision=0 1408Status=640 1409SubClassCode=1 1410SubsystemID=0 1411SubsystemVendorID=0 1412VendorID=32902 1413clk_domain=system.clk_domain 1414config_latency=20000 1415ctrl_offset=2 1416disks=system.cf0 |
1417eventq_index=0 |
|
1244io_shift=1 1245pci_bus=2 1246pci_dev=7 1247pci_func=0 1248pio_latency=30000 1249platform=system.realview 1250system=system 1251config=system.iobus.master[8] 1252dma=system.iobus.slave[2] 1253pio=system.iobus.master[7] 1254 1255[system.realview.clcd] 1256type=Pl111 1257amba_id=1315089 1258clk_domain=system.clk_domain | 1418io_shift=1 1419pci_bus=2 1420pci_dev=7 1421pci_func=0 1422pio_latency=30000 1423platform=system.realview 1424system=system 1425config=system.iobus.master[8] 1426dma=system.iobus.slave[2] 1427pio=system.iobus.master[7] 1428 1429[system.realview.clcd] 1430type=Pl111 1431amba_id=1315089 1432clk_domain=system.clk_domain |
1433enable_capture=true 1434eventq_index=0 |
|
1259gic=system.realview.gic 1260int_num=55 1261pio_addr=268566528 1262pio_latency=10000 1263pixel_clock=41667 1264system=system 1265vnc=system.vncserver 1266dma=system.iobus.slave[1] 1267pio=system.iobus.master[4] 1268 1269[system.realview.dmac_fake] 1270type=AmbaFake 1271amba_id=0 1272clk_domain=system.clk_domain | 1435gic=system.realview.gic 1436int_num=55 1437pio_addr=268566528 1438pio_latency=10000 1439pixel_clock=41667 1440system=system 1441vnc=system.vncserver 1442dma=system.iobus.slave[1] 1443pio=system.iobus.master[4] 1444 1445[system.realview.dmac_fake] 1446type=AmbaFake 1447amba_id=0 1448clk_domain=system.clk_domain |
1449eventq_index=0 |
|
1273ignore_access=false 1274pio_addr=268632064 1275pio_latency=100000 1276system=system 1277pio=system.iobus.master[9] 1278 1279[system.realview.flash_fake] 1280type=IsaFake 1281clk_domain=system.clk_domain | 1450ignore_access=false 1451pio_addr=268632064 1452pio_latency=100000 1453system=system 1454pio=system.iobus.master[9] 1455 1456[system.realview.flash_fake] 1457type=IsaFake 1458clk_domain=system.clk_domain |
1459eventq_index=0 |
|
1282fake_mem=true 1283pio_addr=1073741824 1284pio_latency=100000 1285pio_size=536870912 1286ret_bad_addr=false 1287ret_data16=65535 1288ret_data32=4294967295 1289ret_data64=18446744073709551615 --- 5 unchanged lines hidden (view full) --- 1295 1296[system.realview.gic] 1297type=Pl390 1298clk_domain=system.clk_domain 1299cpu_addr=520093952 1300cpu_pio_delay=10000 1301dist_addr=520097792 1302dist_pio_delay=10000 | 1460fake_mem=true 1461pio_addr=1073741824 1462pio_latency=100000 1463pio_size=536870912 1464ret_bad_addr=false 1465ret_data16=65535 1466ret_data32=4294967295 1467ret_data64=18446744073709551615 --- 5 unchanged lines hidden (view full) --- 1473 1474[system.realview.gic] 1475type=Pl390 1476clk_domain=system.clk_domain 1477cpu_addr=520093952 1478cpu_pio_delay=10000 1479dist_addr=520097792 1480dist_pio_delay=10000 |
1481eventq_index=0 |
|
1303int_latency=10000 1304it_lines=128 | 1482int_latency=10000 1483it_lines=128 |
1484msix_addr=0 |
|
1305platform=system.realview 1306system=system 1307pio=system.membus.master[2] 1308 1309[system.realview.gpio0_fake] 1310type=AmbaFake 1311amba_id=0 1312clk_domain=system.clk_domain | 1485platform=system.realview 1486system=system 1487pio=system.membus.master[2] 1488 1489[system.realview.gpio0_fake] 1490type=AmbaFake 1491amba_id=0 1492clk_domain=system.clk_domain |
1493eventq_index=0 |
|
1313ignore_access=false 1314pio_addr=268513280 1315pio_latency=100000 1316system=system 1317pio=system.iobus.master[16] 1318 1319[system.realview.gpio1_fake] 1320type=AmbaFake 1321amba_id=0 1322clk_domain=system.clk_domain | 1494ignore_access=false 1495pio_addr=268513280 1496pio_latency=100000 1497system=system 1498pio=system.iobus.master[16] 1499 1500[system.realview.gpio1_fake] 1501type=AmbaFake 1502amba_id=0 1503clk_domain=system.clk_domain |
1504eventq_index=0 |
|
1323ignore_access=false 1324pio_addr=268517376 1325pio_latency=100000 1326system=system 1327pio=system.iobus.master[17] 1328 1329[system.realview.gpio2_fake] 1330type=AmbaFake 1331amba_id=0 1332clk_domain=system.clk_domain | 1505ignore_access=false 1506pio_addr=268517376 1507pio_latency=100000 1508system=system 1509pio=system.iobus.master[17] 1510 1511[system.realview.gpio2_fake] 1512type=AmbaFake 1513amba_id=0 1514clk_domain=system.clk_domain |
1515eventq_index=0 |
|
1333ignore_access=false 1334pio_addr=268521472 1335pio_latency=100000 1336system=system 1337pio=system.iobus.master[18] 1338 1339[system.realview.kmi0] 1340type=Pl050 1341amba_id=1314896 1342clk_domain=system.clk_domain | 1516ignore_access=false 1517pio_addr=268521472 1518pio_latency=100000 1519system=system 1520pio=system.iobus.master[18] 1521 1522[system.realview.kmi0] 1523type=Pl050 1524amba_id=1314896 1525clk_domain=system.clk_domain |
1526eventq_index=0 |
|
1343gic=system.realview.gic 1344int_delay=1000000 1345int_num=52 1346is_mouse=false 1347pio_addr=268460032 1348pio_latency=100000 1349system=system 1350vnc=system.vncserver 1351pio=system.iobus.master[5] 1352 1353[system.realview.kmi1] 1354type=Pl050 1355amba_id=1314896 1356clk_domain=system.clk_domain | 1527gic=system.realview.gic 1528int_delay=1000000 1529int_num=52 1530is_mouse=false 1531pio_addr=268460032 1532pio_latency=100000 1533system=system 1534vnc=system.vncserver 1535pio=system.iobus.master[5] 1536 1537[system.realview.kmi1] 1538type=Pl050 1539amba_id=1314896 1540clk_domain=system.clk_domain |
1541eventq_index=0 |
|
1357gic=system.realview.gic 1358int_delay=1000000 1359int_num=53 1360is_mouse=true 1361pio_addr=268464128 1362pio_latency=100000 1363system=system 1364vnc=system.vncserver 1365pio=system.iobus.master[6] 1366 1367[system.realview.l2x0_fake] 1368type=IsaFake 1369clk_domain=system.clk_domain | 1542gic=system.realview.gic 1543int_delay=1000000 1544int_num=53 1545is_mouse=true 1546pio_addr=268464128 1547pio_latency=100000 1548system=system 1549vnc=system.vncserver 1550pio=system.iobus.master[6] 1551 1552[system.realview.l2x0_fake] 1553type=IsaFake 1554clk_domain=system.clk_domain |
1555eventq_index=0 |
|
1370fake_mem=false 1371pio_addr=520101888 1372pio_latency=100000 1373pio_size=4095 1374ret_bad_addr=false 1375ret_data16=65535 1376ret_data32=4294967295 1377ret_data64=18446744073709551615 1378ret_data8=255 1379system=system 1380update_data=false 1381warn_access= 1382pio=system.membus.master[3] 1383 1384[system.realview.local_cpu_timer] 1385type=CpuLocalTimer 1386clk_domain=system.clk_domain | 1556fake_mem=false 1557pio_addr=520101888 1558pio_latency=100000 1559pio_size=4095 1560ret_bad_addr=false 1561ret_data16=65535 1562ret_data32=4294967295 1563ret_data64=18446744073709551615 1564ret_data8=255 1565system=system 1566update_data=false 1567warn_access= 1568pio=system.membus.master[3] 1569 1570[system.realview.local_cpu_timer] 1571type=CpuLocalTimer 1572clk_domain=system.clk_domain |
1573eventq_index=0 |
|
1387gic=system.realview.gic 1388int_num_timer=29 1389int_num_watchdog=30 1390pio_addr=520095232 1391pio_latency=100000 1392system=system 1393pio=system.membus.master[5] 1394 1395[system.realview.mmc_fake] 1396type=AmbaFake 1397amba_id=0 1398clk_domain=system.clk_domain | 1574gic=system.realview.gic 1575int_num_timer=29 1576int_num_watchdog=30 1577pio_addr=520095232 1578pio_latency=100000 1579system=system 1580pio=system.membus.master[5] 1581 1582[system.realview.mmc_fake] 1583type=AmbaFake 1584amba_id=0 1585clk_domain=system.clk_domain |
1586eventq_index=0 |
|
1399ignore_access=false 1400pio_addr=268455936 1401pio_latency=100000 1402system=system 1403pio=system.iobus.master[22] 1404 1405[system.realview.nvmem] 1406type=SimpleMemory 1407bandwidth=73.000000 1408clk_domain=system.clk_domain 1409conf_table_reported=false | 1587ignore_access=false 1588pio_addr=268455936 1589pio_latency=100000 1590system=system 1591pio=system.iobus.master[22] 1592 1593[system.realview.nvmem] 1594type=SimpleMemory 1595bandwidth=73.000000 1596clk_domain=system.clk_domain 1597conf_table_reported=false |
1598eventq_index=0 |
|
1410in_addr_map=true 1411latency=30000 1412latency_var=0 1413null=false 1414range=2147483648:2214592511 1415port=system.membus.master[1] 1416 1417[system.realview.realview_io] 1418type=RealViewCtrl 1419clk_domain=system.clk_domain | 1599in_addr_map=true 1600latency=30000 1601latency_var=0 1602null=false 1603range=2147483648:2214592511 1604port=system.membus.master[1] 1605 1606[system.realview.realview_io] 1607type=RealViewCtrl 1608clk_domain=system.clk_domain |
1609eventq_index=0 |
|
1420idreg=0 1421pio_addr=268435456 1422pio_latency=100000 1423proc_id0=201326592 1424proc_id1=201327138 1425system=system 1426pio=system.iobus.master[1] 1427 1428[system.realview.rtc] 1429type=PL031 1430amba_id=3412017 1431clk_domain=system.clk_domain | 1610idreg=0 1611pio_addr=268435456 1612pio_latency=100000 1613proc_id0=201326592 1614proc_id1=201327138 1615system=system 1616pio=system.iobus.master[1] 1617 1618[system.realview.rtc] 1619type=PL031 1620amba_id=3412017 1621clk_domain=system.clk_domain |
1622eventq_index=0 |
|
1432gic=system.realview.gic 1433int_delay=100000 1434int_num=42 1435pio_addr=268529664 1436pio_latency=100000 1437system=system 1438time=Thu Jan 1 00:00:00 2009 1439pio=system.iobus.master[23] 1440 1441[system.realview.sci_fake] 1442type=AmbaFake 1443amba_id=0 1444clk_domain=system.clk_domain | 1623gic=system.realview.gic 1624int_delay=100000 1625int_num=42 1626pio_addr=268529664 1627pio_latency=100000 1628system=system 1629time=Thu Jan 1 00:00:00 2009 1630pio=system.iobus.master[23] 1631 1632[system.realview.sci_fake] 1633type=AmbaFake 1634amba_id=0 1635clk_domain=system.clk_domain |
1636eventq_index=0 |
|
1445ignore_access=false 1446pio_addr=268492800 1447pio_latency=100000 1448system=system 1449pio=system.iobus.master[20] 1450 1451[system.realview.smc_fake] 1452type=AmbaFake 1453amba_id=0 1454clk_domain=system.clk_domain | 1637ignore_access=false 1638pio_addr=268492800 1639pio_latency=100000 1640system=system 1641pio=system.iobus.master[20] 1642 1643[system.realview.smc_fake] 1644type=AmbaFake 1645amba_id=0 1646clk_domain=system.clk_domain |
1647eventq_index=0 |
|
1455ignore_access=false 1456pio_addr=269357056 1457pio_latency=100000 1458system=system 1459pio=system.iobus.master[13] 1460 1461[system.realview.sp810_fake] 1462type=AmbaFake 1463amba_id=0 1464clk_domain=system.clk_domain | 1648ignore_access=false 1649pio_addr=269357056 1650pio_latency=100000 1651system=system 1652pio=system.iobus.master[13] 1653 1654[system.realview.sp810_fake] 1655type=AmbaFake 1656amba_id=0 1657clk_domain=system.clk_domain |
1658eventq_index=0 |
|
1465ignore_access=true 1466pio_addr=268439552 1467pio_latency=100000 1468system=system 1469pio=system.iobus.master[14] 1470 1471[system.realview.ssp_fake] 1472type=AmbaFake 1473amba_id=0 1474clk_domain=system.clk_domain | 1659ignore_access=true 1660pio_addr=268439552 1661pio_latency=100000 1662system=system 1663pio=system.iobus.master[14] 1664 1665[system.realview.ssp_fake] 1666type=AmbaFake 1667amba_id=0 1668clk_domain=system.clk_domain |
1669eventq_index=0 |
|
1475ignore_access=false 1476pio_addr=268488704 1477pio_latency=100000 1478system=system 1479pio=system.iobus.master[19] 1480 1481[system.realview.timer0] 1482type=Sp804 1483amba_id=1316868 1484clk_domain=system.clk_domain 1485clock0=1000000 1486clock1=1000000 | 1670ignore_access=false 1671pio_addr=268488704 1672pio_latency=100000 1673system=system 1674pio=system.iobus.master[19] 1675 1676[system.realview.timer0] 1677type=Sp804 1678amba_id=1316868 1679clk_domain=system.clk_domain 1680clock0=1000000 1681clock1=1000000 |
1682eventq_index=0 |
|
1487gic=system.realview.gic 1488int_num0=36 1489int_num1=36 1490pio_addr=268505088 1491pio_latency=100000 1492system=system 1493pio=system.iobus.master[2] 1494 1495[system.realview.timer1] 1496type=Sp804 1497amba_id=1316868 1498clk_domain=system.clk_domain 1499clock0=1000000 1500clock1=1000000 | 1683gic=system.realview.gic 1684int_num0=36 1685int_num1=36 1686pio_addr=268505088 1687pio_latency=100000 1688system=system 1689pio=system.iobus.master[2] 1690 1691[system.realview.timer1] 1692type=Sp804 1693amba_id=1316868 1694clk_domain=system.clk_domain 1695clock0=1000000 1696clock1=1000000 |
1697eventq_index=0 |
|
1501gic=system.realview.gic 1502int_num0=37 1503int_num1=37 1504pio_addr=268509184 1505pio_latency=100000 1506system=system 1507pio=system.iobus.master[3] 1508 1509[system.realview.uart] 1510type=Pl011 1511clk_domain=system.clk_domain 1512end_on_eot=false | 1698gic=system.realview.gic 1699int_num0=37 1700int_num1=37 1701pio_addr=268509184 1702pio_latency=100000 1703system=system 1704pio=system.iobus.master[3] 1705 1706[system.realview.uart] 1707type=Pl011 1708clk_domain=system.clk_domain 1709end_on_eot=false |
1710eventq_index=0 |
|
1513gic=system.realview.gic 1514int_delay=100000 1515int_num=44 1516pio_addr=268472320 1517pio_latency=100000 1518platform=system.realview 1519system=system 1520terminal=system.terminal 1521pio=system.iobus.master[0] 1522 1523[system.realview.uart1_fake] 1524type=AmbaFake 1525amba_id=0 1526clk_domain=system.clk_domain | 1711gic=system.realview.gic 1712int_delay=100000 1713int_num=44 1714pio_addr=268472320 1715pio_latency=100000 1716platform=system.realview 1717system=system 1718terminal=system.terminal 1719pio=system.iobus.master[0] 1720 1721[system.realview.uart1_fake] 1722type=AmbaFake 1723amba_id=0 1724clk_domain=system.clk_domain |
1725eventq_index=0 |
|
1527ignore_access=false 1528pio_addr=268476416 1529pio_latency=100000 1530system=system 1531pio=system.iobus.master[10] 1532 1533[system.realview.uart2_fake] 1534type=AmbaFake 1535amba_id=0 1536clk_domain=system.clk_domain | 1726ignore_access=false 1727pio_addr=268476416 1728pio_latency=100000 1729system=system 1730pio=system.iobus.master[10] 1731 1732[system.realview.uart2_fake] 1733type=AmbaFake 1734amba_id=0 1735clk_domain=system.clk_domain |
1736eventq_index=0 |
|
1537ignore_access=false 1538pio_addr=268480512 1539pio_latency=100000 1540system=system 1541pio=system.iobus.master[11] 1542 1543[system.realview.uart3_fake] 1544type=AmbaFake 1545amba_id=0 1546clk_domain=system.clk_domain | 1737ignore_access=false 1738pio_addr=268480512 1739pio_latency=100000 1740system=system 1741pio=system.iobus.master[11] 1742 1743[system.realview.uart3_fake] 1744type=AmbaFake 1745amba_id=0 1746clk_domain=system.clk_domain |
1747eventq_index=0 |
|
1547ignore_access=false 1548pio_addr=268484608 1549pio_latency=100000 1550system=system 1551pio=system.iobus.master[12] 1552 1553[system.realview.watchdog_fake] 1554type=AmbaFake 1555amba_id=0 1556clk_domain=system.clk_domain | 1748ignore_access=false 1749pio_addr=268484608 1750pio_latency=100000 1751system=system 1752pio=system.iobus.master[12] 1753 1754[system.realview.watchdog_fake] 1755type=AmbaFake 1756amba_id=0 1757clk_domain=system.clk_domain |
1758eventq_index=0 |
|
1557ignore_access=false 1558pio_addr=268500992 1559pio_latency=100000 1560system=system 1561pio=system.iobus.master[15] 1562 1563[system.terminal] 1564type=Terminal | 1759ignore_access=false 1760pio_addr=268500992 1761pio_latency=100000 1762system=system 1763pio=system.iobus.master[15] 1764 1765[system.terminal] 1766type=Terminal |
1767eventq_index=0 |
|
1565intr_control=system.intrctrl 1566number=0 1567output=true 1568port=3456 1569 1570[system.toL2Bus] 1571type=CoherentBus 1572clk_domain=system.cpu_clk_domain | 1768intr_control=system.intrctrl 1769number=0 1770output=true 1771port=3456 1772 1773[system.toL2Bus] 1774type=CoherentBus 1775clk_domain=system.cpu_clk_domain |
1776eventq_index=0 |
|
1573header_cycles=1 1574system=system 1575use_default_range=false 1576width=8 1577master=system.l2c.cpu_side 1578slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1579 1580[system.vncserver] 1581type=VncServer | 1777header_cycles=1 1778system=system 1779use_default_range=false 1780width=8 1781master=system.l2c.cpu_side 1782slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1783 1784[system.vncserver] 1785type=VncServer |
1786eventq_index=0 |
|
1582frame_capture=false 1583number=0 1584port=5900 1585 1586[system.voltage_domain] 1587type=VoltageDomain | 1787frame_capture=false 1788number=0 1789port=5900 1790 1791[system.voltage_domain] 1792type=VoltageDomain |
1793eventq_index=0 |
|
1588voltage=1.000000 1589 | 1794voltage=1.000000 1795 |