| config.ini (11680:b4d943429dc6) | config.ini (11957:90bb43dfc028) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 14atags_addr=134217728 | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 14atags_addr=134217728 |
| 15boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm | 15boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm |
| 16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 17cache_line_size=64 18clk_domain=system.clk_domain 19default_p_state=UNDEFINED | 16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 17cache_line_size=64 18clk_domain=system.clk_domain 19default_p_state=UNDEFINED |
| 20dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb | 20dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb |
| 21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0 24exit_on_work_items=false 25flags_addr=469827632 26gic_cpu_addr=738205696 27have_large_asid_64=false 28have_lpae=true 29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0 | 21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0 24exit_on_work_items=false 25flags_addr=469827632 26gic_cpu_addr=738205696 27have_large_asid_64=false 28have_lpae=true 29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0 |
| 33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 | 33kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 |
| 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM 38mem_mode=timing 39mem_ranges=2147483648:2415919103:0:0:0:0 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 48panic_on_oops=true 49panic_on_panic=true 50phys_addr_range_64=40 51power_model=Null | 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM 38mem_mode=timing 39mem_ranges=2147483648:2415919103:0:0:0:0 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 48panic_on_oops=true 49panic_on_panic=true 50phys_addr_range_64=40 51power_model=Null |
| 52readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh | 52readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh |
| 53reset_addr_64=0 54symbolfile= 55thermal_components= 56thermal_model=Null 57work_begin_ckpt_count=0 58work_begin_cpu_id_exit=-1 59work_begin_exit_count=0 60work_cpus_ckpt_count=0 --- 33 unchanged lines hidden (view full) --- 94eventq_index=0 95image_file= 96read_only=false 97table_size=65536 98 99[system.cf0.image.child] 100type=RawDiskImage 101eventq_index=0 | 53reset_addr_64=0 54symbolfile= 55thermal_components= 56thermal_model=Null 57work_begin_ckpt_count=0 58work_begin_cpu_id_exit=-1 59work_begin_exit_count=0 60work_cpus_ckpt_count=0 --- 33 unchanged lines hidden (view full) --- 94eventq_index=0 95image_file= 96read_only=false 97table_size=65536 98 99[system.cf0.image.child] 100type=RawDiskImage 101eventq_index=0 |
| 102image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img | 102image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img |
| 103read_only=true 104 105[system.clk_domain] 106type=SrcClockDomain 107clock=1000 108domain_id=-1 109eventq_index=0 110init_perf_level=0 --- 6 unchanged lines hidden (view full) --- 117LQEntries=16 118LSQCheckLoads=true 119LSQDepCheckShift=0 120SQEntries=16 121SSITSize=1024 122activity=0 123backComSize=5 124branchPred=system.cpu0.branchPred | 103read_only=true 104 105[system.clk_domain] 106type=SrcClockDomain 107clock=1000 108domain_id=-1 109eventq_index=0 110init_perf_level=0 --- 6 unchanged lines hidden (view full) --- 117LQEntries=16 118LSQCheckLoads=true 119LSQDepCheckShift=0 120SQEntries=16 121SSITSize=1024 122activity=0 123backComSize=5 124branchPred=system.cpu0.branchPred |
| 125cachePorts=200 | 125cacheStorePorts=200 |
| 126checker=Null 127clk_domain=system.cpu_clk_domain 128commitToDecodeDelay=1 129commitToFetchDelay=1 130commitToIEWDelay=1 131commitToRenameDelay=1 132commitWidth=8 133cpu_id=0 --- 59 unchanged lines hidden (view full) --- 193smtLSQThreshold=100 194smtNumFetchingThreads=1 195smtROBPolicy=Partitioned 196smtROBThreshold=100 197socket_id=0 198squashWidth=8 199store_set_clear_period=250000 200switched_out=false | 126checker=Null 127clk_domain=system.cpu_clk_domain 128commitToDecodeDelay=1 129commitToFetchDelay=1 130commitToIEWDelay=1 131commitToRenameDelay=1 132commitWidth=8 133cpu_id=0 --- 59 unchanged lines hidden (view full) --- 193smtLSQThreshold=100 194smtNumFetchingThreads=1 195smtROBPolicy=Partitioned 196smtROBThreshold=100 197socket_id=0 198squashWidth=8 199store_set_clear_period=250000 200switched_out=false |
| 201syscallRetryLatency=10000 |
|
| 201system=system 202tracer=system.cpu0.tracer 203trapLatency=13 204wbWidth=8 205workload= 206dcache_port=system.cpu0.dcache.cpu_side 207icache_port=system.cpu0.icache.cpu_side 208 --- 19 unchanged lines hidden (view full) --- 228 229[system.cpu0.dcache] 230type=Cache 231children=tags 232addr_ranges=0:18446744073709551615:0:0:0:0 233assoc=2 234clk_domain=system.cpu_clk_domain 235clusivity=mostly_incl | 202system=system 203tracer=system.cpu0.tracer 204trapLatency=13 205wbWidth=8 206workload= 207dcache_port=system.cpu0.dcache.cpu_side 208icache_port=system.cpu0.icache.cpu_side 209 --- 19 unchanged lines hidden (view full) --- 229 230[system.cpu0.dcache] 231type=Cache 232children=tags 233addr_ranges=0:18446744073709551615:0:0:0:0 234assoc=2 235clk_domain=system.cpu_clk_domain 236clusivity=mostly_incl |
| 237data_latency=2 |
|
| 236default_p_state=UNDEFINED 237demand_mshr_reserve=1 238eventq_index=0 | 238default_p_state=UNDEFINED 239demand_mshr_reserve=1 240eventq_index=0 |
| 239hit_latency=2 | |
| 240is_read_only=false 241max_miss_count=0 242mshrs=6 243p_state_clk_gate_bins=20 244p_state_clk_gate_max=1000000000000 245p_state_clk_gate_min=1000 246power_model=Null 247prefetch_on_access=false 248prefetcher=Null 249response_latency=2 250sequential_access=false 251size=32768 252system=system | 241is_read_only=false 242max_miss_count=0 243mshrs=6 244p_state_clk_gate_bins=20 245p_state_clk_gate_max=1000000000000 246p_state_clk_gate_min=1000 247power_model=Null 248prefetch_on_access=false 249prefetcher=Null 250response_latency=2 251sequential_access=false 252size=32768 253system=system |
| 254tag_latency=2 |
|
| 253tags=system.cpu0.dcache.tags 254tgts_per_mshr=8 255write_buffers=16 256writeback_clean=true 257cpu_side=system.cpu0.dcache_port 258mem_side=system.cpu0.toL2Bus.slave[1] 259 260[system.cpu0.dcache.tags] 261type=LRU 262assoc=2 263block_size=64 264clk_domain=system.cpu_clk_domain | 255tags=system.cpu0.dcache.tags 256tgts_per_mshr=8 257write_buffers=16 258writeback_clean=true 259cpu_side=system.cpu0.dcache_port 260mem_side=system.cpu0.toL2Bus.slave[1] 261 262[system.cpu0.dcache.tags] 263type=LRU 264assoc=2 265block_size=64 266clk_domain=system.cpu_clk_domain |
| 267data_latency=2 |
|
| 265default_p_state=UNDEFINED 266eventq_index=0 | 268default_p_state=UNDEFINED 269eventq_index=0 |
| 267hit_latency=2 | |
| 268p_state_clk_gate_bins=20 269p_state_clk_gate_max=1000000000000 270p_state_clk_gate_min=1000 271power_model=Null 272sequential_access=false 273size=32768 | 270p_state_clk_gate_bins=20 271p_state_clk_gate_max=1000000000000 272p_state_clk_gate_min=1000 273power_model=Null 274sequential_access=false 275size=32768 |
| 276tag_latency=2 |
|
| 274 275[system.cpu0.dstage2_mmu] 276type=ArmStage2MMU 277children=stage2_tlb 278eventq_index=0 279stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb 280sys=system 281tlb=system.cpu0.dtb --- 86 unchanged lines hidden (view full) --- 368type=OpDesc 369eventq_index=0 370opClass=IprAccess 371opLat=3 372pipelined=true 373 374[system.cpu0.fuPool.FUList2] 375type=FUDesc | 277 278[system.cpu0.dstage2_mmu] 279type=ArmStage2MMU 280children=stage2_tlb 281eventq_index=0 282stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb 283sys=system 284tlb=system.cpu0.dtb --- 86 unchanged lines hidden (view full) --- 371type=OpDesc 372eventq_index=0 373opClass=IprAccess 374opLat=3 375pipelined=true 376 377[system.cpu0.fuPool.FUList2] 378type=FUDesc |
| 376children=opList | 379children=opList0 opList1 |
| 377count=1 378eventq_index=0 | 380count=1 381eventq_index=0 |
| 379opList=system.cpu0.fuPool.FUList2.opList | 382opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 |
| 380 | 383 |
| 381[system.cpu0.fuPool.FUList2.opList] | 384[system.cpu0.fuPool.FUList2.opList0] |
| 382type=OpDesc 383eventq_index=0 384opClass=MemRead 385opLat=2 386pipelined=true 387 | 385type=OpDesc 386eventq_index=0 387opClass=MemRead 388opLat=2 389pipelined=true 390 |
| 391[system.cpu0.fuPool.FUList2.opList1] 392type=OpDesc 393eventq_index=0 394opClass=FloatMemRead 395opLat=2 396pipelined=true 397 |
|
| 388[system.cpu0.fuPool.FUList3] 389type=FUDesc | 398[system.cpu0.fuPool.FUList3] 399type=FUDesc |
| 390children=opList | 400children=opList0 opList1 |
| 391count=1 392eventq_index=0 | 401count=1 402eventq_index=0 |
| 393opList=system.cpu0.fuPool.FUList3.opList | 403opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 |
| 394 | 404 |
| 395[system.cpu0.fuPool.FUList3.opList] | 405[system.cpu0.fuPool.FUList3.opList0] |
| 396type=OpDesc 397eventq_index=0 398opClass=MemWrite 399opLat=2 400pipelined=true 401 | 406type=OpDesc 407eventq_index=0 408opClass=MemWrite 409opLat=2 410pipelined=true 411 |
| 412[system.cpu0.fuPool.FUList3.opList1] 413type=OpDesc 414eventq_index=0 415opClass=FloatMemWrite 416opLat=2 417pipelined=true 418 |
|
| 402[system.cpu0.fuPool.FUList4] 403type=FUDesc | 419[system.cpu0.fuPool.FUList4] 420type=FUDesc |
| 404children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 | 421children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 |
| 405count=2 406eventq_index=0 | 422count=2 423eventq_index=0 |
| 407opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 | 424opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 system.cpu0.fuPool.FUList4.opList26 system.cpu0.fuPool.FUList4.opList27 |
| 408 409[system.cpu0.fuPool.FUList4.opList00] 410type=OpDesc 411eventq_index=0 412opClass=SimdAdd 413opLat=4 414pipelined=true 415 --- 115 unchanged lines hidden (view full) --- 531opClass=SimdFloatMult 532opLat=3 533pipelined=true 534 535[system.cpu0.fuPool.FUList4.opList18] 536type=OpDesc 537eventq_index=0 538opClass=SimdFloatMultAcc | 425 426[system.cpu0.fuPool.FUList4.opList00] 427type=OpDesc 428eventq_index=0 429opClass=SimdAdd 430opLat=4 431pipelined=true 432 --- 115 unchanged lines hidden (view full) --- 548opClass=SimdFloatMult 549opLat=3 550pipelined=true 551 552[system.cpu0.fuPool.FUList4.opList18] 553type=OpDesc 554eventq_index=0 555opClass=SimdFloatMultAcc |
| 539opLat=1 | 556opLat=5 |
| 540pipelined=true 541 542[system.cpu0.fuPool.FUList4.opList19] 543type=OpDesc 544eventq_index=0 545opClass=SimdFloatSqrt 546opLat=9 547pipelined=true --- 35 unchanged lines hidden (view full) --- 583 584[system.cpu0.fuPool.FUList4.opList25] 585type=OpDesc 586eventq_index=0 587opClass=FloatMult 588opLat=4 589pipelined=true 590 | 557pipelined=true 558 559[system.cpu0.fuPool.FUList4.opList19] 560type=OpDesc 561eventq_index=0 562opClass=SimdFloatSqrt 563opLat=9 564pipelined=true --- 35 unchanged lines hidden (view full) --- 600 601[system.cpu0.fuPool.FUList4.opList25] 602type=OpDesc 603eventq_index=0 604opClass=FloatMult 605opLat=4 606pipelined=true 607 |
| 608[system.cpu0.fuPool.FUList4.opList26] 609type=OpDesc 610eventq_index=0 611opClass=FloatMultAcc 612opLat=5 613pipelined=true 614 615[system.cpu0.fuPool.FUList4.opList27] 616type=OpDesc 617eventq_index=0 618opClass=FloatMisc 619opLat=3 620pipelined=true 621 |
|
| 591[system.cpu0.icache] 592type=Cache 593children=tags 594addr_ranges=0:18446744073709551615:0:0:0:0 595assoc=2 596clk_domain=system.cpu_clk_domain 597clusivity=mostly_incl | 622[system.cpu0.icache] 623type=Cache 624children=tags 625addr_ranges=0:18446744073709551615:0:0:0:0 626assoc=2 627clk_domain=system.cpu_clk_domain 628clusivity=mostly_incl |
| 629data_latency=1 |
|
| 598default_p_state=UNDEFINED 599demand_mshr_reserve=1 600eventq_index=0 | 630default_p_state=UNDEFINED 631demand_mshr_reserve=1 632eventq_index=0 |
| 601hit_latency=1 | |
| 602is_read_only=true 603max_miss_count=0 604mshrs=2 605p_state_clk_gate_bins=20 606p_state_clk_gate_max=1000000000000 607p_state_clk_gate_min=1000 608power_model=Null 609prefetch_on_access=false 610prefetcher=Null 611response_latency=1 612sequential_access=false 613size=32768 614system=system | 633is_read_only=true 634max_miss_count=0 635mshrs=2 636p_state_clk_gate_bins=20 637p_state_clk_gate_max=1000000000000 638p_state_clk_gate_min=1000 639power_model=Null 640prefetch_on_access=false 641prefetcher=Null 642response_latency=1 643sequential_access=false 644size=32768 645system=system |
| 646tag_latency=1 |
|
| 615tags=system.cpu0.icache.tags 616tgts_per_mshr=8 617write_buffers=8 618writeback_clean=true 619cpu_side=system.cpu0.icache_port 620mem_side=system.cpu0.toL2Bus.slave[0] 621 622[system.cpu0.icache.tags] 623type=LRU 624assoc=2 625block_size=64 626clk_domain=system.cpu_clk_domain | 647tags=system.cpu0.icache.tags 648tgts_per_mshr=8 649write_buffers=8 650writeback_clean=true 651cpu_side=system.cpu0.icache_port 652mem_side=system.cpu0.toL2Bus.slave[0] 653 654[system.cpu0.icache.tags] 655type=LRU 656assoc=2 657block_size=64 658clk_domain=system.cpu_clk_domain |
| 659data_latency=1 |
|
| 627default_p_state=UNDEFINED 628eventq_index=0 | 660default_p_state=UNDEFINED 661eventq_index=0 |
| 629hit_latency=1 | |
| 630p_state_clk_gate_bins=20 631p_state_clk_gate_max=1000000000000 632p_state_clk_gate_min=1000 633power_model=Null 634sequential_access=false 635size=32768 | 662p_state_clk_gate_bins=20 663p_state_clk_gate_max=1000000000000 664p_state_clk_gate_min=1000 665power_model=Null 666sequential_access=false 667size=32768 |
| 668tag_latency=1 |
|
| 636 637[system.cpu0.interrupts] 638type=ArmInterrupts 639eventq_index=0 640 641[system.cpu0.isa] 642type=ArmISA 643decoderFlavour=Generic 644eventq_index=0 645fpsid=1090793632 646id_aa64afr0_el1=0 647id_aa64afr1_el1=0 648id_aa64dfr0_el1=1052678 649id_aa64dfr1_el1=0 650id_aa64isar0_el1=0 651id_aa64isar1_el1=0 652id_aa64mmfr0_el1=15728642 653id_aa64mmfr1_el1=0 | 669 670[system.cpu0.interrupts] 671type=ArmInterrupts 672eventq_index=0 673 674[system.cpu0.isa] 675type=ArmISA 676decoderFlavour=Generic 677eventq_index=0 678fpsid=1090793632 679id_aa64afr0_el1=0 680id_aa64afr1_el1=0 681id_aa64dfr0_el1=1052678 682id_aa64dfr1_el1=0 683id_aa64isar0_el1=0 684id_aa64isar1_el1=0 685id_aa64mmfr0_el1=15728642 686id_aa64mmfr1_el1=0 |
| 654id_aa64pfr0_el1=34 655id_aa64pfr1_el1=0 | |
| 656id_isar0=34607377 657id_isar1=34677009 658id_isar2=555950401 659id_isar3=17899825 660id_isar4=268501314 661id_isar5=0 662id_mmfr0=270536963 663id_mmfr1=0 664id_mmfr2=19070976 665id_mmfr3=34611729 | 687id_isar0=34607377 688id_isar1=34677009 689id_isar2=555950401 690id_isar3=17899825 691id_isar4=268501314 692id_isar5=0 693id_mmfr0=270536963 694id_mmfr1=0 695id_mmfr2=19070976 696id_mmfr3=34611729 |
| 666id_pfr0=49 667id_pfr1=4113 | |
| 668midr=1091551472 669pmu=Null 670system=system 671 672[system.cpu0.istage2_mmu] 673type=ArmStage2MMU 674children=stage2_tlb 675eventq_index=0 --- 46 unchanged lines hidden (view full) --- 722 723[system.cpu0.l2cache] 724type=Cache 725children=prefetcher tags 726addr_ranges=0:18446744073709551615:0:0:0:0 727assoc=16 728clk_domain=system.cpu_clk_domain 729clusivity=mostly_excl | 697midr=1091551472 698pmu=Null 699system=system 700 701[system.cpu0.istage2_mmu] 702type=ArmStage2MMU 703children=stage2_tlb 704eventq_index=0 --- 46 unchanged lines hidden (view full) --- 751 752[system.cpu0.l2cache] 753type=Cache 754children=prefetcher tags 755addr_ranges=0:18446744073709551615:0:0:0:0 756assoc=16 757clk_domain=system.cpu_clk_domain 758clusivity=mostly_excl |
| 759data_latency=12 |
|
| 730default_p_state=UNDEFINED 731demand_mshr_reserve=1 732eventq_index=0 | 760default_p_state=UNDEFINED 761demand_mshr_reserve=1 762eventq_index=0 |
| 733hit_latency=12 | |
| 734is_read_only=false 735max_miss_count=0 736mshrs=16 737p_state_clk_gate_bins=20 738p_state_clk_gate_max=1000000000000 739p_state_clk_gate_min=1000 740power_model=Null 741prefetch_on_access=true 742prefetcher=system.cpu0.l2cache.prefetcher 743response_latency=12 744sequential_access=false 745size=1048576 746system=system | 763is_read_only=false 764max_miss_count=0 765mshrs=16 766p_state_clk_gate_bins=20 767p_state_clk_gate_max=1000000000000 768p_state_clk_gate_min=1000 769power_model=Null 770prefetch_on_access=true 771prefetcher=system.cpu0.l2cache.prefetcher 772response_latency=12 773sequential_access=false 774size=1048576 775system=system |
| 776tag_latency=12 |
|
| 747tags=system.cpu0.l2cache.tags 748tgts_per_mshr=8 749write_buffers=8 750writeback_clean=false 751cpu_side=system.cpu0.toL2Bus.master[0] 752mem_side=system.toL2Bus.slave[0] 753 754[system.cpu0.l2cache.prefetcher] --- 26 unchanged lines hidden (view full) --- 781thresh_conf=4 782use_master_id=true 783 784[system.cpu0.l2cache.tags] 785type=RandomRepl 786assoc=16 787block_size=64 788clk_domain=system.cpu_clk_domain | 777tags=system.cpu0.l2cache.tags 778tgts_per_mshr=8 779write_buffers=8 780writeback_clean=false 781cpu_side=system.cpu0.toL2Bus.master[0] 782mem_side=system.toL2Bus.slave[0] 783 784[system.cpu0.l2cache.prefetcher] --- 26 unchanged lines hidden (view full) --- 811thresh_conf=4 812use_master_id=true 813 814[system.cpu0.l2cache.tags] 815type=RandomRepl 816assoc=16 817block_size=64 818clk_domain=system.cpu_clk_domain |
| 819data_latency=12 |
|
| 789default_p_state=UNDEFINED 790eventq_index=0 | 820default_p_state=UNDEFINED 821eventq_index=0 |
| 791hit_latency=12 | |
| 792p_state_clk_gate_bins=20 793p_state_clk_gate_max=1000000000000 794p_state_clk_gate_min=1000 795power_model=Null 796sequential_access=false 797size=1048576 | 822p_state_clk_gate_bins=20 823p_state_clk_gate_max=1000000000000 824p_state_clk_gate_min=1000 825power_model=Null 826sequential_access=false 827size=1048576 |
| 828tag_latency=12 |
|
| 798 799[system.cpu0.toL2Bus] 800type=CoherentXBar 801children=snoop_filter 802clk_domain=system.cpu_clk_domain 803default_p_state=UNDEFINED 804eventq_index=0 805forward_latency=0 --- 30 unchanged lines hidden (view full) --- 836LQEntries=16 837LSQCheckLoads=true 838LSQDepCheckShift=0 839SQEntries=16 840SSITSize=1024 841activity=0 842backComSize=5 843branchPred=system.cpu1.branchPred | 829 830[system.cpu0.toL2Bus] 831type=CoherentXBar 832children=snoop_filter 833clk_domain=system.cpu_clk_domain 834default_p_state=UNDEFINED 835eventq_index=0 836forward_latency=0 --- 30 unchanged lines hidden (view full) --- 867LQEntries=16 868LSQCheckLoads=true 869LSQDepCheckShift=0 870SQEntries=16 871SSITSize=1024 872activity=0 873backComSize=5 874branchPred=system.cpu1.branchPred |
| 844cachePorts=200 | 875cacheStorePorts=200 |
| 845checker=Null 846clk_domain=system.cpu_clk_domain 847commitToDecodeDelay=1 848commitToFetchDelay=1 849commitToIEWDelay=1 850commitToRenameDelay=1 851commitWidth=8 852cpu_id=1 --- 59 unchanged lines hidden (view full) --- 912smtLSQThreshold=100 913smtNumFetchingThreads=1 914smtROBPolicy=Partitioned 915smtROBThreshold=100 916socket_id=0 917squashWidth=8 918store_set_clear_period=250000 919switched_out=false | 876checker=Null 877clk_domain=system.cpu_clk_domain 878commitToDecodeDelay=1 879commitToFetchDelay=1 880commitToIEWDelay=1 881commitToRenameDelay=1 882commitWidth=8 883cpu_id=1 --- 59 unchanged lines hidden (view full) --- 943smtLSQThreshold=100 944smtNumFetchingThreads=1 945smtROBPolicy=Partitioned 946smtROBThreshold=100 947socket_id=0 948squashWidth=8 949store_set_clear_period=250000 950switched_out=false |
| 951syscallRetryLatency=10000 |
|
| 920system=system 921tracer=system.cpu1.tracer 922trapLatency=13 923wbWidth=8 924workload= 925dcache_port=system.cpu1.dcache.cpu_side 926icache_port=system.cpu1.icache.cpu_side 927 --- 19 unchanged lines hidden (view full) --- 947 948[system.cpu1.dcache] 949type=Cache 950children=tags 951addr_ranges=0:18446744073709551615:0:0:0:0 952assoc=2 953clk_domain=system.cpu_clk_domain 954clusivity=mostly_incl | 952system=system 953tracer=system.cpu1.tracer 954trapLatency=13 955wbWidth=8 956workload= 957dcache_port=system.cpu1.dcache.cpu_side 958icache_port=system.cpu1.icache.cpu_side 959 --- 19 unchanged lines hidden (view full) --- 979 980[system.cpu1.dcache] 981type=Cache 982children=tags 983addr_ranges=0:18446744073709551615:0:0:0:0 984assoc=2 985clk_domain=system.cpu_clk_domain 986clusivity=mostly_incl |
| 987data_latency=2 |
|
| 955default_p_state=UNDEFINED 956demand_mshr_reserve=1 957eventq_index=0 | 988default_p_state=UNDEFINED 989demand_mshr_reserve=1 990eventq_index=0 |
| 958hit_latency=2 | |
| 959is_read_only=false 960max_miss_count=0 961mshrs=6 962p_state_clk_gate_bins=20 963p_state_clk_gate_max=1000000000000 964p_state_clk_gate_min=1000 965power_model=Null 966prefetch_on_access=false 967prefetcher=Null 968response_latency=2 969sequential_access=false 970size=32768 971system=system | 991is_read_only=false 992max_miss_count=0 993mshrs=6 994p_state_clk_gate_bins=20 995p_state_clk_gate_max=1000000000000 996p_state_clk_gate_min=1000 997power_model=Null 998prefetch_on_access=false 999prefetcher=Null 1000response_latency=2 1001sequential_access=false 1002size=32768 1003system=system |
| 1004tag_latency=2 |
|
| 972tags=system.cpu1.dcache.tags 973tgts_per_mshr=8 974write_buffers=16 975writeback_clean=true 976cpu_side=system.cpu1.dcache_port 977mem_side=system.cpu1.toL2Bus.slave[1] 978 979[system.cpu1.dcache.tags] 980type=LRU 981assoc=2 982block_size=64 983clk_domain=system.cpu_clk_domain | 1005tags=system.cpu1.dcache.tags 1006tgts_per_mshr=8 1007write_buffers=16 1008writeback_clean=true 1009cpu_side=system.cpu1.dcache_port 1010mem_side=system.cpu1.toL2Bus.slave[1] 1011 1012[system.cpu1.dcache.tags] 1013type=LRU 1014assoc=2 1015block_size=64 1016clk_domain=system.cpu_clk_domain |
| 1017data_latency=2 |
|
| 984default_p_state=UNDEFINED 985eventq_index=0 | 1018default_p_state=UNDEFINED 1019eventq_index=0 |
| 986hit_latency=2 | |
| 987p_state_clk_gate_bins=20 988p_state_clk_gate_max=1000000000000 989p_state_clk_gate_min=1000 990power_model=Null 991sequential_access=false 992size=32768 | 1020p_state_clk_gate_bins=20 1021p_state_clk_gate_max=1000000000000 1022p_state_clk_gate_min=1000 1023power_model=Null 1024sequential_access=false 1025size=32768 |
| 1026tag_latency=2 |
|
| 993 994[system.cpu1.dstage2_mmu] 995type=ArmStage2MMU 996children=stage2_tlb 997eventq_index=0 998stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb 999sys=system 1000tlb=system.cpu1.dtb --- 86 unchanged lines hidden (view full) --- 1087type=OpDesc 1088eventq_index=0 1089opClass=IprAccess 1090opLat=3 1091pipelined=true 1092 1093[system.cpu1.fuPool.FUList2] 1094type=FUDesc | 1027 1028[system.cpu1.dstage2_mmu] 1029type=ArmStage2MMU 1030children=stage2_tlb 1031eventq_index=0 1032stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb 1033sys=system 1034tlb=system.cpu1.dtb --- 86 unchanged lines hidden (view full) --- 1121type=OpDesc 1122eventq_index=0 1123opClass=IprAccess 1124opLat=3 1125pipelined=true 1126 1127[system.cpu1.fuPool.FUList2] 1128type=FUDesc |
| 1095children=opList | 1129children=opList0 opList1 |
| 1096count=1 1097eventq_index=0 | 1130count=1 1131eventq_index=0 |
| 1098opList=system.cpu1.fuPool.FUList2.opList | 1132opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 |
| 1099 | 1133 |
| 1100[system.cpu1.fuPool.FUList2.opList] | 1134[system.cpu1.fuPool.FUList2.opList0] |
| 1101type=OpDesc 1102eventq_index=0 1103opClass=MemRead 1104opLat=2 1105pipelined=true 1106 | 1135type=OpDesc 1136eventq_index=0 1137opClass=MemRead 1138opLat=2 1139pipelined=true 1140 |
| 1141[system.cpu1.fuPool.FUList2.opList1] 1142type=OpDesc 1143eventq_index=0 1144opClass=FloatMemRead 1145opLat=2 1146pipelined=true 1147 |
|
| 1107[system.cpu1.fuPool.FUList3] 1108type=FUDesc | 1148[system.cpu1.fuPool.FUList3] 1149type=FUDesc |
| 1109children=opList | 1150children=opList0 opList1 |
| 1110count=1 1111eventq_index=0 | 1151count=1 1152eventq_index=0 |
| 1112opList=system.cpu1.fuPool.FUList3.opList | 1153opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 |
| 1113 | 1154 |
| 1114[system.cpu1.fuPool.FUList3.opList] | 1155[system.cpu1.fuPool.FUList3.opList0] |
| 1115type=OpDesc 1116eventq_index=0 1117opClass=MemWrite 1118opLat=2 1119pipelined=true 1120 | 1156type=OpDesc 1157eventq_index=0 1158opClass=MemWrite 1159opLat=2 1160pipelined=true 1161 |
| 1162[system.cpu1.fuPool.FUList3.opList1] 1163type=OpDesc 1164eventq_index=0 1165opClass=FloatMemWrite 1166opLat=2 1167pipelined=true 1168 |
|
| 1121[system.cpu1.fuPool.FUList4] 1122type=FUDesc | 1169[system.cpu1.fuPool.FUList4] 1170type=FUDesc |
| 1123children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 | 1171children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 |
| 1124count=2 1125eventq_index=0 | 1172count=2 1173eventq_index=0 |
| 1126opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 | 1174opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 system.cpu1.fuPool.FUList4.opList26 system.cpu1.fuPool.FUList4.opList27 |
| 1127 1128[system.cpu1.fuPool.FUList4.opList00] 1129type=OpDesc 1130eventq_index=0 1131opClass=SimdAdd 1132opLat=4 1133pipelined=true 1134 --- 115 unchanged lines hidden (view full) --- 1250opClass=SimdFloatMult 1251opLat=3 1252pipelined=true 1253 1254[system.cpu1.fuPool.FUList4.opList18] 1255type=OpDesc 1256eventq_index=0 1257opClass=SimdFloatMultAcc | 1175 1176[system.cpu1.fuPool.FUList4.opList00] 1177type=OpDesc 1178eventq_index=0 1179opClass=SimdAdd 1180opLat=4 1181pipelined=true 1182 --- 115 unchanged lines hidden (view full) --- 1298opClass=SimdFloatMult 1299opLat=3 1300pipelined=true 1301 1302[system.cpu1.fuPool.FUList4.opList18] 1303type=OpDesc 1304eventq_index=0 1305opClass=SimdFloatMultAcc |
| 1258opLat=1 | 1306opLat=5 |
| 1259pipelined=true 1260 1261[system.cpu1.fuPool.FUList4.opList19] 1262type=OpDesc 1263eventq_index=0 1264opClass=SimdFloatSqrt 1265opLat=9 1266pipelined=true --- 35 unchanged lines hidden (view full) --- 1302 1303[system.cpu1.fuPool.FUList4.opList25] 1304type=OpDesc 1305eventq_index=0 1306opClass=FloatMult 1307opLat=4 1308pipelined=true 1309 | 1307pipelined=true 1308 1309[system.cpu1.fuPool.FUList4.opList19] 1310type=OpDesc 1311eventq_index=0 1312opClass=SimdFloatSqrt 1313opLat=9 1314pipelined=true --- 35 unchanged lines hidden (view full) --- 1350 1351[system.cpu1.fuPool.FUList4.opList25] 1352type=OpDesc 1353eventq_index=0 1354opClass=FloatMult 1355opLat=4 1356pipelined=true 1357 |
| 1358[system.cpu1.fuPool.FUList4.opList26] 1359type=OpDesc 1360eventq_index=0 1361opClass=FloatMultAcc 1362opLat=5 1363pipelined=true 1364 1365[system.cpu1.fuPool.FUList4.opList27] 1366type=OpDesc 1367eventq_index=0 1368opClass=FloatMisc 1369opLat=3 1370pipelined=true 1371 |
|
| 1310[system.cpu1.icache] 1311type=Cache 1312children=tags 1313addr_ranges=0:18446744073709551615:0:0:0:0 1314assoc=2 1315clk_domain=system.cpu_clk_domain 1316clusivity=mostly_incl | 1372[system.cpu1.icache] 1373type=Cache 1374children=tags 1375addr_ranges=0:18446744073709551615:0:0:0:0 1376assoc=2 1377clk_domain=system.cpu_clk_domain 1378clusivity=mostly_incl |
| 1379data_latency=1 |
|
| 1317default_p_state=UNDEFINED 1318demand_mshr_reserve=1 1319eventq_index=0 | 1380default_p_state=UNDEFINED 1381demand_mshr_reserve=1 1382eventq_index=0 |
| 1320hit_latency=1 | |
| 1321is_read_only=true 1322max_miss_count=0 1323mshrs=2 1324p_state_clk_gate_bins=20 1325p_state_clk_gate_max=1000000000000 1326p_state_clk_gate_min=1000 1327power_model=Null 1328prefetch_on_access=false 1329prefetcher=Null 1330response_latency=1 1331sequential_access=false 1332size=32768 1333system=system | 1383is_read_only=true 1384max_miss_count=0 1385mshrs=2 1386p_state_clk_gate_bins=20 1387p_state_clk_gate_max=1000000000000 1388p_state_clk_gate_min=1000 1389power_model=Null 1390prefetch_on_access=false 1391prefetcher=Null 1392response_latency=1 1393sequential_access=false 1394size=32768 1395system=system |
| 1396tag_latency=1 |
|
| 1334tags=system.cpu1.icache.tags 1335tgts_per_mshr=8 1336write_buffers=8 1337writeback_clean=true 1338cpu_side=system.cpu1.icache_port 1339mem_side=system.cpu1.toL2Bus.slave[0] 1340 1341[system.cpu1.icache.tags] 1342type=LRU 1343assoc=2 1344block_size=64 1345clk_domain=system.cpu_clk_domain | 1397tags=system.cpu1.icache.tags 1398tgts_per_mshr=8 1399write_buffers=8 1400writeback_clean=true 1401cpu_side=system.cpu1.icache_port 1402mem_side=system.cpu1.toL2Bus.slave[0] 1403 1404[system.cpu1.icache.tags] 1405type=LRU 1406assoc=2 1407block_size=64 1408clk_domain=system.cpu_clk_domain |
| 1409data_latency=1 |
|
| 1346default_p_state=UNDEFINED 1347eventq_index=0 | 1410default_p_state=UNDEFINED 1411eventq_index=0 |
| 1348hit_latency=1 | |
| 1349p_state_clk_gate_bins=20 1350p_state_clk_gate_max=1000000000000 1351p_state_clk_gate_min=1000 1352power_model=Null 1353sequential_access=false 1354size=32768 | 1412p_state_clk_gate_bins=20 1413p_state_clk_gate_max=1000000000000 1414p_state_clk_gate_min=1000 1415power_model=Null 1416sequential_access=false 1417size=32768 |
| 1418tag_latency=1 |
|
| 1355 1356[system.cpu1.interrupts] 1357type=ArmInterrupts 1358eventq_index=0 1359 1360[system.cpu1.isa] 1361type=ArmISA 1362decoderFlavour=Generic 1363eventq_index=0 1364fpsid=1090793632 1365id_aa64afr0_el1=0 1366id_aa64afr1_el1=0 1367id_aa64dfr0_el1=1052678 1368id_aa64dfr1_el1=0 1369id_aa64isar0_el1=0 1370id_aa64isar1_el1=0 1371id_aa64mmfr0_el1=15728642 1372id_aa64mmfr1_el1=0 | 1419 1420[system.cpu1.interrupts] 1421type=ArmInterrupts 1422eventq_index=0 1423 1424[system.cpu1.isa] 1425type=ArmISA 1426decoderFlavour=Generic 1427eventq_index=0 1428fpsid=1090793632 1429id_aa64afr0_el1=0 1430id_aa64afr1_el1=0 1431id_aa64dfr0_el1=1052678 1432id_aa64dfr1_el1=0 1433id_aa64isar0_el1=0 1434id_aa64isar1_el1=0 1435id_aa64mmfr0_el1=15728642 1436id_aa64mmfr1_el1=0 |
| 1373id_aa64pfr0_el1=34 1374id_aa64pfr1_el1=0 | |
| 1375id_isar0=34607377 1376id_isar1=34677009 1377id_isar2=555950401 1378id_isar3=17899825 1379id_isar4=268501314 1380id_isar5=0 1381id_mmfr0=270536963 1382id_mmfr1=0 1383id_mmfr2=19070976 1384id_mmfr3=34611729 | 1437id_isar0=34607377 1438id_isar1=34677009 1439id_isar2=555950401 1440id_isar3=17899825 1441id_isar4=268501314 1442id_isar5=0 1443id_mmfr0=270536963 1444id_mmfr1=0 1445id_mmfr2=19070976 1446id_mmfr3=34611729 |
| 1385id_pfr0=49 1386id_pfr1=4113 | |
| 1387midr=1091551472 1388pmu=Null 1389system=system 1390 1391[system.cpu1.istage2_mmu] 1392type=ArmStage2MMU 1393children=stage2_tlb 1394eventq_index=0 --- 46 unchanged lines hidden (view full) --- 1441 1442[system.cpu1.l2cache] 1443type=Cache 1444children=prefetcher tags 1445addr_ranges=0:18446744073709551615:0:0:0:0 1446assoc=16 1447clk_domain=system.cpu_clk_domain 1448clusivity=mostly_excl | 1447midr=1091551472 1448pmu=Null 1449system=system 1450 1451[system.cpu1.istage2_mmu] 1452type=ArmStage2MMU 1453children=stage2_tlb 1454eventq_index=0 --- 46 unchanged lines hidden (view full) --- 1501 1502[system.cpu1.l2cache] 1503type=Cache 1504children=prefetcher tags 1505addr_ranges=0:18446744073709551615:0:0:0:0 1506assoc=16 1507clk_domain=system.cpu_clk_domain 1508clusivity=mostly_excl |
| 1509data_latency=12 |
|
| 1449default_p_state=UNDEFINED 1450demand_mshr_reserve=1 1451eventq_index=0 | 1510default_p_state=UNDEFINED 1511demand_mshr_reserve=1 1512eventq_index=0 |
| 1452hit_latency=12 | |
| 1453is_read_only=false 1454max_miss_count=0 1455mshrs=16 1456p_state_clk_gate_bins=20 1457p_state_clk_gate_max=1000000000000 1458p_state_clk_gate_min=1000 1459power_model=Null 1460prefetch_on_access=true 1461prefetcher=system.cpu1.l2cache.prefetcher 1462response_latency=12 1463sequential_access=false 1464size=1048576 1465system=system | 1513is_read_only=false 1514max_miss_count=0 1515mshrs=16 1516p_state_clk_gate_bins=20 1517p_state_clk_gate_max=1000000000000 1518p_state_clk_gate_min=1000 1519power_model=Null 1520prefetch_on_access=true 1521prefetcher=system.cpu1.l2cache.prefetcher 1522response_latency=12 1523sequential_access=false 1524size=1048576 1525system=system |
| 1526tag_latency=12 |
|
| 1466tags=system.cpu1.l2cache.tags 1467tgts_per_mshr=8 1468write_buffers=8 1469writeback_clean=false 1470cpu_side=system.cpu1.toL2Bus.master[0] 1471mem_side=system.toL2Bus.slave[1] 1472 1473[system.cpu1.l2cache.prefetcher] --- 26 unchanged lines hidden (view full) --- 1500thresh_conf=4 1501use_master_id=true 1502 1503[system.cpu1.l2cache.tags] 1504type=RandomRepl 1505assoc=16 1506block_size=64 1507clk_domain=system.cpu_clk_domain | 1527tags=system.cpu1.l2cache.tags 1528tgts_per_mshr=8 1529write_buffers=8 1530writeback_clean=false 1531cpu_side=system.cpu1.toL2Bus.master[0] 1532mem_side=system.toL2Bus.slave[1] 1533 1534[system.cpu1.l2cache.prefetcher] --- 26 unchanged lines hidden (view full) --- 1561thresh_conf=4 1562use_master_id=true 1563 1564[system.cpu1.l2cache.tags] 1565type=RandomRepl 1566assoc=16 1567block_size=64 1568clk_domain=system.cpu_clk_domain |
| 1569data_latency=12 |
|
| 1508default_p_state=UNDEFINED 1509eventq_index=0 | 1570default_p_state=UNDEFINED 1571eventq_index=0 |
| 1510hit_latency=12 | |
| 1511p_state_clk_gate_bins=20 1512p_state_clk_gate_max=1000000000000 1513p_state_clk_gate_min=1000 1514power_model=Null 1515sequential_access=false 1516size=1048576 | 1572p_state_clk_gate_bins=20 1573p_state_clk_gate_max=1000000000000 1574p_state_clk_gate_min=1000 1575power_model=Null 1576sequential_access=false 1577size=1048576 |
| 1578tag_latency=12 |
|
| 1517 1518[system.cpu1.toL2Bus] 1519type=CoherentXBar 1520children=snoop_filter 1521clk_domain=system.cpu_clk_domain 1522default_p_state=UNDEFINED 1523eventq_index=0 1524forward_latency=0 --- 63 unchanged lines hidden (view full) --- 1588 1589[system.iocache] 1590type=Cache 1591children=tags 1592addr_ranges=2147483648:2415919103:0:0:0:0 1593assoc=8 1594clk_domain=system.clk_domain 1595clusivity=mostly_incl | 1579 1580[system.cpu1.toL2Bus] 1581type=CoherentXBar 1582children=snoop_filter 1583clk_domain=system.cpu_clk_domain 1584default_p_state=UNDEFINED 1585eventq_index=0 1586forward_latency=0 --- 63 unchanged lines hidden (view full) --- 1650 1651[system.iocache] 1652type=Cache 1653children=tags 1654addr_ranges=2147483648:2415919103:0:0:0:0 1655assoc=8 1656clk_domain=system.clk_domain 1657clusivity=mostly_incl |
| 1658data_latency=50 |
|
| 1596default_p_state=UNDEFINED 1597demand_mshr_reserve=1 1598eventq_index=0 | 1659default_p_state=UNDEFINED 1660demand_mshr_reserve=1 1661eventq_index=0 |
| 1599hit_latency=50 | |
| 1600is_read_only=false 1601max_miss_count=0 1602mshrs=20 1603p_state_clk_gate_bins=20 1604p_state_clk_gate_max=1000000000000 1605p_state_clk_gate_min=1000 1606power_model=Null 1607prefetch_on_access=false 1608prefetcher=Null 1609response_latency=50 1610sequential_access=false 1611size=1024 1612system=system | 1662is_read_only=false 1663max_miss_count=0 1664mshrs=20 1665p_state_clk_gate_bins=20 1666p_state_clk_gate_max=1000000000000 1667p_state_clk_gate_min=1000 1668power_model=Null 1669prefetch_on_access=false 1670prefetcher=Null 1671response_latency=50 1672sequential_access=false 1673size=1024 1674system=system |
| 1675tag_latency=50 |
|
| 1613tags=system.iocache.tags 1614tgts_per_mshr=12 1615write_buffers=8 1616writeback_clean=false 1617cpu_side=system.iobus.master[25] 1618mem_side=system.membus.slave[3] 1619 1620[system.iocache.tags] 1621type=LRU 1622assoc=8 1623block_size=64 1624clk_domain=system.clk_domain | 1676tags=system.iocache.tags 1677tgts_per_mshr=12 1678write_buffers=8 1679writeback_clean=false 1680cpu_side=system.iobus.master[25] 1681mem_side=system.membus.slave[3] 1682 1683[system.iocache.tags] 1684type=LRU 1685assoc=8 1686block_size=64 1687clk_domain=system.clk_domain |
| 1688data_latency=50 |
|
| 1625default_p_state=UNDEFINED 1626eventq_index=0 | 1689default_p_state=UNDEFINED 1690eventq_index=0 |
| 1627hit_latency=50 | |
| 1628p_state_clk_gate_bins=20 1629p_state_clk_gate_max=1000000000000 1630p_state_clk_gate_min=1000 1631power_model=Null 1632sequential_access=false 1633size=1024 | 1691p_state_clk_gate_bins=20 1692p_state_clk_gate_max=1000000000000 1693p_state_clk_gate_min=1000 1694power_model=Null 1695sequential_access=false 1696size=1024 |
| 1697tag_latency=50 |
|
| 1634 1635[system.l2c] 1636type=Cache 1637children=tags 1638addr_ranges=0:18446744073709551615:0:0:0:0 1639assoc=8 1640clk_domain=system.cpu_clk_domain 1641clusivity=mostly_incl | 1698 1699[system.l2c] 1700type=Cache 1701children=tags 1702addr_ranges=0:18446744073709551615:0:0:0:0 1703assoc=8 1704clk_domain=system.cpu_clk_domain 1705clusivity=mostly_incl |
| 1706data_latency=20 |
|
| 1642default_p_state=UNDEFINED 1643demand_mshr_reserve=1 1644eventq_index=0 | 1707default_p_state=UNDEFINED 1708demand_mshr_reserve=1 1709eventq_index=0 |
| 1645hit_latency=20 | |
| 1646is_read_only=false 1647max_miss_count=0 1648mshrs=20 1649p_state_clk_gate_bins=20 1650p_state_clk_gate_max=1000000000000 1651p_state_clk_gate_min=1000 1652power_model=Null 1653prefetch_on_access=false 1654prefetcher=Null 1655response_latency=20 1656sequential_access=false 1657size=4194304 1658system=system | 1710is_read_only=false 1711max_miss_count=0 1712mshrs=20 1713p_state_clk_gate_bins=20 1714p_state_clk_gate_max=1000000000000 1715p_state_clk_gate_min=1000 1716power_model=Null 1717prefetch_on_access=false 1718prefetcher=Null 1719response_latency=20 1720sequential_access=false 1721size=4194304 1722system=system |
| 1723tag_latency=20 |
|
| 1659tags=system.l2c.tags 1660tgts_per_mshr=12 1661write_buffers=8 1662writeback_clean=false 1663cpu_side=system.toL2Bus.master[0] 1664mem_side=system.membus.slave[2] 1665 1666[system.l2c.tags] 1667type=LRU 1668assoc=8 1669block_size=64 1670clk_domain=system.cpu_clk_domain | 1724tags=system.l2c.tags 1725tgts_per_mshr=12 1726write_buffers=8 1727writeback_clean=false 1728cpu_side=system.toL2Bus.master[0] 1729mem_side=system.membus.slave[2] 1730 1731[system.l2c.tags] 1732type=LRU 1733assoc=8 1734block_size=64 1735clk_domain=system.cpu_clk_domain |
| 1736data_latency=20 |
|
| 1671default_p_state=UNDEFINED 1672eventq_index=0 | 1737default_p_state=UNDEFINED 1738eventq_index=0 |
| 1673hit_latency=20 | |
| 1674p_state_clk_gate_bins=20 1675p_state_clk_gate_max=1000000000000 1676p_state_clk_gate_min=1000 1677power_model=Null 1678sequential_access=false 1679size=4194304 | 1739p_state_clk_gate_bins=20 1740p_state_clk_gate_max=1000000000000 1741p_state_clk_gate_min=1000 1742power_model=Null 1743sequential_access=false 1744size=4194304 |
| 1745tag_latency=20 |
|
| 1680 1681[system.membus] 1682type=CoherentXBar 1683children=badaddr_responder snoop_filter 1684clk_domain=system.clk_domain 1685default_p_state=UNDEFINED 1686eventq_index=0 1687forward_latency=4 --- 1107 unchanged lines hidden --- | 1746 1747[system.membus] 1748type=CoherentXBar 1749children=badaddr_responder snoop_filter 1750clk_domain=system.clk_domain 1751default_p_state=UNDEFINED 1752eventq_index=0 1753forward_latency=4 --- 1107 unchanged lines hidden --- |