15c15
< boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
---
> boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
20c20
< dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
---
> dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
33c33
< kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
---
> kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
52c52
< readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
---
> readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
102c102
< image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
---
> image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
125c125
< cachePorts=200
---
> cacheStorePorts=200
200a201
> syscallRetryLatency=10000
235a237
> data_latency=2
239d240
< hit_latency=2
252a254
> tag_latency=2
264a267
> data_latency=2
267d269
< hit_latency=2
273a276
> tag_latency=2
376c379
< children=opList
---
> children=opList0 opList1
379c382
< opList=system.cpu0.fuPool.FUList2.opList
---
> opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1
381c384
< [system.cpu0.fuPool.FUList2.opList]
---
> [system.cpu0.fuPool.FUList2.opList0]
387a391,397
> [system.cpu0.fuPool.FUList2.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=2
> pipelined=true
>
390c400
< children=opList
---
> children=opList0 opList1
393c403
< opList=system.cpu0.fuPool.FUList3.opList
---
> opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1
395c405
< [system.cpu0.fuPool.FUList3.opList]
---
> [system.cpu0.fuPool.FUList3.opList0]
401a412,418
> [system.cpu0.fuPool.FUList3.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=2
> pipelined=true
>
404c421
< children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
---
> children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
407c424
< opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25
---
> opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 system.cpu0.fuPool.FUList4.opList26 system.cpu0.fuPool.FUList4.opList27
539c556
< opLat=1
---
> opLat=5
590a608,621
> [system.cpu0.fuPool.FUList4.opList26]
> type=OpDesc
> eventq_index=0
> opClass=FloatMultAcc
> opLat=5
> pipelined=true
>
> [system.cpu0.fuPool.FUList4.opList27]
> type=OpDesc
> eventq_index=0
> opClass=FloatMisc
> opLat=3
> pipelined=true
>
597a629
> data_latency=1
601d632
< hit_latency=1
614a646
> tag_latency=1
626a659
> data_latency=1
629d661
< hit_latency=1
635a668
> tag_latency=1
654,655d686
< id_aa64pfr0_el1=34
< id_aa64pfr1_el1=0
666,667d696
< id_pfr0=49
< id_pfr1=4113
729a759
> data_latency=12
733d762
< hit_latency=12
746a776
> tag_latency=12
788a819
> data_latency=12
791d821
< hit_latency=12
797a828
> tag_latency=12
844c875
< cachePorts=200
---
> cacheStorePorts=200
919a951
> syscallRetryLatency=10000
954a987
> data_latency=2
958d990
< hit_latency=2
971a1004
> tag_latency=2
983a1017
> data_latency=2
986d1019
< hit_latency=2
992a1026
> tag_latency=2
1095c1129
< children=opList
---
> children=opList0 opList1
1098c1132
< opList=system.cpu1.fuPool.FUList2.opList
---
> opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1
1100c1134
< [system.cpu1.fuPool.FUList2.opList]
---
> [system.cpu1.fuPool.FUList2.opList0]
1106a1141,1147
> [system.cpu1.fuPool.FUList2.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemRead
> opLat=2
> pipelined=true
>
1109c1150
< children=opList
---
> children=opList0 opList1
1112c1153
< opList=system.cpu1.fuPool.FUList3.opList
---
> opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1
1114c1155
< [system.cpu1.fuPool.FUList3.opList]
---
> [system.cpu1.fuPool.FUList3.opList0]
1120a1162,1168
> [system.cpu1.fuPool.FUList3.opList1]
> type=OpDesc
> eventq_index=0
> opClass=FloatMemWrite
> opLat=2
> pipelined=true
>
1123c1171
< children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
---
> children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
1126c1174
< opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25
---
> opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 system.cpu1.fuPool.FUList4.opList26 system.cpu1.fuPool.FUList4.opList27
1258c1306
< opLat=1
---
> opLat=5
1309a1358,1371
> [system.cpu1.fuPool.FUList4.opList26]
> type=OpDesc
> eventq_index=0
> opClass=FloatMultAcc
> opLat=5
> pipelined=true
>
> [system.cpu1.fuPool.FUList4.opList27]
> type=OpDesc
> eventq_index=0
> opClass=FloatMisc
> opLat=3
> pipelined=true
>
1316a1379
> data_latency=1
1320d1382
< hit_latency=1
1333a1396
> tag_latency=1
1345a1409
> data_latency=1
1348d1411
< hit_latency=1
1354a1418
> tag_latency=1
1373,1374d1436
< id_aa64pfr0_el1=34
< id_aa64pfr1_el1=0
1385,1386d1446
< id_pfr0=49
< id_pfr1=4113
1448a1509
> data_latency=12
1452d1512
< hit_latency=12
1465a1526
> tag_latency=12
1507a1569
> data_latency=12
1510d1571
< hit_latency=12
1516a1578
> tag_latency=12
1595a1658
> data_latency=50
1599d1661
< hit_latency=50
1612a1675
> tag_latency=50
1624a1688
> data_latency=50
1627d1690
< hit_latency=50
1633a1697
> tag_latency=50
1641a1706
> data_latency=20
1645d1709
< hit_latency=20
1658a1723
> tag_latency=20
1670a1736
> data_latency=20
1673d1738
< hit_latency=20
1679a1745
> tag_latency=20