15c15
< boot_loader=/dist/binaries/boot_emm.arm
---
> boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
20c20
< dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
---
> dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
33c33
< kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
---
> kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
40c40,41
< memories=system.physmem system.realview.vram system.realview.nvmem
---
> memories=system.physmem system.realview.nvmem system.realview.vram
> mmap_using_noreserve=false
46c47
< readfile=/work/gem5.ext/tests/halt.sh
---
> readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
89c90
< image_file=/dist/disks/linux-aarch32-ael.img
---
> image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
192c193
< type=BranchPredictor
---
> type=BiModeBP
202,204d202
< localCtrBits=2
< localHistoryTableSize=2048
< localPredictorSize=2048
206d203
< predType=bi-mode
213a211
> demand_mshr_reserve=1
247a246
> sys=system
265d263
< port=system.cpu0.toL2Bus.slave[5]
554a553
> demand_mshr_reserve=1
556c555
< forward_snoops=true
---
> forward_snoops=false
622a622
> sys=system
640d639
< port=system.cpu0.toL2Bus.slave[4]
664a664
> demand_mshr_reserve=1
685a686
> cache_snoop=false
687,688d687
< cross_pages=false
< data_accesses_only=false
691d689
< inst_tagged=true
693,697c691,701
< on_miss_only=false
< on_prefetch=true
< on_read_only=false
< serial_squash=false
< size=100
---
> max_conf=7
> min_conf=0
> on_data=true
> on_inst=true
> on_miss=false
> on_read=true
> on_write=true
> queue_filter=true
> queue_size=32
> queue_squash=true
> start_conf=4
698a703,706
> table_assoc=4
> table_sets=16
> tag_prefetch=true
> thresh_conf=4
715c723,725
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
716a727
> snoop_response_latency=1
721c732
< slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
819c830
< type=BranchPredictor
---
> type=BiModeBP
829,831d839
< localCtrBits=2
< localHistoryTableSize=2048
< localPredictorSize=2048
833d840
< predType=bi-mode
840a848
> demand_mshr_reserve=1
874a883
> sys=system
892d900
< port=system.cpu1.toL2Bus.slave[5]
1181a1190
> demand_mshr_reserve=1
1183c1192
< forward_snoops=true
---
> forward_snoops=false
1249a1259
> sys=system
1267d1276
< port=system.cpu1.toL2Bus.slave[4]
1291a1301
> demand_mshr_reserve=1
1312a1323
> cache_snoop=false
1314,1315d1324
< cross_pages=false
< data_accesses_only=false
1318d1326
< inst_tagged=true
1320,1324c1328,1338
< on_miss_only=false
< on_prefetch=true
< on_read_only=false
< serial_squash=false
< size=100
---
> max_conf=7
> min_conf=0
> on_data=true
> on_inst=true
> on_miss=false
> on_read=true
> on_write=true
> queue_filter=true
> queue_size=32
> queue_squash=true
> start_conf=4
1325a1340,1343
> table_assoc=4
> table_sets=16
> tag_prefetch=true
> thresh_conf=4
1342c1360,1362
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
1343a1364
> snoop_response_latency=1
1348c1369
< slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
1379c1400,1402
< header_cycles=1
---
> forward_latency=1
> frontend_latency=2
> response_latency=2
1381c1404
< width=8
---
> width=16
1391a1415
> demand_mshr_reserve=1
1426a1451
> demand_mshr_reserve=1
1461c1486,1488
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
1462a1490
> snoop_response_latency=4
1465c1493
< width=8
---
> width=16
1467c1495
< master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
---
> master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
1515c1543
< addr_mapping=RoRaBaChCo
---
> addr_mapping=RoRaBaCoCh
1819d1846
< msix_addr=0
2006c2033
< pio=system.membus.master[3]
---
> pio=system.membus.master[4]
2188c2215
< pio=system.membus.master[4]
---
> pio=system.membus.master[3]
2226c2253,2255
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
2227a2257
> snoop_response_latency=1
2230c2260
< width=8
---
> width=32
< boot_loader=/dist/binaries/boot_emm.arm
---
> boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
20c20
< dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
---
> dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
33c33
< kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
---
> kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
40c40,41
< memories=system.physmem system.realview.vram system.realview.nvmem
---
> memories=system.physmem system.realview.nvmem system.realview.vram
> mmap_using_noreserve=false
46c47
< readfile=/work/gem5.ext/tests/halt.sh
---
> readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
89c90
< image_file=/dist/disks/linux-aarch32-ael.img
---
> image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
192c193
< type=BranchPredictor
---
> type=BiModeBP
202,204d202
< localCtrBits=2
< localHistoryTableSize=2048
< localPredictorSize=2048
206d203
< predType=bi-mode
213a211
> demand_mshr_reserve=1
247a246
> sys=system
265d263
< port=system.cpu0.toL2Bus.slave[5]
554a553
> demand_mshr_reserve=1
556c555
< forward_snoops=true
---
> forward_snoops=false
622a622
> sys=system
640d639
< port=system.cpu0.toL2Bus.slave[4]
664a664
> demand_mshr_reserve=1
685a686
> cache_snoop=false
687,688d687
< cross_pages=false
< data_accesses_only=false
691d689
< inst_tagged=true
693,697c691,701
< on_miss_only=false
< on_prefetch=true
< on_read_only=false
< serial_squash=false
< size=100
---
> max_conf=7
> min_conf=0
> on_data=true
> on_inst=true
> on_miss=false
> on_read=true
> on_write=true
> queue_filter=true
> queue_size=32
> queue_squash=true
> start_conf=4
698a703,706
> table_assoc=4
> table_sets=16
> tag_prefetch=true
> thresh_conf=4
715c723,725
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
716a727
> snoop_response_latency=1
721c732
< slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
819c830
< type=BranchPredictor
---
> type=BiModeBP
829,831d839
< localCtrBits=2
< localHistoryTableSize=2048
< localPredictorSize=2048
833d840
< predType=bi-mode
840a848
> demand_mshr_reserve=1
874a883
> sys=system
892d900
< port=system.cpu1.toL2Bus.slave[5]
1181a1190
> demand_mshr_reserve=1
1183c1192
< forward_snoops=true
---
> forward_snoops=false
1249a1259
> sys=system
1267d1276
< port=system.cpu1.toL2Bus.slave[4]
1291a1301
> demand_mshr_reserve=1
1312a1323
> cache_snoop=false
1314,1315d1324
< cross_pages=false
< data_accesses_only=false
1318d1326
< inst_tagged=true
1320,1324c1328,1338
< on_miss_only=false
< on_prefetch=true
< on_read_only=false
< serial_squash=false
< size=100
---
> max_conf=7
> min_conf=0
> on_data=true
> on_inst=true
> on_miss=false
> on_read=true
> on_write=true
> queue_filter=true
> queue_size=32
> queue_squash=true
> start_conf=4
1325a1340,1343
> table_assoc=4
> table_sets=16
> tag_prefetch=true
> thresh_conf=4
1342c1360,1362
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
1343a1364
> snoop_response_latency=1
1348c1369
< slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
1379c1400,1402
< header_cycles=1
---
> forward_latency=1
> frontend_latency=2
> response_latency=2
1381c1404
< width=8
---
> width=16
1391a1415
> demand_mshr_reserve=1
1426a1451
> demand_mshr_reserve=1
1461c1486,1488
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
1462a1490
> snoop_response_latency=4
1465c1493
< width=8
---
> width=16
1467c1495
< master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
---
> master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
1515c1543
< addr_mapping=RoRaBaChCo
---
> addr_mapping=RoRaBaCoCh
1819d1846
< msix_addr=0
2006c2033
< pio=system.membus.master[3]
---
> pio=system.membus.master[4]
2188c2215
< pio=system.membus.master[4]
---
> pio=system.membus.master[3]
2226c2253,2255
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
2227a2257
> snoop_response_latency=1
2230c2260
< width=8
---
> width=32