Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini

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config.ini (9885:afd9ea6101d9)	config.ini (9924:31ef410b6843)
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 12atags_addr=256 13boot_loader=/dist/m5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15cache_line_size=64 16clk_domain=system.clk_domain 17dtb_filename=False 18early_kernel_symbols=false 19enable_context_switch_stats_dump=false 20flags_addr=268435504 21gic_cpu_addr=520093952 22init_param=0 23kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 24load_addr_mask=268435455 25machine_type=RealView_PBX 26mem_mode=timing 27mem_ranges=0:134217727	1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 12atags_addr=256 13boot_loader=/dist/m5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15cache_line_size=64 16clk_domain=system.clk_domain 17dtb_filename=False 18early_kernel_symbols=false 19enable_context_switch_stats_dump=false 20flags_addr=268435504 21gic_cpu_addr=520093952 22init_param=0 23kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 24load_addr_mask=268435455 25machine_type=RealView_PBX 26mem_mode=timing 27mem_ranges=0:134217727
28memories=system.realview.nvmem system.physmem	28memories=system.physmem system.realview.nvmem
29multi_proc=true 30num_work_ids=16 31panic_on_oops=true 32panic_on_panic=true 33readfile=tests/halt.sh 34symbolfile= 35work_begin_ckpt_count=0 36work_begin_cpu_id_exit=-1 37work_begin_exit_count=0 38work_cpus_ckpt_count=0 39work_end_ckpt_count=0 40work_end_exit_count=0 41work_item_id=-1 42system_port=system.membus.slave[0] 43 44[system.bridge] 45type=Bridge 46clk_domain=system.clk_domain 47delay=50000 48ranges=268435456:520093695 1073741824:1610612735 49req_size=16 50resp_size=16 51master=system.iobus.slave[0] 52slave=system.membus.master[0] 53 54[system.cf0] 55type=IdeDisk 56children=image 57delay=1000000 58driveID=master 59image=system.cf0.image 60 61[system.cf0.image] 62type=CowDiskImage 63children=child 64child=system.cf0.image.child 65image_file= 66read_only=false 67table_size=65536 68 69[system.cf0.image.child] 70type=RawDiskImage 71image_file=/dist/m5/system/disks/linux-arm-ael.img 72read_only=true 73 74[system.clk_domain] 75type=SrcClockDomain 76clock=1000 77voltage_domain=system.voltage_domain 78 79[system.cpu0] 80type=DerivO3CPU 81children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 82LFSTSize=1024 83LQEntries=32 84LSQCheckLoads=true 85LSQDepCheckShift=4 86SQEntries=32 87SSITSize=1024 88activity=0 89backComSize=5 90branchPred=system.cpu0.branchPred 91cachePorts=200 92checker=Null 93clk_domain=system.cpu_clk_domain 94commitToDecodeDelay=1 95commitToFetchDelay=1 96commitToIEWDelay=1 97commitToRenameDelay=1 98commitWidth=8 99cpu_id=0 100decodeToFetchDelay=1 101decodeToRenameDelay=1 102decodeWidth=8 103dispatchWidth=8 104do_checkpoint_insts=true 105do_quiesce=true 106do_statistics_insts=true 107dtb=system.cpu0.dtb 108fetchToDecodeDelay=1 109fetchTrapLatency=1 110fetchWidth=8 111forwardComSize=5 112fuPool=system.cpu0.fuPool 113function_trace=false 114function_trace_start=0 115iewToCommitDelay=1 116iewToDecodeDelay=1 117iewToFetchDelay=1 118iewToRenameDelay=1 119interrupts=system.cpu0.interrupts 120isa=system.cpu0.isa 121issueToExecuteDelay=1 122issueWidth=8 123itb=system.cpu0.itb 124max_insts_all_threads=0 125max_insts_any_thread=0 126max_loads_all_threads=0 127max_loads_any_thread=0 128needsTSO=false 129numIQEntries=64	29multi_proc=true 30num_work_ids=16 31panic_on_oops=true 32panic_on_panic=true 33readfile=tests/halt.sh 34symbolfile= 35work_begin_ckpt_count=0 36work_begin_cpu_id_exit=-1 37work_begin_exit_count=0 38work_cpus_ckpt_count=0 39work_end_ckpt_count=0 40work_end_exit_count=0 41work_item_id=-1 42system_port=system.membus.slave[0] 43 44[system.bridge] 45type=Bridge 46clk_domain=system.clk_domain 47delay=50000 48ranges=268435456:520093695 1073741824:1610612735 49req_size=16 50resp_size=16 51master=system.iobus.slave[0] 52slave=system.membus.master[0] 53 54[system.cf0] 55type=IdeDisk 56children=image 57delay=1000000 58driveID=master 59image=system.cf0.image 60 61[system.cf0.image] 62type=CowDiskImage 63children=child 64child=system.cf0.image.child 65image_file= 66read_only=false 67table_size=65536 68 69[system.cf0.image.child] 70type=RawDiskImage 71image_file=/dist/m5/system/disks/linux-arm-ael.img 72read_only=true 73 74[system.clk_domain] 75type=SrcClockDomain 76clock=1000 77voltage_domain=system.voltage_domain 78 79[system.cpu0] 80type=DerivO3CPU 81children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 82LFSTSize=1024 83LQEntries=32 84LSQCheckLoads=true 85LSQDepCheckShift=4 86SQEntries=32 87SSITSize=1024 88activity=0 89backComSize=5 90branchPred=system.cpu0.branchPred 91cachePorts=200 92checker=Null 93clk_domain=system.cpu_clk_domain 94commitToDecodeDelay=1 95commitToFetchDelay=1 96commitToIEWDelay=1 97commitToRenameDelay=1 98commitWidth=8 99cpu_id=0 100decodeToFetchDelay=1 101decodeToRenameDelay=1 102decodeWidth=8 103dispatchWidth=8 104do_checkpoint_insts=true 105do_quiesce=true 106do_statistics_insts=true 107dtb=system.cpu0.dtb 108fetchToDecodeDelay=1 109fetchTrapLatency=1 110fetchWidth=8 111forwardComSize=5 112fuPool=system.cpu0.fuPool 113function_trace=false 114function_trace_start=0 115iewToCommitDelay=1 116iewToDecodeDelay=1 117iewToFetchDelay=1 118iewToRenameDelay=1 119interrupts=system.cpu0.interrupts 120isa=system.cpu0.isa 121issueToExecuteDelay=1 122issueWidth=8 123itb=system.cpu0.itb 124max_insts_all_threads=0 125max_insts_any_thread=0 126max_loads_all_threads=0 127max_loads_any_thread=0 128needsTSO=false 129numIQEntries=64
	130numPhysCCRegs=0
130numPhysFloatRegs=256 131numPhysIntRegs=256 132numROBEntries=192 133numRobs=1 134numThreads=1 135profile=0 136progress_interval=0 137renameToDecodeDelay=1 138renameToFetchDelay=1 139renameToIEWDelay=2 140renameToROBDelay=1 141renameWidth=8 142simpoint_start_insts= 143smtCommitPolicy=RoundRobin 144smtFetchPolicy=SingleThread 145smtIQPolicy=Partitioned 146smtIQThreshold=100 147smtLSQPolicy=Partitioned 148smtLSQThreshold=100 149smtNumFetchingThreads=1 150smtROBPolicy=Partitioned 151smtROBThreshold=100 152squashWidth=8 153store_set_clear_period=250000 154switched_out=false 155system=system 156tracer=system.cpu0.tracer 157trapLatency=13 158wbDepth=1 159wbWidth=8 160workload= 161dcache_port=system.cpu0.dcache.cpu_side 162icache_port=system.cpu0.icache.cpu_side 163 164[system.cpu0.branchPred] 165type=BranchPredictor 166BTBEntries=4096 167BTBTagSize=16 168RASSize=16 169choiceCtrBits=2 170choicePredictorSize=8192 171globalCtrBits=2 172globalPredictorSize=8192 173instShiftAmt=2 174localCtrBits=2 175localHistoryTableSize=2048 176localPredictorSize=2048 177numThreads=1 178predType=tournament 179 180[system.cpu0.dcache] 181type=BaseCache 182children=tags 183addr_ranges=0:18446744073709551615 184assoc=4 185clk_domain=system.cpu_clk_domain 186forward_snoops=true 187hit_latency=2 188is_top_level=true 189max_miss_count=0 190mshrs=4 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194size=32768 195system=system 196tags=system.cpu0.dcache.tags 197tgts_per_mshr=20 198two_queue=false 199write_buffers=8 200cpu_side=system.cpu0.dcache_port 201mem_side=system.toL2Bus.slave[1] 202 203[system.cpu0.dcache.tags] 204type=LRU 205assoc=4 206block_size=64 207clk_domain=system.cpu_clk_domain 208hit_latency=2 209size=32768 210 211[system.cpu0.dtb] 212type=ArmTLB 213children=walker 214size=64 215walker=system.cpu0.dtb.walker 216 217[system.cpu0.dtb.walker] 218type=ArmTableWalker 219clk_domain=system.cpu_clk_domain 220num_squash_per_cycle=2 221sys=system 222port=system.toL2Bus.slave[3] 223 224[system.cpu0.fuPool] 225type=FUPool 226children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 227FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 228 229[system.cpu0.fuPool.FUList0] 230type=FUDesc 231children=opList 232count=6 233opList=system.cpu0.fuPool.FUList0.opList 234 235[system.cpu0.fuPool.FUList0.opList] 236type=OpDesc 237issueLat=1 238opClass=IntAlu 239opLat=1 240 241[system.cpu0.fuPool.FUList1] 242type=FUDesc 243children=opList0 opList1 244count=2 245opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 246 247[system.cpu0.fuPool.FUList1.opList0] 248type=OpDesc 249issueLat=1 250opClass=IntMult 251opLat=3 252 253[system.cpu0.fuPool.FUList1.opList1] 254type=OpDesc 255issueLat=19 256opClass=IntDiv 257opLat=20 258 259[system.cpu0.fuPool.FUList2] 260type=FUDesc 261children=opList0 opList1 opList2 262count=4 263opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 264 265[system.cpu0.fuPool.FUList2.opList0] 266type=OpDesc 267issueLat=1 268opClass=FloatAdd 269opLat=2 270 271[system.cpu0.fuPool.FUList2.opList1] 272type=OpDesc 273issueLat=1 274opClass=FloatCmp 275opLat=2 276 277[system.cpu0.fuPool.FUList2.opList2] 278type=OpDesc 279issueLat=1 280opClass=FloatCvt 281opLat=2 282 283[system.cpu0.fuPool.FUList3] 284type=FUDesc 285children=opList0 opList1 opList2 286count=2 287opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 288 289[system.cpu0.fuPool.FUList3.opList0] 290type=OpDesc 291issueLat=1 292opClass=FloatMult 293opLat=4 294 295[system.cpu0.fuPool.FUList3.opList1] 296type=OpDesc 297issueLat=12 298opClass=FloatDiv 299opLat=12 300 301[system.cpu0.fuPool.FUList3.opList2] 302type=OpDesc 303issueLat=24 304opClass=FloatSqrt 305opLat=24 306 307[system.cpu0.fuPool.FUList4] 308type=FUDesc 309children=opList 310count=0 311opList=system.cpu0.fuPool.FUList4.opList 312 313[system.cpu0.fuPool.FUList4.opList] 314type=OpDesc 315issueLat=1 316opClass=MemRead 317opLat=1 318 319[system.cpu0.fuPool.FUList5] 320type=FUDesc 321children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 322count=4 323opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 324 325[system.cpu0.fuPool.FUList5.opList00] 326type=OpDesc 327issueLat=1 328opClass=SimdAdd 329opLat=1 330 331[system.cpu0.fuPool.FUList5.opList01] 332type=OpDesc 333issueLat=1 334opClass=SimdAddAcc 335opLat=1 336 337[system.cpu0.fuPool.FUList5.opList02] 338type=OpDesc 339issueLat=1 340opClass=SimdAlu 341opLat=1 342 343[system.cpu0.fuPool.FUList5.opList03] 344type=OpDesc 345issueLat=1 346opClass=SimdCmp 347opLat=1 348 349[system.cpu0.fuPool.FUList5.opList04] 350type=OpDesc 351issueLat=1 352opClass=SimdCvt 353opLat=1 354 355[system.cpu0.fuPool.FUList5.opList05] 356type=OpDesc 357issueLat=1 358opClass=SimdMisc 359opLat=1 360 361[system.cpu0.fuPool.FUList5.opList06] 362type=OpDesc 363issueLat=1 364opClass=SimdMult 365opLat=1 366 367[system.cpu0.fuPool.FUList5.opList07] 368type=OpDesc 369issueLat=1 370opClass=SimdMultAcc 371opLat=1 372 373[system.cpu0.fuPool.FUList5.opList08] 374type=OpDesc 375issueLat=1 376opClass=SimdShift 377opLat=1 378 379[system.cpu0.fuPool.FUList5.opList09] 380type=OpDesc 381issueLat=1 382opClass=SimdShiftAcc 383opLat=1 384 385[system.cpu0.fuPool.FUList5.opList10] 386type=OpDesc 387issueLat=1 388opClass=SimdSqrt 389opLat=1 390 391[system.cpu0.fuPool.FUList5.opList11] 392type=OpDesc 393issueLat=1 394opClass=SimdFloatAdd 395opLat=1 396 397[system.cpu0.fuPool.FUList5.opList12] 398type=OpDesc 399issueLat=1 400opClass=SimdFloatAlu 401opLat=1 402 403[system.cpu0.fuPool.FUList5.opList13] 404type=OpDesc 405issueLat=1 406opClass=SimdFloatCmp 407opLat=1 408 409[system.cpu0.fuPool.FUList5.opList14] 410type=OpDesc 411issueLat=1 412opClass=SimdFloatCvt 413opLat=1 414 415[system.cpu0.fuPool.FUList5.opList15] 416type=OpDesc 417issueLat=1 418opClass=SimdFloatDiv 419opLat=1 420 421[system.cpu0.fuPool.FUList5.opList16] 422type=OpDesc 423issueLat=1 424opClass=SimdFloatMisc 425opLat=1 426 427[system.cpu0.fuPool.FUList5.opList17] 428type=OpDesc 429issueLat=1 430opClass=SimdFloatMult 431opLat=1 432 433[system.cpu0.fuPool.FUList5.opList18] 434type=OpDesc 435issueLat=1 436opClass=SimdFloatMultAcc 437opLat=1 438 439[system.cpu0.fuPool.FUList5.opList19] 440type=OpDesc 441issueLat=1 442opClass=SimdFloatSqrt 443opLat=1 444 445[system.cpu0.fuPool.FUList6] 446type=FUDesc 447children=opList 448count=0 449opList=system.cpu0.fuPool.FUList6.opList 450 451[system.cpu0.fuPool.FUList6.opList] 452type=OpDesc 453issueLat=1 454opClass=MemWrite 455opLat=1 456 457[system.cpu0.fuPool.FUList7] 458type=FUDesc 459children=opList0 opList1 460count=4 461opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 462 463[system.cpu0.fuPool.FUList7.opList0] 464type=OpDesc 465issueLat=1 466opClass=MemRead 467opLat=1 468 469[system.cpu0.fuPool.FUList7.opList1] 470type=OpDesc 471issueLat=1 472opClass=MemWrite 473opLat=1 474 475[system.cpu0.fuPool.FUList8] 476type=FUDesc 477children=opList 478count=1 479opList=system.cpu0.fuPool.FUList8.opList 480 481[system.cpu0.fuPool.FUList8.opList] 482type=OpDesc 483issueLat=3 484opClass=IprAccess 485opLat=3 486 487[system.cpu0.icache] 488type=BaseCache 489children=tags 490addr_ranges=0:18446744073709551615 491assoc=1 492clk_domain=system.cpu_clk_domain 493forward_snoops=true 494hit_latency=2 495is_top_level=true 496max_miss_count=0 497mshrs=4 498prefetch_on_access=false 499prefetcher=Null 500response_latency=2 501size=32768 502system=system 503tags=system.cpu0.icache.tags 504tgts_per_mshr=20 505two_queue=false 506write_buffers=8 507cpu_side=system.cpu0.icache_port 508mem_side=system.toL2Bus.slave[0] 509 510[system.cpu0.icache.tags] 511type=LRU 512assoc=1 513block_size=64 514clk_domain=system.cpu_clk_domain 515hit_latency=2 516size=32768 517 518[system.cpu0.interrupts] 519type=ArmInterrupts 520 521[system.cpu0.isa] 522type=ArmISA 523fpsid=1090793632 524id_isar0=34607377 525id_isar1=34677009 526id_isar2=555950401 527id_isar3=17899825 528id_isar4=268501314 529id_isar5=0 530id_mmfr0=3 531id_mmfr1=0 532id_mmfr2=19070976 533id_mmfr3=4027589137 534id_pfr0=49 535id_pfr1=1 536midr=890224640 537 538[system.cpu0.itb] 539type=ArmTLB 540children=walker 541size=64 542walker=system.cpu0.itb.walker 543 544[system.cpu0.itb.walker] 545type=ArmTableWalker 546clk_domain=system.cpu_clk_domain 547num_squash_per_cycle=2 548sys=system 549port=system.toL2Bus.slave[2] 550 551[system.cpu0.tracer] 552type=ExeTracer 553 554[system.cpu1] 555type=DerivO3CPU 556children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 557LFSTSize=1024 558LQEntries=32 559LSQCheckLoads=true 560LSQDepCheckShift=4 561SQEntries=32 562SSITSize=1024 563activity=0 564backComSize=5 565branchPred=system.cpu1.branchPred 566cachePorts=200 567checker=Null 568clk_domain=system.cpu_clk_domain 569commitToDecodeDelay=1 570commitToFetchDelay=1 571commitToIEWDelay=1 572commitToRenameDelay=1 573commitWidth=8 574cpu_id=1 575decodeToFetchDelay=1 576decodeToRenameDelay=1 577decodeWidth=8 578dispatchWidth=8 579do_checkpoint_insts=true 580do_quiesce=true 581do_statistics_insts=true 582dtb=system.cpu1.dtb 583fetchToDecodeDelay=1 584fetchTrapLatency=1 585fetchWidth=8 586forwardComSize=5 587fuPool=system.cpu1.fuPool 588function_trace=false 589function_trace_start=0 590iewToCommitDelay=1 591iewToDecodeDelay=1 592iewToFetchDelay=1 593iewToRenameDelay=1 594interrupts=system.cpu1.interrupts 595isa=system.cpu1.isa 596issueToExecuteDelay=1 597issueWidth=8 598itb=system.cpu1.itb 599max_insts_all_threads=0 600max_insts_any_thread=0 601max_loads_all_threads=0 602max_loads_any_thread=0 603needsTSO=false 604numIQEntries=64	131numPhysFloatRegs=256 132numPhysIntRegs=256 133numROBEntries=192 134numRobs=1 135numThreads=1 136profile=0 137progress_interval=0 138renameToDecodeDelay=1 139renameToFetchDelay=1 140renameToIEWDelay=2 141renameToROBDelay=1 142renameWidth=8 143simpoint_start_insts= 144smtCommitPolicy=RoundRobin 145smtFetchPolicy=SingleThread 146smtIQPolicy=Partitioned 147smtIQThreshold=100 148smtLSQPolicy=Partitioned 149smtLSQThreshold=100 150smtNumFetchingThreads=1 151smtROBPolicy=Partitioned 152smtROBThreshold=100 153squashWidth=8 154store_set_clear_period=250000 155switched_out=false 156system=system 157tracer=system.cpu0.tracer 158trapLatency=13 159wbDepth=1 160wbWidth=8 161workload= 162dcache_port=system.cpu0.dcache.cpu_side 163icache_port=system.cpu0.icache.cpu_side 164 165[system.cpu0.branchPred] 166type=BranchPredictor 167BTBEntries=4096 168BTBTagSize=16 169RASSize=16 170choiceCtrBits=2 171choicePredictorSize=8192 172globalCtrBits=2 173globalPredictorSize=8192 174instShiftAmt=2 175localCtrBits=2 176localHistoryTableSize=2048 177localPredictorSize=2048 178numThreads=1 179predType=tournament 180 181[system.cpu0.dcache] 182type=BaseCache 183children=tags 184addr_ranges=0:18446744073709551615 185assoc=4 186clk_domain=system.cpu_clk_domain 187forward_snoops=true 188hit_latency=2 189is_top_level=true 190max_miss_count=0 191mshrs=4 192prefetch_on_access=false 193prefetcher=Null 194response_latency=2 195size=32768 196system=system 197tags=system.cpu0.dcache.tags 198tgts_per_mshr=20 199two_queue=false 200write_buffers=8 201cpu_side=system.cpu0.dcache_port 202mem_side=system.toL2Bus.slave[1] 203 204[system.cpu0.dcache.tags] 205type=LRU 206assoc=4 207block_size=64 208clk_domain=system.cpu_clk_domain 209hit_latency=2 210size=32768 211 212[system.cpu0.dtb] 213type=ArmTLB 214children=walker 215size=64 216walker=system.cpu0.dtb.walker 217 218[system.cpu0.dtb.walker] 219type=ArmTableWalker 220clk_domain=system.cpu_clk_domain 221num_squash_per_cycle=2 222sys=system 223port=system.toL2Bus.slave[3] 224 225[system.cpu0.fuPool] 226type=FUPool 227children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 228FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 229 230[system.cpu0.fuPool.FUList0] 231type=FUDesc 232children=opList 233count=6 234opList=system.cpu0.fuPool.FUList0.opList 235 236[system.cpu0.fuPool.FUList0.opList] 237type=OpDesc 238issueLat=1 239opClass=IntAlu 240opLat=1 241 242[system.cpu0.fuPool.FUList1] 243type=FUDesc 244children=opList0 opList1 245count=2 246opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 247 248[system.cpu0.fuPool.FUList1.opList0] 249type=OpDesc 250issueLat=1 251opClass=IntMult 252opLat=3 253 254[system.cpu0.fuPool.FUList1.opList1] 255type=OpDesc 256issueLat=19 257opClass=IntDiv 258opLat=20 259 260[system.cpu0.fuPool.FUList2] 261type=FUDesc 262children=opList0 opList1 opList2 263count=4 264opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 265 266[system.cpu0.fuPool.FUList2.opList0] 267type=OpDesc 268issueLat=1 269opClass=FloatAdd 270opLat=2 271 272[system.cpu0.fuPool.FUList2.opList1] 273type=OpDesc 274issueLat=1 275opClass=FloatCmp 276opLat=2 277 278[system.cpu0.fuPool.FUList2.opList2] 279type=OpDesc 280issueLat=1 281opClass=FloatCvt 282opLat=2 283 284[system.cpu0.fuPool.FUList3] 285type=FUDesc 286children=opList0 opList1 opList2 287count=2 288opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 289 290[system.cpu0.fuPool.FUList3.opList0] 291type=OpDesc 292issueLat=1 293opClass=FloatMult 294opLat=4 295 296[system.cpu0.fuPool.FUList3.opList1] 297type=OpDesc 298issueLat=12 299opClass=FloatDiv 300opLat=12 301 302[system.cpu0.fuPool.FUList3.opList2] 303type=OpDesc 304issueLat=24 305opClass=FloatSqrt 306opLat=24 307 308[system.cpu0.fuPool.FUList4] 309type=FUDesc 310children=opList 311count=0 312opList=system.cpu0.fuPool.FUList4.opList 313 314[system.cpu0.fuPool.FUList4.opList] 315type=OpDesc 316issueLat=1 317opClass=MemRead 318opLat=1 319 320[system.cpu0.fuPool.FUList5] 321type=FUDesc 322children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 323count=4 324opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 325 326[system.cpu0.fuPool.FUList5.opList00] 327type=OpDesc 328issueLat=1 329opClass=SimdAdd 330opLat=1 331 332[system.cpu0.fuPool.FUList5.opList01] 333type=OpDesc 334issueLat=1 335opClass=SimdAddAcc 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList02] 339type=OpDesc 340issueLat=1 341opClass=SimdAlu 342opLat=1 343 344[system.cpu0.fuPool.FUList5.opList03] 345type=OpDesc 346issueLat=1 347opClass=SimdCmp 348opLat=1 349 350[system.cpu0.fuPool.FUList5.opList04] 351type=OpDesc 352issueLat=1 353opClass=SimdCvt 354opLat=1 355 356[system.cpu0.fuPool.FUList5.opList05] 357type=OpDesc 358issueLat=1 359opClass=SimdMisc 360opLat=1 361 362[system.cpu0.fuPool.FUList5.opList06] 363type=OpDesc 364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList07] 369type=OpDesc 370issueLat=1 371opClass=SimdMultAcc 372opLat=1 373 374[system.cpu0.fuPool.FUList5.opList08] 375type=OpDesc 376issueLat=1 377opClass=SimdShift 378opLat=1 379 380[system.cpu0.fuPool.FUList5.opList09] 381type=OpDesc 382issueLat=1 383opClass=SimdShiftAcc 384opLat=1 385 386[system.cpu0.fuPool.FUList5.opList10] 387type=OpDesc 388issueLat=1 389opClass=SimdSqrt 390opLat=1 391 392[system.cpu0.fuPool.FUList5.opList11] 393type=OpDesc 394issueLat=1 395opClass=SimdFloatAdd 396opLat=1 397 398[system.cpu0.fuPool.FUList5.opList12] 399type=OpDesc 400issueLat=1 401opClass=SimdFloatAlu 402opLat=1 403 404[system.cpu0.fuPool.FUList5.opList13] 405type=OpDesc 406issueLat=1 407opClass=SimdFloatCmp 408opLat=1 409 410[system.cpu0.fuPool.FUList5.opList14] 411type=OpDesc 412issueLat=1 413opClass=SimdFloatCvt 414opLat=1 415 416[system.cpu0.fuPool.FUList5.opList15] 417type=OpDesc 418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu0.fuPool.FUList5.opList16] 423type=OpDesc 424issueLat=1 425opClass=SimdFloatMisc 426opLat=1 427 428[system.cpu0.fuPool.FUList5.opList17] 429type=OpDesc 430issueLat=1 431opClass=SimdFloatMult 432opLat=1 433 434[system.cpu0.fuPool.FUList5.opList18] 435type=OpDesc 436issueLat=1 437opClass=SimdFloatMultAcc 438opLat=1 439 440[system.cpu0.fuPool.FUList5.opList19] 441type=OpDesc 442issueLat=1 443opClass=SimdFloatSqrt 444opLat=1 445 446[system.cpu0.fuPool.FUList6] 447type=FUDesc 448children=opList 449count=0 450opList=system.cpu0.fuPool.FUList6.opList 451 452[system.cpu0.fuPool.FUList6.opList] 453type=OpDesc 454issueLat=1 455opClass=MemWrite 456opLat=1 457 458[system.cpu0.fuPool.FUList7] 459type=FUDesc 460children=opList0 opList1 461count=4 462opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 463 464[system.cpu0.fuPool.FUList7.opList0] 465type=OpDesc 466issueLat=1 467opClass=MemRead 468opLat=1 469 470[system.cpu0.fuPool.FUList7.opList1] 471type=OpDesc 472issueLat=1 473opClass=MemWrite 474opLat=1 475 476[system.cpu0.fuPool.FUList8] 477type=FUDesc 478children=opList 479count=1 480opList=system.cpu0.fuPool.FUList8.opList 481 482[system.cpu0.fuPool.FUList8.opList] 483type=OpDesc 484issueLat=3 485opClass=IprAccess 486opLat=3 487 488[system.cpu0.icache] 489type=BaseCache 490children=tags 491addr_ranges=0:18446744073709551615 492assoc=1 493clk_domain=system.cpu_clk_domain 494forward_snoops=true 495hit_latency=2 496is_top_level=true 497max_miss_count=0 498mshrs=4 499prefetch_on_access=false 500prefetcher=Null 501response_latency=2 502size=32768 503system=system 504tags=system.cpu0.icache.tags 505tgts_per_mshr=20 506two_queue=false 507write_buffers=8 508cpu_side=system.cpu0.icache_port 509mem_side=system.toL2Bus.slave[0] 510 511[system.cpu0.icache.tags] 512type=LRU 513assoc=1 514block_size=64 515clk_domain=system.cpu_clk_domain 516hit_latency=2 517size=32768 518 519[system.cpu0.interrupts] 520type=ArmInterrupts 521 522[system.cpu0.isa] 523type=ArmISA 524fpsid=1090793632 525id_isar0=34607377 526id_isar1=34677009 527id_isar2=555950401 528id_isar3=17899825 529id_isar4=268501314 530id_isar5=0 531id_mmfr0=3 532id_mmfr1=0 533id_mmfr2=19070976 534id_mmfr3=4027589137 535id_pfr0=49 536id_pfr1=1 537midr=890224640 538 539[system.cpu0.itb] 540type=ArmTLB 541children=walker 542size=64 543walker=system.cpu0.itb.walker 544 545[system.cpu0.itb.walker] 546type=ArmTableWalker 547clk_domain=system.cpu_clk_domain 548num_squash_per_cycle=2 549sys=system 550port=system.toL2Bus.slave[2] 551 552[system.cpu0.tracer] 553type=ExeTracer 554 555[system.cpu1] 556type=DerivO3CPU 557children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 558LFSTSize=1024 559LQEntries=32 560LSQCheckLoads=true 561LSQDepCheckShift=4 562SQEntries=32 563SSITSize=1024 564activity=0 565backComSize=5 566branchPred=system.cpu1.branchPred 567cachePorts=200 568checker=Null 569clk_domain=system.cpu_clk_domain 570commitToDecodeDelay=1 571commitToFetchDelay=1 572commitToIEWDelay=1 573commitToRenameDelay=1 574commitWidth=8 575cpu_id=1 576decodeToFetchDelay=1 577decodeToRenameDelay=1 578decodeWidth=8 579dispatchWidth=8 580do_checkpoint_insts=true 581do_quiesce=true 582do_statistics_insts=true 583dtb=system.cpu1.dtb 584fetchToDecodeDelay=1 585fetchTrapLatency=1 586fetchWidth=8 587forwardComSize=5 588fuPool=system.cpu1.fuPool 589function_trace=false 590function_trace_start=0 591iewToCommitDelay=1 592iewToDecodeDelay=1 593iewToFetchDelay=1 594iewToRenameDelay=1 595interrupts=system.cpu1.interrupts 596isa=system.cpu1.isa 597issueToExecuteDelay=1 598issueWidth=8 599itb=system.cpu1.itb 600max_insts_all_threads=0 601max_insts_any_thread=0 602max_loads_all_threads=0 603max_loads_any_thread=0 604needsTSO=false 605numIQEntries=64
	606numPhysCCRegs=0
605numPhysFloatRegs=256 606numPhysIntRegs=256 607numROBEntries=192 608numRobs=1 609numThreads=1 610profile=0 611progress_interval=0 612renameToDecodeDelay=1 613renameToFetchDelay=1 614renameToIEWDelay=2 615renameToROBDelay=1 616renameWidth=8 617simpoint_start_insts= 618smtCommitPolicy=RoundRobin 619smtFetchPolicy=SingleThread 620smtIQPolicy=Partitioned 621smtIQThreshold=100 622smtLSQPolicy=Partitioned 623smtLSQThreshold=100 624smtNumFetchingThreads=1 625smtROBPolicy=Partitioned 626smtROBThreshold=100 627squashWidth=8 628store_set_clear_period=250000 629switched_out=false 630system=system 631tracer=system.cpu1.tracer 632trapLatency=13 633wbDepth=1 634wbWidth=8 635workload= 636dcache_port=system.cpu1.dcache.cpu_side 637icache_port=system.cpu1.icache.cpu_side 638 639[system.cpu1.branchPred] 640type=BranchPredictor 641BTBEntries=4096 642BTBTagSize=16 643RASSize=16 644choiceCtrBits=2 645choicePredictorSize=8192 646globalCtrBits=2 647globalPredictorSize=8192 648instShiftAmt=2 649localCtrBits=2 650localHistoryTableSize=2048 651localPredictorSize=2048 652numThreads=1 653predType=tournament 654 655[system.cpu1.dcache] 656type=BaseCache 657children=tags 658addr_ranges=0:18446744073709551615 659assoc=4 660clk_domain=system.cpu_clk_domain 661forward_snoops=true 662hit_latency=2 663is_top_level=true 664max_miss_count=0 665mshrs=4 666prefetch_on_access=false 667prefetcher=Null 668response_latency=2 669size=32768 670system=system 671tags=system.cpu1.dcache.tags 672tgts_per_mshr=20 673two_queue=false 674write_buffers=8 675cpu_side=system.cpu1.dcache_port 676mem_side=system.toL2Bus.slave[5] 677 678[system.cpu1.dcache.tags] 679type=LRU 680assoc=4 681block_size=64 682clk_domain=system.cpu_clk_domain 683hit_latency=2 684size=32768 685 686[system.cpu1.dtb] 687type=ArmTLB 688children=walker 689size=64 690walker=system.cpu1.dtb.walker 691 692[system.cpu1.dtb.walker] 693type=ArmTableWalker 694clk_domain=system.cpu_clk_domain 695num_squash_per_cycle=2 696sys=system 697port=system.toL2Bus.slave[7] 698 699[system.cpu1.fuPool] 700type=FUPool 701children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 702FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 703 704[system.cpu1.fuPool.FUList0] 705type=FUDesc 706children=opList 707count=6 708opList=system.cpu1.fuPool.FUList0.opList 709 710[system.cpu1.fuPool.FUList0.opList] 711type=OpDesc 712issueLat=1 713opClass=IntAlu 714opLat=1 715 716[system.cpu1.fuPool.FUList1] 717type=FUDesc 718children=opList0 opList1 719count=2 720opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 721 722[system.cpu1.fuPool.FUList1.opList0] 723type=OpDesc 724issueLat=1 725opClass=IntMult 726opLat=3 727 728[system.cpu1.fuPool.FUList1.opList1] 729type=OpDesc 730issueLat=19 731opClass=IntDiv 732opLat=20 733 734[system.cpu1.fuPool.FUList2] 735type=FUDesc 736children=opList0 opList1 opList2 737count=4 738opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 739 740[system.cpu1.fuPool.FUList2.opList0] 741type=OpDesc 742issueLat=1 743opClass=FloatAdd 744opLat=2 745 746[system.cpu1.fuPool.FUList2.opList1] 747type=OpDesc 748issueLat=1 749opClass=FloatCmp 750opLat=2 751 752[system.cpu1.fuPool.FUList2.opList2] 753type=OpDesc 754issueLat=1 755opClass=FloatCvt 756opLat=2 757 758[system.cpu1.fuPool.FUList3] 759type=FUDesc 760children=opList0 opList1 opList2 761count=2 762opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 763 764[system.cpu1.fuPool.FUList3.opList0] 765type=OpDesc 766issueLat=1 767opClass=FloatMult 768opLat=4 769 770[system.cpu1.fuPool.FUList3.opList1] 771type=OpDesc 772issueLat=12 773opClass=FloatDiv 774opLat=12 775 776[system.cpu1.fuPool.FUList3.opList2] 777type=OpDesc 778issueLat=24 779opClass=FloatSqrt 780opLat=24 781 782[system.cpu1.fuPool.FUList4] 783type=FUDesc 784children=opList 785count=0 786opList=system.cpu1.fuPool.FUList4.opList 787 788[system.cpu1.fuPool.FUList4.opList] 789type=OpDesc 790issueLat=1 791opClass=MemRead 792opLat=1 793 794[system.cpu1.fuPool.FUList5] 795type=FUDesc 796children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 797count=4 798opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 799 800[system.cpu1.fuPool.FUList5.opList00] 801type=OpDesc 802issueLat=1 803opClass=SimdAdd 804opLat=1 805 806[system.cpu1.fuPool.FUList5.opList01] 807type=OpDesc 808issueLat=1 809opClass=SimdAddAcc 810opLat=1 811 812[system.cpu1.fuPool.FUList5.opList02] 813type=OpDesc 814issueLat=1 815opClass=SimdAlu 816opLat=1 817 818[system.cpu1.fuPool.FUList5.opList03] 819type=OpDesc 820issueLat=1 821opClass=SimdCmp 822opLat=1 823 824[system.cpu1.fuPool.FUList5.opList04] 825type=OpDesc 826issueLat=1 827opClass=SimdCvt 828opLat=1 829 830[system.cpu1.fuPool.FUList5.opList05] 831type=OpDesc 832issueLat=1 833opClass=SimdMisc 834opLat=1 835 836[system.cpu1.fuPool.FUList5.opList06] 837type=OpDesc 838issueLat=1 839opClass=SimdMult 840opLat=1 841 842[system.cpu1.fuPool.FUList5.opList07] 843type=OpDesc 844issueLat=1 845opClass=SimdMultAcc 846opLat=1 847 848[system.cpu1.fuPool.FUList5.opList08] 849type=OpDesc 850issueLat=1 851opClass=SimdShift 852opLat=1 853 854[system.cpu1.fuPool.FUList5.opList09] 855type=OpDesc 856issueLat=1 857opClass=SimdShiftAcc 858opLat=1 859 860[system.cpu1.fuPool.FUList5.opList10] 861type=OpDesc 862issueLat=1 863opClass=SimdSqrt 864opLat=1 865 866[system.cpu1.fuPool.FUList5.opList11] 867type=OpDesc 868issueLat=1 869opClass=SimdFloatAdd 870opLat=1 871 872[system.cpu1.fuPool.FUList5.opList12] 873type=OpDesc 874issueLat=1 875opClass=SimdFloatAlu 876opLat=1 877 878[system.cpu1.fuPool.FUList5.opList13] 879type=OpDesc 880issueLat=1 881opClass=SimdFloatCmp 882opLat=1 883 884[system.cpu1.fuPool.FUList5.opList14] 885type=OpDesc 886issueLat=1 887opClass=SimdFloatCvt 888opLat=1 889 890[system.cpu1.fuPool.FUList5.opList15] 891type=OpDesc 892issueLat=1 893opClass=SimdFloatDiv 894opLat=1 895 896[system.cpu1.fuPool.FUList5.opList16] 897type=OpDesc 898issueLat=1 899opClass=SimdFloatMisc 900opLat=1 901 902[system.cpu1.fuPool.FUList5.opList17] 903type=OpDesc 904issueLat=1 905opClass=SimdFloatMult 906opLat=1 907 908[system.cpu1.fuPool.FUList5.opList18] 909type=OpDesc 910issueLat=1 911opClass=SimdFloatMultAcc 912opLat=1 913 914[system.cpu1.fuPool.FUList5.opList19] 915type=OpDesc 916issueLat=1 917opClass=SimdFloatSqrt 918opLat=1 919 920[system.cpu1.fuPool.FUList6] 921type=FUDesc 922children=opList 923count=0 924opList=system.cpu1.fuPool.FUList6.opList 925 926[system.cpu1.fuPool.FUList6.opList] 927type=OpDesc 928issueLat=1 929opClass=MemWrite 930opLat=1 931 932[system.cpu1.fuPool.FUList7] 933type=FUDesc 934children=opList0 opList1 935count=4 936opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 937 938[system.cpu1.fuPool.FUList7.opList0] 939type=OpDesc 940issueLat=1 941opClass=MemRead 942opLat=1 943 944[system.cpu1.fuPool.FUList7.opList1] 945type=OpDesc 946issueLat=1 947opClass=MemWrite 948opLat=1 949 950[system.cpu1.fuPool.FUList8] 951type=FUDesc 952children=opList 953count=1 954opList=system.cpu1.fuPool.FUList8.opList 955 956[system.cpu1.fuPool.FUList8.opList] 957type=OpDesc 958issueLat=3 959opClass=IprAccess 960opLat=3 961 962[system.cpu1.icache] 963type=BaseCache 964children=tags 965addr_ranges=0:18446744073709551615 966assoc=1 967clk_domain=system.cpu_clk_domain 968forward_snoops=true 969hit_latency=2 970is_top_level=true 971max_miss_count=0 972mshrs=4 973prefetch_on_access=false 974prefetcher=Null 975response_latency=2 976size=32768 977system=system 978tags=system.cpu1.icache.tags 979tgts_per_mshr=20 980two_queue=false 981write_buffers=8 982cpu_side=system.cpu1.icache_port 983mem_side=system.toL2Bus.slave[4] 984 985[system.cpu1.icache.tags] 986type=LRU 987assoc=1 988block_size=64 989clk_domain=system.cpu_clk_domain 990hit_latency=2 991size=32768 992 993[system.cpu1.interrupts] 994type=ArmInterrupts 995 996[system.cpu1.isa] 997type=ArmISA 998fpsid=1090793632 999id_isar0=34607377 1000id_isar1=34677009 1001id_isar2=555950401 1002id_isar3=17899825 1003id_isar4=268501314 1004id_isar5=0 1005id_mmfr0=3 1006id_mmfr1=0 1007id_mmfr2=19070976 1008id_mmfr3=4027589137 1009id_pfr0=49 1010id_pfr1=1 1011midr=890224640 1012 1013[system.cpu1.itb] 1014type=ArmTLB 1015children=walker 1016size=64 1017walker=system.cpu1.itb.walker 1018 1019[system.cpu1.itb.walker] 1020type=ArmTableWalker 1021clk_domain=system.cpu_clk_domain 1022num_squash_per_cycle=2 1023sys=system 1024port=system.toL2Bus.slave[6] 1025 1026[system.cpu1.tracer] 1027type=ExeTracer 1028 1029[system.cpu_clk_domain] 1030type=SrcClockDomain 1031clock=500 1032voltage_domain=system.voltage_domain 1033 1034[system.intrctrl] 1035type=IntrControl 1036sys=system 1037 1038[system.iobus] 1039type=NoncoherentBus 1040clk_domain=system.clk_domain 1041header_cycles=1 1042use_default_range=false 1043width=8 1044master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 1045slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 1046 1047[system.iocache] 1048type=BaseCache 1049children=tags 1050addr_ranges=0:134217727 1051assoc=8 1052clk_domain=system.clk_domain 1053forward_snoops=false 1054hit_latency=50 1055is_top_level=true 1056max_miss_count=0 1057mshrs=20 1058prefetch_on_access=false 1059prefetcher=Null 1060response_latency=50 1061size=1024 1062system=system 1063tags=system.iocache.tags 1064tgts_per_mshr=12 1065two_queue=false 1066write_buffers=8 1067cpu_side=system.iobus.master[25] 1068mem_side=system.membus.slave[2] 1069 1070[system.iocache.tags] 1071type=LRU 1072assoc=8 1073block_size=64 1074clk_domain=system.clk_domain 1075hit_latency=50 1076size=1024 1077 1078[system.l2c] 1079type=BaseCache 1080children=tags 1081addr_ranges=0:18446744073709551615 1082assoc=8 1083clk_domain=system.cpu_clk_domain 1084forward_snoops=true 1085hit_latency=20 1086is_top_level=false 1087max_miss_count=0 1088mshrs=20 1089prefetch_on_access=false 1090prefetcher=Null 1091response_latency=20 1092size=4194304 1093system=system 1094tags=system.l2c.tags 1095tgts_per_mshr=12 1096two_queue=false 1097write_buffers=8 1098cpu_side=system.toL2Bus.master[0] 1099mem_side=system.membus.slave[1] 1100 1101[system.l2c.tags] 1102type=LRU 1103assoc=8 1104block_size=64 1105clk_domain=system.cpu_clk_domain 1106hit_latency=20 1107size=4194304 1108 1109[system.membus] 1110type=CoherentBus 1111children=badaddr_responder 1112clk_domain=system.clk_domain 1113header_cycles=1 1114system=system 1115use_default_range=false 1116width=8 1117default=system.membus.badaddr_responder.pio 1118master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 1119slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1120 1121[system.membus.badaddr_responder] 1122type=IsaFake 1123clk_domain=system.clk_domain 1124fake_mem=false 1125pio_addr=0 1126pio_latency=100000 1127pio_size=8 1128ret_bad_addr=true 1129ret_data16=65535 1130ret_data32=4294967295 1131ret_data64=18446744073709551615 1132ret_data8=255 1133system=system 1134update_data=false 1135warn_access=warn 1136pio=system.membus.default 1137 1138[system.physmem] 1139type=SimpleDRAM 1140activation_limit=4 1141addr_mapping=RaBaChCo 1142banks_per_rank=8 1143burst_length=8 1144channels=1 1145clk_domain=system.clk_domain 1146conf_table_reported=true 1147device_bus_width=8 1148device_rowbuffer_size=1024 1149devices_per_rank=8 1150in_addr_map=true 1151mem_sched_policy=frfcfs 1152null=false 1153page_policy=open 1154range=0:134217727 1155ranks_per_channel=2 1156read_buffer_size=32 1157static_backend_latency=10000 1158static_frontend_latency=10000 1159tBURST=5000 1160tCL=13750 1161tRCD=13750 1162tREFI=7800000 1163tRFC=300000 1164tRP=13750 1165tWTR=7500 1166tXAW=40000 1167write_buffer_size=32 1168write_thresh_perc=70 1169port=system.membus.master[6] 1170 1171[system.realview] 1172type=RealView 1173children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1174intrctrl=system.intrctrl 1175max_mem_size=268435456 1176mem_start_addr=0 1177pci_cfg_base=0 1178system=system 1179 1180[system.realview.a9scu] 1181type=A9SCU 1182clk_domain=system.clk_domain 1183pio_addr=520093696 1184pio_latency=100000 1185system=system 1186pio=system.membus.master[4] 1187 1188[system.realview.aaci_fake] 1189type=AmbaFake 1190amba_id=0 1191clk_domain=system.clk_domain 1192ignore_access=false 1193pio_addr=268451840 1194pio_latency=100000 1195system=system 1196pio=system.iobus.master[21] 1197 1198[system.realview.cf_ctrl] 1199type=IdeController 1200BAR0=402653184 1201BAR0LegacyIO=true 1202BAR0Size=16 1203BAR1=402653440 1204BAR1LegacyIO=true 1205BAR1Size=1 1206BAR2=1 1207BAR2LegacyIO=false 1208BAR2Size=8 1209BAR3=1 1210BAR3LegacyIO=false 1211BAR3Size=4 1212BAR4=1 1213BAR4LegacyIO=false 1214BAR4Size=16 1215BAR5=1 1216BAR5LegacyIO=false 1217BAR5Size=0 1218BIST=0 1219CacheLineSize=0 1220CardbusCIS=0 1221ClassCode=1 1222Command=1 1223DeviceID=28945 1224ExpansionROM=0 1225HeaderType=0 1226InterruptLine=31 1227InterruptPin=1 1228LatencyTimer=0 1229MaximumLatency=0 1230MinimumGrant=0 1231ProgIF=133 1232Revision=0 1233Status=640 1234SubClassCode=1 1235SubsystemID=0 1236SubsystemVendorID=0 1237VendorID=32902 1238clk_domain=system.clk_domain 1239config_latency=20000 1240ctrl_offset=2 1241disks=system.cf0 1242io_shift=1 1243pci_bus=2 1244pci_dev=7 1245pci_func=0 1246pio_latency=30000 1247platform=system.realview 1248system=system 1249config=system.iobus.master[8] 1250dma=system.iobus.slave[2] 1251pio=system.iobus.master[7] 1252 1253[system.realview.clcd] 1254type=Pl111 1255amba_id=1315089 1256clk_domain=system.clk_domain 1257gic=system.realview.gic 1258int_num=55 1259pio_addr=268566528 1260pio_latency=10000 1261pixel_clock=41667 1262system=system 1263vnc=system.vncserver 1264dma=system.iobus.slave[1] 1265pio=system.iobus.master[4] 1266 1267[system.realview.dmac_fake] 1268type=AmbaFake 1269amba_id=0 1270clk_domain=system.clk_domain 1271ignore_access=false 1272pio_addr=268632064 1273pio_latency=100000 1274system=system 1275pio=system.iobus.master[9] 1276 1277[system.realview.flash_fake] 1278type=IsaFake 1279clk_domain=system.clk_domain 1280fake_mem=true 1281pio_addr=1073741824 1282pio_latency=100000 1283pio_size=536870912 1284ret_bad_addr=false 1285ret_data16=65535 1286ret_data32=4294967295 1287ret_data64=18446744073709551615 1288ret_data8=255 1289system=system 1290update_data=false 1291warn_access= 1292pio=system.iobus.master[24] 1293 1294[system.realview.gic] 1295type=Pl390 1296clk_domain=system.clk_domain 1297cpu_addr=520093952 1298cpu_pio_delay=10000 1299dist_addr=520097792 1300dist_pio_delay=10000 1301int_latency=10000 1302it_lines=128 1303platform=system.realview 1304system=system 1305pio=system.membus.master[2] 1306 1307[system.realview.gpio0_fake] 1308type=AmbaFake 1309amba_id=0 1310clk_domain=system.clk_domain 1311ignore_access=false 1312pio_addr=268513280 1313pio_latency=100000 1314system=system 1315pio=system.iobus.master[16] 1316 1317[system.realview.gpio1_fake] 1318type=AmbaFake 1319amba_id=0 1320clk_domain=system.clk_domain 1321ignore_access=false 1322pio_addr=268517376 1323pio_latency=100000 1324system=system 1325pio=system.iobus.master[17] 1326 1327[system.realview.gpio2_fake] 1328type=AmbaFake 1329amba_id=0 1330clk_domain=system.clk_domain 1331ignore_access=false 1332pio_addr=268521472 1333pio_latency=100000 1334system=system 1335pio=system.iobus.master[18] 1336 1337[system.realview.kmi0] 1338type=Pl050 1339amba_id=1314896 1340clk_domain=system.clk_domain 1341gic=system.realview.gic 1342int_delay=1000000 1343int_num=52 1344is_mouse=false 1345pio_addr=268460032 1346pio_latency=100000 1347system=system 1348vnc=system.vncserver 1349pio=system.iobus.master[5] 1350 1351[system.realview.kmi1] 1352type=Pl050 1353amba_id=1314896 1354clk_domain=system.clk_domain 1355gic=system.realview.gic 1356int_delay=1000000 1357int_num=53 1358is_mouse=true 1359pio_addr=268464128 1360pio_latency=100000 1361system=system 1362vnc=system.vncserver 1363pio=system.iobus.master[6] 1364 1365[system.realview.l2x0_fake] 1366type=IsaFake 1367clk_domain=system.clk_domain 1368fake_mem=false 1369pio_addr=520101888 1370pio_latency=100000 1371pio_size=4095 1372ret_bad_addr=false 1373ret_data16=65535 1374ret_data32=4294967295 1375ret_data64=18446744073709551615 1376ret_data8=255 1377system=system 1378update_data=false 1379warn_access= 1380pio=system.membus.master[3] 1381 1382[system.realview.local_cpu_timer] 1383type=CpuLocalTimer 1384clk_domain=system.clk_domain 1385gic=system.realview.gic 1386int_num_timer=29 1387int_num_watchdog=30 1388pio_addr=520095232 1389pio_latency=100000 1390system=system 1391pio=system.membus.master[5] 1392 1393[system.realview.mmc_fake] 1394type=AmbaFake 1395amba_id=0 1396clk_domain=system.clk_domain 1397ignore_access=false 1398pio_addr=268455936 1399pio_latency=100000 1400system=system 1401pio=system.iobus.master[22] 1402 1403[system.realview.nvmem] 1404type=SimpleMemory 1405bandwidth=73.000000 1406clk_domain=system.clk_domain 1407conf_table_reported=false 1408in_addr_map=true 1409latency=30000 1410latency_var=0 1411null=false 1412range=2147483648:2214592511 1413port=system.membus.master[1] 1414 1415[system.realview.realview_io] 1416type=RealViewCtrl 1417clk_domain=system.clk_domain 1418idreg=0 1419pio_addr=268435456 1420pio_latency=100000 1421proc_id0=201326592 1422proc_id1=201327138 1423system=system 1424pio=system.iobus.master[1] 1425 1426[system.realview.rtc] 1427type=PL031 1428amba_id=3412017 1429clk_domain=system.clk_domain 1430gic=system.realview.gic 1431int_delay=100000 1432int_num=42 1433pio_addr=268529664 1434pio_latency=100000 1435system=system 1436time=Thu Jan 1 00:00:00 2009 1437pio=system.iobus.master[23] 1438 1439[system.realview.sci_fake] 1440type=AmbaFake 1441amba_id=0 1442clk_domain=system.clk_domain 1443ignore_access=false 1444pio_addr=268492800 1445pio_latency=100000 1446system=system 1447pio=system.iobus.master[20] 1448 1449[system.realview.smc_fake] 1450type=AmbaFake 1451amba_id=0 1452clk_domain=system.clk_domain 1453ignore_access=false 1454pio_addr=269357056 1455pio_latency=100000 1456system=system 1457pio=system.iobus.master[13] 1458 1459[system.realview.sp810_fake] 1460type=AmbaFake 1461amba_id=0 1462clk_domain=system.clk_domain 1463ignore_access=true 1464pio_addr=268439552 1465pio_latency=100000 1466system=system 1467pio=system.iobus.master[14] 1468 1469[system.realview.ssp_fake] 1470type=AmbaFake 1471amba_id=0 1472clk_domain=system.clk_domain 1473ignore_access=false 1474pio_addr=268488704 1475pio_latency=100000 1476system=system 1477pio=system.iobus.master[19] 1478 1479[system.realview.timer0] 1480type=Sp804 1481amba_id=1316868 1482clk_domain=system.clk_domain 1483clock0=1000000 1484clock1=1000000 1485gic=system.realview.gic 1486int_num0=36 1487int_num1=36 1488pio_addr=268505088 1489pio_latency=100000 1490system=system 1491pio=system.iobus.master[2] 1492 1493[system.realview.timer1] 1494type=Sp804 1495amba_id=1316868 1496clk_domain=system.clk_domain 1497clock0=1000000 1498clock1=1000000 1499gic=system.realview.gic 1500int_num0=37 1501int_num1=37 1502pio_addr=268509184 1503pio_latency=100000 1504system=system 1505pio=system.iobus.master[3] 1506 1507[system.realview.uart] 1508type=Pl011 1509clk_domain=system.clk_domain 1510end_on_eot=false 1511gic=system.realview.gic 1512int_delay=100000 1513int_num=44 1514pio_addr=268472320 1515pio_latency=100000 1516platform=system.realview 1517system=system 1518terminal=system.terminal 1519pio=system.iobus.master[0] 1520 1521[system.realview.uart1_fake] 1522type=AmbaFake 1523amba_id=0 1524clk_domain=system.clk_domain 1525ignore_access=false 1526pio_addr=268476416 1527pio_latency=100000 1528system=system 1529pio=system.iobus.master[10] 1530 1531[system.realview.uart2_fake] 1532type=AmbaFake 1533amba_id=0 1534clk_domain=system.clk_domain 1535ignore_access=false 1536pio_addr=268480512 1537pio_latency=100000 1538system=system 1539pio=system.iobus.master[11] 1540 1541[system.realview.uart3_fake] 1542type=AmbaFake 1543amba_id=0 1544clk_domain=system.clk_domain 1545ignore_access=false 1546pio_addr=268484608 1547pio_latency=100000 1548system=system 1549pio=system.iobus.master[12] 1550 1551[system.realview.watchdog_fake] 1552type=AmbaFake 1553amba_id=0 1554clk_domain=system.clk_domain 1555ignore_access=false 1556pio_addr=268500992 1557pio_latency=100000 1558system=system 1559pio=system.iobus.master[15] 1560 1561[system.terminal] 1562type=Terminal 1563intr_control=system.intrctrl 1564number=0 1565output=true 1566port=3456 1567 1568[system.toL2Bus] 1569type=CoherentBus 1570clk_domain=system.cpu_clk_domain 1571header_cycles=1 1572system=system 1573use_default_range=false 1574width=8 1575master=system.l2c.cpu_side 1576slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1577 1578[system.vncserver] 1579type=VncServer 1580frame_capture=false 1581number=0 1582port=5900 1583 1584[system.voltage_domain] 1585type=VoltageDomain 1586voltage=1.000000 1587	607numPhysFloatRegs=256 608numPhysIntRegs=256 609numROBEntries=192 610numRobs=1 611numThreads=1 612profile=0 613progress_interval=0 614renameToDecodeDelay=1 615renameToFetchDelay=1 616renameToIEWDelay=2 617renameToROBDelay=1 618renameWidth=8 619simpoint_start_insts= 620smtCommitPolicy=RoundRobin 621smtFetchPolicy=SingleThread 622smtIQPolicy=Partitioned 623smtIQThreshold=100 624smtLSQPolicy=Partitioned 625smtLSQThreshold=100 626smtNumFetchingThreads=1 627smtROBPolicy=Partitioned 628smtROBThreshold=100 629squashWidth=8 630store_set_clear_period=250000 631switched_out=false 632system=system 633tracer=system.cpu1.tracer 634trapLatency=13 635wbDepth=1 636wbWidth=8 637workload= 638dcache_port=system.cpu1.dcache.cpu_side 639icache_port=system.cpu1.icache.cpu_side 640 641[system.cpu1.branchPred] 642type=BranchPredictor 643BTBEntries=4096 644BTBTagSize=16 645RASSize=16 646choiceCtrBits=2 647choicePredictorSize=8192 648globalCtrBits=2 649globalPredictorSize=8192 650instShiftAmt=2 651localCtrBits=2 652localHistoryTableSize=2048 653localPredictorSize=2048 654numThreads=1 655predType=tournament 656 657[system.cpu1.dcache] 658type=BaseCache 659children=tags 660addr_ranges=0:18446744073709551615 661assoc=4 662clk_domain=system.cpu_clk_domain 663forward_snoops=true 664hit_latency=2 665is_top_level=true 666max_miss_count=0 667mshrs=4 668prefetch_on_access=false 669prefetcher=Null 670response_latency=2 671size=32768 672system=system 673tags=system.cpu1.dcache.tags 674tgts_per_mshr=20 675two_queue=false 676write_buffers=8 677cpu_side=system.cpu1.dcache_port 678mem_side=system.toL2Bus.slave[5] 679 680[system.cpu1.dcache.tags] 681type=LRU 682assoc=4 683block_size=64 684clk_domain=system.cpu_clk_domain 685hit_latency=2 686size=32768 687 688[system.cpu1.dtb] 689type=ArmTLB 690children=walker 691size=64 692walker=system.cpu1.dtb.walker 693 694[system.cpu1.dtb.walker] 695type=ArmTableWalker 696clk_domain=system.cpu_clk_domain 697num_squash_per_cycle=2 698sys=system 699port=system.toL2Bus.slave[7] 700 701[system.cpu1.fuPool] 702type=FUPool 703children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 704FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 705 706[system.cpu1.fuPool.FUList0] 707type=FUDesc 708children=opList 709count=6 710opList=system.cpu1.fuPool.FUList0.opList 711 712[system.cpu1.fuPool.FUList0.opList] 713type=OpDesc 714issueLat=1 715opClass=IntAlu 716opLat=1 717 718[system.cpu1.fuPool.FUList1] 719type=FUDesc 720children=opList0 opList1 721count=2 722opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 723 724[system.cpu1.fuPool.FUList1.opList0] 725type=OpDesc 726issueLat=1 727opClass=IntMult 728opLat=3 729 730[system.cpu1.fuPool.FUList1.opList1] 731type=OpDesc 732issueLat=19 733opClass=IntDiv 734opLat=20 735 736[system.cpu1.fuPool.FUList2] 737type=FUDesc 738children=opList0 opList1 opList2 739count=4 740opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 741 742[system.cpu1.fuPool.FUList2.opList0] 743type=OpDesc 744issueLat=1 745opClass=FloatAdd 746opLat=2 747 748[system.cpu1.fuPool.FUList2.opList1] 749type=OpDesc 750issueLat=1 751opClass=FloatCmp 752opLat=2 753 754[system.cpu1.fuPool.FUList2.opList2] 755type=OpDesc 756issueLat=1 757opClass=FloatCvt 758opLat=2 759 760[system.cpu1.fuPool.FUList3] 761type=FUDesc 762children=opList0 opList1 opList2 763count=2 764opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 765 766[system.cpu1.fuPool.FUList3.opList0] 767type=OpDesc 768issueLat=1 769opClass=FloatMult 770opLat=4 771 772[system.cpu1.fuPool.FUList3.opList1] 773type=OpDesc 774issueLat=12 775opClass=FloatDiv 776opLat=12 777 778[system.cpu1.fuPool.FUList3.opList2] 779type=OpDesc 780issueLat=24 781opClass=FloatSqrt 782opLat=24 783 784[system.cpu1.fuPool.FUList4] 785type=FUDesc 786children=opList 787count=0 788opList=system.cpu1.fuPool.FUList4.opList 789 790[system.cpu1.fuPool.FUList4.opList] 791type=OpDesc 792issueLat=1 793opClass=MemRead 794opLat=1 795 796[system.cpu1.fuPool.FUList5] 797type=FUDesc 798children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 799count=4 800opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 801 802[system.cpu1.fuPool.FUList5.opList00] 803type=OpDesc 804issueLat=1 805opClass=SimdAdd 806opLat=1 807 808[system.cpu1.fuPool.FUList5.opList01] 809type=OpDesc 810issueLat=1 811opClass=SimdAddAcc 812opLat=1 813 814[system.cpu1.fuPool.FUList5.opList02] 815type=OpDesc 816issueLat=1 817opClass=SimdAlu 818opLat=1 819 820[system.cpu1.fuPool.FUList5.opList03] 821type=OpDesc 822issueLat=1 823opClass=SimdCmp 824opLat=1 825 826[system.cpu1.fuPool.FUList5.opList04] 827type=OpDesc 828issueLat=1 829opClass=SimdCvt 830opLat=1 831 832[system.cpu1.fuPool.FUList5.opList05] 833type=OpDesc 834issueLat=1 835opClass=SimdMisc 836opLat=1 837 838[system.cpu1.fuPool.FUList5.opList06] 839type=OpDesc 840issueLat=1 841opClass=SimdMult 842opLat=1 843 844[system.cpu1.fuPool.FUList5.opList07] 845type=OpDesc 846issueLat=1 847opClass=SimdMultAcc 848opLat=1 849 850[system.cpu1.fuPool.FUList5.opList08] 851type=OpDesc 852issueLat=1 853opClass=SimdShift 854opLat=1 855 856[system.cpu1.fuPool.FUList5.opList09] 857type=OpDesc 858issueLat=1 859opClass=SimdShiftAcc 860opLat=1 861 862[system.cpu1.fuPool.FUList5.opList10] 863type=OpDesc 864issueLat=1 865opClass=SimdSqrt 866opLat=1 867 868[system.cpu1.fuPool.FUList5.opList11] 869type=OpDesc 870issueLat=1 871opClass=SimdFloatAdd 872opLat=1 873 874[system.cpu1.fuPool.FUList5.opList12] 875type=OpDesc 876issueLat=1 877opClass=SimdFloatAlu 878opLat=1 879 880[system.cpu1.fuPool.FUList5.opList13] 881type=OpDesc 882issueLat=1 883opClass=SimdFloatCmp 884opLat=1 885 886[system.cpu1.fuPool.FUList5.opList14] 887type=OpDesc 888issueLat=1 889opClass=SimdFloatCvt 890opLat=1 891 892[system.cpu1.fuPool.FUList5.opList15] 893type=OpDesc 894issueLat=1 895opClass=SimdFloatDiv 896opLat=1 897 898[system.cpu1.fuPool.FUList5.opList16] 899type=OpDesc 900issueLat=1 901opClass=SimdFloatMisc 902opLat=1 903 904[system.cpu1.fuPool.FUList5.opList17] 905type=OpDesc 906issueLat=1 907opClass=SimdFloatMult 908opLat=1 909 910[system.cpu1.fuPool.FUList5.opList18] 911type=OpDesc 912issueLat=1 913opClass=SimdFloatMultAcc 914opLat=1 915 916[system.cpu1.fuPool.FUList5.opList19] 917type=OpDesc 918issueLat=1 919opClass=SimdFloatSqrt 920opLat=1 921 922[system.cpu1.fuPool.FUList6] 923type=FUDesc 924children=opList 925count=0 926opList=system.cpu1.fuPool.FUList6.opList 927 928[system.cpu1.fuPool.FUList6.opList] 929type=OpDesc 930issueLat=1 931opClass=MemWrite 932opLat=1 933 934[system.cpu1.fuPool.FUList7] 935type=FUDesc 936children=opList0 opList1 937count=4 938opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 939 940[system.cpu1.fuPool.FUList7.opList0] 941type=OpDesc 942issueLat=1 943opClass=MemRead 944opLat=1 945 946[system.cpu1.fuPool.FUList7.opList1] 947type=OpDesc 948issueLat=1 949opClass=MemWrite 950opLat=1 951 952[system.cpu1.fuPool.FUList8] 953type=FUDesc 954children=opList 955count=1 956opList=system.cpu1.fuPool.FUList8.opList 957 958[system.cpu1.fuPool.FUList8.opList] 959type=OpDesc 960issueLat=3 961opClass=IprAccess 962opLat=3 963 964[system.cpu1.icache] 965type=BaseCache 966children=tags 967addr_ranges=0:18446744073709551615 968assoc=1 969clk_domain=system.cpu_clk_domain 970forward_snoops=true 971hit_latency=2 972is_top_level=true 973max_miss_count=0 974mshrs=4 975prefetch_on_access=false 976prefetcher=Null 977response_latency=2 978size=32768 979system=system 980tags=system.cpu1.icache.tags 981tgts_per_mshr=20 982two_queue=false 983write_buffers=8 984cpu_side=system.cpu1.icache_port 985mem_side=system.toL2Bus.slave[4] 986 987[system.cpu1.icache.tags] 988type=LRU 989assoc=1 990block_size=64 991clk_domain=system.cpu_clk_domain 992hit_latency=2 993size=32768 994 995[system.cpu1.interrupts] 996type=ArmInterrupts 997 998[system.cpu1.isa] 999type=ArmISA 1000fpsid=1090793632 1001id_isar0=34607377 1002id_isar1=34677009 1003id_isar2=555950401 1004id_isar3=17899825 1005id_isar4=268501314 1006id_isar5=0 1007id_mmfr0=3 1008id_mmfr1=0 1009id_mmfr2=19070976 1010id_mmfr3=4027589137 1011id_pfr0=49 1012id_pfr1=1 1013midr=890224640 1014 1015[system.cpu1.itb] 1016type=ArmTLB 1017children=walker 1018size=64 1019walker=system.cpu1.itb.walker 1020 1021[system.cpu1.itb.walker] 1022type=ArmTableWalker 1023clk_domain=system.cpu_clk_domain 1024num_squash_per_cycle=2 1025sys=system 1026port=system.toL2Bus.slave[6] 1027 1028[system.cpu1.tracer] 1029type=ExeTracer 1030 1031[system.cpu_clk_domain] 1032type=SrcClockDomain 1033clock=500 1034voltage_domain=system.voltage_domain 1035 1036[system.intrctrl] 1037type=IntrControl 1038sys=system 1039 1040[system.iobus] 1041type=NoncoherentBus 1042clk_domain=system.clk_domain 1043header_cycles=1 1044use_default_range=false 1045width=8 1046master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 1047slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 1048 1049[system.iocache] 1050type=BaseCache 1051children=tags 1052addr_ranges=0:134217727 1053assoc=8 1054clk_domain=system.clk_domain 1055forward_snoops=false 1056hit_latency=50 1057is_top_level=true 1058max_miss_count=0 1059mshrs=20 1060prefetch_on_access=false 1061prefetcher=Null 1062response_latency=50 1063size=1024 1064system=system 1065tags=system.iocache.tags 1066tgts_per_mshr=12 1067two_queue=false 1068write_buffers=8 1069cpu_side=system.iobus.master[25] 1070mem_side=system.membus.slave[2] 1071 1072[system.iocache.tags] 1073type=LRU 1074assoc=8 1075block_size=64 1076clk_domain=system.clk_domain 1077hit_latency=50 1078size=1024 1079 1080[system.l2c] 1081type=BaseCache 1082children=tags 1083addr_ranges=0:18446744073709551615 1084assoc=8 1085clk_domain=system.cpu_clk_domain 1086forward_snoops=true 1087hit_latency=20 1088is_top_level=false 1089max_miss_count=0 1090mshrs=20 1091prefetch_on_access=false 1092prefetcher=Null 1093response_latency=20 1094size=4194304 1095system=system 1096tags=system.l2c.tags 1097tgts_per_mshr=12 1098two_queue=false 1099write_buffers=8 1100cpu_side=system.toL2Bus.master[0] 1101mem_side=system.membus.slave[1] 1102 1103[system.l2c.tags] 1104type=LRU 1105assoc=8 1106block_size=64 1107clk_domain=system.cpu_clk_domain 1108hit_latency=20 1109size=4194304 1110 1111[system.membus] 1112type=CoherentBus 1113children=badaddr_responder 1114clk_domain=system.clk_domain 1115header_cycles=1 1116system=system 1117use_default_range=false 1118width=8 1119default=system.membus.badaddr_responder.pio 1120master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 1121slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1122 1123[system.membus.badaddr_responder] 1124type=IsaFake 1125clk_domain=system.clk_domain 1126fake_mem=false 1127pio_addr=0 1128pio_latency=100000 1129pio_size=8 1130ret_bad_addr=true 1131ret_data16=65535 1132ret_data32=4294967295 1133ret_data64=18446744073709551615 1134ret_data8=255 1135system=system 1136update_data=false 1137warn_access=warn 1138pio=system.membus.default 1139 1140[system.physmem] 1141type=SimpleDRAM 1142activation_limit=4 1143addr_mapping=RaBaChCo 1144banks_per_rank=8 1145burst_length=8 1146channels=1 1147clk_domain=system.clk_domain 1148conf_table_reported=true 1149device_bus_width=8 1150device_rowbuffer_size=1024 1151devices_per_rank=8 1152in_addr_map=true 1153mem_sched_policy=frfcfs 1154null=false 1155page_policy=open 1156range=0:134217727 1157ranks_per_channel=2 1158read_buffer_size=32 1159static_backend_latency=10000 1160static_frontend_latency=10000 1161tBURST=5000 1162tCL=13750 1163tRCD=13750 1164tREFI=7800000 1165tRFC=300000 1166tRP=13750 1167tWTR=7500 1168tXAW=40000 1169write_buffer_size=32 1170write_thresh_perc=70 1171port=system.membus.master[6] 1172 1173[system.realview] 1174type=RealView 1175children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1176intrctrl=system.intrctrl 1177max_mem_size=268435456 1178mem_start_addr=0 1179pci_cfg_base=0 1180system=system 1181 1182[system.realview.a9scu] 1183type=A9SCU 1184clk_domain=system.clk_domain 1185pio_addr=520093696 1186pio_latency=100000 1187system=system 1188pio=system.membus.master[4] 1189 1190[system.realview.aaci_fake] 1191type=AmbaFake 1192amba_id=0 1193clk_domain=system.clk_domain 1194ignore_access=false 1195pio_addr=268451840 1196pio_latency=100000 1197system=system 1198pio=system.iobus.master[21] 1199 1200[system.realview.cf_ctrl] 1201type=IdeController 1202BAR0=402653184 1203BAR0LegacyIO=true 1204BAR0Size=16 1205BAR1=402653440 1206BAR1LegacyIO=true 1207BAR1Size=1 1208BAR2=1 1209BAR2LegacyIO=false 1210BAR2Size=8 1211BAR3=1 1212BAR3LegacyIO=false 1213BAR3Size=4 1214BAR4=1 1215BAR4LegacyIO=false 1216BAR4Size=16 1217BAR5=1 1218BAR5LegacyIO=false 1219BAR5Size=0 1220BIST=0 1221CacheLineSize=0 1222CardbusCIS=0 1223ClassCode=1 1224Command=1 1225DeviceID=28945 1226ExpansionROM=0 1227HeaderType=0 1228InterruptLine=31 1229InterruptPin=1 1230LatencyTimer=0 1231MaximumLatency=0 1232MinimumGrant=0 1233ProgIF=133 1234Revision=0 1235Status=640 1236SubClassCode=1 1237SubsystemID=0 1238SubsystemVendorID=0 1239VendorID=32902 1240clk_domain=system.clk_domain 1241config_latency=20000 1242ctrl_offset=2 1243disks=system.cf0 1244io_shift=1 1245pci_bus=2 1246pci_dev=7 1247pci_func=0 1248pio_latency=30000 1249platform=system.realview 1250system=system 1251config=system.iobus.master[8] 1252dma=system.iobus.slave[2] 1253pio=system.iobus.master[7] 1254 1255[system.realview.clcd] 1256type=Pl111 1257amba_id=1315089 1258clk_domain=system.clk_domain 1259gic=system.realview.gic 1260int_num=55 1261pio_addr=268566528 1262pio_latency=10000 1263pixel_clock=41667 1264system=system 1265vnc=system.vncserver 1266dma=system.iobus.slave[1] 1267pio=system.iobus.master[4] 1268 1269[system.realview.dmac_fake] 1270type=AmbaFake 1271amba_id=0 1272clk_domain=system.clk_domain 1273ignore_access=false 1274pio_addr=268632064 1275pio_latency=100000 1276system=system 1277pio=system.iobus.master[9] 1278 1279[system.realview.flash_fake] 1280type=IsaFake 1281clk_domain=system.clk_domain 1282fake_mem=true 1283pio_addr=1073741824 1284pio_latency=100000 1285pio_size=536870912 1286ret_bad_addr=false 1287ret_data16=65535 1288ret_data32=4294967295 1289ret_data64=18446744073709551615 1290ret_data8=255 1291system=system 1292update_data=false 1293warn_access= 1294pio=system.iobus.master[24] 1295 1296[system.realview.gic] 1297type=Pl390 1298clk_domain=system.clk_domain 1299cpu_addr=520093952 1300cpu_pio_delay=10000 1301dist_addr=520097792 1302dist_pio_delay=10000 1303int_latency=10000 1304it_lines=128 1305platform=system.realview 1306system=system 1307pio=system.membus.master[2] 1308 1309[system.realview.gpio0_fake] 1310type=AmbaFake 1311amba_id=0 1312clk_domain=system.clk_domain 1313ignore_access=false 1314pio_addr=268513280 1315pio_latency=100000 1316system=system 1317pio=system.iobus.master[16] 1318 1319[system.realview.gpio1_fake] 1320type=AmbaFake 1321amba_id=0 1322clk_domain=system.clk_domain 1323ignore_access=false 1324pio_addr=268517376 1325pio_latency=100000 1326system=system 1327pio=system.iobus.master[17] 1328 1329[system.realview.gpio2_fake] 1330type=AmbaFake 1331amba_id=0 1332clk_domain=system.clk_domain 1333ignore_access=false 1334pio_addr=268521472 1335pio_latency=100000 1336system=system 1337pio=system.iobus.master[18] 1338 1339[system.realview.kmi0] 1340type=Pl050 1341amba_id=1314896 1342clk_domain=system.clk_domain 1343gic=system.realview.gic 1344int_delay=1000000 1345int_num=52 1346is_mouse=false 1347pio_addr=268460032 1348pio_latency=100000 1349system=system 1350vnc=system.vncserver 1351pio=system.iobus.master[5] 1352 1353[system.realview.kmi1] 1354type=Pl050 1355amba_id=1314896 1356clk_domain=system.clk_domain 1357gic=system.realview.gic 1358int_delay=1000000 1359int_num=53 1360is_mouse=true 1361pio_addr=268464128 1362pio_latency=100000 1363system=system 1364vnc=system.vncserver 1365pio=system.iobus.master[6] 1366 1367[system.realview.l2x0_fake] 1368type=IsaFake 1369clk_domain=system.clk_domain 1370fake_mem=false 1371pio_addr=520101888 1372pio_latency=100000 1373pio_size=4095 1374ret_bad_addr=false 1375ret_data16=65535 1376ret_data32=4294967295 1377ret_data64=18446744073709551615 1378ret_data8=255 1379system=system 1380update_data=false 1381warn_access= 1382pio=system.membus.master[3] 1383 1384[system.realview.local_cpu_timer] 1385type=CpuLocalTimer 1386clk_domain=system.clk_domain 1387gic=system.realview.gic 1388int_num_timer=29 1389int_num_watchdog=30 1390pio_addr=520095232 1391pio_latency=100000 1392system=system 1393pio=system.membus.master[5] 1394 1395[system.realview.mmc_fake] 1396type=AmbaFake 1397amba_id=0 1398clk_domain=system.clk_domain 1399ignore_access=false 1400pio_addr=268455936 1401pio_latency=100000 1402system=system 1403pio=system.iobus.master[22] 1404 1405[system.realview.nvmem] 1406type=SimpleMemory 1407bandwidth=73.000000 1408clk_domain=system.clk_domain 1409conf_table_reported=false 1410in_addr_map=true 1411latency=30000 1412latency_var=0 1413null=false 1414range=2147483648:2214592511 1415port=system.membus.master[1] 1416 1417[system.realview.realview_io] 1418type=RealViewCtrl 1419clk_domain=system.clk_domain 1420idreg=0 1421pio_addr=268435456 1422pio_latency=100000 1423proc_id0=201326592 1424proc_id1=201327138 1425system=system 1426pio=system.iobus.master[1] 1427 1428[system.realview.rtc] 1429type=PL031 1430amba_id=3412017 1431clk_domain=system.clk_domain 1432gic=system.realview.gic 1433int_delay=100000 1434int_num=42 1435pio_addr=268529664 1436pio_latency=100000 1437system=system 1438time=Thu Jan 1 00:00:00 2009 1439pio=system.iobus.master[23] 1440 1441[system.realview.sci_fake] 1442type=AmbaFake 1443amba_id=0 1444clk_domain=system.clk_domain 1445ignore_access=false 1446pio_addr=268492800 1447pio_latency=100000 1448system=system 1449pio=system.iobus.master[20] 1450 1451[system.realview.smc_fake] 1452type=AmbaFake 1453amba_id=0 1454clk_domain=system.clk_domain 1455ignore_access=false 1456pio_addr=269357056 1457pio_latency=100000 1458system=system 1459pio=system.iobus.master[13] 1460 1461[system.realview.sp810_fake] 1462type=AmbaFake 1463amba_id=0 1464clk_domain=system.clk_domain 1465ignore_access=true 1466pio_addr=268439552 1467pio_latency=100000 1468system=system 1469pio=system.iobus.master[14] 1470 1471[system.realview.ssp_fake] 1472type=AmbaFake 1473amba_id=0 1474clk_domain=system.clk_domain 1475ignore_access=false 1476pio_addr=268488704 1477pio_latency=100000 1478system=system 1479pio=system.iobus.master[19] 1480 1481[system.realview.timer0] 1482type=Sp804 1483amba_id=1316868 1484clk_domain=system.clk_domain 1485clock0=1000000 1486clock1=1000000 1487gic=system.realview.gic 1488int_num0=36 1489int_num1=36 1490pio_addr=268505088 1491pio_latency=100000 1492system=system 1493pio=system.iobus.master[2] 1494 1495[system.realview.timer1] 1496type=Sp804 1497amba_id=1316868 1498clk_domain=system.clk_domain 1499clock0=1000000 1500clock1=1000000 1501gic=system.realview.gic 1502int_num0=37 1503int_num1=37 1504pio_addr=268509184 1505pio_latency=100000 1506system=system 1507pio=system.iobus.master[3] 1508 1509[system.realview.uart] 1510type=Pl011 1511clk_domain=system.clk_domain 1512end_on_eot=false 1513gic=system.realview.gic 1514int_delay=100000 1515int_num=44 1516pio_addr=268472320 1517pio_latency=100000 1518platform=system.realview 1519system=system 1520terminal=system.terminal 1521pio=system.iobus.master[0] 1522 1523[system.realview.uart1_fake] 1524type=AmbaFake 1525amba_id=0 1526clk_domain=system.clk_domain 1527ignore_access=false 1528pio_addr=268476416 1529pio_latency=100000 1530system=system 1531pio=system.iobus.master[10] 1532 1533[system.realview.uart2_fake] 1534type=AmbaFake 1535amba_id=0 1536clk_domain=system.clk_domain 1537ignore_access=false 1538pio_addr=268480512 1539pio_latency=100000 1540system=system 1541pio=system.iobus.master[11] 1542 1543[system.realview.uart3_fake] 1544type=AmbaFake 1545amba_id=0 1546clk_domain=system.clk_domain 1547ignore_access=false 1548pio_addr=268484608 1549pio_latency=100000 1550system=system 1551pio=system.iobus.master[12] 1552 1553[system.realview.watchdog_fake] 1554type=AmbaFake 1555amba_id=0 1556clk_domain=system.clk_domain 1557ignore_access=false 1558pio_addr=268500992 1559pio_latency=100000 1560system=system 1561pio=system.iobus.master[15] 1562 1563[system.terminal] 1564type=Terminal 1565intr_control=system.intrctrl 1566number=0 1567output=true 1568port=3456 1569 1570[system.toL2Bus] 1571type=CoherentBus 1572clk_domain=system.cpu_clk_domain 1573header_cycles=1 1574system=system 1575use_default_range=false 1576width=8 1577master=system.l2c.cpu_side 1578slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1579 1580[system.vncserver] 1581type=VncServer 1582frame_capture=false 1583number=0 1584port=5900 1585 1586[system.voltage_domain] 1587type=VoltageDomain 1588voltage=1.000000 1589